DS90UR124Q
DS25CP152Q
MONITOR
1
1 TO 24
Navigation
Computer
BLUE
MONITOR
2
GREEN
RED
BLUE
GREEN
RED
DS90UR124Q
1 TO 24
2x2 CROSSPOINT
DS90UR241Q
24 TO 1
DS90UR241Q
24 TO 1
BLUE
GREEN
RED
BLUE
GREEN
RED
Entertainment
System
SEL1
SEL0
DS25CP152Q
www.ti.com
SNLS294E –MAY 2008–REVISED APRIL 2013
DS25CP152Q Automotive 3.125 Gbps LVDS 2x2 Crosspoint Switch
Check for Samples: DS25CP152Q
1FEATURES DESCRIPTION
The DS25CP152Q is a 3.125 Gbps 2x2 LVDS
2• AECQ-100 Grade 3 crosspoint switch optimized for high-speed signal
• DC - 3.125 Gbps Low Jitter, Low Skew, Low routing and switching over lossy FR-4 printed circuit
Power Operation board backplanes and balanced cables. Fully
• Pin Configurable, Fully Differential, Non- differential signal paths ensure exceptional signal
integrity and noise immunity. The non-blocking
Blocking Architecture architecture allows connections of any input to any
• On-chip 100ΩInput and Output Terminations output or outputs.
Minimize Return Losses, Reduce Component
Count and Minimize Board Space Wide input common mode range allows the switch to
accept signals with LVDS, CML and LVPECL levels;
• 8 kV ESD on LVDS I/O Pins Protects Adjoining the output levels are LVDS. A very small package
Components footprint requires a minimal space on the board while
• Small 4 mm x 4 mm WQFN-16 Space Saving the flow-through pinout allows easy board layout.
Package Each differential input and output is internally
terminated with a 100Ωresistor to lower device return
APPLICATIONS losses, reduce component count and further minimize
board space.
• Automotive Display Applications
• Clock and Data Buffering and Muxing
• OC-48 / STM-16
• SD/HD/3G HD SDI Routers
Typical Application
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
IN0+
IN0-
IN1+
IN1-
OUT0+
OUT0-
OUT1+
OUT1-
1
2
3
4
12
10
9
11
(GND)
DAP
GND
NC
SEL0
SEL1
5
6
7
8
VCC
NC
EN0
EN1
16
14
13
15
2 X 2
IN0+
IN0-
IN1+
IN1-
EN0
OUT0+
EN1
OUT0-
OUT1+
OUT1-
SEL1 SEL0
DS25CP152Q
SNLS294E –MAY 2008–REVISED APRIL 2013
www.ti.com
Block Diagram
Connection Diagram
Figure 1. DS25CP152Q Pin Diagram
PIN DESCRIPTIONS
Pin
Pin Name I/O, Type Pin Description
Number
IN0+, IN0- , 1, 2, I, LVDS Inverting and non-inverting high speed LVDS input pins.
IN1+, IN1- 3, 4
OUT0+, OUT0-, 12, 11, O, LVDS Inverting and non-inverting high speed LVDS output pins.
OUT1+, OUT1- 10, 9
SEL0, SEL1 7, 8 I, LVCMOS Switch configuration pins. There is a 20 kΩpulldown resistor on each pin.
EN0, EN1 14, 13 I, LVCMOS Output enable pins. There is a 20 kΩpulldown resistor on each pin.
NC 6, 15 I, LVCMOS "NO CONNECT" pins.
VDD 16 Power Power supply pin.
GND 5, DAP Power Ground pin and Device Attach Pad (DAP) ground.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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DS25CP152Q
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SNLS294E –MAY 2008–REVISED APRIL 2013
Absolute Maximum Ratings(1)(2)
Supply Voltage −0.3V to +4V
LVCMOS Input Voltage −0.3V to (VCC + 0.3V)
LVDS Input Voltage −0.3V to +4V
Differential Input Voltage |VID| 1.0V
LVDS Output Voltage −0.3V to (VCC + 0.3V)
LVDS Differential Output Voltage 0V to 1.0V
LVDS Output Short Circuit Current Duration 5 ms
Junction Temperature +105°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range
Soldering (4 sec.) +260°C
Maximum Package Power Dissipation at 25°C
RGH0016A Package 1.91W
Derate RGH0016A Package 23.9 mW/°C above +25°C
Package Thermal Resistance
θJA +41.8°C/W
θJC +6.9°C/W
ESD Susceptibility
HBM (3) ≥8 kV
MM (4) ≥250V
CDM (5) ≥1250V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) Human Body Model, applicable std. JESD22-A114C
(4) Machine Model, applicable std. JESD22-A115-A
(5) Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions Min Typ Max Units
Supply Voltage (VCC) 3.0 3.3 3.6 V
Receiver Differential Input Voltage (VID) 0 1 V
Operating Free Air Temperature (TA)−40 +25 +85 °C
DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1)(2)(3)
Symbol Parameter Conditions Min Typ Max Units
LVCMOS DC SPECIFICATIONS
VIH High Level Input Voltage 2.0 VCC V
VIL Low Level Input Voltage GND 0.8 V
IIH High Level Input Current VIN = 3.6V 40 175 250 μA
VCC = 3.6V
IIL Low Level Input Current VIN = GND 0 ±10 μA
VCC = 3.6V
(1) The Electrical Characteristics tables list ensure specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not
ensured.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD.
(3) Typical values represent most likely parametric norms for VCC = +3.3V and TA= +25°C, and at the Recommended Operating Conditions
at the time of product characterization and are not ensured.
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DS25CP152Q
SNLS294E –MAY 2008–REVISED APRIL 2013
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DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (1)(2)(3)
Symbol Parameter Conditions Min Typ Max Units
VCL Input Clamp Voltage ICL =−18 mA, VCC = 0V −0.9 −1.5 V
LVDS INPUT DC SPECIFICATIONS
VID Input Differential Voltage 0 1 V
VTH Differential Input High Threshold VCM = +0.05V or VCC-0.05V 0 +100 mV
VTL Differential Input Low Threshold −100 0 mV
VCMR Common Mode Voltage Range VID = 100 mV 0.05 VCC - V
0.05
VIN = +3.6V or 0V ±1 ±10 μA
IIN Input Current VCC = 3.6V or 0V
CIN Input Capacitance Any LVDS Input Pin to GND 1.7 pF
RIN Input Termination Resistor Between IN+ and IN- 100 Ω
LVDS OUTPUT DC SPECIFICATIONS
VOD Differential Output Voltage 250 350 450 mV
RL= 100Ω
ΔVOD Change in Magnitude of VOD for Complimentary -35 35 mV
Output States
VOS Offset Voltage 1.05 1.2 1.375 V
RL= 100Ω
ΔVOS Change in Magnitude of VOS for Complimentary -35 35 mV
Output States
IOS Output Short Circuit Current (4) OUT to GND -35 -55 mA
OUT to VCC 7 55 mA
COUT Output Capacitance Any LVDS Output Pin to GND 1.2 pF
ROUT Output Termination Resistor Between OUT+ and OUT- 100 Ω
SUPPLY CURRENT
ICC Supply Current EN0 = EN1 = High 64 77 mA
ICCZ Supply Current with Outputs Disabled EN0 = EN1 = Low 23 29 mA
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified (1)(2)(3)
Symbol Parameter Conditions Min Typ Max Units
LVDS OUTPUT AC SPECIFICATIONS
tPLHD Differential Propagation Delay Low to 340 500 ps
High RL= 100Ω
tPHLD Differential Propagation Delay High to 344 500 ps
Low
tSKD1 Pulse Skew |tPLHD −tPHLD| 4 35 ps
(4)
tSKD2 Channel to Channel Skew 12 40 ps
(5)
tSKD3 Part to Part Skew 50 150 ps
(6)
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms for VCC = +3.3V and TA= +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
(3) Specification is ensured by characterization and is not tested in production.
(4) tSKD1, |tPLHD −tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
(5) tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode
(any one input to all outputs).
(6) tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
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Product Folder Links: DS25CP152Q
RL
OUT+
OUT-
IN+
IN-
Signal Generator R D
R D RL
VOL
OUT+
OUT-
IN+
IN-
Power Supply
Power Supply
VOH
DS25CP152Q
www.ti.com
SNLS294E –MAY 2008–REVISED APRIL 2013
AC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified (1)(2)(3)
Symbol Parameter Conditions Min Typ Max Units
tLHT Rise Time 65 120 ps
RL= 100Ω
tHLT Fall Time 65 120 ps
tON Output Enable Time ENn = LH to output active 7 20 μs
tOFF Output Disable Time ENn = HL to output inactive 5 12 ns
tSEL Select Time SELn LH or HL to output 3.5 12 ns
JITTER PERFORMANCE (3)
tRJ1 VID = 350 mV 2.5 Gbps 0.5 1 ps
Random Jitter (RMS Value) VCM = 1.2V
tRJ2 (7) 3.125 Gbps 0.5 1 ps
Clock (RZ)
tDJ1 VID = 350 mV 2.5 Gbps 8 25 ps
Deterministic Jitter (Peak to Peak) VCM = 1.2V
tDJ2 (8) 3.125 Gbps 3 19 ps
K28.5 (NRZ)
tTJ1 VID = 350 mV 2.5 Gbps 0.04 0.08 UIP-P
Total Jitter (Peak to Peak) VCM = 1.2V
tTJ2 (9) 3.125 Gbps 0.03 0.09 UIP-P
PRBS-23 (NRZ)
(7) Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
(8) Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
(9) Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted.
DC Test Circuits
AC Test Circuits and Timing Diagrams
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
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OUT+
OUT-
50:
VCC
CML3.3V or CML2.5V
Driver
100: Differential T-Line
DS25CP152
Receiver
IN+
IN-
100:
50:
OUT+
OUT-
DS25CP152
Receiver
IN+
IN-
100: Differential T-Line
100:
LVDS
Driver
DS25CP152Q
SNLS294E –MAY 2008–REVISED APRIL 2013
www.ti.com
FUNCTIONAL DESCRIPTION
The DS25CP152Q is a 3.125 Gbps 2x2 LVDS digital crosspoint switch optimized for high-speed signal routing
and switching over lossy FR-4 printed circuit board backplanes and balanced cables.
Switch Configuration Truth Table
S1 S0 OUT1 OUT0
0 0 IN0 IN0
0 1 IN0 IN1
1 0 IN1 IN0
1 1 IN1 IN1
Output Enable Truth Table
EN1 EN0 OUT1 OUT0
0 0 Disabled Disabled
0 1 Disabled Enabled
1 0 Enabled Disabled
1 1 Enabled Enabled
Input Interfacing
The DS25CP152Q accepts differential signals and allows simple AC or DC coupling. With a wide common mode
range, the DS25CP152Q can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML).
The following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the
DS25CP152Q inputs are internally terminated with a 100Ωresistor.
Figure 2. Typical LVDS Driver DC-Coupled Interface to DS25CP152Q Input
Figure 3. Typical CML Driver DC-Coupled Interface to DS25CP152Q Input
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Product Folder Links: DS25CP152Q
OUT+
OUT-
CML or
LVPECL or
LVDS
IN+
IN-
100:
100: Differential T-Line
Differential
Receiver
DS25CP152
Driver
100:
OUT+
OUT-
150-250:
100: Differential T-Line LVDS
Receiver
IN+
IN-
100:
LVPECL
Driver
150-250:
DS25CP152Q
www.ti.com
SNLS294E –MAY 2008–REVISED APRIL 2013
Figure 4. Typical LVPECL Driver DC-Coupled Interface to DS25CP152Q Input
Output Interfacing
The DS25CP152Q outputs signals that are compliant to the LVDS standard. Its outputs can be DC-coupled to
most common differential receivers. The following figure illustrates typical DC-coupled interface to common
differential receivers and assumes that the receivers have high impedance inputs. While most differential
receivers have a common mode input range that can accommodate LVDS compliant signals, it is recommended
to check the respective receiver's data sheet prior to implementing the suggested interface implementation.
Figure 5. Typical DS25CP152Q Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: DS25CP152Q
60
50
40
30
20
10
00 0.66 1.32 1.98 2.64 3.3
VCC = 3.3V
TA = 25°C
3.125 Gbps
NRZ PRBS-7
VID = 350 mV
TOTAL JITTER (ps)
INPUT COMMON MODE VOLTAGE (V)
60
50
40
30
20
10
00 0.8 1.6 2.4 3.2 4.0
VCC = 3.3V
TA = 25°C
NRZ PRBS-7
TOTAL JITTER (ps)
DATA RATE (Gbps)
DS25CP152Q
SNLS294E –MAY 2008–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics
Figure 6. A 3.125 Gbps NRZ PRBS-7 After 2" Figure 7. A 2.5 Gbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline Differential FR-4 Stripline
V:100 mV / DIV, H:50 ps / DIV V:100 mV / DIV, H:75 ps / DIV
Figure 8. Total Jitter as a Function of Input Common Mode Figure 9. Total Jitter as a Function of Data Rate
Voltage
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DS25CP152Q
www.ti.com
SNLS294E –MAY 2008–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision D (April 2013) to Revision E Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 8
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
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PACKAGE OPTION ADDENDUM
www.ti.com 15-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
DS25CP152QSQ/NOPB ACTIVE WQFN RGH 16 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 2C152QS
DS25CP152QSQX/NOPB ACTIVE WQFN RGH 16 4500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 2C152QS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS25CP152QSQ/NOPB WQFN RGH 16 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
DS25CP152QSQX/NOPB WQFN RGH 16 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Oct-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS25CP152QSQ/NOPB WQFN RGH 16 1000 210.0 185.0 35.0
DS25CP152QSQX/NOPB WQFN RGH 16 4500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Oct-2013
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
SEE TERMINAL
DETAIL
16X 0.3
0.2
2.6 0.1
16X 0.5
0.3
0.8 MAX
(A) TYP
0.05
0.00
12X 0.5
4X
1.5
B4.1
3.9 A
4.1
3.9 0.3
0.2
0.5
0.3
WQFN - 0.8 mm max heightRGH0016A
PLASTIC QUAD FLATPACK - NO LEAD
4214978/B 01/2017
DIM A
OPT 1 OPT 1
(0.1) (0.2)
PIN 1 INDEX AREA
0.08
SEATING PLANE
1
49
12
58
16 13
(OPTIONAL)
PIN 1 ID
0.1 C A B
0.05
EXPOSED
THERMAL PAD
17 SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
SCALE 3.000
DETAIL
OPTIONAL TERMINAL
TYPICAL
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
16X (0.25)
16X (0.6)
( 0.2) TYP
VIA
12X (0.5)
(3.8)
(3.8)
(1)
( 2.6)
(R0.05)
TYP
(1)
WQFN - 0.8 mm max heightRGH0016A
PLASTIC QUAD FLATPACK - NO LEAD
4214978/B 01/2017
SYMM
1
4
58
9
12
13
16
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
17
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
16X (0.6)
16X (0.25)
12X (0.5)
(3.8)
(3.8)
4X ( 1.15)
(0.675)
TYP
(0.675) TYP
(R0.05)
TYP
WQFN - 0.8 mm max heightRGH0016A
PLASTIC QUAD FLATPACK - NO LEAD
4214978/B 01/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SYMM
TYP
EXPOSED METAL
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
SYMM
1
4
58
9
12
13
16
17
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