An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMR14206
SNVS733D –OCTOBER 2011–REVISED APRIL 2013
LMR14206 SIMPLE SWITCHER
®
42Vin, 0.6A Step-Down Voltage Regulator in SOT-23
Check for Samples: LMR14206
All trademarks are the property of their respective owners.
1
1 Features
1• Input Voltage Range of 4.5V to 42V
• Output Voltage Range of 0.765V to 34V
• Output Vurrent up to 0.6A
• 1.25 MHz Switching Frequency
• Low Shutdown Iq, 16 µA Typical
• Short Circuit Protected
• Internally Compensated
• Soft-Start Function
• Thin 6-Pin SOT Package (2.97 x 1.65 x 1mm)
• Fully Enabled for WEBENCH® Power Designer
2 Performance Benefits
• Tight Accuracy for Powering Digital ICs
• Extremely Easy to Use
• Tiny Overall Solution Reduces System Cost
3 Applications
• Point-of-Load Conversions from 5V, 12V, and 24V
Rails
• Space Constrained Applications
• Battery Powered Equipment
• Industrial Distributed Power Applications
• Power Meters
• Portable Hand-Held Instruments
4 Description
The LMR14206 is a PWM DC/DC buck (step-down)
regulator. With a wide input range from 4.5V-42V,
they are suitable for a wide range of applications
such as power conditioning from unregulated
sources. They feature a low RDSON (0.9Ωtypical)
internal switch for maximum efficiency (85% typical).
Operating frequency is fixed at 1.25 MHz allowing the
use of small external components while still being
able to have low output voltage ripple. Soft-start can
be implemented using the shutdown pin with an
external RC circuit allowing the user to tailor the soft-
start time to a specific application.
The LMR14206 is optimized for up to 600 mA load
current with a 0.765V nominal feedback voltage.
Additional features include: thermal shutdown, VIN
under-voltage lockout, and gate drive under-voltage
lockout. The LMR14206 is available in a low profile 6-
pin SOT package.
CB 1
2
3 4
5
6
LMR14206
GND
FB
SW
PIN 1 ID
VIN
SHDN
LMR14206
VOUT
VIN
L1
D1
R1
R2
CBOOT
CIN COUT
FB
SW
CB
GND
SHDN
VIN
0.0 0.1 0.2 0.3 0.4 0.5 0.6
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
LOAD CURRENT (A)
1.2Vout
3.3Vout
0.0 0.1 0.2 0.3 0.4 0.5 0.6
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
LOAD CURRENT (A)
1.2Vout
3.3Vout
2
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4.1 System Performance
Efficiency vs Load Current
VIN = 12V, VOUT = 1.2V and 3.3V Efficiency vs Load Current
VIN = 24V, VOUT = 1.2V and 3.3V
Figure 1.
4.2 Connection Diagram
Figure 2. 6-Pin SOT (Top View)
See DDC Package
3
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Connection Diagram (continued)
PIN DESCRIPTIONS
Pin Name Function
1 CB SW FET gate bias voltage. Connect CBOOT cap between CB and SW.
2 GND Ground connection.
3 FB Feedback pin: Set feedback voltage divider ratio with VOUT = VFB (1+(R1/R2)). Resistors should be
in the 100-10K range to avoid input bias errors.
4 SHDN Logic level shutdown input. Pull to GND to disable the device and pull high to enable the device. If
this function is not used tie to VIN or leave open.
5 VIN Power input voltage pin: 4.5V to 42V normal operating range.
6 SW Power FET output: Connect to inductor, diode, and CBOOT cap.
4
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the
device is intended to be functional, but device parameter specifications may not be ensured. For ensured specifications and test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using: PD(MAX) = (TJ(MAX) −TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and
the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. Thermal
shutdown engages at TJ=175°C (typ.) and disengages at TJ=155°C (typ).
(4) Human Body Model, applicable std. JESD22-A114-C.
5 Absolute Maximum Ratings(1)(2)
VIN -0.3V to +45V
SHDN -0.3V to (VIN+0.3V) <45V
SW Voltage -0.3V to +45V
CB Voltage above SW Voltage 7V
FB Voltage -0.3V to +5V
Maximum Junction Temperature 150°C
Power Dissipation(3) Internally Limited
Lead Temperature 300°C
Vapor Phase (60 sec.) 215°C
Infrared (15 sec.) 220°C
ESD Susceptibility Human Body Model(4) 1.5 kV
For soldering specifications see SNOA549
(1) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
100% production tested. All limits at temperature extremes are ensured via correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
6 Operating Conditions
Operating Junction Temperature Range(1) −40°C to +125°C
Storage Temperature −65°C to +150°C
Input Voltage VIN 4.5V to 42V
SW Voltage Up to 42V
5
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(1) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
100% production tested. All limits at temperature extremes are ensured via correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely norm.
(3) Includes the bond wires, RDSON from VIN pin to SW pin.
(4) Current limit at 0% duty cycle.
(5) Bias currents flow into pin.
(6) All numbers apply for packages soldered directly onto a 3" x 3" PC board with 2 oz. copper on 4 layers in still air in accordance to
JEDEC standards. Thermal resistance varies greatly with layout, copper thickness, number of layers in PCB, power distribution, number
of thermal vias, board size, ambient temperature, and air flow.
7 Electrical Characteristics
Specifications in standard type face are for TJ= 25°C and those with boldface type apply over the full Operating
Temperature Range ( TJ=−40°C to +125°C). Minimum and Maximum limits are ensured through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ= +25°C, and are provided for reference purposes
only. Unless otherwise stated the following conditions apply: VIN = 12V.
Symbol Parameter Conditions Min(1) Typ(2) Max(1) Units
IQQuiescent current SHDN = 0V 16 40 µA
Device On, Not Switching 1.30 1.75 mA
Device On, No Load 1.35 1.85
RDSON Switch ON resistance See (3) 0.9 1.6 Ω
ILSW Switch leakage current VIN = 42V 0.0 0.5 µA
ICL Switch current limit See (4) 1.15 A
IFB Feedback pin bias current See (5) 0.1 1.0 µA
VFB FB Pin reference voltage 0.747 0.765 0.782 V
tMIN Minimum ON time 100 ns
fSW Switching frequency VFB = 0.5V 0.95 1.25 1.50 MHz
VFB = 0V 0.35
DMAX Maximum duty cycle 81 87 %
VUVP Undervoltage lockout
thresholds On threshold 4.4 3.7 V
Off threshold 3.5 3.25
VSHDN Shutdown threshold Device on 2.3 1.0 V
Device off 0.9 0.3
ISHDN Shutdown pin input bias current VSHDN = 2.3V(5) 0.05 1.5 µA
VSHDN = 0V 0.02 1.5
THERMAL SPECIFICATIONS
RθJA Junction-to-Ambient Thermal
Resistance, SOT Package See (6) 121 °C/W
SWITCH CURRENT LIMIT (A)
1.1 1.7 2.3 2.8 3.4 4.0
SHDN PIN VOLTAGE (V)
1.2
1.0
0.9
0.7
0.6
0.4
6
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8 Typical Performance Characteristics
Input UVLO vs. Temperature SHDN Pin Current vs. SHDN Pin Voltage
Figure 3. Figure 4.
Switching Node and Output Voltage Waveforms Load Transient Waveforms
VIN = 12V, VOUT = 3.3V, IOUT = 200 mA
Top trace: VOUT, 10 mV/div, AC Coupled
Bottom trace: SW, 5V/div, DC Coupled
T = 1 µs/div
VIN = 12V, VOUT = 3.3V, IOUT = 300 mA to 200 mA to 300 mA
Top trace: VOUT, 20 mV/div, AC Coupled
Bottom trace: IOUT, 100 mA/div, DC Coupled
T = 200 µs/div
Figure 5. Figure 6.
Start-Up Waveform Switch Current Limit vs. SHDN Pin Voltage
(Soft-Start Implementation)
VIN = 12V, VOUT = 3.3V, IOUT = 50 mA
Top trace: VOUT, 1V/div, DC Coupled
Bottom trace: SHDN, 2V/div, DC Coupled
T = 40 µs/div Figure 7. Figure 8.
Max Duty
Cycle Limit
OSC
DC
LIMIT
SET
+
+
-
+
PWM
Comp RESET
FET
Driver
BUCK
DRIVE
+
-
Error
Amp
FB
Bandgap Soft
Start
Thermal
Shutdown
TSD
SHDN
Inductor
Current
Measurement
CB
SW
GND
UVLO
Comp
BG
UVLO
Voltage
Regulator
VIN
7
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8.1 Block Diagram
L = (VIN - VOUT)VOUT
VIN x IRIPPLE x fSW
8
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9 APPLICATION INFORMATION
9.1 PROTECTION
The LMR14206 has dedicated protection circuitry running during normal operation to protect the IC. The thermal
shutdown circuitry turns off the power device when the die temperature reaches excessive levels. The UVLO
comparator protects the power device during supply power startup and shutdown to prevent operation at
voltages less than the minimum input voltage. A gate drive (CB) under-voltage lockout is included to ensured that
there is enough gate drive voltage to drive the MOSFET before the device tries to start switching. The
LMR14206 also features a shutdown mode decreasing the supply current to approximately 16 µA.
9.2 CONTINUOUS CONDUCTION MODE
The LMR14206 contains a current-mode, PWM buck regulator. A buck regulator steps the input voltage down to
a lower output voltage. In continuous conduction mode (when the inductor current never reaches zero at steady
state), the buck regulator operates in two cycles. The power switch is connected between VIN and SW. In the first
cycle of operation the transistor is closed and the diode is reverse biased. Energy is collected in the inductor and
the load current is supplied by COUT and the rising current through the inductor. During the second cycle the
transistor is open and the diode is forward biased due to the fact that the inductor current cannot instantaneously
change direction. The energy stored in the inductor is transferred to the load and output capacitor. The ratio of
these two cycles determines the output voltage. The output voltage is defined approximately as:
D=VOUT/VIN and D’ = (1-D)
where
• D is the duty cycle of the switch. (1)
D and D' will be required for design calculations.
9.3 DESIGN PROCEDURE
This section presents guidelines for selecting external components.
9.4 SETTING THE OUTPUT VOLTAGE
The output voltage is set using the feedback pin and a resistor divider connected to the output as shown on the
front page schematic, Figure 1. The feedback pin voltage is 0.765V, so the ratio of the feedback resistors sets
the output voltage according to the following equation:
VOUT=0.765V(1+(R1/R2)) (2)
Typically R2 will be given as 100Ω-10 kΩfor a starting value. To solve for R1 given R2 and VOUT, use:
R1=R2((VOUT/0.765V)-1). (3)
9.5 INPUT CAPACITOR
A low ESR ceramic capacitor (CIN) is needed between the VIN pin and GND pin. This capacitor prevents large
voltage transients from appearing at the input. Use a 2.2 µF-10 µF value with X5R or X7R dielectric. Depending
on construction, a ceramic capacitor’s value can decrease up to 50% of its nominal value when rated voltage is
applied. Consult with the capacitor manufacturer's data sheet for information on capacitor derating over voltage
and temperature.
9.6 INDUCTOR SELECTION
The most critical parameters for the inductor are the inductance, peak current, and the DC resistance. The
inductance is related to the peak-to-peak inductor ripple current, the input and the output voltages.
(4)
9
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INDUCTOR SELECTION (continued)
A higher value of ripple current reduces inductance, but increases the conductance loss, core loss, and current
stress for the inductor and switch devices. It also requires a bigger output capacitor for the same output voltage
ripple requirement. A reasonable value is setting the ripple current to be 30% of the DC output current. Since the
ripple current increases with the input voltage, the maximum input voltage is always used to determine the
inductance. The DC resistance of the inductor is a key parameter for the efficiency. Lower DC resistance is
available with a bigger winding area. A good tradeoff between the efficiency and the core size is letting the
inductor copper loss equal 2% of the output power. See AN-1197 for more information on selecting inductors. A
good starting point for most applications is a 10 µH to 22 µH with 1.1A or greater current rating. Using such a
rating will enable the LMR14206 to current limit without saturating the inductor. This is preferable to the device
going into thermal shutdown mode and the possibility of damaging the inductor if the output is shorted to ground
or other longterm overload.
9.7 OUTPUT CAPACITOR
The selection of COUT is driven by the maximum allowable output voltage ripple. The output ripple in the constant
frequency, PWM mode is approximated by:
VRIPPLE = IRIPPLE(ESR+(1/(8fSWCOUT))) (5)
The ESR term usually plays the dominant role in determining the voltage ripple. Low ESR ceramic capacitors are
recommended. Capacitors in the range of 22 µF-100 µF are a good starting point with an ESR of 0.1Ωor less.
9.8 BOOTSTRAP CAPACITOR
A 0.15 µF ceramic capacitor or larger is recommended for the bootstrap capacitor (CBOOT). For applications
where the input voltage is less than twice the output voltage a larger capacitor is recommended, generally 0.15
µF to 1 µF to ensure plenty of gate drive for the internal switches and a consistently low RDSON.
9.9 SOFT-START COMPONENTS
The LMR14206 has circuitry that is used in conjunction with the SHDN pin to limit the inrush current on start-up
of the DC/DC switching regulator. The SHDN pin in conjunction with a RC filter is used to tailor the soft-start for a
specific application. When a voltage applied to the SHDN pin is between 0V and up to 2.3V it will cause the cycle
by cycle current limit in the power stage to be modulated for minimum current limit at 0V up to the rated current
limit at 2.3V. Thus controlling the output rise time and inrush current at startup. The resistor value should be
selected so the current sourced into the SHDN pin will be greater then the leakage current of the SHDN pin (1.5
µA ) when the voltage at SHDN is equal or greater then 2.3V.
9.10 SHUTDOWN OPERATION
The SHDN pin of the LMR14206 is designed so that it may be controlled using 2.3V or higher logic signals. If the
shutdown function is not to be used the SHDN pin may be tied to VIN. The maximum voltage to the SHDN pin
should not exceed 42V. If the use of a higher voltage is desired due to system or other constraints it may be
used, however a 100 kΩor larger resistor is recommended between the applied voltage and the SHDN pin to
protect the device.
9.11 SCHOTTKY DIODE
The breakdown voltage rating of the diode (D1) is preferred to be 25% higher than the maximum input voltage.
The current rating for the diode should be equal to the maximum output current for best reliability in most
applications. In cases where the duty cycle is greater than 50%, the average diode current is lower. In this case it
is possible to use a diode with a lower average current rating, approximately (1-D)IOUT, however the peak current
rating should be higher than the maximum load current. A 0.5A to 1A rated diode is a good starting point.
FB
GND
SW
CB
SHDN
LMR14206
5V OUT
7V to 42V IN
L1
D1
60V 1A
R1
R2
5.62k
1.02k
VIN
CIN
CBOOT
COUT
47 PF
15 PH
2.2 PF
0.15 PF
FB
GND
SW
CB
SHDN
LMR14206
3.3V OUT
4.5V to 42V IN
L1
D1
60V 1A
R1
R2
3.4k
1.02k
VIN
CIN
CBOOT
COUT
47 PF
15 PH
0.15 PF
2.2 PF
10
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9.12 LAYOUT CONSIDERATIONS
To reduce problems with conducted noise pick up, the ground side of the feedback network should be connected
directly to the GND pin with its own connection. The feedback network, resistors R1 and R2, should be kept
close to the FB pin, and away from the inductor to minimize coupling noise into the feedback pin. The input
bypass capacitor CIN must be placed close to the VIN pin. This will reduce copper trace resistance which effects
input voltage ripple of the IC. The inductor L1 should be placed close to the SW pin to reduce EMI and capacitive
coupling. The output capacitor, COUT should be placed close to the junction of L1 and the diode D1. The L1, D1,
and COUT trace should be as short as possible to reduce conducted and radiated noise and increase overall
efficiency. The ground connection for the diode, CIN, and COUT should be as small as possible and tied to the
system ground plane in only one spot (preferably at the COUT ground point) to minimize conducted noise in the
system ground plane. For more detail on switching power supply layout considerations see Application Note AN-
1149: Layout Guidelines for Switching Power Supplies SNVA021.
9.13 Typical Applications
Figure 9. Application Circuit, 3.3V Output
Figure 10. Application Circuit, 5V Output
FB
GND
SW
CB
SHDN
LMR14206
12V OUT
15V to 42V IN
L1
D1
60V 1A
R1
R2
14.7k
1k
VIN
CIN
CBOOT
COUT
22 PF
47 PH
0.15 PF
2.2 PF
11
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Typical Applications (continued)
Figure 11. Application Circuit, 12V Output
Figure 12. Application Circuit, 15V Output
FB
GND
SW
CB
SHDN
LMR14206
0.8V OUT
4.5V to 12V IN D1
60V 1A
R1
R2
30.9
787
L1
CIN
CBOOT
COUT
100 PF
10 PH
0.15 PF
2.2 PF
VIN
12
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Typical Applications (continued)
Figure 13. Application Circuit, 0.8V Output
13
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10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 12
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMR14206XMK/NOPB ACTIVE SOT-23-THIN DDC 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SJ2B
LMR14206XMKE/NOPB ACTIVE SOT-23-THIN DDC 6 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SJ2B
LMR14206XMKX/NOPB ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SJ2B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMR14206XMK/NOPB SOT-
23-THIN DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMR14206XMKE/NOPB SOT-
23-THIN DDC 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMR14206XMKX/NOPB SOT-
23-THIN DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Mar-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMR14206XMK/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0
LMR14206XMKE/NOPB SOT-23-THIN DDC 6 250 210.0 185.0 35.0
LMR14206XMKX/NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Mar-2017
Pack Materials-Page 2
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PACKAGE OUTLINE
C
0.20
0.12 TYP 0.25
3.05
2.55
4X 0.95
1.100
0.847
0.1
0.0 TYP
6X 0.5
0.3
0.6
0.3 TYP
1.9
0 -8 TYP
A
3.05
2.75
B
1.75
1.45
SOT - 1.1 max heightDDC0006A
SOT
4214841/B 11/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
34
0.2 C A B
16
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
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EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
6X (1.1)
6X (0.6)
(2.7)
4X (0.95)
(R0.05) TYP
4214841/B 11/2020
SOT - 1.1 max heightDDC0006A
SOT
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
SYMM
1
34
6
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDERMASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.7)
4X(0.95)
6X (1.1)
6X (0.6)
(R0.05) TYP
SOT - 1.1 max heightDDC0006A
SOT
4214841/B 11/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
SYMM
SYMM
1
34
6
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