- BI: Bad block Information

>Host can use complete spare area except BI and ECC code area. For example,

Host can write data to Spare area buffer except for the area controlled by ECC logic at program operation.

>In case of ’with ECC’ mode, OneNAND automatically generates ECC code for both main and spare data of memory during program operation

but does not update ECC code to spare bufferRAM during load operation.

>When loading/programming spare area, spare area BufferRAM address(BSA) and BufferRAM sector count(BSC) is chosen via Start buffer register

as it is.

Note that all commands should be issued right after INT is turned from ready state to busy state. (i.e. right after 0 is written to INT register.) After any

command is issued and the corresponding operation is completed, INT goes back to ready state. (00F0h and 00F3h may be accepted during busy state

of some operations. Refer to the rightmost column of the command register table above.)

LS (Locked Status): ’1’ value of this bit specifies that there is locked block in NAND Flash.

ERm (ECC Error for Main area data) & ERs (ECC Error for Spare area data)

ERm and ERs show the number of error in a sector as a result of ECC check at the load operation.

3. ECClogSector: ECC error position address that selects one of the 2nd word and LSB of the 3rd word of spare area. Refer to the below table.

The entire address range, except for the boot area, can be used for the data buffer. All commands are written to the boot partition. Writes outside the

Note: 1) Bootcode copy operation starts 400us later than POR activation.

Host can read Bootcode in BootRAM(1K bytes) after Bootcode copy completion.