TLC7701-EP, TLC7705-EP, TLC7733-EP SGLS013E - MARCH 2003 - REVISED NOVEMBER 2011 www.ti.com MICROPOWER SUPPLY VOLTAGE SUPERVISORS Check for Samples: TLC7701-EP, TLC7705-EP, TLC7733-EP FEATURES SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS 1 * * * * * * * * * * Power-On Reset Generator Automatic Reset Generation After Voltage Drop Precision Voltage Sensor Temperature-Compensated Voltage Reference Programmable Delay Time by External Capacitor Supply Voltage Range . . . 2 V to 6 V Defined RESET Output from VDD 1 V Power-Down Control Support for Static RAM With Battery Backup Maximum Supply Current of 16 mA Power Saving Totem-Pole Outputs * * * * Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Extended (-40C/125C and -55C/125C), Temperature Ranges (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability * * * (1) Additional temperature ranges available - contact factory D OR PW PACKAGE (TOP VIEW) CONTROL RESIN CT GND 1 8 2 7 3 6 4 5 VDD SENSE RESET RESET DESCRIPTION The TLC77xx family of micropower supply voltage supervisors provide reset control, primarily in microcomputer and microprocessor systems. During power-on, RESET is asserted when VDD reaches 1 V. After minimum VDD ( 2 V) is established, the circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (VI(SENSE)) remains below the threshold voltage. An internal timer delays return of the output to the inactive state to ensure proper system reset. The delay time (td) is determined by an external capacitor: td = 2.1 x 104 x CT (1) Where CT is in farads td is in seconds Except for the TLC7701, which can be customized with two external resistors, each supervisor has a fixed sense threshold voltage set by an internal voltage divider. When SENSE voltage drops below the threshold voltage, the outputs become active and stay in that state until SENSE voltage returns above threshold voltage and the delay time (td) has expired. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2003-2011, Texas Instruments Incorporated TLC7701-EP, TLC7705-EP, TLC7733-EP SGLS013E - MARCH 2003 - REVISED NOVEMBER 2011 www.ti.com In addition to the power-on reset and undervoltage-supervisor function, the TLC77xx adds power-down control support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The voltage monitor contains additional logic intended for control of static memories with battery backup during power failure. By driving the chip select (CS) of the memory circuit with the RESET output of the TLC77xx and with the CONTROL driven by the memory bank select signal (CSH1) of the microprocessor (see Figure 11), the memory circuit is automatically disabled during a power loss. (In this application the TLC77xx power has to be supplied by the battery.) ORDERING INFORMATION TA -40C to 125C -55C to 125C (1) PACKAGE (1) TSSOP - PW ORDERABLE PART NUMBER TOP-SIDE MARKING VID NUMBER TLC7701QPWREP 7701QE V62/04604 - 01XE TLC7705QPWREP 7705QE V62/04604 - 02XE Tape and reel TSSOP - PW Tape and reel SOIC - D Tape and reel TLC7733QPWREP 7733QE V62/04604 - 03XE TLC7701MPWREP 7701ME V62/04604 - 04XE TLC7733MPWREP 7733ME V62/04604 - 06XE TLC7701MDREP 7701ME V62/04604 - 04YE The PW package is only available left-end taped and reeled (indicated by the R suffix on the device type; e.g., TLC7701QPWREP). Table 1. FUNCTION TABLE (1) CONTROL RESIN VI(SENSE) > VIT+ RESET RESET L L False H L L L L True H L H False H L L H True L (1) H (1) H L False H L H L True H L H H False H L H H True H H (1) RESET and RESET states shown are valid for t > td. 1 COMP 7 S SENSE S<VIT VIT RESIN Z1 2 1 3 CT x Z2 CX 1 1 5 Z3 RESET 2 1 1 CONTROL 6 RESET 3 (1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Figure 1. Logic Symbol 2 Submit Documentation Feedback Copyright (c) 2003-2011, Texas Instruments Incorporated Product Folder Link(s): TLC7701-EP TLC7705-EP TLC7733-EP TLC7701-EP, TLC7705-EP, TLC7733-EP SGLS013E - MARCH 2003 - REVISED NOVEMBER 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM 8 CONTROL 1 6 50 A 5 RESIN SENSE VDD RESET(1) RESET(1) 2 7 R1(2) R2 1 M 1.1 V 4 3 CT (1) Outputs are totem-pole configuration. External pullup or pulldown resistors are not required. (2) Nominal values: R1 (Typ) R2 (Typ) TLC7701 0 TLC7705 910 k 290 k TLC7733 750 k 450 k GND TIMING DIAGRAM VDD and VI(SENSE) VIT+ VIT+ Threshold Voltages VITVres t RESET Output td td Output Undefined t Copyright (c) 2003-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLC7701-EP TLC7705-EP TLC7733-EP 3 TLC7701-EP, TLC7705-EP, TLC7733-EP SGLS013E - MARCH 2003 - REVISED NOVEMBER 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VDD Supply voltage VALUE UNIT 7 V (2) Input voltage range, CONTROL, RESIN, SENSE (2) -0.3 to 7 V IOL Maximum low output current 10 mA IOH Maximum high output current 10 mA IIK Input clamp current, (VI < 0 or VI > VDD) 10 mA IOK Output clamp current, (VO < 0 or VO > VDD) 10 mA TA Operating free-air temperature range Tstg Storage temperature range (1) (2) TL77xxQ -40 to 125 TL77xxM -55 to 125 C C -65 to 150 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. THERMAL INFORMATION TLC77xx-EP THERMAL METRIC (1) TLC77xx-EP D PW 8 PINS 8 PINS JA Junction-to-ambient thermal resistance 97.1 168 JC Junction-to-case thermal resistance 39.4 38.9 JB Junction-to-board thermal resistance - 96.6 JT Junction-to-top characterization parameter - 1.5 JB Junction-to-board characterization parameter - 94.7 (1) UNITS C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS (1) over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage 2 6 V VI Input voltage 0 VDD V (2) VIH High-level input voltage at RESIN and CONTROL VIL Low-level input voltage at RESIN and CONTROL IOH High-level output current, VDD 2.7 V IOL Low-level output current, VDD 2.7 V t/V Input transition rise and fall rate at RESIN and CONTROL TA Operating free-air temperature range (1) (2) 4 0.7xVDD V 0.2xVDD -2 V mA 2 mA 100 ns/V Q temperature range -40 125 M temperature range -55 125 C Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging. To ensure a low supply current, VIL should be kept <0.3 V and VIH > -0.3 V. Submit Documentation Feedback Copyright (c) 2003-2011, Texas Instruments Incorporated Product Folder Link(s): TLC7701-EP TLC7705-EP TLC7733-EP TLC7701-EP, TLC7705-EP, TLC7733-EP SGLS013E - MARCH 2003 - REVISED NOVEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating conditions (1) (unless otherwise noted) PARAMETER High-level output voltage VOH TEST CONDITIONS IOH = - 20 A IOH = - 20 mA Low-level output voltage VOL IOH = - 20 A IOH = - 20 mA Negative-going input threshold voltage, SENSE (3) VIT- 1.8 2.5 2.5 VDD = 4.5 V 4.3 4.3 VDD = 4.5 V 3.7 Power-up reset voltage (4) II Input current V 3.7 0.2 VDD = 2.7 V 0.2 0.2 VDD = 4.5 V 0.2 0.2 0.5 0.5 VDD = 4.5 V 1.04 VDD = 2 V to 6 V 1.1 1.16 4.43 4.5 4.63 2.855 2.93 3.03 V V 2.8 2.93 3.03 30 VDD = 2 V to 6 V 70 mV 70 70 IOL = 20 A 1 1 RESIN VI = 0 V to VDD 2 2 CONTROL VI = VDD 7 15 7 15 SENSE VI = 5 V 5 10 5 10 A SENSE, TLC7701 only VI = 5 V Supply current IDD(d) Supply current during td VDD = 5 V, VCT = 0 , RESIN = VDD, SENSE = VDD CONTROL = 0 V, Outputs open CI Input capacitance, SENSE VI = 0 V to VDD (1) (2) (3) (4) UNIT MAX 0.2 RESIN = VDD, SENSE = VDD VITmax + 0.2 V CONTROL = 0 V, Outputs open IDD TYP (2) VDD = 2 V TLC7733 Vres MIN 1.8 TLC7733 TLC7705 TA = -55C to 125C MAX VDD = 2.7 V TLC7701 Hysteresis voltage, SENSE Vhys TYP (2) VDD = 2 V TLC7701 TLC7705 TA = -40C to 125C MIN V 2 9 16 9 18 A 120 150 120 150 A 50 50 pF All characteristics are measured with CT = 0.1 F. Typical values apply at TA = 25C. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 F) should be connected near the supply terminals. The lowest supply voltage at which RESET becomes active. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. Rise time of VDD 15 ms/V. Copyright (c) 2003-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLC7701-EP TLC7705-EP TLC7733-EP 5 TLC7701-EP, TLC7705-EP, TLC7733-EP SGLS013E - MARCH 2003 - REVISED NOVEMBER 2011 www.ti.com SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) MEASURED PARAMETER td Delay time tPLH Propagation delay time, low-to-high level output tPLH Propagation delay time, high-to-low level output tPLH Propagation delay time, low-to-high level output tPLH Propagation delay time, high-to-low level output tPLH Propagation delay time, low-to-high level output tPLH Propagation delay time, high-to-low level output tPLH Propagation delay time, low-to-high level output tPLH Propagation delay time, high-to-low level output tPLH Propagation delay time, low-to-high level output tPLH Propagation delay time, high-to-low level output Low-level minimum pulse duration to switch RESET and RESET tr Rise time tf Fall time (1) 6 FROM (INPUT) TO (OUTPUT) TA = -40C to 125C TEST CONDITIONS RESIN = 0.7 x VDD, CONTROL = 0.2 x VDD,CT = 100 nF, TA = Full range, See timing diagram MIN TYP TA = -55C to 125C MAX MIN TYP MAX UNIT ms 1.1 2.1 4.2 2.1 20 20 5 5 5 5 20 20 20 20 60 60 65 65 20 20 58 58 58 58 RESET VIH = VIT+max + 0.2 V, VIL = VIT-min - 0.2 V, RESIN = 0.7 x VDD,CONTROL = 0.2 x VDD, CT = NC (1) SENSE s RESET s RESET VIH = 0.7 x VDD, VIL = 0.2 x VDD,SENSE = VIT+max + 0.2 V, CONTROL = 0.2 x VDD, CT = NC (1) RESIN ns RESET CONTR OL RESET s VIH = 0.7 x VDD, VIL = 0.2 x VDD,SENSE = VIT+max + 0.2 V, RESIN = 0.7 x VDD, CT = NC (1) ns ns SENSE VIH = VIT+max + 0.2 V, VIL = VIT-min - 0.2 V 3 4 RESIN VIL = 0.2 x VDD, VIH = 0.7 x VDD 1 1 RESET and RESET s 10% to 90% 8 8 90% to 10% 4 4 ns/V NC = No capacitor, and includes up to 100-pF probe and jig capacitance. Submit Documentation Feedback Copyright (c) 2003-2011, Texas Instruments Incorporated Product Folder Link(s): TLC7701-EP TLC7705-EP TLC7733-EP TLC7701-EP, TLC7705-EP, TLC7733-EP SGLS013E - MARCH 2003 - REVISED NOVEMBER 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION 5V DUT RL (see Note A) A. For switching characteristics, RL = 2 k B. CL = 50 pF includes jig and probe capacitance CL (see Note B) Figure 2. RESET AND RESET Output Configurations I, Q, and Y suffixed devices tw(L) 0.7 x V DD 0.5 x V DD 0.2 x V DD M suffixed devices tw(L) tw(L) 2.7 V 1.5 V 0.4 V (a) RESIN VIT+max + 200 mV VIT+ VIT- min - 200 mV VIT(b) SENSE Figure 3. Input Pulse Definition Waveforms Copyright (c) 2003-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLC7701-EP TLC7705-EP TLC7733-EP 7 TLC7701-EP, TLC7705-EP, TLC7733-EP SGLS013E - MARCH 2003 - REVISED NOVEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE 10 9 1.005 8 1.004 I DD - Suppl y Current - A Normalized Input Threshold Voltage - VIT- (TA )/V IT- (25 C) NORMALIZED INPUT THRESHOLD VOLTAGE vs TEMPERATURE 1.003 1.002 1.001 1 7 6 5 4 3 RESIN = V DD = -1 V to 6.5 V SENSE = GND CONTROL = GND CT = Open = 100 pF TA = 25C 2 1 0.999 0 0.998 0.997 -40 -1 -0.5 -20 0 20 40 60 80 100 0.5 1.5 2.5 3.5 4.5 5.5 6.5 VDD - Suppl y Voltage - V 120 TA - Temperature - C Figure 4. Figure 5. HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 5 6 4 0C 3.5 -55 C 125C 3 2.5 85C 2 25C 1.5 -40 C 1 0.5 0 -0.5 VDD = 4.5 V RESIN = 4.5 V SENSE = 0.5 V CONTROL = 0 V CT = Open = 100 pF -1 5 0 -5 -10 -15 -20 -25 -30 -35 -40 IOH - High-Le vel Output Current - mA VOL - Lo w-Level Output Voltage - V VOH - High-Le vel Output Voltage - V 4.5 5 4 VDD = 4.5 V RESIN = 4.5 V SENSE = 5 V CONTROL = 0 V CT = Open = 100 pF 125C 85C 25C 0C 3 2 -40 C 1 -55 C 0 -1 -5 0 5 Figure 6. 8 Submit Documentation Feedback 10 15 20 25 30 IOL - Lo w-Level Output Current - mA Figure 7. Copyright (c) 2003-2011, Texas Instruments Incorporated Product Folder Link(s): TLC7701-EP TLC7705-EP TLC7733-EP TLC7701-EP, TLC7705-EP, TLC7733-EP SGLS013E - MARCH 2003 - REVISED NOVEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) INPUT CURRENT vs INPUT VOLTAGE AT SENSE MINIMUM PULSE DURATION AT SENSE vs SENSE THRESHOLD OVERDRIVE 7 6 VDD = 4.5 V CT = Open = 100 pF t w - Minim um Pulse Duration at SENSE - s 8 125C I I - Input Current - A 4 -55 C 2 0 -2 125C -4 -55 C -6 -8 -10 -1 VDD = 2 V Control = 0.4 V RESIN = 1.4 V CT = Open = 100 pF 6 5 4 3 2 1 0 0 1 2 3 4 VI - Input Voltage at SENSE - V 5 6 0 50 100 150 Figure 8. Copyright (c) 2003-2011, Texas Instruments Incorporated 200 250 300 350 400 Sense Threshold Overdrive - mV Figure 9. Submit Documentation Feedback Product Folder Link(s): TLC7701-EP TLC7705-EP TLC7733-EP 9 TLC7701-EP, TLC7705-EP, TLC7733-EP SGLS013E - MARCH 2003 - REVISED NOVEMBER 2011 www.ti.com APPLICATION INFORMATION VDD 0.1 F 0.1 F 100 k VDD VDD TLC77xx RESIN RESET SENSE RESET CT RESET TMS70C20 NC CONTROL RESET GND GND Figure 10. Reset Controller in a Microcomputer System VDD 0.1 F VDD TLC77xx RESIN 0.1 F 0.1 F SENSE RESET CONTROL VDD CT RESET CS RESET GND CSH1 32K 8 CMOS RAM TMS370 16 ADD0 - 15 A0 - A15 8 DATA0 - 7 D0 - D7 R/W R/W GND GND Figure 11. Data Retention During Power Down Using Static CMOS RAMs 10 Submit Documentation Feedback Copyright (c) 2003-2011, Texas Instruments Incorporated Product Folder Link(s): TLC7701-EP TLC7705-EP TLC7733-EP PACKAGE OPTION ADDENDUM www.ti.com 5-May-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TLC7701MDREP ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 7701ME TLC7701MPWREP ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 7701ME TLC7701MPWREPG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 7701ME TLC7701QPWREP ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7701QE TLC7705QPWREP ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7705QE TLC7733MPWREP ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 7733ME TLC7733MPWTEP PREVIEW TSSOP PW 8 TBD Call TI Call TI -55 to 125 TLC7733QPWREP ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7733QE V62/04604-01XE ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7701QE V62/04604-02XE ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7705QE V62/04604-03XE ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7733QE V62/04604-04XE ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 7701ME V62/04604-04YE ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 7701ME V62/04604-06XE ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 7733ME (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 5-May-2015 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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OTHER QUALIFIED VERSIONS OF TLC7701-EP, TLC7705-EP, TLC7733-EP : * Catalog: TLC7701, TLC7705, TLC7733 * Automotive: TLC7701-Q1, TLC7705-Q1, TLC7733-Q1 * Military: TLC7705M, TLC7733M NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 5-May-2015 * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects * Military - QML certified for Military and Defense Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 30-Apr-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLC7701MDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC7701MPWREP TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC7701QPWREP TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC7705QPWREP TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC7733MPWREP TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC7733QPWREP TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Apr-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC7701MDREP SOIC D 8 2500 367.0 367.0 35.0 TLC7701MPWREP TSSOP PW 8 2000 367.0 367.0 35.0 TLC7701QPWREP TSSOP PW 8 2000 367.0 367.0 35.0 TLC7705QPWREP TSSOP PW 8 2000 367.0 367.0 35.0 TLC7733MPWREP TSSOP PW 8 2000 367.0 367.0 35.0 TLC7733QPWREP TSSOP PW 8 2000 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP 6.2 SEATING PLANE PIN 1 ID AREA A 0.1 C 6X 0.65 8 1 3.1 2.9 NOTE 3 2X 1.95 4 5 B 4.5 4.3 NOTE 4 SEE DETAIL A 8X 0.30 0.19 0.1 C A 1.2 MAX B (0.15) TYP 0.25 GAGE PLANE 0 -8 0.15 0.05 0.75 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM 1 8 (R0.05) TYP SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) TYP 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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