1
2
3
4
8
7
6
5
CONTROL
RESIN
CT
GND
VDD
SENSE
RESET
RESET
D OR PW PACKAGE
(TOP VIEW)
TLC7701-EP, TLC7705-EP, TLC7733-EP
www.ti.com
SGLS013E –MARCH 2003–REVISED NOVEMBER 2011
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
Check for Samples: TLC7701-EP,TLC7705-EP,TLC7733-EP
1FEATURES SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•Power-On Reset Generator
•Controlled Baseline
•Automatic Reset Generation After Voltage
Drop •One Assembly/Test Site
•Precision Voltage Sensor •One Fabrication Site
•Temperature-Compensated Voltage Reference •Available in Extended (–40°C/125°C
and –55°C/125°C), Temperature Ranges(1)
•Programmable Delay Time by External
Capacitor •Extended Product Life Cycle
•Supply Voltage Range . . . 2 V to 6 V •Extended Product-Change Notification
•Defined RESET Output from VDD ≥1 V •Product Traceability
•Power-Down Control Support for Static RAM
With Battery Backup
•Maximum Supply Current of 16 mA
•Power Saving Totem-Pole Outputs (1) Additional temperature ranges available - contact factory
DESCRIPTION
The TLC77xx family of micropower supply voltage supervisors provide reset control, primarily in microcomputer
and microprocessor systems.
During power-on, RESET is asserted when VDD reaches 1 V. After minimum VDD (≥2 V) is established, the
circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (VI(SENSE)) remains
below the threshold voltage. An internal timer delays return of the output to the inactive state to ensure proper
system reset. The delay time (td) is determined by an external capacitor:
td= 2.1 ×104×CT(1)
Where
CTis in farads
tdis in seconds
Except for the TLC7701, which can be customized with two external resistors, each supervisor has a fixed sense
threshold voltage set by an internal voltage divider. When SENSE voltage drops below the threshold voltage, the
outputs become active and stay in that state until SENSE voltage returns above threshold voltage and the delay
time (td) has expired.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright ©2003–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
6
1
3
2
7
SENSE
≥1
≥1
≥1
RESET
5
COMP
S
VIT
S<VIT
Z1
Z2
Z3
RESIN
CT
CONTROL RESET
3
2
1
1
CX
×
TLC7701-EP, TLC7705-EP, TLC7733-EP
SGLS013E –MARCH 2003–REVISED NOVEMBER 2011
www.ti.com
In addition to the power-on reset and undervoltage-supervisor function, the TLC77xx adds power-down control
support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The voltage monitor
contains additional logic intended for control of static memories with battery backup during power failure. By
driving the chip select (CS) of the memory circuit with the RESET output of the TLC77xx and with the CONTROL
driven by the memory bank select signal (CSH1) of the microprocessor (see Figure 11), the memory circuit is
automatically disabled during a power loss. (In this application the TLC77xx power has to be supplied by the
battery.)
ORDERING INFORMATION
ORDERABLE PART TOP-SIDE
TAPACKAGE(1) VID NUMBER
NUMBER MARKING
TLC7701QPWREP 7701QE V62/04604 - 01XE
-40°C to 125°C TSSOP - PW Tape and reel TLC7705QPWREP 7705QE V62/04604 - 02XE
TLC7733QPWREP 7733QE V62/04604 - 03XE
TLC7701MPWREP 7701ME V62/04604 - 04XE
TSSOP - PW Tape and reel
-55°C to 125°C TLC7733MPWREP 7733ME V62/04604 - 06XE
SOIC - D Tape and reel TLC7701MDREP 7701ME V62/04604 - 04YE
(1) The PW package is only available left-end taped and reeled (indicated by the R suffix on the device type; e.g., TLC7701QPWREP).
Table 1. FUNCTION TABLE
CONTROL RESIN VI(SENSE) >VIT+ RESET RESET
L L False H L
L L True H L
L H False H L
L H True L(1) H(1)
H L False H L
H L True H L
H H False H L
H H True H H(1)
(1) RESET and RESET states shown are valid for t >td.
(1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Figure 1. Logic Symbol
2Submit Documentation Feedback Copyright ©2003–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC7701-EP TLC7705-EP TLC7733-EP
1.1 V
R2‡
R1(2)
RESET(1)
RESET(1)
VDD
GND
8
6
5
4
RESIN
CONTROL
SENSE
CT
3
1
2
7
1 MΩ
50 µA
RESET
Output
Output
Undefined
VDD and VI(SENSE)
td
Threshold Voltages
Vres
VIT-
VIT+
td
t
t
VIT+
TLC7701-EP, TLC7705-EP, TLC7733-EP
www.ti.com
SGLS013E –MARCH 2003–REVISED NOVEMBER 2011
FUNCTIONAL BLOCK DIAGRAM
(1) Outputs are totem-pole configuration. External pullup or pulldown resistors are not required.
(2) Nominal values:
R1 (Typ) R2 (Typ)
TLC7701 0 ∞
TLC7705 910 kΩ290 kΩ
TLC7733 750 kΩ450 kΩ
TIMING DIAGRAM
Copyright ©2003–2011, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TLC7701-EP TLC7705-EP TLC7733-EP
TLC7701-EP, TLC7705-EP, TLC7733-EP
SGLS013E –MARCH 2003–REVISED NOVEMBER 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE UNIT
VDD Supply voltage(2) 7 V
Input voltage range, CONTROL, RESIN, SENSE (2) -0.3 to 7 V
IOL Maximum low output current 10 mA
IOH Maximum high output current 10 mA
IIK Input clamp current, (VI<0 or VI>VDD)±10 mA
IOK Output clamp current, (VO<0 or VO>VDD)±10 mA
TL77xxQ -40 to 125
TAOperating free-air temperature range °C
TL77xxM -55 to 125
Tstg Storage temperature range -65 to 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions"is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
THERMAL INFORMATION TLC77xx-EP TLC77xx-EP
THERMAL METRIC(1) D PW UNITS
8 PINS 8 PINS
θJA Junction-to-ambient thermal resistance 97.1 168
θJC Junction-to-case thermal resistance 39.4 38.9
θJB Junction-to-board thermal resistance - 96.6 °C/W
ψJT Junction-to-top characterization parameter - 1.5
ψJB Junction-to-board characterization parameter - 94.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS(1)
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
VDD Supply voltage 2 6 V
VIInput voltage 0 VDD V
VIH High-level input voltage at RESIN and CONTROL(2) 0.7×VDD V
VIL Low-level input voltage at RESIN and CONTROL 0.2×VDD V
IOH High-level output current, VDD ≥2.7 V -2 mA
IOL Low-level output current, VDD ≥2.7 V 2 mA
Δt/ΔV Input transition rise and fall rate at RESIN and CONTROL 100 ns/V
Q temperature range -40 125
TAOperating free-air temperature range °C
M temperature range -55 125
(1) Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
(2) To ensure a low supply current, VIL should be kept <0.3 V and VIH >-0.3 V.
4Submit Documentation Feedback Copyright ©2003–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC7701-EP TLC7705-EP TLC7733-EP
TLC7701-EP, TLC7705-EP, TLC7733-EP
www.ti.com
SGLS013E –MARCH 2003–REVISED NOVEMBER 2011
ELECTRICAL CHARACTERISTICS
over recommended operating conditions(1) (unless otherwise noted) TA= -40°C to 125°C TA= -55°C to 125°C
PARAMETER TEST CONDITIONS UNIT
MIN TYP(2) MAX MIN TYP(2) MAX
VDD = 2 V 1.8 1.8
IOH = - 20 μA VDD = 2.7 V 2.5 2.5
High-level output
VOH V
voltage VDD = 4.5 V 4.3 4.3
IOH = - 20 mA VDD = 4.5 V 3.7 3.7
VDD = 2 V 0.2 0.2
IOH = - 20 μA VDD = 2.7 V 0.2 0.2
Low-level output
VOL V
voltage VDD = 4.5 V 0.2 0.2
IOH = - 20 mA VDD = 4.5 V 0.5 0.5
TLC7701 1.04 1.1 1.16
Negative-going input
VIT- threshold voltage, TLC7705 VDD = 2 V to 6 V 4.43 4.5 4.63 V
SENSE(3) TLC7733 2.855 2.93 3.03 2.8 2.93 3.03
TLC7701 30
Hysteresis voltage,
Vhys TLC7705 VDD = 2 V to 6 V 70 mV
SENSE TLC7733 70 70
Vres Power-up reset voltage(4) IOL = 20 μA 1 1 V
RESIN VI= 0 V to VDD 2 2
CONTROL VI= VDD 7 15 7 15
IIInput current μA
SENSE VI= 5 V 5 10 5 10
SENSE, TLC7701 VI= 5 V 2
only
RESIN = VDD,
SENSE = VDD ≥VITmax
IDD Supply current + 0.2 V 9 16 9 18 μA
CONTROL = 0 V,
Outputs open
VDD = 5 V, VCT = 0 ,
RESIN = VDD,
IDD(d) Supply current during tdSENSE = VDD 120 150 120 150 μA
CONTROL = 0 V,
Outputs open
CIInput capacitance, SENSE VI= 0 V to VDD 50 50 pF
(1) All characteristics are measured with CT= 0.1 μF.
(2) Typical values apply at TA= 25°C.
(3) To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 μF) should be connected near the supply terminals.
(4) The lowest supply voltage at which RESET becomes active. The symbol Vres is not currently listed within EIA or JEDEC standards for
semiconductor symbology. Rise time of VDD ≥15 ms/V.
Copyright ©2003–2011, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TLC7701-EP TLC7705-EP TLC7733-EP
TLC7701-EP, TLC7705-EP, TLC7733-EP
SGLS013E –MARCH 2003–REVISED NOVEMBER 2011
www.ti.com
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
MEASURED TA= -40°C to 125°C TA= -55°C to 125°C
PARAMETER TEST CONDITIONS UNIT
FROM TO MIN TYP MAX MIN TYP MAX
(INPUT) (OUTPUT)
RESIN = 0.7 ×VDD, ms
CONTROL = 0.2 ×
tdDelay time VDD,CT = 100 nF, 1.1 2.1 4.2 2.1
TA= Full range, See
timing diagram
Propagation delay
tPLH time, low-to-high level 20 20
output RESET
Propagation delay VIH = VIT+max + 0.2 V,
tPLH time, high-to-low level 5 5
VIL = VIT-min - 0.2 V,
output SENSE RESIN = 0.7 × μs
Propagation delay VDD,CONTROL = 0.2 ×VDD,
tPLH time, low-to-high level 5 5
CT= NC(1)
output RESET
Propagation delay
tPLH time, high-to-low level 20 20
output
Propagation delay μs
tPLH time, low-to-high level 20 20
output RESET
Propagation delay VIH = 0.7 ×VDD,
tPLH time, high-to-low level 60 60
VIL = 0.2 ×VDD,SENSE =
output RESIN VIT+max + 0.2 V, ns
Propagation delay CONTROL = 0.2 ×VDD,
tPLH time, low-to-high level 65 65
CT= NC(1)
output RESET
Propagation delay μs
tPLH time, high-to-low level 20 20
output
Propagation delay VIH = 0.7 ×VDD, ns
tPLH time, low-to-high level VIL = 0.2 ×VDD,SENSE = 58 58
output VIT+max + 0.2 V,
CONTR RESET RESIN = 0.7 ×VDD,
OL
Propagation delay ns
CT= NC(1)
tPLH time, high-to-low level 58 58
output
VIH = VIT+max + 0.2 V,
SENSE 3 4
Low-level minimum VIL = VIT-min - 0.2 V
pulse duration to switch μs
VIL = 0.2 ×VDD,
RESET and RESET RESIN 1 1
VIH = 0.7 ×VDD
trRise time RESET 10% to 90% 8 8
and ns/V
90% to 10%
tfFall time 4 4
RESET
(1) NC = No capacitor, and includes up to 100-pF probe and jig capacitance.
6Submit Documentation Feedback Copyright ©2003–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC7701-EP TLC7705-EP TLC7733-EP
DUT
RL
(see Note A) CL
(see Note B)
5 V
VIT-
tw(L) tw(L)
VIT+max + 200 mV2.7 V
VIT+
VIT- min - 200 mV
(a) RESIN (b) SENSE
0.4 V
1.5 V
tw(L)
0.7 ×VDD
0.2 ×VDD
0.5 ×VDD
M suffixed devices
I, Q, and Y suffixed devices
TLC7701-EP, TLC7705-EP, TLC7733-EP
www.ti.com
SGLS013E –MARCH 2003–REVISED NOVEMBER 2011
PARAMETER MEASUREMENT INFORMATION
A. For switching characteristics, RL= 2 kΩ
B. CL= 50 pF includes jig and probe capacitance
Figure 2. RESET AND RESET Output Configurations
Figure 3. Input Pulse Definition Waveforms
Copyright ©2003–2011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TLC7701-EP TLC7705-EP TLC7733-EP
10
-0.5
9
8
7
6
5
4
3
2
0.5 1.5 2.5 3.5 4.5 5.5 6.5
VDD - Suppl y Voltage - V
1
0
-1
RESIN = VDD = -1 V to 6.5 V
SENSE = GND
CONTROL = GND
CT = Open = 100 pF
TA= 25°C
- Suppl y Current - Aµ
IDD
Normalized Input Threshold V
oltage -
1.005
-40
1.004
1.003
1.002
1.001
1
0.999
0.998
0.997
-20 0 20 40 60 80 100 120
TA- Temperature - °C
VIT- (T
A)/VIT- (25 C)
°
-5
6
5
4
3
2
0 5 10 15 20 25 30
IOL - Lo w-Level Output Current - mA
1
0
-1
VDD = 4.5 V
RESIN = 4.5 V
SENSE = 5 V
CONTROL = 0 V
CT = Open = 100 pF
- Lo w-Level Output V
oltage - V
V
OL
-40 °C
-55 °C
125°C
85°C
25°C
0°C
TLC7701-EP, TLC7705-EP, TLC7733-EP
SGLS013E –MARCH 2003–REVISED NOVEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS
NORMALIZED INPUT THRESHOLD VOLTAGE SUPPLY CURRENT
vs vs
TEMPERATURE SUPPLY VOLTAGE
Figure 4. Figure 5.
HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
vs vs
HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
Figure 6. Figure 7.
8Submit Documentation Feedback Copyright ©2003–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC7701-EP TLC7705-EP TLC7733-EP
0
7
6
5
4
3
50 100 150 200
Sense Threshold Overdrive - mV
2
1
0
- Minim um Pulse Duration at SENSE - sµ
tw
250 300 350 400
VDD = 2 V
Control = 0.4 V
RESIN = 1.4 V
CT = Open = 100 pF
-1
4
2
0
-2
-4
0 1 2 3 4 5 6
VI- Input Voltage at SENSE - V
-6
-8
-10
-55 °C
125°C
VDD = 4.5 V
CT = Open = 100 pF
8
6
- Input Current - Aµ
II
-55 °C
125°C
TLC7701-EP, TLC7705-EP, TLC7733-EP
www.ti.com
SGLS013E –MARCH 2003–REVISED NOVEMBER 2011
TYPICAL CHARACTERISTICS (continued)
INPUT CURRENT MINIMUM PULSE DURATION AT SENSE
vs vs
INPUT VOLTAGE AT SENSE SENSE THRESHOLD OVERDRIVE
Figure 8. Figure 9.
Copyright ©2003–2011, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TLC7701-EP TLC7705-EP TLC7733-EP
TLC77xx
GND
0.1 µF
RESETRESIN
RESETSENSE
CONTROLCT
GND
RESET
VDD
TMS70C20
NC
100 kΩ
RESET
VDD
VDD
0.1 µF
VDD
GND
RESET
SENSE
CONTROL
CT
RESET
GND
CS
VDD
TLC77xx
RESET
CSH1
ADD0 - 15
GND
R / W
16
8
A0 - A15
D0 - D7DATA0 - 7
R / W
32K 8
CMOS RAM
TMS370
VDD
RESIN
0.1 µF
0.1 µF
0.1 µF
TLC7701-EP, TLC7705-EP, TLC7733-EP
SGLS013E –MARCH 2003–REVISED NOVEMBER 2011
www.ti.com
APPLICATION INFORMATION
Figure 10. Reset Controller in a Microcomputer System
Figure 11. Data Retention During Power Down Using Static CMOS RAMs
10 Submit Documentation Feedback Copyright ©2003–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC7701-EP TLC7705-EP TLC7733-EP
PACKAGE OPTION ADDENDUM
www.ti.com 5-May-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLC7701MDREP ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 7701ME
TLC7701MPWREP ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 7701ME
TLC7701MPWREPG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 7701ME
TLC7701QPWREP ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7701QE
TLC7705QPWREP ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7705QE
TLC7733MPWREP ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 7733ME
TLC7733MPWTEP PREVIEW TSSOP PW 8 TBD Call TI Call TI -55 to 125
TLC7733QPWREP ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7733QE
V62/04604-01XE ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7701QE
V62/04604-02XE ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7705QE
V62/04604-03XE ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7733QE
V62/04604-04XE ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 7701ME
V62/04604-04YE ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 7701ME
V62/04604-06XE ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 7733ME
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 5-May-2015
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC7701-EP, TLC7705-EP, TLC7733-EP :
•Catalog: TLC7701, TLC7705, TLC7733
•Automotive: TLC7701-Q1, TLC7705-Q1, TLC7733-Q1
•Military: TLC7705M, TLC7733M
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 5-May-2015
Addendum-Page 3
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC7701MDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC7701MPWREP TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLC7701QPWREP TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLC7705QPWREP TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLC7733MPWREP TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLC7733QPWREP TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Apr-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC7701MDREP SOIC D 8 2500 367.0 367.0 35.0
TLC7701MPWREP TSSOP PW 8 2000 367.0 367.0 35.0
TLC7701QPWREP TSSOP PW 8 2000 367.0 367.0 35.0
TLC7705QPWREP TSSOP PW 8 2000 367.0 367.0 35.0
TLC7733MPWREP TSSOP PW 8 2000 367.0 367.0 35.0
TLC7733QPWREP TSSOP PW 8 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Apr-2016
Pack Materials-Page 2
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PACKAGE OUTLINE
C
TYP
6.6
6.2
1.2 MAX
6X 0.65
8X 0.30
0.19
2X
1.95
0.15
0.05
(0.15) TYP
0 - 8
0.25
GAGE PLANE
0.75
0.50
A
NOTE 3
3.1
2.9
B
NOTE 4
4.5
4.3
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
18
0.1 C A B
5
4
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
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EXAMPLE BOARD LAYOUT
(5.8)
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
8X (1.5)
8X (0.45)
6X (0.65)
(R )
TYP
0.05
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:10X
1
45
8
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
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EXAMPLE STENCIL DESIGN
(5.8)
6X (0.65)
8X (0.45)
8X (1.5)
(R ) TYP0.05
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
45
8
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
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