BD82QM67SLJ4M 914325 - INTEL

Document Number: 324645-006

Intel® 6 Series Chipset and

Intel® C200 Series Chipset

Datasheet

May 2011

2Datasheet

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Datasheet 3

Contents

1Introduction............................................................................................................ 41

1.1 About This Manual ............................................................................................. 41

1.2 Overview ......................................................................................................... 44

1.2.1 Capability Overview............................................................................. 45

1.3 Intel® 6 Series Chipset and Intel® C200 Series Chipset SKU Definition ..................... 51

2 Signal Description ................................................................................................... 55

2.1 Direct Media Interface (DMI) to Host Controller ..................................................... 57

2.2 PCI Express* .................................................................................................... 57

2.3 PCI Interface .................................................................................................... 58

2.4 Serial ATA Interface........................................................................................... 60

2.5 LPC Interface.................................................................................................... 63

2.6 Interrupt Interface ............................................................................................ 63

2.7 USB Interface ................................................................................................... 64

2.8 Power Management Interface.............................................................................. 65

2.9 Processor Interface............................................................................................ 69

2.10 SMBus Interface................................................................................................ 69

2.11 System Management Interface............................................................................ 69

2.12 Real Time Clock Interface ................................................................................... 70

2.13 Miscellaneous Signals ........................................................................................ 70

2.14 Intel® High Definition Audio Link ......................................................................... 72

2.15 Controller Link .................................................................................................. 73

2.16 Serial Peripheral Interface (SPI) .......................................................................... 73

2.17 Thermal Signals ................................................................................................ 73

2.18 Testability Signals ............................................................................................. 74

2.19 Clock Signals .................................................................................................... 74

2.20 LVDS Signals .................................................................................................... 77

2.21 Analog Display /VGA DAC Signals ........................................................................ 78

2.22 Intel® Flexible Display Interface (Intel® FDI) ........................................................ 78

2.23 Digital Display Signals........................................................................................ 79

2.24 General Purpose I/O Signals ............................................................................... 82

2.25 Manageability Signals ........................................................................................ 86

2.26 Power and Ground Signals.................................................................................. 87

2.27 Pin Straps ........................................................................................................ 89

2.28 External RTC Circuitry........................................................................................ 92

3PCH Pin States......................................................................................................... 93

3.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 93

3.2 Output and I/O Signals Planes and States............................................................. 95

3.3 Power Planes for Input Signals .......................................................................... 107

4 PCH and System Clocks ......................................................................................... 113

4.1 Platform Clocking Requirements ........................................................................ 113

4.2 Functional Blocks ............................................................................................ 116

4.3 Clock Configuration Access Overview ................................................................. 117

4.4 Straps Related to Clock Configuration ................................................................ 117

5 Functional Description........................................................................................... 119

5.1 DMI-to-PCI Bridge (D30:F0) ............................................................................. 119

5.1.1 PCI Bus Interface.............................................................................. 119

5.1.2 PCI Bridge As an Initiator................................................................... 120

5.1.2.1 Memory Reads and Writes .................................................. 120

5.1.2.2 I/O Reads and Writes ......................................................... 120

5.1.2.3 Configuration Reads and Writes ........................................... 120

5.1.2.4 Locked Cycles ................................................................... 120

5.1.2.5 Target / Master Aborts ....................................................... 120

5.1.2.6 Secondary Master Latency Timer ......................................... 120

5.1.2.7 Dual Address Cycle (DAC)................................................... 121

5.1.2.8 Memory and I/O Decode to PCI ........................................... 121

5.1.3 Parity Error Detection and Generation.................................................. 121

5.1.4 PCIRST# ......................................................................................... 122

5.1.5 Peer Cycles ...................................................................................... 122

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5.1.6 PCI-to-PCI Bridge Model..................................................................... 122

5.1.7 IDSEL to Device Number Mapping........................................................123

5.1.8 Standard PCI Bus Configuration Mechanism ..........................................123

5.1.9 PCI Legacy Mode............................................................................... 123

5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) ..................................... 124

5.2.1 Interrupt Generation..........................................................................124

5.2.2 Power Management ........................................................................... 125

5.2.2.1 S3/S4/S5 Support.............................................................. 125

5.2.2.2 Resuming from Suspended State.......................................... 125

5.2.2.3 Device Initiated PM_PME Message ........................................ 125

5.2.2.4 SMI/SCI Generation ........................................................... 126

5.2.3 SERR# Generation............................................................................. 126

5.2.4 Hot-Plug .......................................................................................... 126

5.2.4.1 Presence Detection............................................................. 126

5.2.4.2 Message Generation ........................................................... 127

5.2.4.3 Attention Button Detection ..................................................127

5.2.4.4 SMI/SCI Generation ........................................................... 127

5.3 Gigabit Ethernet Controller (B0:D25:F0) ............................................................. 128

5.3.1 GbE PCI Express* Bus Interface ..........................................................130

5.3.1.1 Transaction Layer...............................................................130

5.3.1.2 Data Alignment..................................................................130

5.3.1.3 Configuration Request Retry Status ...................................... 130

5.3.2 Error Events and Error Reporting ......................................................... 131

5.3.2.1 Data Parity Error................................................................ 131

5.3.2.2 Completion with Unsuccessful Completion Status....................131

5.3.3 Ethernet Interface ............................................................................. 131

5.3.3.1 82579 LAN PHY Interface .................................................... 131

5.3.4 PCI Power Management...................................................................... 132

5.3.4.1 Wake Up........................................................................... 132

5.3.5 Configurable LEDs .............................................................................134

5.3.6 Function Level Reset Support (FLR) ..................................................... 135

5.3.6.1 FLR Steps ......................................................................... 135

5.4 LPC Bridge (with System and Management Functions) (D31:F0).............................136

5.4.1 LPC Interface.................................................................................... 136

5.4.1.1 LPC Cycle Types................................................................. 137

5.4.1.2 Start Field Definition........................................................... 137

5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR) ...............................138

5.4.1.4 Size ................................................................................. 138

5.4.1.5 SYNC................................................................................ 138

5.4.1.6 SYNC Time-Out..................................................................139

5.4.1.7 SYNC Error Indication ......................................................... 139

5.4.1.8 LFRAME# Usage................................................................. 139

5.4.1.9 I/O Cycles......................................................................... 139

5.4.1.10 Bus Master Cycles ..............................................................140

5.4.1.11 LPC Power Management ...................................................... 140

5.4.1.12 Configuration and PCH Implications ...................................... 140

5.5 DMA Operation (D31:F0) .................................................................................. 141

5.5.1 Channel Priority ................................................................................ 141

5.5.1.1 Fixed Priority ..................................................................... 141

5.5.1.2 Rotating Priority.................................................................142

5.5.2 Address Compatibility Mode ................................................................ 142

5.5.3 Summary of DMA Transfer Sizes.......................................................... 142

5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count

by Words .......................................................................... 142

5.5.4 Autoinitialize..................................................................................... 143

5.5.5 Software Commands..........................................................................143

5.6 LPC DMA ........................................................................................................144

5.6.1 Asserting DMA Requests.....................................................................144

5.6.2 Abandoning DMA Requests ................................................................. 145

5.6.3 General Flow of DMA Transfers............................................................ 145

5.6.4 Terminal Count ................................................................................. 145

5.6.5 Verify Mode ...................................................................................... 146

5.6.6 DMA Request Deassertion................................................................... 146

5.6.7 SYNC Field / LDRQ# Rules .................................................................. 147

5.7 8254 Timers (D31:F0) ...................................................................................... 147

5.7.1 Timer Programming ...........................................................................148

5.7.2 Reading from the Interval Timer..........................................................149

Datasheet 5

5.7.2.1 Simple Read ..................................................................... 149

5.7.2.2 Counter Latch Command .................................................... 149

5.7.2.3 Read Back Command ......................................................... 149

5.8 8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 150

5.8.1 Interrupt Handling ............................................................................ 151

5.8.1.1 Generating Interrupts......................................................... 151

5.8.1.2 Acknowledging Interrupts ................................................... 151

5.8.1.3 Hardware/Software Interrupt Sequence ................................ 152

5.8.2 Initialization Command Words (ICWx) ................................................. 152

5.8.2.1 ICW1 ............................................................................... 152

5.8.2.2 ICW2 ............................................................................... 153

5.8.2.3 ICW3 ............................................................................... 153

5.8.2.4 ICW4 ............................................................................... 153

5.8.3 Operation Command Words (OCW) ..................................................... 153

5.8.4 Modes of Operation ........................................................................... 153

5.8.4.1 Fully Nested Mode ............................................................. 153

5.8.4.2 Special Fully-Nested Mode .................................................. 154

5.8.4.3 Automatic Rotation Mode (Equal Priority Devices) .................. 154

5.8.4.4 Specific Rotation Mode (Specific Priority) .............................. 154

5.8.4.5 Poll Mode.......................................................................... 154

5.8.4.6 Cascade Mode ................................................................... 155

5.8.4.7 Edge and Level Triggered Mode ........................................... 155

5.8.4.8 End of Interrupt (EOI) Operations ........................................ 155

5.8.4.9 Normal End of Interrupt ..................................................... 155

5.8.4.10 Automatic End of Interrupt Mode ......................................... 155

5.8.5 Masking Interrupts............................................................................ 156

5.8.5.1 Masking on an Individual Interrupt Request........................... 156

5.8.5.2 Special Mask Mode............................................................. 156

5.8.6 Steering PCI Interrupts...................................................................... 156

5.9 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 157

5.9.1 Interrupt Handling ............................................................................ 157

5.9.2 Interrupt Mapping ............................................................................. 157

5.9.3 PCI / PCI Express* Message-Based Interrupts....................................... 158

5.9.4 IOxAPIC Address Remapping .............................................................. 158

5.9.5 External Interrupt Controller Support................................................... 158

5.10 Serial Interrupt (D31:F0) ................................................................................. 159

5.10.1 Start Frame ..................................................................................... 159

5.10.2 Data Frames .................................................................................... 160

5.10.3 Stop Frame ...................................................................................... 160

5.10.4 Specific Interrupts Not Supported Using SERIRQ ................................... 160

5.10.5 Data Frame Format ........................................................................... 161

5.11 Real Time Clock (D31:F0)................................................................................. 162

5.11.1 Update Cycles .................................................................................. 162

5.11.2 Interrupts ........................................................................................ 163

5.11.3 Lockable RAM Ranges........................................................................ 163

5.11.4 Century Rollover ............................................................................... 163

5.11.5 Clearing Battery-Backed RTC RAM....................................................... 163

5.12 Processor Interface (D31:F0) ............................................................................ 165

5.12.1 Processor Interface Signals and VLW Messages ..................................... 165

5.12.1.1 A20M# (Mask A20) / A20GATE............................................ 165

5.12.1.2 INIT (Initialization) ............................................................ 166

5.12.1.3 FERR# (Numeric Coprocessor Error)..................................... 166

5.12.1.4 NMI (Non-Maskable Interrupt)............................................. 167

5.12.1.5 Processor Power Good (PROCPWRGD) .................................. 167

5.12.2 Dual-Processor Issues ....................................................................... 167

5.12.2.1 Usage Differences.............................................................. 167

5.12.3 Virtual Legacy Wire (VLW) Messages ................................................... 167

5.13 Power Management ......................................................................................... 168

5.13.1 Features .......................................................................................... 168

5.13.2 PCH and System Power States ............................................................ 168

5.13.3 System Power Planes ........................................................................ 170

5.13.4 SMI#/SCI Generation ........................................................................ 171

5.13.4.1 PCI Express* SCI............................................................... 173

5.13.4.2 PCI Express* Hot-Plug........................................................ 173

5.13.5 C-States .......................................................................................... 173

5.13.6 Dynamic PCI Clock Control (Mobile Only) ............................................. 173

5.13.6.1 Conditions for Checking the PCI Clock .................................. 173

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5.13.6.2 Conditions for Maintaining the PCI Clock................................174

5.13.6.3 Conditions for Stopping the PCI Clock ...................................174

5.13.6.4 Conditions for Re-Starting the PCI Clock................................174

5.13.6.5 LPC Devices and CLKRUN#.................................................. 174

5.13.7 Sleep States ..................................................................................... 174

5.13.7.1 Sleep State Overview .........................................................174

5.13.7.2 Initiating Sleep State.......................................................... 175

5.13.7.3 Exiting Sleep States ........................................................... 175

5.13.7.4 PCI Express* WAKE# Signal and PME Event Message..............177

5.13.7.5 Sx-G3-Sx, Handling Power Failures....................................... 178

5.13.7.6 Deep S4/S5.......................................................................179

5.13.8 Event Input Signals and Their Usage....................................................180

5.13.8.1 PWRBTN# (Power Button) ...................................................180

5.13.8.2 RI# (Ring Indicator) ...........................................................181

5.13.8.3 PME# (PCI Power Management Event) ..................................181

5.13.8.4 SYS_RESET# Signal ........................................................... 182

5.13.8.5 THRMTRIP# Signal .............................................................182

5.13.9 ALT Access Mode............................................................................... 183

5.13.9.1 Write Only Registers with Read Paths in ALT Access Mode........ 184

5.13.9.2 PIC Reserved Bits...............................................................186

5.13.9.3 Read Only Registers with Write Paths in ALT Access Mode........ 186

5.13.10 System Power Supplies, Planes, and Signals ......................................... 187

5.13.10.1 Power Plane Control with SLP_S3#,

SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN# ......................... 187

5.13.10.2 SLP_S4# and Suspend-To-RAM Sequencing...........................187

5.13.10.3 PWROK Signal ...................................................................187

5.13.10.4 BATLOW# (Battery Low) (Mobile Only) ................................. 188

5.13.10.5 SLP_LAN# Pin Behavior ...................................................... 188

5.13.10.6 RTCRST# and SRTCRST#.................................................... 188

5.13.11 Clock Generators............................................................................... 188

5.13.12 Legacy Power Management Theory of Operation .................................... 189

5.13.12.1 APM Power Management (Desktop Only) ............................... 189

5.13.12.2 Mobile APM Power Management (Mobile Only)........................189

5.13.13 Reset Behavior..................................................................................189

5.14 System Management (D31:F0) .......................................................................... 192

5.14.1 Theory of Operation...........................................................................192

5.14.1.1 Detecting a System Lockup .................................................192

5.14.1.2 Handling an Intruder .......................................................... 193

5.14.1.3 Detecting Improper Flash Programming ................................193

5.14.1.4 Heartbeat and Event Reporting using SMLink/SMBus...............193

5.14.2 TCO Modes .......................................................................................194

5.14.2.1 TCO Legacy/Compatible Mode..............................................194

5.14.2.2 Advanced TCO Mode........................................................... 195

5.15 General Purpose I/O (D31:F0) ........................................................................... 196

5.15.1 Power Wells...................................................................................... 196

5.15.2 SMI# SCI and NMI Routing................................................................. 196

5.15.3 Triggering ........................................................................................ 196

5.15.4 GPIO Registers Lockdown ................................................................... 196

5.15.5 Serial POST Codes over GPIO..............................................................197

5.15.5.1 Theory of Operation ........................................................... 197

5.15.5.2 Serial Message Format........................................................ 198

5.16 SATA Host Controller (D31:F2, F5)..................................................................... 199

5.16.1 SATA 6 Gb/s Support ......................................................................... 200

5.16.2 SATA Feature Support........................................................................200

5.16.3 Theory of Operation...........................................................................201

5.16.3.1 Standard ATA Emulation .....................................................201

5.16.3.2 48-Bit LBA Operation.......................................................... 201

5.16.4 SATA Swap Bay Support..................................................................... 201

5.16.5 Hot Plug Operation ............................................................................201

5.16.5.1 Low Power Device Presence Detection................................... 201

5.16.6 Function Level Reset Support (FLR) .....................................................202

5.16.6.1 FLR Steps .........................................................................202

5.16.7 Intel® Rapid Storage Technology Configuration ..................................... 202

5.16.7.1 Intel® Rapid Storage Manager RAID Option ROM.................... 203

5.16.8 Intel® Smart Response Technology......................................................203

5.16.9 Power Management Operation............................................................. 203

5.16.9.1 Power State Mappings ........................................................203

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5.16.9.2 Power State Transitions ...................................................... 204

5.16.9.3 SMI Trapping (APM) ........................................................... 205

5.16.10 SATA Device Presence ....................................................................... 205

5.16.11 SATA LED ........................................................................................ 206

5.16.12 AHCI Operation ................................................................................ 206

5.16.13 SGPIO Signals .................................................................................. 206

5.16.13.1 Mechanism ....................................................................... 206

5.16.13.2 Message Format ................................................................ 207

5.16.13.3 LED Message Type............................................................. 208

5.16.13.4 SGPIO Waveform............................................................... 209

5.16.14 External SATA .................................................................................. 210

5.17 High Precision Event Timers.............................................................................. 210

5.17.1 Timer Accuracy................................................................................. 210

5.17.2 Interrupt Mapping ............................................................................. 211

5.17.3 Periodic versus Non-Periodic Modes ..................................................... 212

5.17.4 Enabling the Timers .......................................................................... 212

5.17.5 Interrupt Levels ................................................................................ 213

5.17.6 Handling Interrupts ........................................................................... 213

5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors .......................... 213

5.18 USB EHCI Host Controllers (D29:F0 and D26:F0)................................................. 214

5.18.1 EHC Initialization .............................................................................. 214

5.18.1.1 BIOS Initialization.............................................................. 214

5.18.1.2 Driver Initialization ............................................................ 214

5.18.1.3 EHC Resets....................................................................... 214

5.18.2 Data Structures in Main Memory ......................................................... 214

5.18.3 USB 2.0 Enhanced Host Controller DMA ............................................... 215

5.18.4 Data Encoding and Bit Stuffing ........................................................... 215

5.18.5 Packet Formats................................................................................. 215

5.18.6 USB 2.0 Interrupts and Error Conditions .............................................. 215

5.18.6.1 Aborts on USB 2.0-Initiated Memory Reads ........................... 216

5.18.7 USB 2.0 Power Management............................................................... 216

5.18.7.1 Pause Feature ................................................................... 216

5.18.7.2 Suspend Feature ............................................................... 216

5.18.7.3 ACPI Device States ............................................................ 216

5.18.7.4 ACPI System States ........................................................... 217

5.18.8 USB 2.0 Legacy Keyboard Operation.................................................... 217

5.18.9 USB 2.0 Based Debug Port ................................................................. 217

5.18.9.1 Theory of Operation .......................................................... 218

5.18.10 EHCI Caching ................................................................................... 222

5.18.11 Intel® USB Pre-Fetch Based Pause ...................................................... 222

5.18.12 Function Level Reset Support (FLR) ..................................................... 222

5.18.12.1 FLR Steps ......................................................................... 222

5.18.13 USB Overcurrent Protection................................................................ 223

5.19 Integrated USB 2.0 Rate Matching Hub .............................................................. 224

5.19.1 Overview ......................................................................................... 224

5.19.2 Architecture ..................................................................................... 224

5.20 SMBus Controller (D31:F3) ............................................................................... 225

5.20.1 Host Controller ................................................................................. 225

5.20.1.1 Command Protocols ........................................................... 226

5.20.2 Bus Arbitration ................................................................................. 229

5.20.3 Bus Timing....................................................................................... 230

5.20.3.1 Clock Stretching ................................................................ 230

5.20.3.2 Bus Time Out (The PCH as SMBus Master) ............................ 230

5.20.4 Interrupts / SMI# ............................................................................. 230

5.20.5 SMBALERT# ..................................................................................... 231

5.20.6 SMBus CRC Generation and Checking .................................................. 231

5.20.7 SMBus Slave Interface....................................................................... 232

5.20.7.1 Format of Slave Write Cycle ................................................ 233

5.20.7.2 Format of Read Command .................................................. 234

5.20.7.3 Slave Read of RTC Time Bytes............................................. 236

5.20.7.4 Format of Host Notify Command .......................................... 237

5.21 Thermal Management ...................................................................................... 238

5.21.1 Thermal Sensor ................................................................................ 238

5.21.1.1 Internal Thermal Sensor Operation ...................................... 238

5.21.2 PCH Thermal Throttling...................................................................... 239

5.21.3 Thermal Reporting Over System Management Link 1 Interface (SMLink1). 240

5.21.3.1 Supported Addresses ......................................................... 241

8Datasheet

5.21.3.2 I2C Write Commands to the Intel® ME .................................. 242

5.21.3.3 Block Read Command.........................................................242

5.21.3.4 Read Data Format ..............................................................244

5.21.3.5 Thermal Data Update Rate ..................................................244

5.21.3.6 Temperature Comparator and Alert ......................................244

5.21.3.7 BIOS Set Up......................................................................246

5.21.3.8 SMBus Rules ..................................................................... 246

5.21.3.9 Case for Considerations ...................................................... 247

5.22 Intel® High Definition Audio Overview (D27:F0)................................................... 249

5.22.1 Intel® High Definition Audio Docking (Mobile Only) ................................ 249

5.22.1.1 Dock Sequence..................................................................249

5.22.1.2 Exiting D3/CRST# When Docked ..........................................250

5.22.1.3 Cold Boot/Resume from S3 When Docked.............................. 251

5.22.1.4 Undock Sequence............................................................... 251

5.22.1.5 Normal Undock .................................................................. 251

5.22.1.6 Surprise Undock ................................................................ 252

5.22.1.7 Interaction between Dock/Undock and Power Management

States .............................................................................. 252

5.22.1.8 Relationship between HDA_DOCK_RST# and HDA_RST#......... 252

5.23 Intel® ME and Intel® ME Firmware 7.0 ............................................................... 253

5.23.1 Intel® ME Requirements..................................................................... 254

5.24 Serial Peripheral Interface (SPI) ........................................................................ 255

5.24.1 SPI Supported Feature Overview .........................................................255

5.24.1.1 Non-Descriptor Mode .......................................................... 255

5.24.1.2 Descriptor Mode.................................................................255

5.24.2 Flash Descriptor ................................................................................256

5.24.2.1 Descriptor Master Region .................................................... 258

5.24.3 Flash Access ..................................................................................... 259

5.24.3.1 Direct Access Security ........................................................259

5.24.3.2 Register Access Security ..................................................... 259

5.24.4 Serial Flash Device Compatibility Requirements ..................................... 260

5.24.4.1 PCH SPI-Based BIOS Requirements ...................................... 260

5.24.4.2 Integrated LAN Firmware SPI Flash Requirements .................. 260

5.24.4.3 Intel® Management Engine Firmware SPI Flash Requirements.. 261

5.24.4.4 Hardware Sequencing Requirements.....................................261

5.24.5 Multiple Page Write Usage Model .........................................................262

5.24.5.1 Soft Flash Protection........................................................... 263

5.24.5.2 BIOS Range Write Protection ............................................... 263

5.24.5.3 SMI# Based Global Write Protection .....................................263

5.24.6 Flash Device Configurations ................................................................ 263

5.24.7 SPI Flash Device Recommended Pinout ................................................264

5.24.8 Serial Flash Device Package ................................................................264

5.24.8.1 Common Footprint Usage Model ........................................... 264

5.24.8.2 Serial Flash Device Package Recommendations ......................265

5.24.9 PWM Outputs (Server/Workstation Only) .............................................. 265

5.24.10 TACH Inputs (Server/Workstation Only) ............................................... 265

5.25 Feature Capability Mechanism ........................................................................... 265

5.26 PCH Display Interfaces and Intel® Flexible Display Interconnect.............................266

5.26.1 Analog Display Interface Characteristics ............................................... 266

5.26.1.1 Integrated RAMDAC............................................................ 267

5.26.1.2 DDC (Display Data Channel) ................................................ 267

5.26.2 Digital Display Interfaces.................................................................... 267

5.26.2.1 LVDS (Mobile only)............................................................. 267

5.26.2.2 High Definition Multimedia Interface ..................................... 270

5.26.2.3 Digital Video Interface (DVI)................................................ 271

5.26.2.4 DisplayPort*...................................................................... 271

5.26.2.5 Embedded DisplayPort ........................................................272

5.26.2.6 DisplayPort Aux Channel ..................................................... 272

5.26.2.7 DisplayPort Hot-Plug Detect (HPD) ....................................... 272

5.26.2.8 Integrated Audio over HDMI and DisplayPort ......................... 272

5.26.2.9 Serial Digital Video Out (SDVO) ...........................................272

5.26.3 Mapping of Digital Display Interface Signals ..........................................274

5.26.4 Multiple Display Configurations............................................................ 275

5.26.5 High-bandwidth Digital Content Protection (HDCP) .................................275

5.26.6 Intel® Flexible Display Interconnect..................................................... 276

5.27 Intel® Virtualization Technology ........................................................................ 276

5.27.1 Intel® VT-d Objectives ....................................................................... 276

Datasheet 9

5.27.2 Intel® VT-d Features Supported.......................................................... 276

5.27.3 Support for Function Level Reset (FLR) in PCH ...................................... 277

5.27.4 Virtualization Support for PCH’s IOxAPIC.............................................. 277

5.27.5 Virtualization Support for High Precision Event Timer (HPET) .................. 277

6 Ballout Definition................................................................................................... 279

6.1 Desktop PCH Ballout ........................................................................................ 279

6.2 Mobile PCH Ballout .......................................................................................... 290

6.3 Mobile SFF PCH Ballout .................................................................................... 302

7 Package Information ............................................................................................. 307

7.1 Desktop PCH package ...................................................................................... 307

7.2 Mobile PCH Package......................................................................................... 309

7.3 Mobile SFF PCH Package................................................................................... 311

8 Electrical Characteristics ....................................................................................... 313

8.1 Thermal Specifications ..................................................................................... 313

8.1.1 Desktop Storage Specifications and Thermal Design Power (TDP) ............ 313

8.1.2 Mobile Storage Specifications and Thermal Design Power (TDP) .............. 313

8.2 Absolute Maximum Ratings............................................................................... 314

8.3 PCH Power Supply Range ................................................................................. 315

8.4 General DC Characteristics ............................................................................... 315

8.5 Display DC Characteristics ................................................................................ 328

8.6 AC Characteristics ........................................................................................... 330

8.7 Power Sequencing and Reset Signal Timings ....................................................... 347

8.8 Power Management Timing Diagrams................................................................. 350

8.9 AC Timing Diagrams ........................................................................................ 355

9 Register and Memory Mapping............................................................................... 365

9.1 PCI Devices and Functions................................................................................ 366

9.2 PCI Configuration Map ..................................................................................... 367

9.3 I/O Map ......................................................................................................... 367

9.3.1 Fixed I/O Address Ranges .................................................................. 367

9.3.2 Variable I/O Decode Ranges ............................................................... 370

9.4 Memory Map................................................................................................... 371

9.4.1 Boot-Block Update Scheme ................................................................ 373

10 Chipset Configuration Registers............................................................................. 375

10.1 Chipset Configuration Registers (Memory Space) ................................................. 375

10.1.1 CIR0—Chipset Initialization Register 0 ................................................. 377

10.1.2 RPC—Root Port Configuration Register ................................................. 377

10.1.3 RPFN—Root Port Function Number and Hide for PCI

Express* Root Ports Register .............................................................. 378

10.1.4 FLRSTAT—Function Level Reset Pending Status Register ........................ 379

10.1.5 TRSR—Trap Status Register ............................................................... 380

10.1.6 TRCR—Trapped Cycle Register............................................................ 380

10.1.7 TWDR—Trapped Write Data Register ................................................... 381

10.1.8 IOTRn—I/O Trap Register (0–3).......................................................... 381

10.1.9 V0CTL—Virtual Channel 0 Resource Control Register.............................. 382

10.1.10 V0STS—Virtual Channel 0 Resource Status Register............................... 382

10.1.11 V1CTL—Virtual Channel 1 Resource Control Register.............................. 383

10.1.12 V1STS—Virtual Channel 1 Resource Status Register............................... 383

10.1.13 REC—Root Error Command Register .................................................... 384

10.1.14 LCAP—Link Capabilities Register ......................................................... 384

10.1.15 LCTL—Link Control Register................................................................ 385

10.1.16 LSTS—Link Status Register ................................................................ 385

10.1.17 DLCTL2—DMI Link Control 2 Register .................................................. 385

10.1.18 DMIC—DMI Control Register............................................................... 386

10.1.19 TCTL—TCO Configuration Register....................................................... 386

10.1.20 D31IP—Device 31 Interrupt Pin Register .............................................. 387

10.1.21 D30IP—Device 30 Interrupt Pin Register .............................................. 388

10.1.22 D29IP—Device 29 Interrupt Pin Register .............................................. 388

10.1.23 D28IP—Device 28 Interrupt Pin Register .............................................. 388

10.1.24 D27IP—Device 27 Interrupt Pin Register .............................................. 390

10.1.25 D26IP—Device 26 Interrupt Pin Register .............................................. 390

10.1.26 D25IP—Device 25 Interrupt Pin Register .............................................. 390

10.1.27 D22IP—Device 22 Interrupt Pin Register .............................................. 391

10.1.28 D31IR—Device 31 Interrupt Route Register .......................................... 392

10 Datasheet

10.1.29 D29IR—Device 29 Interrupt Route Register........................................... 393

10.1.30 D28IR—Device 28 Interrupt Route Register........................................... 394

10.1.31 D27IR—Device 27 Interrupt Route Register........................................... 395

10.1.32 D26IR—Device 26 Interrupt Route Register........................................... 396

10.1.33 D25IR—Device 25 Interrupt Route Register........................................... 397

10.1.34 D22IR—Device 22 Interrupt Route Register........................................... 398

10.1.35 OIC—Other Interrupt Control Register .................................................. 399

10.1.36 PRSTS—Power and Reset Status Register .............................................400

10.1.37 PM_CFG—Power Management Configuration Register ............................. 401

10.1.38 DEEP_S4_POL—Deep S4/S5 From S4 Power Policies

10.1.39 DEEP_S5_POL—Deep S4/S5 From S5 Power Policies

10.1.40 PMSYNC_CFG—PMSYNC Configuration Register ..................................... 403

10.1.41 RC—RTC Configuration Register .......................................................... 404

10.1.42 HPTC—High Precision Timer Configuration Register ................................ 404

10.1.43 GCS—General Control and Status Register............................................405

10.1.44 BUC—Backed Up Control Register ........................................................407

10.1.45 FD—Function Disable Register ............................................................. 407

10.1.46 CG—Clock Gating Register .................................................................. 409

10.1.47 FDSW—Function Disable SUS Well Register........................................... 410

10.1.48 DISPBDF—Display Bus, Device and Function

Initialization Register ......................................................................... 411

10.1.49 FD2—Function Disable 2 Register ........................................................411

10.1.50 MISCCTL—Miscellaneous Control Register ............................................. 412

10.1.51 USBOCM1—Overcurrent MAP Register 1 ...............................................413

10.1.52 USBOCM2—Overcurrent MAP Register 2 ...............................................414

10.1.53 RMHWKCTL—Rate Matching Hub Wake Control Register.......................... 415

11 PCI-to-PCI Bridge Registers (D30:F0).................................................................... 417

11.1 PCI Configuration Registers (D30:F0) .................................................................417

11.1.1 VID— Vendor Identification Register (PCI-PCI—D30:F0) ......................... 418

11.1.2 DID— Device Identification Register (PCI-PCI—D30:F0).......................... 418

11.1.3 PCICMD—PCI Command (PCI-PCI—D30:F0)..........................................418

11.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0)....................................... 419

11.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0) ........................ 421

11.1.6 CC—Class Code Register (PCI-PCI—D30:F0) .........................................421

11.1.7 PMLT—Primary Master Latency Timer Register

(PCI-PCI—D30:F0) ............................................................................ 422

11.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0) ..............................422

11.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0) ...................................422

11.1.10 SMLT—Secondary Master Latency Timer Register

(PCI-PCI—D30:F0) ............................................................................ 423

11.1.11 IOBASE_LIMIT—I/O Base and Limit Register

(PCI-PCI—D30:F0) ............................................................................ 423

11.1.12 SECSTS—Secondary Status Register (PCI-PCI—D30:F0) ......................... 424

11.1.13 MEMBASE_LIMIT—Memory Base and Limit Register

(PCI-PCI—D30:F0) ............................................................................ 425

11.1.14 PREF_MEM_BASE_LIMIT—Prefetchable Memory Base

and Limit Register (PCI-PCI—D30:F0) .................................................. 425

11.1.15 PMBU32—Prefetchable Memory Base Upper 32 Bits

11.1.16 PMLU32—Prefetchable Memory Limit Upper 32 Bits

11.1.17 CAPP—Capability List Pointer Register (PCI-PCI—D30:F0) ....................... 426

11.1.18 INTR—Interrupt Information Register (PCI-PCI—D30:F0)........................ 426

11.1.19 BCTRL—Bridge Control Register (PCI-PCI—D30:F0) ............................... 427

11.1.20 SPDH—Secondary PCI Device Hiding Register

(PCI-PCI—D30:F0) ............................................................................ 428

11.1.21 DTC—Delayed Transaction Control Register

(PCI-PCI—D30:F0) ............................................................................ 429

11.1.22 BPS—Bridge Proprietary Status Register

(PCI-PCI—D30:F0) ............................................................................ 430

11.1.23 BPC—Bridge Policy Configuration Register

(PCI-PCI—D30:F0) ............................................................................ 431

11.1.24 SVCAP—Subsystem Vendor Capability Register

(PCI-PCI—D30:F0) ............................................................................ 432

Datasheet 11

11.1.25 SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0) ..................... 433

12 Gigabit LAN Configuration Registers ...................................................................... 435

12.1 Gigabit LAN Configuration Registers

(Gigabit LAN — D25:F0)................................................................................... 435

12.1.1 VID—Vendor Identification Register

(Gigabit LAN—D25:F0) ...................................................................... 436

12.1.2 DID—Device Identification Register

(Gigabit LAN—D25:F0) ...................................................................... 436

12.1.3 PCICMD—PCI Command Register

(Gigabit LAN—D25:F0) ...................................................................... 437

12.1.4 PCISTS—PCI Status Register

(Gigabit LAN—D25:F0) ...................................................................... 438

12.1.5 RID—Revision Identification Register

(Gigabit LAN—D25:F0) ...................................................................... 439

12.1.6 CC—Class Code Register

(Gigabit LAN—D25:F0) ...................................................................... 439

12.1.7 CLS—Cache Line Size Register

(Gigabit LAN—D25:F0) ...................................................................... 439

12.1.8 PLT—Primary Latency Timer Register

(Gigabit LAN—D25:F0) ...................................................................... 439

12.1.9 HEADTYP—Header Type Register

(Gigabit LAN—D25:F0) ...................................................................... 439

12.1.10 MBARA—Memory Base Address Register A

(Gigabit LAN—D25:F0) ...................................................................... 440

12.1.11 MBARB—Memory Base Address Register B

(Gigabit LAN—D25:F0) ...................................................................... 440

12.1.12 MBARC—Memory Base Address Register C

(Gigabit LAN—D25:F0) ...................................................................... 441

12.1.13 SVID—Subsystem Vendor ID Register

(Gigabit LAN—D25:F0) ...................................................................... 441

12.1.14 SID—Subsystem ID Register

(Gigabit LAN—D25:F0) ...................................................................... 441

12.1.15 ERBA—Expansion ROM Base Address Register

(Gigabit LAN—D25:F0) ...................................................................... 441

12.1.16 CAPP—Capabilities List Pointer Register

(Gigabit LAN—D25:F0) ...................................................................... 442

12.1.17 INTR—Interrupt Information Register

(Gigabit LAN—D25:F0) ...................................................................... 442

12.1.18 MLMG—Maximum Latency/Minimum Grant Register

(Gigabit LAN—D25:F0) ...................................................................... 442

12.1.19 CLIST1—Capabilities List Register 1

(Gigabit LAN—D25:F0) ...................................................................... 442

12.1.20 PMC—PCI Power Management Capabilities Register

(Gigabit LAN—D25:F0) ...................................................................... 443

12.1.21 PMCS—PCI Power Management Control and Status

12.1.22 DR—Data Register

(Gigabit LAN—D25:F0) ...................................................................... 445

12.1.23 CLIST2—Capabilities List Register 2

(Gigabit LAN—D25:F0) ...................................................................... 445

12.1.24 MCTL—Message Control Register

(Gigabit LAN—D25:F0) ...................................................................... 445

12.1.25 MADDL—Message Address Low Register

(Gigabit LAN—D25:F0) ...................................................................... 446

12.1.26 MADDH—Message Address High Register

(Gigabit LAN—D25:F0) ...................................................................... 446

12.1.27 MDAT—Message Data Register

(Gigabit LAN—D25:F0) ...................................................................... 446

12.1.28 FLRCAP—Function Level Reset Capability

(Gigabit LAN—D25:F0) ...................................................................... 446

12.1.29 FLRCLV—Function Level Reset Capability Length and

Version Register (Gigabit LAN—D25:F0)............................................... 447

12.1.30 DEVCTRL—Device Control Register (Gigabit LAN—D25:F0) ..................... 447

12 Datasheet

13 LPC Interface Bridge Registers (D31:F0) ............................................................... 449

13.1 PCI Configuration Registers (LPC I/F—D31:F0) .................................................... 449

13.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0) ........................... 450

13.1.2 DID—Device Identification Register (LPC I/F—D31:F0) ........................... 450

13.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0) ............................. 451

13.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0) ....................................451

13.1.5 RID—Revision Identification Register (LPC I/F—D31:F0) ......................... 452

13.1.6 PI—Programming Interface Register (LPC I/F—D31:F0) ..........................452

13.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0)..................................453

13.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0)................................. 453

13.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0)......................... 453

13.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0)............................... 453

13.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0).......................... 454

13.1.12 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0) .......................454

13.1.13 ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0).......................... 455

13.1.14 GPIOBASE—GPIO Base Address Register (LPC I/F — D31:F0)..................455

13.1.15 GC—GPIO Control Register (LPC I/F — D31:F0)..................................... 456

13.1.16 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register

(LPC I/F—D31:F0) ............................................................................. 457

13.1.17 SIRQ_CNTL—Serial IRQ Control Register

(LPC I/F—D31:F0) ............................................................................. 458

13.1.18 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register

(LPC I/F—D31:F0) ............................................................................. 459

13.1.19 LPC_IBDF—IOxAPIC Bus:Device:Function

(LPC I/F—D31:F0) ............................................................................. 459

13.1.20 LPC_HnBDF—HPET n Bus:Device:Function

(LPC I/F—D31:F0) ............................................................................. 460

13.1.21 LPC_I/O_DEC—I/O Decode Ranges Register

(LPC I/F—D31:F0) ............................................................................. 461

13.1.22 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)............................. 462

13.1.23 GEN1_DEC—LPC I/F Generic Decode Range 1 Register

(LPC I/F—D31:F0) ............................................................................. 463

13.1.24 GEN2_DEC—LPC I/F Generic Decode Range 2 Register

(LPC I/F—D31:F0) ............................................................................. 463

13.1.25 GEN3_DEC—LPC I/F Generic Decode Range 3 Register

(LPC I/F—D31:F0) ............................................................................. 464

13.1.26 GEN4_DEC—LPC I/F Generic Decode Range 4 Register

(LPC I/F—D31:F0) ............................................................................. 464

13.1.27 ULKMC — USB Legacy Keyboard / Mouse

Control Register (LPC I/F—D31:F0)...................................................... 465

13.1.28 LGMR — LPC I/F Generic Memory Range Register

(LPC I/F—D31:F0) ............................................................................. 466

13.1.29 BIOS_SEL1—BIOS Select 1 Register

(LPC I/F—D31:F0) ............................................................................. 467

13.1.30 BIOS_SEL2—BIOS Select 2 Register

(LPC I/F—D31:F0) ............................................................................. 468

13.1.31 BIOS_DEC_EN1—BIOS Decode Enable

13.1.32 BIOS_CNTL—BIOS Control Register

(LPC I/F—D31:F0) ............................................................................. 471

13.1.33 FDCAP—Feature Detection Capability ID Register

(LPC I/F—D31:F0) ............................................................................. 472

13.1.34 FDLEN—Feature Detection Capability Length Register

(LPC I/F—D31:F0) ............................................................................. 472

13.1.35 FDVER—Feature Detection Version Register

(LPC I/F—D31:F0) ............................................................................. 472

13.1.36 FVECIDX—Feature Vector Index Register

(LPC I/F—D31:F0) ............................................................................. 472

13.1.37 FVECD—Feature Vector Data Register

(LPC I/F—D31:F0) ............................................................................. 473

13.1.38 Feature Vector Space......................................................................... 473

13.1.38.1 FVEC0—Feature Vector Register 0 ........................................473

13.1.38.2 FVEC1—Feature Vector Register 1 ........................................474

13.1.38.3 FVEC2—Feature Vector Register 2 ........................................474

13.1.38.4 FVEC3—Feature Vector Register 3 ........................................475

13.1.39 RCBA—Root Complex Base Address Register

(LPC I/F—D31:F0) ............................................................................. 475

Datasheet 13

13.2 DMA I/O Registers........................................................................................... 476

13.2.1 DMABASE_CA—DMA Base and Current Address Registers ....................... 477

13.2.2 DMABASE_CC—DMA Base and Current Count Registers.......................... 478

13.2.3 DMAMEM_LP—DMA Memory Low Page Registers ................................... 478

13.2.4 DMACMD—DMA Command Register ..................................................... 479

13.2.5 DMASTA—DMA Status Register ........................................................... 479

13.2.6 DMA_WRSMSK—DMA Write Single Mask Register .................................. 480

13.2.7 DMACH_MODE—DMA Channel Mode Register........................................ 480

13.2.8 DMA Clear Byte Pointer Register ......................................................... 481

13.2.9 DMA Master Clear Register ................................................................. 481

13.2.10 DMA_CLMSK—DMA Clear Mask Register ............................................... 481

13.2.11 DMA_WRMSK—DMA Write All Mask Register ......................................... 482

13.3 Timer I/O Registers ......................................................................................... 482

13.3.1 TCW—Timer Control Word Register ..................................................... 483

13.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register ....................... 485

13.3.3 Counter Access Ports Register............................................................. 486

13.4 8259 Interrupt Controller (PIC) Registers ........................................................... 486

13.4.1 Interrupt Controller I/O MAP............................................................... 486

13.4.2 ICW1—Initialization Command Word 1 Register .................................... 487

13.4.3 ICW2—Initialization Command Word 2 Register .................................... 488

13.4.4 ICW3—Master Controller Initialization Command

Word 3 Register................................................................................ 488

13.4.5 ICW3—Slave Controller Initialization Command

Word 3 Register................................................................................ 489

13.4.6 ICW4—Initialization Command Word 4 Register .................................... 489

13.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)

13.4.8 OCW2—Operational Control Word 2 Register ........................................ 490

13.4.9 OCW3—Operational Control Word 3 Register ........................................ 491

13.4.10 ELCR1—Master Controller Edge/Level Triggered Register ........................ 492

13.4.11 ELCR2—Slave Controller Edge/Level Triggered Register.......................... 493

13.5 Advanced Programmable Interrupt Controller (APIC)............................................ 494

13.5.1 APIC Register Map ............................................................................ 494

13.5.2 IND—Index Register.......................................................................... 494

13.5.3 DAT—Data Register........................................................................... 495

13.5.4 EOIR—EOI Register ........................................................................... 495

13.5.5 ID—Identification Register.................................................................. 496

13.5.6 VER—Version Register ....................................................................... 496

13.5.7 REDIR_TBL—Redirection Table Register ............................................... 497

13.6 Real Time Clock Registers................................................................................. 499

13.6.1 I/O Register Address Map .................................................................. 499

13.6.2 Indexed Registers ............................................................................. 500

13.6.2.1 RTC_REGA—Register A....................................................... 501

13.6.2.2 RTC_REGB—Register B (General Configuration) ..................... 502

13.6.2.3 RTC_REGC—Register C (Flag Register) ................................. 503

13.6.2.4 RTC_REGD—Register D (Flag Register) ................................. 503

13.7 Processor Interface Registers ............................................................................ 504

13.7.1 NMI_SC—NMI Status and Control Register ........................................... 504

13.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)

13.7.3 PORT92—Fast A20 and Init Register .................................................... 505

13.7.4 COPROC_ERR—Coprocessor Error Register ........................................... 505

13.7.5 RST_CNT—Reset Control Register ....................................................... 506

13.8 Power Management Registers ........................................................................... 507

13.8.1 Power Management PCI Configuration Registers

(PM—D31:F0)................................................................................... 507

13.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register

(PM—D31:F0) ................................................................... 508

13.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register

(PM—D31:F0) ................................................................... 509

13.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register

(PM—D31:F0) ................................................................... 510

13.8.1.4 GEN_PMCON_LOCK—General Power Management

Configuration Lock Register................................................. 514

13.8.1.5 CIR4—Chipset Initialization Register 4 (PM—D31:F0).............. 514

13.8.1.6 BM_BREAK_EN_2 Register #2 (PM—D31:F0)......................... 514

13.8.1.7 BM_BREAK_EN Register (PM—D31:F0) ................................. 515

14 Datasheet

13.8.1.8 PMIR—Power Management Initialization Register (PM—D31:F0) 516

13.8.1.9 GPIO_ROUT—GPIO Routing Control Register

(PM—D31:F0).................................................................... 516

13.8.2 APM I/O Decode Register.................................................................... 517

13.8.2.1 APM_CNT—Advanced Power Management Control Port

13.8.2.2 APM_STS—Advanced Power Management Status Port

13.8.3 Power Management I/O Registers ........................................................ 518

13.8.3.1 PM1_STS—Power Management 1 Status Register ................... 519

13.8.3.2 PM1_EN—Power Management 1 Enable Register.....................521

13.8.3.3 PM1_CNT—Power Management 1 Control Register .................. 522

13.8.3.4 PM1_TMR—Power Management 1 Timer Register .................... 523

13.8.3.5 GPE0_STS—General Purpose Event 0 Status Register.............. 524

13.8.3.6 GPE0_EN—General Purpose Event 0 Enables Register ............. 527

13.8.3.7 SMI_EN—SMI Control and Enable Register.............................529

13.8.3.8 SMI_STS—SMI Status Register ............................................531

13.8.3.9 ALT_GP_SMI_EN—Alternate GPI SMI Enable Register.............. 533

13.8.3.10 ALT_GP_SMI_STS—Alternate GPI SMI Status Register ............ 534

13.8.3.11 GPE_CNTL—General Purpose Control Register ........................ 534

13.8.3.12 DEVACT_STS — Device Activity Status Register .....................535

13.8.3.13 PM2_CNT—Power Management 2 Control Register .................. 535

13.9 System Management TCO Registers ................................................................... 536

13.9.1 TCO_RLD—TCO Timer Reload and Current Value Register ....................... 536

13.9.2 TCO_DAT_IN—TCO Data In Register ....................................................537

13.9.3 TCO_DAT_OUT—TCO Data Out Register ............................................... 537

13.9.4 TCO1_STS—TCO1 Status Register .......................................................537

13.9.5 TCO2_STS—TCO2 Status Register .......................................................539

13.9.6 TCO1_CNT—TCO1 Control Register ...................................................... 540

13.9.7 TCO2_CNT—TCO2 Control Register ...................................................... 541

13.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers ....................................541

13.9.9 TCO_WDCNT—TCO Watchdog Control Register ...................................... 542

13.9.10 SW_IRQ_GEN—Software IRQ Generation Register ................................. 542

13.9.11 TCO_TMR—TCO Timer Initial Value Register.......................................... 542

13.10 General Purpose I/O Registers...........................................................................543

13.10.1 GPIO_USE_SEL—GPIO Use Select Register ........................................... 544

13.10.2 GP_IO_SEL—GPIO Input/Output Select Register ....................................544

13.10.3 GP_LVL—GPIO Level for Input or Output Register ..................................545

13.10.4 GPO_BLINK—GPO Blink Enable Register ............................................... 545

13.10.5 GP_SER_BLINK—GP Serial Blink Register..............................................546

13.10.6 GP_SB_CMDSTS—GP Serial Blink Command

Status Register ................................................................................. 546

13.10.7 GP_SB_DATA—GP Serial Blink Data Register ......................................... 547

13.10.8 GPI_NMI_EN—GPI NMI Enable Register ................................................ 547

13.10.9 GPI_NMI_STS—GPI NMI Status Register...............................................547

13.10.10 GPI_INV—GPIO Signal Invert Register.................................................. 548

13.10.11 GPIO_USE_SEL2—GPIO Use Select 2 Register .......................................548

13.10.12 GP_IO_SEL2—GPIO Input/Output Select 2 Register ............................... 549

13.10.13 GP_LVL2—GPIO Level for Input or Output 2 Register.............................. 549

13.10.14 GPIO_USE_SEL3—GPIO Use Select 3 Register .......................................550

13.10.15 GPIO_SEL3—GPIO Input/Output Select 3 Register .................................550

13.10.16 GP_LVL3—GPIO Level for Input or Output 3 Register.............................. 551

13.10.17 GP_RST_SEL1—GPIO Reset Select Register........................................... 551

13.10.18 GP_RST_SEL2—GPIO Reset Select Register........................................... 552

13.10.19 GP_RST_SEL3—GPIO Reset Select Register........................................... 552

14 SATA Controller Registers (D31:F2) ....................................................................... 553

14.1 PCI Configuration Registers (SATA–D31:F2) ........................................................ 553

14.1.1 VID—Vendor Identification Register (SATA—D31:F2).............................. 555

14.1.2 DID—Device Identification Register (SATA—D31:F2) .............................. 555

14.1.3 PCICMD—PCI Command Register (SATA–D31:F2).................................. 555

14.1.4 PCISTS — PCI Status Register (SATA–D31:F2) ......................................556

14.1.5 RID—Revision Identification Register (SATA—D31:F2)............................557

14.1.6 PI—Programming Interface Register (SATA–D31:F2)..............................557

14.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h...... 557

14.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h...... 557

14.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h...... 558

Datasheet 15

14.1.7 SCC—Sub Class Code Register (SATA–D31:F2) ..................................... 558

14.1.8 BCC—Base Class Code Register

(SATA–D31:F2SATA–D31:F2) ............................................................. 558

14.1.9 PMLT—Primary Master Latency Timer Register

(SATA–D31:F2) ................................................................................ 559

14.1.10 HTYPE—Header Type Register

(SATA–D31:F2) ................................................................................ 559

14.1.11 PCMD_BAR—Primary Command Block Base Address

14.1.12 PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F2) ................................................................................ 560

14.1.13 SCMD_BAR—Secondary Command Block Base Address

14.1.14 SCNL_BAR—Secondary Control Block Base Address

14.1.15 BAR—Legacy Bus Master Base Address Register

(SATA–D31:F2) ................................................................................ 561

14.1.16 ABAR/SIDPBA1—AHCI Base Address Register/Serial ATA

Index Data Pair Base Address (SATA–D31:F2) ...................................... 561

14.1.16.1 When SCC is not 01h ......................................................... 561

14.1.16.2 When SCC is 01h............................................................... 562

14.1.17 SVID—Subsystem Vendor Identification Register

(SATA–D31:F2) ................................................................................ 562

14.1.18 SID—Subsystem Identification Register (SATA–D31:F2)......................... 562

14.1.19 CAP—Capabilities Pointer Register (SATA–D31:F2) ................................ 562

14.1.20 INT_LN—Interrupt Line Register (SATA–D31:F2)................................... 563

14.1.21 INT_PN—Interrupt Pin Register (SATA–D31:F2) .................................... 563

14.1.22 IDE_TIM—IDE Timing Register (SATA–D31:F2) ..................................... 563

14.1.23 PID—PCI Power Management Capability Identification

14.1.24 PC—PCI Power Management Capabilities Register

(SATA–D31:F2) ................................................................................ 564

14.1.25 PMCS—PCI Power Management Control and Status

14.1.26 MSICI—Message Signaled Interrupt Capability

Identification Register (SATA–D31:F2)................................................. 566

14.1.27 MSIMC—Message Signaled Interrupt Message

Control Register (SATA–D31:F2) ......................................................... 566

14.1.28 MSIMA— Message Signaled Interrupt Message

Address Register (SATA–D31:F2) ........................................................ 568

14.1.29 MSIMD—Message Signaled Interrupt Message

Data Register (SATA–D31:F2) ............................................................ 568

14.1.30 MAP—Address Map Register (SATA–D31:F2)......................................... 569

14.1.31 PCS—Port Control and Status Register (SATA–D31:F2) .......................... 570

14.1.32 SCLKCG—SATA Clock Gating Control Register ....................................... 572

14.1.33 SCLKGC—SATA Clock General Configuration Register............................. 572

14.1.34 SATACR0—SATA Capability Register 0 (SATA–D31:F2)........................... 573

14.1.35 SATACR1—SATA Capability Register 1 (SATA–D31:F2)........................... 574

14.1.36 FLRCID—FLR Capability ID Register (SATA–D31:F2) .............................. 574

14.1.37 FLRCLV—FLR Capability Length and Version Register

(SATA–D31:F2) ................................................................................ 575

14.1.38 FLRC—FLR Control Register (SATA–D31:F2) ......................................... 575

14.1.39 ATC—APM Trapping Control Register (SATA–D31:F2)............................. 576

14.1.40 ATS—APM Trapping Status Register (SATA–D31:F2) .............................. 576

14.1.41 SP Scratch Pad Register (SATA–D31:F2) .............................................. 576

14.1.42 BFCS—BIST FIS Control/Status Register (SATA–D31:F2)........................ 577

14.1.43 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2)..................... 579

14.1.44 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)..................... 579

14.2 Bus Master IDE I/O Registers (D31:F2) .............................................................. 580

14.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2)....................... 581

14.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2)............................ 582

14.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

14.2.4 AIR—AHCI Index Register (D31:F2) .................................................... 583

14.2.5 AIDR—AHCI Index Data Register (D31:F2)........................................... 583

14.3 Serial ATA Index/Data Pair Superset Registers .................................................... 584

14.3.1 SINDX—Serial ATA Index Register (D31:F2) ......................................... 584

16 Datasheet

14.3.2 SDATA—Serial ATA Data Register (D31:F2)........................................... 585

14.3.2.1 PxSSTS—Serial ATA Status Register (D31:F2)........................ 585

14.3.2.2 PxSCTL—Serial ATA Control Register (D31:F2) ....................... 586

14.3.2.3 PxSERR—Serial ATA Error Register (D31:F2).......................... 587

14.4 AHCI Registers (D31:F2) .................................................................................. 588

14.4.1 AHCI Generic Host Control Registers (D31:F2) ......................................589

14.4.1.1 CAP—Host Capabilities Register (D31:F2) .............................. 590

14.4.1.2 GHC—Global PCH Control Register (D31:F2) .......................... 592

14.4.1.3 IS—Interrupt Status Register (D31:F2) .................................593

14.4.1.4 PI—Ports Implemented Register (D31:F2) ............................. 594

14.4.1.5 VS—AHCI Version Register (D31:F2) .................................... 595

14.4.1.6 EM_LOC—Enclosure Management Location Register (D31:F2) .. 595

14.4.1.7 EM_CTRL—Enclosure Management Control Register (D31:F2) .. 596

14.4.1.8 CAP2—HBA Capabilities Extended Register ............................ 597

14.4.1.9 VSP—Vendor Specific Register (D31:F2)................................597

14.4.1.10 RSTF—Intel® RST Feature Capabilities Register ...................... 598

14.4.2 Port Registers (D31:F2) ..................................................................... 599

14.4.2.1 PxCLB—Port [5:0] Command List Base Address Register

(D31:F2) .......................................................................... 602

14.4.2.2 PxCLBU—Port [5:0] Command List Base Address Upper

32-Bits Register (D31:F2) ...................................................602

14.4.2.3 PxFB—Port [5:0] FIS Base Address Register (D31:F2).............602

14.4.2.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits

14.4.2.5 PxIS—Port [5:0] Interrupt Status Register (D31:F2) ...............603

14.4.2.6 PxIE—Port [5:0] Interrupt Enable Register (D31:F2)...............605

14.4.2.7 PxCMD—Port [5:0] Command Register (D31:F2) .................... 606

14.4.2.8 PxTFD—Port [5:0] Task File Data Register (D31:F2) ...............609

14.4.2.9 PxSIG—Port [5:0] Signature Register (D31:F2)...................... 609

14.4.2.10 PxSSTS—Port [5:0] Serial ATA Status Register (D31:F2) ......... 610

14.4.2.11 PxSCTL — Port [5:0] Serial ATA Control Register (D31:F2) ...... 611

14.4.2.12 PxSERR—Port [5:0] Serial ATA Error Register (D31:F2) ........... 612

14.4.2.13 PxSACT—Port [5:0] Serial ATA Active Register (D31:F2) ......... 614

14.4.2.14 PxCI—Port [5:0] Command Issue Register (D31:F2) ............... 614

15 SATA Controller Registers (D31:F5) ....................................................................... 615

15.1 PCI Configuration Registers (SATA–D31:F5) ........................................................ 615

15.1.1 VID—Vendor Identification Register (SATA—D31:F5).............................. 616

15.1.2 DID—Device Identification Register (SATA—D31:F5) .............................. 616

15.1.3 PCICMD—PCI Command Register (SATA–D31:F5).................................. 617

15.1.4 PCISTS — PCI Status Register (SATA–D31:F5) ......................................618

15.1.5 RID—Revision Identification Register (SATA—D31:F5)............................618

15.1.6 PI—Programming Interface Register (SATA–D31:F5)..............................619

15.1.7 SCC—Sub Class Code Register (SATA–D31:F5)...................................... 619

15.1.8 BCC—Base Class Code Register

(SATA–D31:F5SATA–D31:F5) ............................................................. 619

15.1.9 PMLT—Primary Master Latency Timer Register

(SATA–D31:F5)................................................................................. 620

15.1.10 PCMD_BAR—Primary Command Block Base Address

15.1.11 PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F5)................................................................................. 620

15.1.12 SCMD_BAR—Secondary Command Block Base Address

15.1.13 SCNL_BAR—Secondary Control Block Base Address

15.1.14 BAR—Legacy Bus Master Base Address Register

(SATA–D31:F5)................................................................................. 622

15.1.15 SIDPBA—SATA Index/Data Pair Base Address Register

(SATA–D31:F5)................................................................................. 622

15.1.16 SVID—Subsystem Vendor Identification Register

(SATA–D31:F5)................................................................................. 623

15.1.17 SID—Subsystem Identification Register (SATA–D31:F5) ......................... 623

15.1.18 CAP—Capabilities Pointer Register (SATA–D31:F5)................................. 623

15.1.19 INT_LN—Interrupt Line Register (SATA–D31:F5) ...................................623

15.1.20 INT_PN—Interrupt Pin Register (SATA–D31:F5)..................................... 623

15.1.21 IDE_TIM—IDE Timing Register (SATA–D31:F5) ..................................... 624

Datasheet 17

15.1.22 PID—PCI Power Management Capability Identification

15.1.23 PC—PCI Power Management Capabilities Register

(SATA–D31:F5) ................................................................................ 624

15.1.24 PMCS—PCI Power Management Control and Status

15.1.25 MAP—Address Map Register (SATA–D31:F5)......................................... 626

15.1.26 PCS—Port Control and Status Register (SATA–D31:F5) .......................... 627

15.1.27 SATACR0— SATA Capability Register 0 (SATA–D31:F5).......................... 628

15.1.28 SATACR1— SATA Capability Register 1 (SATA–D31:F5).......................... 628

15.1.29 FLRCID— FLR Capability ID Register (SATA–D31:F5) ............................. 628

15.1.30 FLRCLV— FLR Capability Length and

Value Register (SATA–D31:F5) ........................................................... 629

15.1.31 FLRCTRL— FLR Control Register (SATA–D31:F5) ................................... 629

15.1.32 ATC—APM Trapping Control Register (SATA–D31:F5)............................. 630

15.1.33 ATC—APM Trapping Control Register (SATA–D31:F5)............................. 630

15.2 Bus Master IDE I/O Registers (D31:F5) .............................................................. 631

15.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F5)....................... 632

15.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F5)............................ 633

15.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

15.3 Serial ATA Index/Data Pair Superset Registers .................................................... 634

15.3.1 SINDX—SATA Index Register (D31:F5) ................................................ 634

15.3.2 SDATA—SATA Index Data Register (D31:F5) ........................................ 634

15.3.2.1 PxSSTS—Serial ATA Status Register (D31:F5) ....................... 635

15.3.2.2 PxSCTL—Serial ATA Control Register (D31:F5) ...................... 636

15.3.2.3 PxSERR—Serial ATA Error Register (D31:F5) ......................... 637

16 EHCI Controller Registers (D29:F0, D26:F0) .......................................................... 639

16.1 USB EHCI Configuration Registers

(USB EHCI—D29:F0, D26:F0) ........................................................................... 639

16.1.1 VID—Vendor Identification Register

(USB EHCI—D29:F0, D26:F0)............................................................. 641

16.1.2 DID—Device Identification Register

(USB EHCI—D29:F0, D26:F0)............................................................. 641

16.1.3 PCICMD—PCI Command Register

(USB EHCI—D29:F0, D26:F0)............................................................. 641

16.1.4 PCISTS—PCI Status Register

(USB EHCI—D29:F0, D26:F0)............................................................. 643

16.1.5 RID—Revision Identification Register

(USB EHCI—D29:F0, D26:F0)............................................................. 644

16.1.6 PI—Programming Interface Register

(USB EHCI—D29:F0, D26:F0)............................................................. 644

16.1.7 SCC—Sub Class Code Register

(USB EHCI—D29:F0, D26:F0)............................................................. 644

16.1.8 BCC—Base Class Code Register

(USB EHCI—D29:F0, D26:F0)............................................................. 644

16.1.9 PMLT—Primary Master Latency Timer Register

(USB EHCI—D29:F0, D26:F0)............................................................. 645

16.1.10 HEADTYP—Header Type Register

(USB EHCI—D29:F0, D26:F0)............................................................. 645

16.1.11 MEM_BASE—Memory Base Address Register

(USB EHCI—D29:F0, D26:F0)............................................................. 645

16.1.12 SVID—USB EHCI Subsystem Vendor ID Register

(USB EHCI—D29:F0, D26:F0)............................................................. 646

16.1.13 SID—USB EHCI Subsystem ID Register

(USB EHCI—D29:F0, D26:F0)............................................................. 646

16.1.14 CAP_PTR—Capabilities Pointer Register

(USB EHCI—D29:F0, D26:F0)............................................................. 646

16.1.15 INT_LN—Interrupt Line Register

(USB EHCI—D29:F0, D26:F0)............................................................. 646

16.1.16 INT_PN—Interrupt Pin Register

(USB EHCI—D29:F0, D26:F0)............................................................. 647

16.1.17 PWR_CAPID—PCI Power Management Capability ID

16.1.18 NXT_PTR1—Next Item Pointer #1 Register

(USB EHCI—D29:F0, D26:F0)............................................................. 647

18 Datasheet

16.1.19 PWR_CAP—Power Management Capabilities Register

(USB EHCI—D29:F0, D26:F0) ............................................................. 648

16.1.20 PWR_CNTL_STS—Power Management Control/

Status Register (USB EHCI—D29:F0, D26:F0) .......................................649

16.1.21 DEBUG_CAPID—Debug Port Capability ID Register

(USB EHCI—D29:F0, D26:F0) ............................................................. 650

16.1.22 NXT_PTR2—Next Item Pointer #2 Register

(USB EHCI—D29:F0, D26:F0) ............................................................. 650

16.1.23 DEBUG_BASE—Debug Port Base Offset Register

(USB EHCI—D29:F0, D26:F0) ............................................................. 650

16.1.24 USB_RELNUM—USB Release Number Register

(USB EHCI—D29:F0, D26:F0) ............................................................. 650

16.1.25 FL_ADJ—Frame Length Adjustment Register

(USB EHCI—D29:F0, D26:F0) ............................................................. 651

16.1.26 PWAKE_CAP—Port Wake Capability Register

(USB EHCI—D29:F0, D26:F0) ............................................................. 652

16.1.27 LEG_EXT_CAP—USB EHCI Legacy Support Extended

Capability Register (USB EHCI—D29:F0, D26:F0) .................................. 653

16.1.28 LEG_EXT_CS—USB EHCI Legacy Support Extended

Control / Status Register (USB EHCI—D29:F0, D26:F0) ..........................654

16.1.29 SPECIAL_SMI—Intel Specific USB 2.0 SMI Register

(USB EHCI—D29:F0, D26:F0) ............................................................. 656

16.1.30 ACCESS_CNTL—Access Control Register

(USB EHCI—D29:F0, D26:F0) ............................................................. 657

16.1.31 EHCIIR1—EHCI Initialization Register 1

(USB EHCI—D29:F0, D26:F0) ............................................................. 658

16.1.32 EHCIIR2—EHCI Initialization Register 2 (USB EHCI—D29:F0, D26:F0) ...... 658

16.1.33 FLR_CID—Function Level Reset Capability ID Register

(USB EHCI—D29:F0, D26:F0) ............................................................. 659

16.1.34 FLR_NEXT—Function Level Reset Next Capability

Pointer Register (USB EHCI—D29:F0, D26:F0) ......................................659

16.1.35 FLR_CLV—Function Level Reset Capability Length and

Version Register (USB EHCI—D29:F0, D26:F0)...................................... 660

16.1.36 FLR_CTRL—Function Level Reset Control Register

(USB EHCI—D29:F0, D26:F0) ............................................................. 660

16.1.37 FLR_STS—Function Level Reset Status Register

(USB EHCI—D29:F0, D26:F0) ............................................................. 661

16.1.38 EHCIIR3—EHCI Initialization Register 3 (USB EHCI—D29:F0, D26:F0) ...... 661

16.1.39 EHCIIR4—EHCI Initialization Register 4 (USB EHCI—D29:F0, D26:F0) ...... 661

16.2 Memory-Mapped I/O Registers ..........................................................................662

16.2.1 Host Controller Capability Registers ..................................................... 662

16.2.1.1 CAPLENGTH—Capability Registers Length Register.................. 663

16.2.1.2 HCIVERSION—Host Controller Interface Version Number

16.2.1.3 HCSPARAMS—Host Controller Structural Parameters Register... 663

16.2.1.4 HCCPARAMS—Host Controller Capability Parameters

16.2.2 Host Controller Operational Registers ...................................................665

16.2.2.1 USB2.0_CMD—USB 2.0 Command Register ........................... 666

16.2.2.2 USB2.0_STS—USB 2.0 Status Register.................................. 669

16.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register .................. 671

16.2.2.4 FRINDEX—Frame Index Register ..........................................672

16.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment

16.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address

16.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address

16.2.2.8 CONFIGFLAG—Configure Flag Register .................................. 674

16.2.2.9 PORTSC—Port N Status and Control Register ......................... 675

16.2.3 USB 2.0-Based Debug Port Registers ...................................................680

16.2.3.1 CNTL_STS—Control/Status Register......................................681

16.2.3.2 USBPID—USB PIDs Register ................................................ 683

16.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register .................... 683

16.2.3.4 CONFIG—Configuration Register........................................... 683

Datasheet 19

17 Integrated Intel® High Definition Audio Controller Registers................................. 685

17.1 Intel® High Definition Audio Controller Registers (D27:F0).................................... 685

17.1.1 Intel® High Definition Audio PCI Configuration Space

(Intel® High Definition Audio— D27:F0) ............................................... 685

17.1.1.1 VID—Vendor Identification Register

(Intel® High Definition Audio Controller—D27:F0) .................. 687

17.1.1.2 DID—Device Identification Register

(Intel® High Definition Audio Controller—D27:F0) .................. 687

17.1.1.3 PCICMD—PCI Command Register

(Intel® High Definition Audio Controller—D27:F0) .................. 688

17.1.1.4 PCISTS—PCI Status Register

(Intel® High Definition Audio Controller—D27:F0) .................. 689

17.1.1.5 RID—Revision Identification Register

(Intel® High Definition Audio Controller—D27:F0) .................. 689

17.1.1.6 PI—Programming Interface Register

(Intel® High Definition Audio Controller—D27:F0) .................. 689

17.1.1.7 SCC—Sub Class Code Register

(Intel® High Definition Audio Controller—D27:F0) .................. 690

17.1.1.8 BCC—Base Class Code Register

(Intel® High Definition Audio Controller—D27:F0) .................. 690

17.1.1.9 CLS—Cache Line Size Register

(Intel® High Definition Audio Controller—D27:F0) .................. 690

17.1.1.10 LT—Latency Timer Register

(Intel® High Definition Audio Controller—D27:F0) .................. 690

17.1.1.11 HEADTYP—Header Type Register

(Intel® High Definition Audio Controller—D27:F0) .................. 690

17.1.1.12 HDBARL—Intel® High Definition Audio Lower Base Address

17.1.1.13 HDBARU—Intel® High Definition Audio Upper Base Address

17.1.1.14 SVID—Subsystem Vendor Identification Register

(Intel® High Definition Audio Controller—D27:F0) .................. 691

17.1.1.15 SID—Subsystem Identification Register

(Intel® High Definition Audio Controller—D27:F0) .................. 692

17.1.1.16 CAPPTR—Capabilities Pointer Register

(Intel® High Definition Audio Controller—D27:F0) .................. 692

17.1.1.17 INTLN—Interrupt Line Register

(Intel® High Definition Audio Controller—D27:F0) .................. 692

17.1.1.18 INTPN—Interrupt Pin Register

(Intel® High Definition Audio Controller—D27:F0) .................. 692

17.1.1.19 HDCTL—Intel® High Definition Audio Control Register

(Intel® High Definition Audio Controller—D27:F0) .................. 693

17.1.1.20 HDINIT1—Intel® High Definition Audio Initialization Register 1

(Intel® High Definition Audio Controller—D27:F0) .................. 693

17.1.1.21 DCKCTL—Docking Control Register (Mobile Only)

(Intel® High Definition Audio Controller—D27:F0) .................. 693

17.1.1.22 DCKSTS—Docking Status Register (Mobile Only)

(Intel® High Definition Audio Controller—D27:F0) .................. 694

17.1.1.23 PID—PCI Power Management Capability ID Register

(Intel® High Definition Audio Controller—D27:F0) .................. 694

17.1.1.24 PC—Power Management Capabilities Register

(Intel® High Definition Audio Controller—D27:F0) .................. 695

17.1.1.25 PCS—Power Management Control and Status Register

(Intel® High Definition Audio Controller—D27:F0) .................. 695

17.1.1.26 MID—MSI Capability ID Register

(Intel® High Definition Audio Controller—D27:F0) .................. 696

17.1.1.27 MMC—MSI Message Control Register

(Intel® High Definition Audio Controller—D27:F0) .................. 696

17.1.1.28 MMLA—MSI Message Lower Address Register

(Intel® High Definition Audio Controller—D27:F0) .................. 697

17.1.1.29 MMUA—MSI Message Upper Address Register

(Intel® High Definition Audio Controller—D27:F0) .................. 697

17.1.1.30 MMD—MSI Message Data Register

(Intel® High Definition Audio Controller—D27:F0) .................. 697

17.1.1.31 PXID—PCI Express* Capability ID Register

(Intel® High Definition Audio Controller—D27:F0) .................. 697

20 Datasheet

17.1.1.32 PXC—PCI Express* Capabilities Register

(Intel® High Definition Audio Controller—D27:F0) .................. 698

17.1.1.33 DEVCAP—Device Capabilities Register

(Intel® High Definition Audio Controller—D27:F0) .................. 698

17.1.1.34 DEVC—Device Control Register

(Intel® High Definition Audio Controller—D27:F0) .................. 699

17.1.1.35 DEVS—Device Status Register

(Intel® High Definition Audio Controller—D27:F0) .................. 700

17.1.1.36 VCCAP—Virtual Channel Enhanced Capability Header

(Intel® High Definition Audio Controller—D27:F0) .................. 700

17.1.1.37 PVCCAP1—Port VC Capability Register 1

(Intel® High Definition Audio Controller—D27:F0) .................. 701

17.1.1.38 PVCCAP2 — Port VC Capability Register 2

(Intel® High Definition Audio Controller—D27:F0) .................. 701

17.1.1.39 PVCCTL — Port VC Control Register

(Intel® High Definition Audio Controller—D27:F0) .................. 701

17.1.1.40 PVCSTS—Port VC Status Register

(Intel® High Definition Audio Controller—D27:F0) .................. 702

17.1.1.41 VC0CAP—VC0 Resource Capability Register

(Intel® High Definition Audio Controller—D27:F0) .................. 702

17.1.1.42 VC0CTL—VC0 Resource Control Register

(Intel® High Definition Audio Controller—D27:F0) .................. 703

17.1.1.43 VC0STS—VC0 Resource Status Register

(Intel® High Definition Audio Controller—D27:F0) .................. 703

17.1.1.44 VCiCAP—VCi Resource Capability Register

(Intel® High Definition Audio Controller—D27:F0) .................. 704

17.1.1.45 VCiCTL—VCi Resource Control Register

(Intel® High Definition Audio Controller—D27:F0) .................. 704

17.1.1.46 VCiSTS—VCi Resource Status Register

(Intel® High Definition Audio Controller—D27:F0) .................. 705

17.1.1.47 RCCAP—Root Complex Link Declaration Enhanced

Capability Header Register

(Intel® High Definition Audio Controller—D27:F0) .................. 705

17.1.1.48 ESD—Element Self Description Register

(Intel® High Definition Audio Controller—D27:F0) .................. 705

17.1.1.49 L1DESC—Link 1 Description Register

(Intel® High Definition Audio Controller—D27:F0) .................. 706

17.1.1.50 L1ADDL—Link 1 Lower Address Register

(Intel® High Definition Audio Controller—D27:F0) .................. 706

17.1.1.51 L1ADDU—Link 1 Upper Address Register

(Intel® High Definition Audio Controller—D27:F0) .................. 706

17.1.2 Intel® High Definition Audio Memory Mapped Configuration Registers

(Intel® High Definition Audio D27:F0) ..................................................707

17.1.2.1 GCAP—Global Capabilities Register

(Intel® High Definition Audio Controller—D27:F0) .................. 711

17.1.2.2 VMIN—Minor Version Register

(Intel® High Definition Audio Controller—D27:F0) .................. 711

17.1.2.3 VMAJ—Major Version Register

(Intel® High Definition Audio Controller—D27:F0) .................. 711

17.1.2.4 OUTPAY—Output Payload Capability Register

(Intel® High Definition Audio Controller—D27:F0) .................. 712

17.1.2.5 INPAY—Input Payload Capability Register

(Intel® High Definition Audio Controller—D27:F0) .................. 712

17.1.2.6 GCTL—Global Control Register

(Intel® High Definition Audio Controller—D27:F0) .................. 713

17.1.2.7 WAKEEN—Wake Enable Register

(Intel® High Definition Audio Controller—D27:F0) .................. 714

17.1.2.8 STATESTS—State Change Status Register

(Intel® High Definition Audio Controller—D27:F0) .................. 714

17.1.2.9 GSTS—Global Status Register

(Intel® High Definition Audio Controller—D27:F0) .................. 715

17.1.2.10 OUTSTRMPAY—Output Stream Payload Capability

(Intel® High Definition Audio Controller—D27:F0) .................. 715

17.1.2.11 INSTRMPAY—Input Stream Payload Capability

(Intel® High Definition Audio Controller—D27:F0) .................. 715

17.1.2.12 INTCTL—Interrupt Control Register

(Intel® High Definition Audio Controller—D27:F0) .................. 716

Datasheet 21

17.1.2.13 INTSTS—Interrupt Status Register

(Intel® High Definition Audio Controller—D27:F0) .................. 717

17.1.2.14 WALCLK—Wall Clock Counter Register

(Intel® High Definition Audio Controller—D27:F0) .................. 717

17.1.2.15 SSYNC—Stream Synchronization Register

(Intel® High Definition Audio Controller—D27:F0) .................. 718

17.1.2.16 CORBLBASE—CORB Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0) .................. 718

17.1.2.17 CORBUBASE—CORB Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0) .................. 719

17.1.2.18 CORBWP—CORB Write Pointer Register

(Intel® High Definition Audio Controller—D27:F0) .................. 719

17.1.2.19 CORBRP—CORB Read Pointer Register

(Intel® High Definition Audio Controller—D27:F0) .................. 719

17.1.2.20 CORBCTL—CORB Control Register

(Intel® High Definition Audio Controller—D27:F0) .................. 720

17.1.2.21 CORBST—CORB Status Register

(Intel® High Definition Audio Controller—D27:F0) .................. 720

17.1.2.22 CORBSIZE—CORB Size Register

Intel® High Definition Audio Controller—D27:F0) ................... 720

17.1.2.23 RIRBLBASE—RIRB Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0) .................. 721

17.1.2.24 RIRBUBASE—RIRB Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0) .................. 721

17.1.2.25 RIRBWP—RIRB Write Pointer Register

(Intel® High Definition Audio Controller—D27:F0) .................. 721

17.1.2.26 RINTCNT—Response Interrupt Count Register

(Intel® High Definition Audio Controller—D27:F0) .................. 722

17.1.2.27 RIRBCTL—RIRB Control Register

(Intel® High Definition Audio Controller—D27:F0) .................. 722

17.1.2.28 RIRBSTS—RIRB Status Register

(Intel® High Definition Audio Controller—D27:F0) .................. 723

17.1.2.29 RIRBSIZE—RIRB Size Register

(Intel® High Definition Audio Controller—D27:F0) .................. 723

17.1.2.30 IC—Immediate Command Register

(Intel® High Definition Audio Controller—D27:F0) .................. 723

17.1.2.31 IR—Immediate Response Register

(Intel® High Definition Audio Controller—D27:F0) .................. 724

17.1.2.32 ICS—Immediate Command Status Register

(Intel® High Definition Audio Controller—D27:F0) .................. 724

17.1.2.33 DPLBASE—DMA Position Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0) .................. 725

17.1.2.34 DPUBASE—DMA Position Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0) .................. 725

17.1.2.35 SDCTL—Stream Descriptor Control Register

(Intel® High Definition Audio Controller—D27:F0) .................. 726

17.1.2.36 SDSTS—Stream Descriptor Status Register

(Intel® High Definition Audio Controller—D27:F0) .................. 727

17.1.2.37 SDLPIB—Stream Descriptor Link Position in Buffer

17.1.2.38 SDCBL—Stream Descriptor Cyclic Buffer Length Register

(Intel® High Definition Audio Controller—D27:F0) .................. 728

17.1.2.39 SDLVI—Stream Descriptor Last Valid Index Register

(Intel® High Definition Audio Controller—D27:F0) .................. 729

17.1.2.40 SDFIFOW—Stream Descriptor FIFO Watermark Register

(Intel® High Definition Audio Controller—D27:F0) .................. 729

17.1.2.41 SDFIFOS—Stream Descriptor FIFO Size Register – Input

Streams (Intel® High Definition Audio Controller—D27:F0)...... 730

17.1.2.42 SDFIFOS—Stream Descriptor FIFO Size Register – Output

Streams (Intel® High Definition Audio Controller—D27:F0)...... 730

17.1.2.43 SDFMT—Stream Descriptor Format Register

(Intel® High Definition Audio Controller—D27:F0) .................. 731

17.1.2.44 SDBDPL—Stream Descriptor Buffer Descriptor List

Pointer Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0) .................. 732

22 Datasheet

17.1.2.45 SDBDPU—Stream Descriptor Buffer Descriptor List

Pointer Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0) .................. 732

17.2 Integrated Digital Display Audio Registers and Verb IDs........................................ 733

17.2.1 Configuration Default Register............................................................. 733

18 SMBus Controller Registers (D31:F3) ..................................................................... 739

18.1 PCI Configuration Registers (SMBus—D31:F3) ..................................................... 739

18.1.1 VID—Vendor Identification Register (SMBus—D31:F3)............................739

18.1.2 DID—Device Identification Register (SMBus—D31:F3) ............................740

18.1.3 PCICMD—PCI Command Register (SMBus—D31:F3) ............................... 740

18.1.4 PCISTS—PCI Status Register (SMBus—D31:F3) ..................................... 741

18.1.5 RID—Revision Identification Register (SMBus—D31:F3) .......................... 741

18.1.6 PI—Programming Interface Register (SMBus—D31:F3)........................... 742

18.1.7 SCC—Sub Class Code Register (SMBus—D31:F3)................................... 742

18.1.8 BCC—Base Class Code Register (SMBus—D31:F3) .................................742

18.1.9 SMBMBAR0—D31_F3_SMBus Memory Base Address 0

18.1.10 SMBMBAR1—D31_F3_SMBus Memory Base Address 1

18.1.11 SMB_BASE—SMBus Base Address Register

(SMBus—D31:F3).............................................................................. 743

18.1.12 SVID—Subsystem Vendor Identification Register

(SMBus—D31:F2/F4) ......................................................................... 743

18.1.13 SID—Subsystem Identification Register

(SMBus—D31:F2/F4) ......................................................................... 744

18.1.14 INT_LN—Interrupt Line Register (SMBus—D31:F3) ................................744

18.1.15 INT_PN—Interrupt Pin Register (SMBus—D31:F3)..................................744

18.1.16 HOSTC—Host Configuration Register (SMBus—D31:F3) ..........................745

18.2 SMBus I/O and Memory Mapped I/O Registers .....................................................746

18.2.1 HST_STS—Host Status Register (SMBus—D31:F3)................................. 747

18.2.2 HST_CNT—Host Control Register (SMBus—D31:F3) ............................... 748

18.2.3 HST_CMD—Host Command Register (SMBus—D31:F3)...........................750

18.2.4 XMIT_SLVA—Transmit Slave Address Register

(SMBus—D31:F3).............................................................................. 750

18.2.5 HST_D0—Host Data 0 Register (SMBus—D31:F3) .................................. 750

18.2.6 HST_D1—Host Data 1 Register (SMBus—D31:F3) .................................. 750

18.2.7 Host_BLOCK_DB—Host Block Data Byte Register

(SMBus—D31:F3).............................................................................. 751

18.2.8 PEC—Packet Error Check (PEC) Register

(SMBus—D31:F3).............................................................................. 751

18.2.9 RCV_SLVA—Receive Slave Address Register

(SMBus—D31:F3).............................................................................. 752

18.2.10 SLV_DATA—Receive Slave Data Register (SMBus—D31:F3) .................... 752

18.2.11 AUX_STS—Auxiliary Status Register (SMBus—D31:F3) ........................... 752

18.2.12 AUX_CTL—Auxiliary Control Register (SMBus—D31:F3) .......................... 753

18.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register

(SMBus—D31:F3).............................................................................. 753

18.2.14 SMBus_PIN_CTL—SMBus Pin Control Register

(SMBus—D31:F3).............................................................................. 754

18.2.15 SLV_STS—Slave Status Register (SMBus—D31:F3) ................................ 754

18.2.16 SLV_CMD—Slave Command Register (SMBus—D31:F3).......................... 755

18.2.17 NOTIFY_DADDR—Notify Device Address Register

(SMBus—D31:F3).............................................................................. 755

18.2.18 NOTIFY_DLOW—Notify Data Low Byte Register

(SMBus—D31:F3).............................................................................. 756

18.2.19 NOTIFY_DHIGH—Notify Data High Byte Register

(SMBus—D31:F3).............................................................................. 756

19 PCI Express* Configuration Registers .................................................................... 757

19.1 PCI Express* Configuration Registers

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................................757

19.1.1 VID—Vendor Identification Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................759

19.1.2 DID—Device Identification Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................759

Datasheet 23

19.1.3 PCICMD—PCI Command Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 760

19.1.4 PCISTS—PCI Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 761

19.1.5 RID—Revision Identification Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 762

19.1.6 PI—Programming Interface Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 762

19.1.7 SCC—Sub Class Code Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 762

19.1.8 BCC—Base Class Code Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 762

19.1.9 CLS—Cache Line Size Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 763

19.1.10 PLT—Primary Latency Timer Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 763

19.1.11 HEADTYP—Header Type Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 763

19.1.12 BNUM—Bus Number Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 764

19.1.13 SLT—Secondary Latency Timer Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 764

19.1.14 IOBL—I/O Base and Limit Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 764

19.1.15 SSTS—Secondary Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 765

19.1.16 MBL—Memory Base and Limit Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 766

19.1.17 PMBL—Prefetchable Memory Base and Limit Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 766

19.1.18 PMBU32—Prefetchable Memory Base Upper 32 Bits

19.1.19 PMLU32—Prefetchable Memory Limit Upper 32 Bits

19.1.20 CAPP—Capabilities List Pointer Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 767

19.1.21 INTR—Interrupt Information Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 768

19.1.22 BCTRL—Bridge Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 769

19.1.23 CLIST—Capabilities List Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .................................... 770

19.1.24 XCAP—PCI Express* Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .................................... 770

19.1.25 DCAP—Device Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .................................... 771

19.1.26 DCTL—Device Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .................................... 772

19.1.27 DSTS—Device Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .................................... 773

19.1.28 LCAP—Link Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .................................... 774

19.1.29 LCTL—Link Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .................................... 776

19.1.30 LSTS—Link Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .................................... 777

19.1.31 SLCAP—Slot Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .................................... 778

19.1.32 SLCTL—Slot Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .................................... 779

19.1.33 SLSTS—Slot Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .................................... 780

19.1.34 RCTL—Root Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .................................... 781

19.1.35 RSTS—Root Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .................................... 781

24 Datasheet

19.1.36 DCAP2—Device Capabilities 2 Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................782

19.1.37 DCTL2—Device Control 2 Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................782

19.1.38 LCTL2—Link Control 2 Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................783

19.1.39 LSTS2—Link Status 2 Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................784

19.1.40 MID—Message Signaled Interrupt Identifiers Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................784

19.1.41 MC—Message Signaled Interrupt Message Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................784

19.1.42 MA—Message Signaled Interrupt Message Address

19.1.43 MD—Message Signaled Interrupt Message Data Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................785

19.1.44 SVCAP—Subsystem Vendor Capability Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................785

19.1.45 SVID—Subsystem Vendor Identification Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................785

19.1.46 PMCAP—Power Management Capability Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................786

19.1.47 PMC—PCI Power Management Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................786

19.1.48 PMCS—PCI Power Management Control and Status

19.1.49 MPC2—Miscellaneous Port Configuration Register 2

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................788

19.1.50 MPC—Miscellaneous Port Configuration Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................789

19.1.51 SMSCS—SMI/SCI Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................791

19.1.52 RPDCGEN—Root Port Dynamic Clock Gating Enable

19.1.53 PECR1—PCI Express* Configuration Register 1

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................792

19.1.54 PECR3—PCI Express* Configuration Register 3

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................793

19.1.55 UES—Uncorrectable Error Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................794

19.1.56 UEM—Uncorrectable Error Mask Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................795

19.1.57 UEV — Uncorrectable Error Severity Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................796

19.1.58 CES — Correctable Error Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................797

19.1.59 CEM — Correctable Error Mask Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................797

19.1.60 AECC — Advanced Error Capabilities and Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................798

19.1.61 RES — Root Error Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................798

19.1.62 PECR2 — PCI Express* Configuration Register 2

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................799

19.1.63 PEETM — PCI Express* Extended Test Mode Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................799

19.1.64 PEC1 — PCI Express* Configuration Register 1

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................799

20 High Precision Event Timer Registers..................................................................... 801

20.1 Memory Mapped Registers ................................................................................ 801

20.1.1 GCAP_ID—General Capabilities and Identification Register ...................... 803

20.1.2 GEN_CONF—General Configuration Register.......................................... 803

20.1.3 GINTR_STA—General Interrupt Status Register ..................................... 804

20.1.4 MAIN_CNT—Main Counter Value Register.............................................. 804

20.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register .................. 805

20.1.6 TIMn_COMP—Timer n Comparator Value Register ..................................808

Datasheet 25

20.1.7 TIMERn_PROCMSG_ROUT—Timer n Processor Message

Interrupt Rout Register...................................................................... 809

21 Serial Peripheral Interface (SPI) ........................................................................... 811

21.1 Serial Peripheral Interface Memory Mapped Configuration Registers ....................... 811

21.1.1 BFPR –BIOS Flash Primary Region Register

(SPI Memory Mapped Configuration Registers)...................................... 813

21.1.2 HSFS—Hardware Sequencing Flash Status Register

(SPI Memory Mapped Configuration Registers)...................................... 813

21.1.3 HSFC—Hardware Sequencing Flash Control Register

(SPI Memory Mapped Configuration Registers)...................................... 815

21.1.4 FADDR—Flash Address Register

(SPI Memory Mapped Configuration Registers)...................................... 815

21.1.5 FDATA0—Flash Data 0 Register

(SPI Memory Mapped Configuration Registers)...................................... 816

21.1.6 FDATAN—Flash Data [N] Register

(SPI Memory Mapped Configuration Registers)...................................... 816

21.1.7 FRAP—Flash Regions Access Permissions Register

(SPI Memory Mapped Configuration Registers)...................................... 817

21.1.8 FREG0—Flash Region 0 (Flash Descriptor) Register

(SPI Memory Mapped Configuration Registers)...................................... 818

21.1.9 FREG1—Flash Region 1 (BIOS Descriptor) Register

(SPI Memory Mapped Configuration Registers)...................................... 818

21.1.10 FREG2—Flash Region 2 (Intel® ME) Register

(SPI Memory Mapped Configuration Registers)...................................... 819

21.1.11 FREG3—Flash Region 3 (GbE) Register

(SPI Memory Mapped Configuration Registers)...................................... 819

21.1.12 FREG4—Flash Region 4 (Platform Data) Register

(SPI Memory Mapped Configuration Registers)...................................... 820

21.1.13 PR0—Protected Range 0 Register

(SPI Memory Mapped Configuration Registers)...................................... 820

21.1.14 PR1—Protected Range 1 Register

(SPI Memory Mapped Configuration Registers)...................................... 821

21.1.15 PR2—Protected Range 2 Register

(SPI Memory Mapped Configuration Registers)...................................... 822

21.1.16 PR3—Protected Range 3 Register

(SPI Memory Mapped Configuration Registers)...................................... 823

21.1.17 PR4—Protected Range 4 Register

(SPI Memory Mapped Configuration Registers)...................................... 824

21.1.18 SSFS—Software Sequencing Flash Status Register

(SPI Memory Mapped Configuration Registers)...................................... 825

21.1.19 SSFC—Software Sequencing Flash Control Register

(SPI Memory Mapped Configuration Registers)...................................... 826

21.1.20 PREOP—Prefix Opcode Configuration Register

(SPI Memory Mapped Configuration Registers)...................................... 827

21.1.21 OPTYPE—Opcode Type Configuration Register

(SPI Memory Mapped Configuration Registers)...................................... 827

21.1.22 OPMENU—Opcode Menu Configuration Register

(SPI Memory Mapped Configuration Registers)...................................... 828

21.1.23 BBAR—BIOS Base Address Configuration Register

(SPI Memory Mapped Configuration Registers)...................................... 829

21.1.24 FDOC—Flash Descriptor Observability Control Register

(SPI Memory Mapped Configuration Registers)...................................... 829

21.1.25 FDOD—Flash Descriptor Observability Data Register

(SPI Memory Mapped Configuration Registers)...................................... 830

21.1.26 AFC—Additional Flash Control Register

(SPI Memory Mapped Configuration Registers)...................................... 830

21.1.27 LVSCC— Host Lower Vendor Specific Component Capabilities Register

(SPI Memory Mapped Configuration Registers)...................................... 830

21.1.28 UVSCC— Host Upper Vendor Specific Component Capabilities Register

(SPI Memory Mapped Configuration Registers)...................................... 832

21.1.29 FPB — Flash Partition Boundary Register

(SPI Memory Mapped Configuration Registers)...................................... 833

21.1.30 SRDL — Soft Reset Data Lock Register

(SPI Memory Mapped Configuration Registers)...................................... 834

21.1.31 SRDC — Soft Reset Data Control Register

(SPI Memory Mapped Configuration Registers)...................................... 834

26 Datasheet

21.1.32 SRD — Soft Reset Data Register

(SPI Memory Mapped Configuration Registers) ......................................834

21.2 Flash Descriptor Records................................................................................... 835

21.3 OEM Section ................................................................................................... 835

21.4 GbE SPI Flash Program Registers ....................................................................... 835

21.4.1 GLFPR –Gigabit LAN Flash Primary Region Register

(GbE LAN Memory Mapped Configuration Registers)...............................836

21.4.2 HSFS—Hardware Sequencing Flash Status Register

(GbE LAN Memory Mapped Configuration Registers)...............................836

21.4.3 HSFC—Hardware Sequencing Flash Control Register

(GbE LAN Memory Mapped Configuration Registers)...............................838

21.4.4 FADDR—Flash Address Register

(GbE LAN Memory Mapped Configuration Registers)...............................838

21.4.5 FDATA0—Flash Data 0 Register

(GbE LAN Memory Mapped Configuration Registers)...............................839

21.4.6 FRAP—Flash Regions Access Permissions Register

(GbE LAN Memory Mapped Configuration Registers)...............................839

21.4.7 FREG0—Flash Region 0 (Flash Descriptor) Register

(GbE LAN Memory Mapped Configuration Registers)...............................840

21.4.8 FREG1—Flash Region 1 (BIOS Descriptor) Register

(GbE LAN Memory Mapped Configuration Registers)...............................840

21.4.9 FREG2—Flash Region 2 (Intel® ME) Register

(GbE LAN Memory Mapped Configuration Registers)...............................840

21.4.10 FREG3—Flash Region 3 (GbE) Register

(GbE LAN Memory Mapped Configuration Registers)...............................841

21.4.11 PR0—Protected Range 0 Register

(GbE LAN Memory Mapped Configuration Registers)...............................841

21.4.12 PR1—Protected Range 1 Register

(GbE LAN Memory Mapped Configuration Registers)...............................842

21.4.13 SSFS—Software Sequencing Flash Status Register

(GbE LAN Memory Mapped Configuration Registers)...............................843

21.4.14 SSFC—Software Sequencing Flash Control Register

(GbE LAN Memory Mapped Configuration Registers)...............................844

21.4.15 PREOP—Prefix Opcode Configuration Register

(GbE LAN Memory Mapped Configuration Registers)...............................845

21.4.16 OPTYPE—Opcode Type Configuration Register

(GbE LAN Memory Mapped Configuration Registers)...............................845

21.4.17 OPMENU—Opcode Menu Configuration Register

(GbE LAN Memory Mapped Configuration Registers)...............................846

22 Thermal Sensor Registers (D31:F6) ....................................................................... 847

22.1 PCI Bus Configuration Registers......................................................................... 847

22.1.1 VID—Vendor Identification Register ..................................................... 848

22.1.2 DID—Device Identification Register...................................................... 848

22.1.3 CMD—Command Register ...................................................................848

22.1.4 STS—Status Register .........................................................................849

22.1.5 RID—Revision Identification Register.................................................... 849

22.1.6 PI— Programming Interface Register.................................................... 849

22.1.7 SCC—Sub Class Code Register ............................................................ 850

22.1.8 BCC—Base Class Code Register ........................................................... 850

22.1.9 CLS—Cache Line Size Register ............................................................ 850

22.1.10 LT—Latency Timer Register.................................................................850

22.1.11 HTYPE—Header Type Register ............................................................. 850

22.1.12 TBAR—Thermal Base Register .............................................................851

22.1.13 TBARH—Thermal Base High DWord Register .........................................851

22.1.14 SVID—Subsystem Vendor ID Register .................................................. 851

22.1.15 SID—Subsystem ID Register...............................................................852

22.1.16 CAP_PTR—Capabilities Pointer Register ................................................ 852

22.1.17 INTLN—Interrupt Line Register............................................................ 852

22.1.18 INTPN—Interrupt Pin Register ............................................................. 852

22.1.19 TBARB—BIOS Assigned Thermal Base Address Register .......................... 853

22.1.20 TBARBH—BIOS Assigned Thermal Base High DWord

22.1.21 PID—PCI Power Management Capability ID Register............................... 853

22.1.22 PC—Power Management Capabilities Register ........................................ 854

22.1.23 PCS—Power Management Control And Status Register............................ 854

Datasheet 27

22.2 Thermal Memory Mapped Configuration Registers

(Thermal Sensor – D31:F26) ............................................................................ 855

22.2.1 TSIU—Thermal Sensor In Use Register ................................................ 856

22.2.2 TSE—Thermal Sensor Enable Register.................................................. 856

22.2.3 TSS—Thermal Sensor Status Register.................................................. 856

22.2.4 TSTR—Thermal Sensor Thermometer Read Register .............................. 857

22.2.5 TSTTP—Thermal Sensor Temperature Trip Point

22.2.6 TSCO—Thermal Sensor Catastrophic Lock-Down

22.2.7 TSES—Thermal Sensor Error Status Register ........................................ 859

22.2.8 TSGPEN—Thermal Sensor General Purpose Event

Enable Register ................................................................................ 860

22.2.9 TSPC—Thermal Sensor Policy Control Register ...................................... 861

22.2.10 PTA—PCH Temperature Adjust Register................................................ 862

22.2.11 TRC—Thermal Reporting Control Register............................................. 862

22.2.12 AE—Alert Enable Register................................................................... 863

22.2.13 PTL—Processor Temperature Limit Register .......................................... 863

22.2.14 PTV — Processor Temperature Value Register ....................................... 863

22.2.15 TT—Thermal Throttling Register.......................................................... 864

22.2.16 PHL—PCH Hot Level Register .............................................................. 864

22.2.17 TSPIEN—Thermal Sensor PCI Interrupt Enable Register.......................... 865

22.2.18 TSLOCK—Thermal Sensor Register Lock Control Register........................ 866

22.2.19 TC2—Thermal Compares 2 Register..................................................... 866

22.2.20 DTV—DIMM Temperature Values Register ............................................ 867

22.2.21 ITV—Internal Temperature Values Register .......................................... 867

23 Intel® Management Engine Subsystem Registers (D22:F[3:0]) ............................. 869

23.1 First Intel® Management Engine Interface (Intel®MEI) Configuration Registers

(Intel® MEI 1 — D22:F0) ................................................................................. 869

23.1.1 PCI Configuration Registers (Intel® MEI 1—D22:F0) .............................. 869

23.1.1.1 VID—Vendor Identification Register

(Intel® MEI 1—D22:F0)...................................................... 870

23.1.1.2 DID—Device Identification Register

(Intel® MEI 1—D22:F0)...................................................... 870

23.1.1.3 PCICMD—PCI Command Register

(Intel® MEI 1—D22:F0)...................................................... 871

23.1.1.4 PCISTS—PCI Status Register

(Intel® MEI 1—D22:F0)...................................................... 871

23.1.1.5 RID—Revision Identification Register

(Intel® MEI 1—D22:F0)...................................................... 872

23.1.1.6 CC—Class Code Register

(Intel® MEI 1—D22:F0)...................................................... 872

23.1.1.7 HTYPE—Header Type Register

(Intel® MEI 1—D22:F0)...................................................... 872

23.1.1.8 MEI0_MBAR—MEI0 MMIO Base Address Register

(Intel® MEI 1—D22:F0)...................................................... 872

23.1.1.9 SVID—Subsystem Vendor ID Register

(Intel® MEI 1—D22:F0)...................................................... 873

23.1.1.10 SID—Subsystem ID Register

(Intel® MEI 1—D22:F0)...................................................... 873

23.1.1.11 CAPP—Capabilities List Pointer Register

(Intel® MEI 1—D22:F0)...................................................... 873

23.1.1.12 INTR—Interrupt Information Register

(Intel® MEI 1—D22:F0)...................................................... 873

23.1.1.13 HFS—Host Firmware Status Register

(Intel® MEI 1—D22:F0)...................................................... 874

23.1.1.14 ME_UMA—Intel® Management Engine UMA Register

(Intel® MEI 1—D22:F0)...................................................... 874

23.1.1.15 GMES—General Intel® ME Status Register

(Intel® MEI 1—D22:F0)...................................................... 875

23.1.1.16 H_GS—Host General Status Register

(Intel® MEI 1—D22:F0)...................................................... 875

23.1.1.17 PID—PCI Power Management Capability ID Register

(Intel® MEI 1—D22:F0)...................................................... 875

23.1.1.18 PC—PCI Power Management Capabilities Register

(Intel® MEI 1—D22:F0)...................................................... 875

28 Datasheet

23.1.1.19 PMCS—PCI Power Management Control and Status

23.1.1.20 MID—Message Signaled Interrupt Identifiers Register

(Intel® MEI 1—D22:F0) ...................................................... 876

23.1.1.21 MC—Message Signaled Interrupt Message Control Register

(Intel® MEI 1—D22:F0) ...................................................... 877

23.1.1.22 MA—Message Signaled Interrupt Message Address Register

(Intel® MEI 1—D22:F0) ...................................................... 877

23.1.1.23 MUA—Message Signaled Interrupt Upper Address Register

(Intel® MEI 1—D22:F0) ...................................................... 877

23.1.1.24 MD—Message Signaled Interrupt Message Data Register

(Intel® MEI 1—D22:F0) ...................................................... 877

23.1.1.25 HIDM—MEI Interrupt Delivery Mode Register

(Intel® MEI 1—D22:F0) ...................................................... 878

23.1.1.26 HERES—Intel® MEI Extend Register Status

(Intel® MEI 1—D22:F0) ...................................................... 878

23.1.1.27 HERX—Intel® MEI Extend Register DWX

(Intel® MEI 1—D22:F0) ...................................................... 879

23.1.2 MEI0_MBAR—Intel® MEI 1 MMIO Registers...........................................879

23.1.2.1 H_CB_WW—Host Circular Buffer Write Window Register

(Intel® MEI 1 MMIO Register) .............................................. 879

23.1.2.2 H_CSR—Host Control Status Register

(Intel® MEI 1 MMIO Register) .............................................. 880

23.1.2.3 ME_CB_RW—Intel® ME Circular Buffer Read Window Register

(Intel® MEI 1 MMIO Register) .............................................. 881

23.1.2.4 ME_CSR_HA—Intel® ME Control Status Host Access Register

(Intel® MEI 1 MMIO Register) .............................................. 881

23.2 Second Intel® Management Engine Interface

(Intel® MEI 2) Configuration Registers

(Intel® MEI 2—D22:F1).................................................................................... 882

23.2.1 PCI Configuration Registers (Intel® MEI 2—D22:F2)............................... 882

23.2.1.1 VID—Vendor Identification Register

(Intel® MEI 2—D22:F1) ...................................................... 883

23.2.1.2 DID—Device Identification Register

(Intel® MEI 2—D22:F1) ...................................................... 883

23.2.1.3 PCICMD—PCI Command Register

(Intel® MEI 2—D22:F1) ...................................................... 884

23.2.1.4 PCISTS—PCI Status Register

(Intel® MEI 2—D22:F1) ...................................................... 884

23.2.1.5 RID—Revision Identification Register

(Intel® MEI 2—D22:F1) ...................................................... 885

23.2.1.6 CC—Class Code Register

(Intel® MEI 2—D22:F1) ...................................................... 885

23.2.1.7 HTYPE—Header Type Register

(Intel® MEI 2—D22:F1) ...................................................... 885

23.2.1.8 MEI_MBAR—Intel® MEI MMIO Base Address Register

(Intel® MEI 2—D22:F1) ...................................................... 885

23.2.1.9 SVID—Subsystem Vendor ID Register

(Intel® MEI 2—D22:F1) ...................................................... 886

23.2.1.10 SID—Subsystem ID Register

(Intel® MEI 2—D22:F1) ...................................................... 886

23.2.1.11 CAPP—Capabilities List Pointer Register

(Intel® MEI 2—D22:F1) ...................................................... 886

23.2.1.12 INTR—Interrupt Information Register

(Intel® MEI 2—D22:F1) ...................................................... 886

23.2.1.13 HFS—Host Firmware Status Register

(Intel® MEI 2—D22:F1) ...................................................... 887

23.2.1.14 GMES—General Intel® ME Status Register

(Intel® MEI 2—D22:F1) ...................................................... 887

23.2.1.15 H_GS—Host General Status Register

(Intel® MEI 2—D22:F1) ...................................................... 887

23.2.1.16 PID—PCI Power Management Capability ID Register

(Intel® MEI 2—D22:F1) ...................................................... 888

23.2.1.17 PC—PCI Power Management Capabilities Register

(Intel® MEI 2—D22:F1) ...................................................... 888

23.2.1.18 PMCS—PCI Power Management Control and Status

Datasheet 29

23.2.1.19 MID—Message Signaled Interrupt Identifiers Register

(Intel® MEI 2—D22:F1)...................................................... 889

23.2.1.20 MC—Message Signaled Interrupt Message Control Register

(Intel® MEI 2—D22:F1)...................................................... 889

23.2.1.21 MA—Message Signaled Interrupt Message Address Register

(Intel® MEI 2—D22:F1)...................................................... 889

23.2.1.22 MUA—Message Signaled Interrupt Upper Address Register

(Intel® MEI 2—D22:F1)...................................................... 890

23.2.1.23 MD—Message Signaled Interrupt Message Data Register

(Intel® MEI 2—D22:F1)...................................................... 890

23.2.1.24 HIDM—Intel® MEI Interrupt Delivery Mode Register

(Intel® MEI 2—D22:F1)...................................................... 890

23.2.1.25 HERES—Intel® MEI Extend Register Status

(Intel® MEI 2—D22:F1)...................................................... 891

23.2.1.26 HERX—Intel® MEI Extend Register DWX

(Intel® MEI 2—D22:F1)...................................................... 891

23.2.2 MEI1_MBAR—Intel® MEI 2 MMIO Registers .......................................... 892

23.2.2.1 H_CB_WW—Host Circular Buffer Write Window

(Intel® MEI 2 MMIO Register) ............................................. 892

23.2.2.2 H_CSR—Host Control Status Register

(Intel® MEI 2 MMIO Register) ............................................. 893

23.2.2.3 ME_CB_RW—Intel® ME Circular Buffer Read Window Register

(Intel® MEI 2 MMIO Register) ............................................. 894

23.2.2.4 ME_CSR_HA—Intel® ME Control Status Host Access Register

(Intel® MEI 2 MMIO Register) ............................................. 894

23.3 IDE Redirect IDER Registers (IDER — D22:F2) .................................................... 895

23.3.1 PCI Configuration Registers (IDER—D22:F2)......................................... 895

23.3.1.1 VID—Vendor Identification Register (IDER—D22:F2) .............. 896

23.3.1.2 DID—Device Identification Register (IDER—D22:F2)............... 896

23.3.1.3 PCICMD— PCI Command Register (IDER—D22:F2)................. 896

23.3.1.4 PCISTS—PCI Device Status Register (IDER—D22:F2) ............. 897

23.3.1.5 RID—Revision Identification Register (IDER—D22:F2)............. 897

23.3.1.6 CC—Class Codes Register (IDER—D22:F2) ............................ 897

23.3.1.7 CLS—Cache Line Size Register (IDER—D22:F2) ..................... 897

23.3.1.8 PCMDBA—Primary Command Block IO Bar

23.3.1.9 PCTLBA—Primary Control Block Base Address

23.3.1.10 SCMDBA—Secondary Command Block Base Address

23.3.1.11 SCTLBA—Secondary Control Block base Address

23.3.1.12 LBAR—Legacy Bus Master Base Address Register

(IDER—D22:F2) ................................................................ 899

23.3.1.13 SVID—Subsystem Vendor ID Register (IDER—D22:F2) ........... 899

23.3.1.14 SID—Subsystem ID Register (IDER—D22:F2)........................ 899

23.3.1.15 CAPP—Capabilities List Pointer Register

(IDER—D22:F2) ................................................................ 900

23.3.1.16 INTR—Interrupt Information Register

(IDER—D22:F2) ................................................................ 900

23.3.1.17 PID—PCI Power Management Capability ID Register

(IDER—D22:F2) ................................................................ 900

23.3.1.18 PC—PCI Power Management Capabilities Register

(IDER—D22:F2) ................................................................ 901

23.3.1.19 PMCS—PCI Power Management Control and Status

23.3.1.20 MID—Message Signaled Interrupt Capability ID

23.3.1.21 MC—Message Signaled Interrupt Message Control

23.3.1.22 MA—Message Signaled Interrupt Message Address

23.3.1.23 MAU—Message Signaled Interrupt Message Upper

Address Register (IDER—D22:F2) ........................................ 902

23.3.1.24 MD—Message Signaled Interrupt Message Data

23.3.2 IDER BAR0 Registers ......................................................................... 903

30 Datasheet

23.3.2.1 IDEDATA—IDE Data Register (IDER—D22:F2)........................ 904

23.3.2.2 IDEERD1—IDE Error Register DEV1

(IDER—D22:F2)................................................................. 904

23.3.2.3 IDEERD0—IDE Error Register DEV0

(IDER—D22:F2)................................................................. 905

23.3.2.4 IDEFR—IDE Features Register

(IDER—D22:F2)................................................................. 905

23.3.2.5 IDESCIR—IDE Sector Count In Register

(IDER—D22:F2)................................................................. 905

23.3.2.6 IDESCOR1—IDE Sector Count Out Register Device 1

23.3.2.7 IDESCOR0—IDE Sector Count Out Register Device

0 Register (IDER—D22:F2).................................................. 906

23.3.2.8 IDESNOR0—IDE Sector Number Out Register

Device 0 Register (IDER—D22:F2)........................................906

23.3.2.9 IDESNOR1—IDE Sector Number Out Register

Device 1 Register (IDER—D22:F2)........................................907

23.3.2.10 IDESNIR—IDE Sector Number In Register

(IDER—D22:F2)................................................................. 907

23.3.2.11 IDECLIR—IDE Cylinder Low In Register

(IDER—D22:F2)................................................................. 907

23.3.2.12 IDCLOR1—IDE Cylinder Low Out Register Device 1

23.3.2.13 IDCLOR0—IDE Cylinder Low Out Register Device 0

23.3.2.14 IDCHOR0—IDE Cylinder High Out Register Device 0

23.3.2.15 IDCHOR1—IDE Cylinder High Out Register Device 1

23.3.2.16 IDECHIR—IDE Cylinder High In Register

(IDER—D22:F2)................................................................. 909

23.3.2.17 IDEDHIR—IDE Drive/Head In Register

(IDER—D22:F2)................................................................. 909

23.3.2.18 IDDHOR1—IDE Drive Head Out Register Device 1

23.3.2.19 IDDHOR0—IDE Drive Head Out Register Device 0

23.3.2.20 IDESD0R—IDE Status Device 0 Register

(IDER—D22:F2)................................................................. 911

23.3.2.21 IDESD1R—IDE Status Device 1 Register

(IDER—D22:F2)................................................................. 912

23.3.2.22 IDECR—IDE Command Register (IDER—D22:F2) ....................912

23.3.3 IDER BAR1 Registers ......................................................................... 913

23.3.3.1 IDDCR—IDE Device Control Register (IDER—D22:F2) ............. 913

23.3.3.2 IDASR—IDE Alternate Status Register (IDER—D22:F2) ........... 913

23.3.4 IDER BAR4 Registers ......................................................................... 914

23.3.4.1 IDEPBMCR—IDE Primary Bus Master Command

23.3.4.2 IDEPBMDS0R—IDE Primary Bus Master Device

Specific 0 Register (IDER—D22:F2) ...................................... 915

23.3.4.3 IDEPBMSR—IDE Primary Bus Master Status

23.3.4.4 IDEPBMDS1R—IDE Primary Bus Master Device

Specific 1 Register (IDER—D22:F2) ...................................... 916

23.3.4.5 IDEPBMDTPR0—IDE Primary Bus Master Descriptor

Table Pointer Byte 0 Register (IDER—D22:F2) ....................... 916

23.3.4.6 IDEPBMDTPR1—IDE Primary Bus Master Descriptor

Table Pointer Byte 1 Register (IDER—D22:F2) ....................... 917

23.3.4.7 IDEPBMDTPR2—IDE Primary Bus Master Descriptor

Table Pointer Byte 2 Register (IDER—D22:F2) ....................... 917

23.3.4.8 IDEPBMDTPR3—IDE Primary Bus Master Descriptor

Table Pointer Byte 3 Register (IDER—D22:F2) ....................... 917

23.3.4.9 IDESBMCR—IDE Secondary Bus Master Command

23.3.4.10 IDESBMDS0R—IDE Secondary Bus Master Device

Specific 0 Register (IDER—D22:F2) ...................................... 918

Datasheet 31

23.3.4.11 IDESBMSR—IDE Secondary Bus Master Status

23.3.4.12 IDESBMDS1R—IDE Secondary Bus Master Device

Specific 1 Register (IDER—D22:F2)...................................... 919

23.3.4.13 IDESBMDTPR0—IDE Secondary Bus Master Descriptor

Table Pointer Byte 0 Register (IDER—D22:F2) ....................... 919

23.3.4.14 IDESBMDTPR1—IDE Secondary Bus Master Descriptor

Table Pointer Byte 1 Register (IDER—D22:F2) ....................... 920

23.3.4.15 IDESBMDTPR2—IDE Secondary Bus Master Descriptor

Table Pointer Byte 2 Register (IDER—D22:F2) ....................... 920

23.3.4.16 IDESBMDTPR3—IDE Secondary Bus Master Descriptor

Table Pointer Byte 3 Register (IDER—D22:F2) ....................... 920

23.4 Serial Port for Remote Keyboard and Text (KT)

Redirection (KT — D22:F3) ............................................................................... 921

23.4.1 PCI Configuration Registers (KT — D22:F3) .......................................... 921

23.4.1.1 VID—Vendor Identification Register (KT—D22:F3).................. 922

23.4.1.2 DID—Device Identification Register (KT—D22:F3) .................. 922

23.4.1.3 CMD—Command Register (KT—D22:F3)............ ................... 922

23.4.1.4 STS—Device Status Register (KT—D22:F3) ........................... 923

23.4.1.5 RID—Revision ID Register (KT—D22:F3)............................... 923

23.4.1.6 CC—Class Codes Register (KT—D22:F3) ............................... 923

23.4.1.7 CLS—Cache Line Size Register (KT—D22:F3)......................... 924

23.4.1.8 KTIBA—KT IO Block Base Address Register

(KT—D22:F3).................................................................... 924

23.4.1.9 KTMBA—KT Memory Block Base Address Register

(KT—D22:F3).................................................................... 924

23.4.1.10 SVID—Subsystem Vendor ID Register (KT—D22:F3) .............. 925

23.4.1.11 SID—Subsystem ID Register (KT—D22:F3) ........................... 925

23.4.1.12 CAP—Capabilities Pointer Register (KT—D22:F3).................... 925

23.4.1.13 INTR—Interrupt Information Register (KT—D22:F3) ............... 925

23.4.1.14 PID—PCI Power Management Capability ID Register

(KT—D22:F3).................................................................... 926

23.4.1.15 PC—PCI Power Management Capabilities ID Register

(KT—D22:F3).................................................................... 926

23.4.1.16 MID—Message Signaled Interrupt Capability ID

23.4.1.17 MC—Message Signaled Interrupt Message Control

23.4.1.18 MA—Message Signaled Interrupt Message Address

23.4.1.19 MAU—Message Signaled Interrupt Message Upper

Address Register (KT—D22:F3) ........................................... 928

23.4.1.20 MD—Message Signaled Interrupt Message Data

23.4.2 KT IO/Memory Mapped Device Registers .............................................. 928

23.4.2.1 KTRxBR—KT Receive Buffer Register (KT—D22:F3) ................ 929

23.4.2.2 KTTHR—KT Transmit Holding Register (KT—D22:F3) .............. 929

23.4.2.3 KTDLLR—KT Divisor Latch LSB Register (KT—D22:F3) ............ 929

23.4.2.4 KTIER—KT Interrupt Enable Register (KT—D22:F3) ................ 930

23.4.2.5 KTDLMR—KT Divisor Latch MSB Register (KT—D22:F3)........... 930

23.4.2.6 KTIIR—KT Interrupt Identification Register

(KT—D22:F3).................................................................... 931

23.4.2.7 KTFCR—KT FIFO Control Register (KT—D22:F3)..................... 931

23.4.2.8 KTLCR—KT Line Control Register (KT—D22:F3) ..................... 932

23.4.2.9 KTMCR—KT Modem Control Register (KT—D22:F3) ................ 932

23.4.2.10 KTLSR—KT Line Status Register (KT—D22:F3)....................... 933

23.4.2.11 KTMSR—KT Modem Status Register (KT—D22:F3).................. 934

32 Datasheet

Figures

2-1 PCH Interface Signals Block Diagram (not all signals are on all SKUs)..........................56

2-2 Example External RTC Circuit.................................................................................92

4-1 PCH High-Level Clock Diagram ............................................................................. 115

5-1 Generation of SERR# to Platform ......................................................................... 126

5-2 LPC Interface Diagram ........................................................................................136

5-3 PCH DMA Controller............................................................................................ 141

5-4 DMA Request Assertion through LDRQ# ................................................................144

5-5 TCO Legacy/Compatible Mode SMBus Configuration ................................................ 194

5-6 Advanced TCO Mode...........................................................................................195

5-7 Serial Post over GPIO Reference Circuit .................................................................197

5-8 Flow for Port Enable / Device Present Bits.............................................................. 205

5-9 Serial Data transmitted over the SGPIO Interface ...................................................209

5-10 EHCI with USB 2.0 with Rate Matching Hub ........................................................... 224

5-11 PCH Intel® Management Engine High-Level Block Diagram ...................................... 254

5-12 Flash Descriptor Sections .................................................................................... 257

5-13 Analog Port Characteristics .................................................................................. 266

5-14 LVDS Signals and Swing Voltage .......................................................................... 268

5-15 LVDS Clock and Data Relationship ........................................................................ 268

5-16 Panel Power Sequencing .....................................................................................269

5-17 HDMI Overview.................................................................................................. 270

5-18 DisplayPort Overview..........................................................................................271

5-19 SDVO Conceptual Block Diagram.......................................................................... 273

6-1 Desktop PCH Ballout (Top View - Upper Left) ......................................................... 279

6-2 Desktop PCH Ballout (Top View - Lower Left) ......................................................... 280

6-3 Desktop PCH Ballout (Top View - Upper Right) ....................................................... 281

6-4 Desktop PCH Ballout (Top View - Lower Right) .......................................................282

6-5 Mobile PCH Ballout (Top View - Upper Left)............................................................ 290

6-6 Mobile PCH Ballout (Top View - Lower Left)............................................................ 291

6-7 Mobile PCH Ballout (Top View - Upper Right).......................................................... 292

6-8 Mobile PCH Ballout (Top View - Lower Right)..........................................................293

6-9 Mobile SFF PCH Package (Top View – Upper Left) ................................................... 302

6-10 Mobile SFF PCH Package (Top View – Lower Left) ................................................... 303

6-11 Mobile SFF PCH Package (Top View – Upper Right) ................................................. 304

6-12 Mobile SFF PCH Package (Top View – Lower Right) ................................................. 305

7-1 Desktop PCH Package Drawing.............................................................................308

7-2 Mobile PCH Package Drawing ...............................................................................310

7-3 Mobile SFF PCH Package Drawing .........................................................................312

8-1 G3 w/RTC Loss to S4/S5 (With Deep S4/S5 Support) Timing Diagram ....................... 350

8-2 G3 w/RTC Loss to S4/S5 (Without Deep S4/S5 Support) Timing Diagram .................. 350

8-3 S5 to S0 Timing Diagram ....................................................................................351

8-4 S3/M3 to S0 Timing Diagram ...............................................................................352

8-5 S5/Moff - S5/M3 Timing Diagram .........................................................................352

8-6 S0 to S5 Timing Diagram ....................................................................................353

8-7 S4/S5 to Deep S4/S5 to G3 w/ RTC Loss Timing Diagram ........................................ 354

8-8 DRAMPWROK Timing Diagram..............................................................................354

8-9 Clock Cycle Time................................................................................................ 355

8-10 Transmitting Position (Data to Strobe) .................................................................. 355

8-11 Clock Timing...................................................................................................... 355

8-13 Setup and Hold Times......................................................................................... 356

8-14 Float Delay........................................................................................................356

8-15 Pulse Width ....................................................................................................... 356

8-12 Valid Delay from Rising Clock Edge ....................................................................... 356

8-16 Output Enable Delay........................................................................................... 357

8-17 USB Rise and Fall Times...................................................................................... 357

8-18 USB Jitter .........................................................................................................357

8-19 USB EOP Width .................................................................................................. 358

8-20 SMBus Transaction .............................................................................................358

8-21 SMBus Timeout..................................................................................................358

8-22 SPI Timings.......................................................................................................359

8-23 Intel® High Definition Audio Input and Output Timings............................................ 359

8-24 Dual Channel Interface Timings............................................................................ 360

8-25 Dual Channel Interface Timings............................................................................ 360

8-26 LVDS Load and Transition Times ..........................................................................360

8-27 Transmitting Position (Data to Strobe) .................................................................. 361

8-28 PCI Express Transmitter Eye................................................................................361

Datasheet 33

8-29 PCI Express Receiver Eye.................................................................................... 362

8-30 Measurement Points for Differential Waveforms. .................................................... 363

8-31 PCH Test Load................................................................................................... 364

8-32 Controller Link Receive Timings ........................................................................... 364

8-33 Controller Link Receive Slew Rate ........................................................................ 364

Tables

1-1 Industry Specifications ......................................................................................... 42

1-2 Desktop Intel® 6 Series Chipset SKUs .................................................................... 51

1-3 Mobile Intel® 6 Series Chipset SKUs....................................................................... 52

1-4 Server/Workstation Intel® C200 Series Chipset SKUs ............................................... 53

2-1 Direct Media Interface Signals ............................................................................... 57

2-2 PCI Express* Signals............................................................................................ 57

2-3 PCI Interface Signals............................................................................................ 58

2-4 Serial ATA Interface Signals .................................................................................. 60

2-5 LPC Interface Signals ........................................................................................... 63

2-6 Interrupt Signals ................................................................................................. 63

2-7 USB Interface Signals........................................................................................... 64

2-8 Power Management Interface Signals ..................................................................... 65

2-9 Processor Interface Signals ................................................................................... 69

2-10 SM Bus Interface Signals ...................................................................................... 69

2-11 System Management Interface Signals ................................................................... 69

2-12 Real Time Clock Interface ..................................................................................... 70

2-13 Miscellaneous Signals ........................................................................................... 70

2-14 Intel® High Definition Audio Link Signals................................................................. 72

2-15 Controller Link Signals.......................................................................................... 73

2-16 Serial Peripheral Interface (SPI) Signals.................................................................. 73

2-17 Thermal Signals................................................................................................... 73

2-18 Testability Signals................................................................................................ 74

2-19 Clock Interface Signals ......................................................................................... 74

2-20 LVDS Interface Signals ......................................................................................... 77

2-21 Analog Display Interface Signals ............................................................................ 78

2-22 Intel® Flexible Display Interface Signals.................................................................. 78

2-23 Digital Display Interface Signals............................................................................. 79

2-24 General Purpose I/O Signals.................................................................................. 82

2-25 Manageability Signals ........................................................................................... 86

2-26 Power and Ground Signals .................................................................................... 87

2-27 Functional Strap Definitions................................................................................... 89

3-1 Integrated Pull-Up and Pull-Down Resistors ............................................................. 93

3-2 Power Plane and States for Output and I/O Signals for Desktop Configurations ............ 95

3-3 Power Plane and States for Output and I/O Signals for Mobile Configurations ............. 101

3-4 Power Plane for Input Signals for Desktop Configurations ........................................ 107

3-5 Power Plane for Input Signals for Mobile Configurations .......................................... 110

4-1 PCH Clock Inputs ............................................................................................... 113

4-2 Clock Outputs ................................................................................................... 114

4-3 PCH PLLs .......................................................................................................... 116

4-4 SSC Blocks ....................................................................................................... 117

5-1 PCI Bridge Initiator Cycle Types........................................................................... 120

5-2 Type 1 Address Format....................................................................................... 122

5-3 MSI versus PCI IRQ Actions................................................................................. 124

5-4 LAN Mode Support ............................................................................................. 131

5-5 LPC Cycle Types Supported ................................................................................. 137

5-6 Start Field Bit Definitions .................................................................................... 137

5-7 Cycle Type Bit Definitions ................................................................................... 138

5-8 Transfer Size Bit Definition.................................................................................. 138

5-9 SYNC Bit Definition ............................................................................................ 138

5-10 DMA Transfer Size ............................................................................................. 142

5-11 Address Shifting in 16-Bit I/O DMA Transfers......................................................... 143

5-12 Counter Operating Modes ................................................................................... 148

5-13 Interrupt Controller Core Connections................................................................... 150

5-14 Interrupt Status Registers................................................................................... 151

5-15 Content of Interrupt Vector Byte.......................................................................... 151

5-16 APIC Interrupt Mapping1 .................................................................................... 157

5-17 Stop Frame Explanation...................................................................................... 160

5-18 Data Frame Format............................................................................................ 161

5-19 Configuration Bits Reset by RTCRST# Assertion ..................................................... 164

34 Datasheet

5-20 INIT# Going Active.............................................................................................166

5-21 NMI Sources...................................................................................................... 167

5-22 General Power States for Systems Using the PCH ...................................................168

5-23 State Transition Rules for the PCH ........................................................................ 169

5-24 System Power Plane ...........................................................................................170

5-25 Causes of SMI and SCI ....................................................................................... 171

5-26 Sleep Types....................................................................................................... 175

5-27 Causes of Wake Events .......................................................................................176

5-28 GPI Wake Events ...............................................................................................177

5-29 Transitions Due to Power Failure .......................................................................... 178

5-30 Supported Deep S4/S5 Policy Configurations..........................................................179

5-31 Deep S4/S5 Wake Events.................................................................................... 179

5-32 Transitions Due to Power Button .......................................................................... 180

5-33 Transitions Due to RI# Signal ..............................................................................181

5-34 Write Only Registers with Read Paths in ALT Access Mode........................................184

5-35 PIC Reserved Bits Return Values .......................................................................... 186

5-36 Register Write Accesses in ALT Access Mode .......................................................... 186

5-37 SLP_LAN# Pin Behavior ...................................................................................... 188

5-38 Causes of Host and Global Resets.........................................................................190

5-39 Event Transitions that Cause Messages ................................................................. 194

5-40 Multi-activity LED Message Type........................................................................... 208

5-41 Legacy Replacement Routing ...............................................................................211

5-42 Debug Port Behavior........................................................................................... 218

5-43 I2C Block Read...................................................................................................228

5-44 Enable for SMBALERT# .......................................................................................230

5-45 Enables for SMBus Slave Write and SMBus Host Events ...........................................231

5-46 Enables for the Host Notify Command ................................................................... 231

5-47 Slave Write Registers..........................................................................................233

5-48 Command Types ................................................................................................ 233

5-49 Slave Read Cycle Format..................................................................................... 234

5-50 Data Values for Slave Read Registers.................................................................... 235

5-51 Host Notify Format ............................................................................................. 237

5-52 PCH Thermal Throttle States (T-states) .................................................................240

5-53 PCH Thermal Throttling Configuration Registers...................................................... 240

5-54 I2C Write Commands to the Intel® ME .................................................................. 242

5-55 Block Read Command – Byte Definition................................................................. 243

5-56 Region Size versus Erase Granularity of Flash Components ...................................... 256

5-57 Region Access Control Table ................................................................................258

5-58 Hardware Sequencing Commands and Opcode Requirements ................................... 261

5-59 Flash Protection Mechanism Summary .................................................................. 263

5-60 Recommended Pinout for 8-Pin Serial Flash Device ................................................. 264

5-61 Recommended Pinout for 16-Pin Serial Flash Device ............................................... 264

5-59 PCH Supported Audio Formats over HDMI and DisplayPort* ..................................... 272

5-60 PCH Digital Port Pin Mapping................................................................................274

5-61 Display Co-Existence Table.................................................................................. 275

6-1 Desktop PCH Ballout By Signal Name .................................................................... 283

6-2 Mobile PCH Ballout By Signal Name ...................................................................... 294

8-1 Storage Conditions and Thermal Junction Operating Temperature Limits....................313

8-2 Mobile Thermal Design Power ..............................................................................314

8-3 PCH Absolute Maximum Ratings ........................................................................... 314

8-4 PCH Power Supply Range .................................................................................... 315

8-5 Measured ICC (Desktop Only)............................................................................... 315

8-6 Measured ICC (Mobile Only) .................................................................................316

8-7 DC Characteristic Input Signal Association ............................................................. 318

8-8 DC Input Characteristics ..................................................................................... 320

8-9 DC Characteristic Output Signal Association ........................................................... 323

8-10 DC Output Characteristics ................................................................................... 325

8-11 Other DC Characteristics .....................................................................................327

8-12 Signal Groups .................................................................................................... 328

8-13 CRT DAC Signal Group DC Characteristics: Functional Operating Range

(VccADAC = 3.3 V ±5%).....................................................................................328

8-14 LVDS Interface: Functional Operating Range (VccALVDS = 1.8 V ±5%)..................... 329

8-15 Display Port Auxiliary Signal Group DC Characteristics............................................. 329

8-16 PCI Express* Interface Timings............................................................................ 330

8-17 HDMI Interface Timings (DDP[D:B][3:0])Timings ...................................................331

8-18 SDVO Interface Timings ...................................................................................... 331

8-19 DisplayPort Interface Timings (DDP[D:B][3:0]) ...................................................... 332

Datasheet 35

8-20 DisplayPort Aux Interface ................................................................................... 333

8-21 DDC Characteristics ........................................................................................... 333

8-22 LVDS Interface AC Characteristics at Various Frequencies ....................................... 334

8-23 CRT DAC AC Characteristics ................................................................................ 336

8-24 Clock Timings.................................................................................................... 336

8-25 PCI Interface Timing .......................................................................................... 340

8-26 Universal Serial Bus Timing ................................................................................. 341

8-27 SATA Interface Timings ...................................................................................... 342

8-28 SMBus and SMLink Timing .................................................................................. 343

8-29 Intel® High Definition Audio Timing...................................................................... 344

8-30 LPC Timing ....................................................................................................... 344

8-31 Miscellaneous Timings ........................................................................................ 344

8-32 SPI Timings (20 MHz)......................................................................................... 345

8-33 SPI Timings (33 MHz)......................................................................................... 345

8-34 SPI Timings (50 MHz)......................................................................................... 346

8-35 SST Timings (Server/Workstation Only) ................................................................ 346

8-36 Controller Link Receive Timings ........................................................................... 347

8-37 Power Sequencing and Reset Signal Timings.......................................................... 347

9-1 PCI Devices and Functions .................................................................................. 366

9-2 Fixed I/O Ranges Decoded by PCH ....................................................................... 368

9-3 Variable I/O Decode Ranges................................................................................ 370

9-4 Memory Decode Ranges from Processor Perspective ............................................... 371

9-5 SPI Mode Address Swapping ............................................................................... 373

10-1 Chipset Configuration Register Memory Map (Memory Space) .................................. 375

11-1 PCI Bridge Register Address Map (PCI-PCI—D30:F0) .............................................. 417

12-1 Gigabit LAN Configuration Registers Address Map

(Gigabit LAN —D25:F0) ...................................................................................... 435

13-1 LPC Interface PCI Register Address Map (LPC I/F—D31:F0) ..................................... 449

13-2 DMA Registers................................................................................................... 476

13-3 PIC Registers .................................................................................................... 486

13-4 APIC Direct Registers ......................................................................................... 494

13-5 APIC Indirect Registers....................................................................................... 494

13-6 RTC I/O Registers .............................................................................................. 499

13-7 RTC (Standard) RAM Bank .................................................................................. 500

13-8 Processor Interface PCI Register Address Map ....................................................... 504

13-9 Power Management PCI Register Address Map (PM—D31:F0)................................... 507

13-10 APM Register Map .............................................................................................. 517

13-11 ACPI and Legacy I/O Register Map ....................................................................... 518

13-12 TCO I/O Register Address Map............................................................................. 536

13-13 Registers to Control GPIO Address Map................................................................. 543

14-1 SATA Controller PCI Register Address Map (SATA–D31:F2)...................................... 553

14-2 Bus Master IDE I/O Register Address Map ............................................................. 580

14-3 AHCI Register Address Map ................................................................................. 588

14-4 Generic Host Controller Register Address Map........................................................ 589

14-5 Port [5:0] DMA Register Address Map................................................................... 599

15-1 SATA Controller PCI Register Address Map (SATA–D31:F5)...................................... 615

15-2 Bus Master IDE I/O Register Address Map ............................................................. 631

16-1 USB EHCI PCI Register Address Map (USB EHCI—D29:F0, D26:F0) .......................... 639

16-2 Enhanced Host Controller Capability Registers ....................................................... 662

16-3 Enhanced Host Controller Operational Register Address Map.................................... 665

16-4 Debug Port Register Address Map ........................................................................ 680

17-1 Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0) .................................................................. 685

17-2 Intel® High Definition Audio Memory Mapped Configuration Registers

Address Map (Intel® High Definition Audio D27:F0) ................................................ 707

17-3 Configuration Default ......................................................................................... 733

17-4 Configuration Data Structure............................................................................... 733

17-5 Port Connectivity ............................................................................................... 735

17-6 Location ........................................................................................................... 735

17-7 Default Device................................................................................................... 736

17-8 Connection Type................................................................................................ 736

17-9 Color................................................................................................................ 737

17-10 Misc................................................................................................................. 737

18-1 SMBus Controller PCI Register Address Map (SMBus—D31:F3)................................. 739

18-2 SMBus I/O and Memory Mapped I/O Register Address Map...................................... 746

19-1 PCI Express* Configuration Registers Address Map

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ..................................................... 757

36 Datasheet

20-1 Memory-Mapped Register Address Map .................................................................801

21-1 Serial Peripheral Interface (SPI) Register Address Map

(SPI Memory Mapped Configuration Registers) ....................................................... 811

21-2 Gigabit LAN SPI Flash Program Register Address Map

(GbE LAN Memory Mapped Configuration Registers)................................................ 835

22-1 Thermal Sensor Register Address Map...................................................................847

22-2 Thermal Memory Mapped Configuration Register Address Map..................................855

23-1 Intel® MEI 1 Configuration Registers Address Map

(Intel® MEI 1—D22:F0) ......................................................................................869

23-2 Intel® MEI 1 MMIO Register Address Map ..............................................................879

23-3 Intel® MEI 2 Configuration Registers Address Map

(Intel® MEI 2—D22:F1) ......................................................................................882

23-4 Intel® MEI 2 MMIO Register Address Map ..............................................................892

23-5 IDE Redirect Function IDER Register Address Map .................................................. 895

23-6 IDER BAR0 Register Address Map .........................................................................903

23-7 IDER BAR1 Register Address Map .........................................................................913

23-8 IDER BAR4 Register Address Map .........................................................................914

23-9 Serial Port for Remote Keyboard and Text (KT) Redirection Register

Address Map...................................................................................................... 921

23-10 KT IO/Memory Mapped Device Register Address Map .............................................. 928

Datasheet 37

Revision History

Revision Description Date

001 • Initial Release January 2011

002

• Added the Intel Q67, B65, H61, QM67, UM67, and QS67 Chipset

•Chapter 1

—Updated Table 1-1

— Updated following sub-sections in Section 1.2.1

- Intel® Active Management Technology (Intel® AMT)

- SOL Function

- KVM (new)

- IDE-R Function

•Chapter 5

— Updated Table 5-22, 5-23, and 5-29.

•Chapter 6

— Added SFF Top View Ballout figures in Section 6.3.

•Chapter 8

— Updated Table 8-1 to add Tj for Mobile.

•Chapter 9

— Updated Table 9-3, Variable I/O Decode Ranges

•Chapter 10

— Updated Section 10.1.54, DEEP_S4_POL—Deep S4/S5 From S4 Power Policies

— Updated Section 10.1.55, DEEP_S5_POL—Deep S4/S5 From S5 Power Policies

— Updated Bits 29:28 in Section 10.1.78, CG—Clock Gating

•Chapter 13

— Updated Section 13.8.1.8, PMIR—Power Management Initialization Register (PM—

D31:F0)

•Chapter 17

— Added Section 17.1.1.20, HDINIT1—Intel® High Definition Audio Initialization

•Chapter 23

— Added Section 23.1.2, MEI0_MBAR—Intel® MEI 1 MMIO Registers

• Updated Section 23.2.2.2, CG—Clock Gating

February 2011

003 • Added Intel Q65 Chipset April 2011

004 • Added Intel C200 Series Chipset April 2011

005 • Added Intel Z68 Series Chipset

• Minor updates throughout for clarity May 2011

006 • Minor updates for clarity May 2011

38 Datasheet

Platform Controller Hub Features

Direct Media Interface

— NEW: Up to 20 Gb/s each direction, full

duplex

— Transparent to software

PCI Express*

— Up to eight PCI Express root ports

— NEW: Supports PCI Express Rev 2.0

running at up to 5.0 GT/s

— Ports 1-4 and 5-8 can independently be

configured to support eight x1s, two x4s,

two x2s and four x1s, or one x4 and four x1

port widths

— Module based Hot-Plug supported (that is,

ExpressCard*)

Integrated Serial ATA Host Controller

—Up to six SATA ports

— NEW: Data transfer rates up to 6.0 Gb/s

(600 MB/s) on up to two ports

— Data transfer rates up to 3.0 Gb/s

(300 MB/s) and up to 1.5 Gb/s

(150 MB/s) on all ports

— Integrated AHCI controller

External SATA support on all ports

— 3.0 Gb/s / 1.5 Gb/s support

— Port Disable Capability

Intel® Rapid Storage Technology

— Configures the PCH SATA controller as a

RAID controller supporting RAID 0/1/5/10

NEW: Intel® Smart Response Technology

Intel® High Definition Audio Interface

— PCI Express endpoint

— Independent Bus Master logic for eight

general purpose streams: four input and

four output

— Support four external Codecs

— Supports variable length stream slots

— Supports multichannel, 32-bit sample

depth, 192 kHz sample rate output

— Provides mic array support

— Allows for non-48 kHz sampling output

— Support for ACPI Device States

—Low Voltage

Eight TACH signals and Four PWM signals

(Server and Workstation Only)

Platform Environmental Control Interface

(PECI) and Simple Serial Transport (SST) 1.0

Bus (Server and Workstation Only)

USB

— Two EHCI Host Controllers, supporting up

to fourteen external USB 2.0 ports

— Two USB 2.0 Rate Matching Hubs

— Per-Port-Disable Capability

— Includes up to two USB 2.0 High-speed

Debug Ports

— Supports wake-up from sleeping states S1-

— Supports legacy Keyboard/Mouse software

Integrated Gigabit LAN Controller

— Connection utilizes PCI Express pins

— Integrated ASF Management Controller

— Network security with System Defense

— Supports IEEE 802.3

— 10/100/1000 Mbps Ethernet Support

—Jumbo Frame Support

Intel® Active Management Technology with

System Defense

— Network Outbreak Containment Heuristics

Intel® I/O Virtualization (Intel® VT-d) Support

Intel® Trusted Execution Technology Support

Intel® Anti-Theft Technology

Power Management Logic

— Supports ACPI 4.0a

— ACPI-defined power states (processor

driven C states)

— ACPI Power Management Timer

—SMI# generation

— All registers readable/restorable for proper

resume from 0 V core well suspend states

— Support for APM-based legacy power

management for non-ACPI

implementations

Integrated Clock Controller

— Full featured platform clocking without

need for a discrete clock chip

— Ten PCIe 2.0 specification compliant clocks,

four 33 MHz PCI clocks, four Flex Clocks

that can be configured for various crystal

replacement frequencies, one 120 MHz

clock for embedded DisplayPort*

— Two isolated PCIe* 2.0 jitter specification

compliant clock domains

Datasheet 39

Note: Not all features are available on all PCH SKUs. See Section 1.3 for more details.

§ §

External Glue Integration

— Integrated Pull-down and Series resistors

on USB

Enhanced DMA Controller

— Two cascaded 8237 DMA controllers

— Supports LPC DMA

PCI Bus Interface (not available on all SKUs)

— Supports PCI Rev 2.3 Specification at

33 MHz

— Four available PCI REQ/GNT pairs

— Support for 64-bit addressing on PCI using

DAC protocol

SMBus

— Interface speeds of up to 100 kbps

— Flexible SMBus/SMLink architecture to

optimize for ASF

— Provides independent manageability bus

through SMLink interface

— Supports SMBus 2.0 Specification

— Host interface allows processor to

communicate using SMBus

— Slave interface allows an internal or

external microcontroller to access system

resources

— Compatible with most two-wire

components that are also I2C compatible

High Precision Event Timers

— Advanced operating system interrupt

scheduling

Timers Based on 82C54

— System timer, Refresh request, Speaker

tone output

Real-Time Clock

— 256 byte battery-backed CMOS RAM

— Integrated oscillator components

— Lower Power DC/DC Converter

implementation

System TCO Reduction Circuits

— Timers to generate SMI# and Reset upon

detection of system hang

— Timers to detect improper processor reset

— Supports ability to disable external devices

JTAG

— Boundary Scan for testing during board

manufacturing

Serial Peripheral Interface (SPI)

— Supports up to two SPI devices

— Supports 20 MHz, 33 MHz, and 50 MHz SPI

devices

— Support up to two different erase

granularities

Firmware Hub I/F supports BIOS Memory size

up to 8 MB

Low Pin Count (LPC) I/F

— Supports two Master/DMA devices.

— Support for Security Device (Trusted

Platform Module) connected to LPC

Interrupt Controller

— Supports up to eight PCI interrupt pins

— Supports PCI 2.3 Message Signaled

Interrupts

— Two cascaded 82C59 with 15 interrupts

— Integrated I/O APIC capability with 24

interrupts

— Supports Processor System Bus interrupt

delivery

1.05 V operation with 1.5/3.3 V I/O

— 5 V tolerant buffers on PCI, USB and

selected Legacy signals

1.05 V Core Voltage

Integrated Voltage Regulators for select power

rails

GPIO

— Open-Drain, Inversion

— GPIO lock down

Analog Display (VGA)

Digital Display

— Three Digital Ports capable of supporting

HDMI/DVI, DisplayPort*, and embedded

DisplayPort (eDP*)

— One Digital Port supporting SDVO

—LVDS

— Integrated DisplayPort/HDMI Audio

— HDCP Support

Package

— 27 mm x 27 mm FCBGA (Desktop Only)

— 25 mm x 25 mm FCBGA (Mobile Only)

— 22 mm x 22 mm FCBGA (Mobile SFF Only)

40 Datasheet

Datasheet 41

Introduction

1 Introduction

1.1 About This Manual

This document is intended for Original Equipment Manufacturers and BIOS vendors

creating Intel® 6 Series Chipset and Intel® C200 Series Chipset based products (See

Section 1.3 for currently defined SKUs).

Note: Throughout this document, Platform Controller Hub (PCH) is used as a general term

and refers to all Intel 6 Series Chipset and Intel C200 Series Chipset SKUs, unless

specifically noted otherwise.

Note: Throughout this document, the terms “Desktop” and “Desktop Only” refer to

information that is applicable only to the Intel® Q67 Chipset, Intel® Q65 Chipset,

Intel® B65 Chipset, Intel® Z68 Chipset, Intel® H67 Chipset, Intel® P67 Chipset, Intel®

H61 Chipset, Intel® C202 Chipset, Intel® C204 Chipset, and Intel® C206 Chipset,

unless specifically noted otherwise.

Note: Throughout this document, the terms “Server/Workstation” and “Server/Workstation

Only” refers to information that is applicable only to the Intel® C202 Chipset, Intel®

C204 Chipset, and Intel® C206 Chipset, unless specifically noted otherwise.

Note: Throughout this document, the terms “Mobile” and “Mobile Only” refers to information

that is applicable only to the Intel® QM67 Chipset, Intel® UM67 Chipset, Intel® HM67

Chipset, Intel® HM65 Chipset, and Intel® QS67 Chipset, unless specifically noted

otherwise.

Note: Throughout this document, the terms “Small Form Factor Only” and “SFF Only” refers

to information that is applicable only to the Intel® QS67 Chipset, unless specifically

noted otherwise.

This manual assumes a working knowledge of the vocabulary and principles of PCI

Express*, USB, AHCI, SATA, Intel® High Definition Audio (Intel® HD Audio), SMBus,

PCI, ACPI and LPC. Although some details of these features are described within this

manual, refer to the individual industry specifications listed in Table 1 - 1 for the

complete details.

All PCI buses, devices and functions in this manual are abbreviated using the following

nomenclature; Bus:Device:Function. This manual abbreviates buses as Bn, devices as

Dn and functions as Fn. For example Device 31 Function 0 is abbreviated as D31:F0,

Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will

not be used, and can be considered to be Bus 0. Note that the PCH’s external PCI bus is

typically Bus 1, but may be assigned a different number depending upon system

configuration.

Introduction

42 Datasheet

Chapter 1, “Introduction”

Chapter 1 introduces the PCH and provides information on manual organization and

gives a general overview of the PCH.

Chapter 2, “Signal Description”

Chapter 2 provides a block diagram of the PCH and a detailed description of each

signal. Signals are arranged according to interface and details are provided as to the

drive characteristics (Input/Output, Open Drain, etc.) of all signals.

Chapter 3, “PCH Pin States”

Chapter 3 provides a complete list of signals, their associated power well, their logic

level in each suspend state, and their logic level before and after reset.

Chapter 4, “PCH and System Clocks”

Chapter 4 provides a list of each clock domain associated with the PCH.

Table 1-1. Industry Specifications

Specification Location

PCI Express* Base Specification, Revision 2.0 http://www.pcisig.com/specifications

Low Pin Count Interface Specification, Revision 1.1 (LPC) http://developer.intel.com/design/chipsets/

industry/lpc.htm

System Management Bus Specification, Version 2.0 (SMBus) http://www.smbus.org/specs/

PCI Local Bus Specification, Revision 2.3 (PCI) http://www.pcisig.com/specifications

PCI Power Manage ment Specification, Revision 1.2 http://www.pcisig.com/specifications

Universa l Serial Bus Specification (USB), Revisio n 2.0 http://www.usb.org/developers/docs

Advanced Configuration and Power Interface, Version 4.0a

(ACPI) http://www.acpi.info/spec.htm

Enhanced Host Controller Interface Specification fo r Universal

Serial Bus, Revision 1.0 (EHCI) http://developer.intel.com/technology/usb/

ehcispec.htm

Serial ATA Specification, Revision 3.0 http://www.serialata.org/

Serial ATA II: Extensions to Serial ATA 1.0, Revision 1.0 http://www.serialata.org

Serial ATA II Cables and Connectors Volume 2 Gold http://www.serialata.org

Alert Standard Format Specification, Version 1.03 http://www.dmtf.org/standards/asf

IEEE 802.3 Fast Ethernet http://standards.ieee.org/getieee802/

AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) http://T13.org (T13 1410D)

IA-PC HPET (High Pr ecision Event Timers) Specification,

Revision 1.0a http://www.intel.com/hardwaredesign/

hpetspec_1.pdf

TPM Specification 1.02, Level 2 Revision 103 http://www.trustedcomputinggroup.org/specs/

TPM

Intel® Virtualization Technology http://www.intel.com/technology/

virtualization/index.htm

SFF-8485 Specification for Serial GPIO (SGPIO) Bus, Revision

0.7 http://www.intel.com/technology/

virtualization/index.htm

Advanced Host Controller Interface specification for Serial

ATA, Revision 1.3 http://www.intel.com/technology/serialata/

ahci.htm

Intel® High Definition Audio Specification, Revision 1.0a http://www.intel.com/standards/hdaudio/

Datasheet 43

Introduction

Chapter 5, “Functional Description”

Chapter 5 provides a detailed description of the functions in the PCH.

Chapter 6, “Ballout Definition”

Chapter 6 provides the ball assignment table and the ball-map for the Desktop, Mobile

and Mobile SFF packages.

Chapter 7, “Package Information”

Chapter 7 provides drawings of the physical dimensions and characteristics of the

Desktop, Mobile and Mobile SFF packages.

Chapter 8, “Electrical Characteristics”

Chapter 8 provides all AC and DC characteristics including detailed timing diagrams.

Chapter 9, “Register and Memory Mapping”

Chapter 9 provides an overview of the registers, fixed I/O ranges, variable I/O ranges

and memory ranges decoded by the PCH.

Chapter 10, “Chipset Configuration Registers”

Chapter 10 provides a detailed description of registers and base functionality that is

related to chipset configuration. It contains the root complex register block, which

describes the behavior of the upstream internal link.

Chapter 11, “PCI-to-PCI Bridge Registers (D30:F0)”

Chapter 11 provides a detailed description of registers that reside in the PCI-to-PCI

bridge. This bridge resides at Device 30, Function 0 (D30:F0).

Chapter 12, “Gigabit LAN Configuration Registers”

Chapter 12 provides a detailed description of registers that reside in the PCH’s

integrated LAN controller. The integrated LAN Controller resides at Device 25,

Function 0 (D25:F0).

Chapter 13, “LPC Interface Bridge Registers (D31:F0)”

Chapter 13 provides a detailed description of registers that reside in the LPC bridge.

This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers

for many different units within the PCH including DMA, Timers, Interrupts, Processor

Interface, GPIO, Power Management, System Management and RTC.

Chapter 14, “SATA Controller Registers (D31:F2)”

Chapter 14 provides a detailed description of registers that reside in the SATA

controller #1. This controller resides at Device 31, Function 2 (D31:F2).

Chapter 15, “SATA Controller Registers (D31:F5)”

Chapter 15 provides a detailed description of registers that reside in the SATA

controller #2. This controller resides at Device 31, Function 5 (D31:F5).

Chapter 16, “EHCI Controller Registers (D29:F0, D26:F0)”

Chapter 16 provides a detailed description of registers that reside in the two EHCI host

controllers. These controllers reside at Device 29, Function 0 (D29:F0) and Device 26,

Function 0 (D26:F0).

Chapter 17, “Integrated Intel® High Definition Audio Controller Registers”

Chapter 17 provides a detailed description of registers that reside in the Intel High

Definition Audio controller. This controller resides at Device 27, Function 0 (D27:F0).

Chapter 18, “SMBus Controller Registers (D31:F3)”

Chapter 18 provides a detailed description of registers that reside in the SMBus

controller. This controller resides at Device 31, Function 3 (D31:F3).

Introduction

44 Datasheet

Chapter 19, “PCI Express* Configuration Registers”

Chapter 19 provides a detailed description of registers that reside in the PCI Express

controller. This controller resides at Device 28, Functions 0 to 7 (D28:F0-F7).

Chapter 20, “High Precision Event Timer Registers”

Chapter 20 provides a detailed description of registers that reside in the multimedia

timer memory mapped register space.

Chapter 21, “Serial Peripheral Interface (SPI)”

Chapter 21 provides a detailed description of registers that reside in the SPI memory

mapped register space.

Chapter 22, “Thermal Sensor Registers (D31:F6)”

Chapter 22 provides a detailed description of registers that reside in the thermal

sensors PCI configuration space. The registers reside at Device 31, Function 6

(D31:F6).

Chapter 23, “Intel® Management Engine Subsystem Registers (D22:F[3:0])”

Chapter 23 provides a detailed description of registers that reside in the Intel ME

controller. The registers reside at Device 22, Function 0 (D22:F0).

1.2 Overview

The PCH provides extensive I/O support. Functions and capabilities include:

•PCI Express* Base Specification, Revision 2.0 support for up to eight ports with

transfers up to 5 GT/s

•PCI Local Bus Specification, Revision 2.3 support for 33 MHz PCI operations

(supports up to four Req/Gnt pairs)

• ACPI Power Management Logic Support, Revision 4.0a

• Enhanced DMA controller, interrupt controller, and timer functions

• Integrated Serial ATA host controllers with independent DMA operation on up to six

ports

• USB host interface with two EHCI high-speed USB 2.0 Host controllers and two rate

matching hubs provide support for up to fourteen USB 2.0 ports

• Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense

•System Management Bus (SMBus) Specification, Version 2.0 with additional

support for I2C devices

•Supports Intel

® High Definition Audio (Intel® HD Audio)

•Supports Intel

® Rapid Storage Technology (Intel® RST)

•Supports Intel

® Active Management Technology (Intel® AMT)

•Supports Intel

® Virtualization Technology for Directed I/O (Intel® VT-d)

•Supports Intel

® Trusted Execution Technology (Intel® TXT)

• Integrated Clock Controller

•Intel

® Flexible Display Interconnect (Intel® FDI)

• Analog and digital display ports

—Analog VGA

—HDMI

—DVI

— DisplayPort* 1.1, Embedded DisplayPort

—SDVO

— LVDS (Mobile Only)

• Low Pin Count (LPC) interface

• Firmware Hub (FWH) interface support

Datasheet 45

Introduction

• Serial Peripheral Interface (SPI) support

•Intel

® Anti-Theft Technology (Intel® AT)

• JTAG Boundary Scan support

The PCH incorporates a variety of PCI devices and functions separated into logical

devices, as shown in Ta b l e 9 - 1 .

Note: Not all functions and capabilities may be available on all SKUs. Please see Section 1.3

for details on SKU feature availability.

1.2.1 Capability Overview

The following sub-sections provide an overview of the PCH capabilities.

Direct Media Interface (DMI)

Direct Media Interface (DMI) is the chip-to-chip connection between the processor and

PCH. This high-speed interface integrates advanced priority-based servicing allowing

for concurrent traffic and true isochronous transfer capabilities. Base functionality is

completely software-transparent, permitting current and legacy software to operate

normally.

Intel® Flexible Display Interconnect (FDI)

Intel® FDI connects the display engine in the processor with the display interfaces on

the PCH. The display data from the frame buffer is processed by the display engine and

sent to the PCH where it is transcoded and driven out on the panel. Intel FDI involves

two channels – A and B for display data transfer.

Intel FDI Channel A has 4 lanes and Channel B supports 4 lanes depending on the

display configuration. Each of the Intel FDI Channel lanes uses differential signal

supporting 2.7 Gb/s. For two display configurations Intel FDI CH A maps to display pipe

A while Intel CH B maps to the second display pipe B.

PCH Display Interface

The PCH integrates latest display technologies such as HDMI*, DisplayPort*, Embedded

DisplayPort (eDP*), SDVO, and DVI along with legacy display technologies—Analog

Port (VGA) and LVDS (mobile only). The Analog Port and LVDS Port are dedicated ports

on the PCH and the Digital Ports B, C, and D can be configured to drive HDMI, DVI, or

DisplayPort. Digital Port B can also be configured as SDVO while Digital Port D can be

configured as eDP. The HDMI interface supports the HDMI* 1.4a specification while the

DisplayPort interface supports the DisplayPort* 1.1a specification. The PCH supports

High-bandwidth Digital Content Protection for high definition content playback over

digital interfaces. The PCH also integrates audio codecs for audio support over HDMI

and DisplayPort interfaces.

The PCH receives the display data over Intel FDI and transcodes the data as per the

display technology protocol and sends the data through the display interface.

PCI Express* Interface

The PCH provides up to 8 PCI Express Root Ports, supporting the PCI Express Base

Specification, Revision 2.0. Each Root Port x1 lane supports up to 5 Gb/s bandwidth in

each direction (10 Gb/s concurrent). PCI Express Root Ports 1-4 or Ports 5-8 can

independently be configured to support four x1s, two x2s, one x2 and two x1s, or one

x4 port widths. Please see Section 1.3 for details on SKU feature availability.

Introduction

46 Datasheet

Serial ATA (SATA) Controller

The PCH has two integrated SATA host controllers that support independent DMA

operation on up to six ports and supports data transfer rates of up to 6.0 Gb/s

(600 MB/s) on up to two ports while all ports support rates up to 3.0 Gb/s (300 MB/s)

and up to 1.5 Gb/s (150 MB/s). The SATA controller contains two modes of operation—

a legacy mode using I/O space, and an AHCI mode using memory space. Software that

uses legacy mode will not have AHCI capabilities.

The PCH supports the Serial ATA Specification, Revision 3.0. The PCH also supports

several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0 Specification,

Revision 1.0 (AHCI support is required for some elements). Please see Section 1.3 for

details on SKU feature availability.

AHCI

The PCH provides hardware support for Advanced Host Controller Interface (AHCI), a

standardized programming interface for SATA host controllers. Platforms supporting

AHCI may take advantage of performance features such as no master/slave

designation for SATA devices—each device is treated as a master—and hardware-

assisted native command queuing. AHCI also provides usability enhancements such as

Hot-Plug. AHCI requires appropriate software support (such as, an AHCI driver) and for

some features, hardware support in the SATA device or additional platform hardware.

Please see Section 1.3 for details on SKU feature availability.

Intel® Rapid Storage Technology

The PCH provides support for Intel Rapid Storage Technology, providing both AHCI (see

above for details on AHCI) and integrated RAID functionality. The RAID capability

provides high-performance RAID 0, 1, 5, and 10 functionality on up to 6 SATA ports of

the PCH. Matrix RAID support is provided to allow multiple RAID levels to be combined

on a single set of hard drives, such as RAID 0 and RAID 1 on two disks. Other RAID

features include hot spare support, SMART alerting, and RAID 0 auto replace. Software

components include an Option ROM for pre-boot configuration and boot functionality, a

Microsoft Windows* compatible driver, and a user interface for configuration and

management of the RAID capability of PCH. See Section 1.3 for details on SKU feature

availability.

Intel® Smart Response Technology

Intel® Smart Response Technology is a disk caching solution that can provide improved

computer system performance with improved power savings. It allows configuration of

a computer systems with the advantage of having HDDs for maximum storage capacity

with system performance at or near SSD performance levels. See Section 1.3 for

details on SKU feature availability.

PCI Interface

The PCH PCI interface provides a 33 MHz, Revision 2.3 implementation. The PCH

integrates a PCI arbiter that supports up to four external PCI bus masters in addition to

the internal PCH requests. This allows for combinations of up to four PCI down devices

and PCI slots. See Section 1.3 for details on SKU feature availability.

Low Pin Count (LPC) Interface

The PCH implements an LPC Interface as described in the LPC 1.1 Specification. The

Low Pin Count (LPC) bridge function of the PCH resides in PCI Device 31:Function 0. In

addition to the LPC bridge interface function, D31:F0 contains other functional units

including DMA, interrupt controllers, timers, power management, system management,

GPIO, and RTC.

Datasheet 47

Introduction

Serial Peripheral Interface (SPI)

The PCH implements an SPI Interface as an alternative interface for the BIOS flash

device. An SPI flash device can be used as a replacement for the FWH, and is required

to support Gigabit Ethernet and Intel Active Management Technology. The PCH

supports up to two SPI flash devices with speeds up to 50 MHz, using two chip select

pins.

Compatibility Modules (DMA Controller, Timer/Counters, Interrupt

Controller)

The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven

independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-

byte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any

two of the seven DMA channels can be programmed to support fast Type-F transfers.

Channel 4 is reserved as a generic bus master request.

The PCH supports LPC DMA, which is similar to ISA DMA, through the PCH’s DMA

controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals

and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and

Increment modes are supported on the LPC interface.

The timer/counter block contains three counters that are equivalent in function to those

found in one 82C54 programmable interval timer. These three counters are combined

to provide the system timer function, and speaker tone. The 14.31818-MHz oscillator

input provides the clock source for these three counters.

The PCH provides an ISA-Compatible Programmable Interrupt Controller (PIC) that

incorporates the functionality of two, 82C59 interrupt controllers. The two interrupt

controllers are cascaded so that 14 external and two internal interrupts are possible. In

addition, the PCH supports a serial interrupt scheme.

All of the registers in these modules can be read and restored. This is required to save

and restore system state after power has been removed and restored to the platform.

Advanced Programmable Interrupt Controller (APIC)

In addition to the standard ISA compatible Programmable Interrupt controller (PIC)

described in the previous section, the PCH incorporates the Advanced Programmable

Interrupt Controller (APIC).

Universal Serial Bus (USB) Controllers

The PCH contains up to two Enhanced Host Controller Interface (EHCI) host controllers

that support USB high-speed signaling. High-speed USB 2.0 allows data transfers up to

480 Mb/s which is up to 40 times faster than full-speed USB. The PCH supports up to

fourteen USB 2.0 ports. All ports are high-speed, full-speed, and low-speed capable.

Please see Section 1.3 for details on SKU feature availability.

Introduction

48 Datasheet

Gigabit Ethernet Controller

The Gigabit Ethernet Controller provides a system interface using a PCI function. The

controller provides a full memory-mapped or IO mapped interface along with a 64 bit

address master support for systems using more than 4 GB of physical memory and

DMA (Direct Memory Addressing) mechanisms for high performance data transfers. Its

bus master capabilities enable the component to process high-level commands and

perform multiple operations; this lowers processor utilization by off-loading

communication tasks from the processor. Two large configurable transmit and receive

FIFOs (up to 20 KB each) help prevent data underruns and overruns while waiting for

bus accesses. This enables the integrated LAN controller to transmit data with

minimum interframe spacing (IFS).

The LAN controller can operate at multiple speeds (10/100/1000 MB/s) and in either

full duplex or half duplex mode. In full duplex mode the LAN controller adheres with the

IEEE 802.3x Flow Control Specification. Half duplex performance is enhanced by a

proprietary collision reduction mechanism. See Section 5.3 for details.

RTC

The PCH contains a Motorola MC146818B-compatible real-time clock with 256 bytes of

battery-backed RAM. The real-time clock performs two key functions—keeping track of

the time of day and storing system data, even when the system is powered down. The

RTC operates on a 32.768 KHz crystal and a 3 V battery.

The RTC also supports two lockable memory ranges. By setting bits in the configuration

space, two 8-byte ranges can be locked to read and write accesses. This prevents

unauthorized reading of passwords or other system security information.

The RTC also supports a date alarm that allows for scheduling a wake up event up to 30

days in advance, rather than just 24 hours in advance.

GPIO

Various general purpose inputs and outputs are provided for custom system design.

The number of inputs and outputs varies depending on PCH configuration.

Enhanced Power Management

The PCH’s power management functions include enhanced clock control and various

low-power (suspend) states (such as Suspend-to-RAM and Suspend-to-Disk). A

hardware-based thermal management circuit permits software-independent entrance

to low-power states. The PCH contains full support for the Advanced Configuration and

Power Interface (ACPI) Specification, Revision 4.0a.

Intel® Active Management Technology (Intel® AMT)

Intel AMT is a fundamental component of Intel® vPro™ technology. Intel AMT is a set of

advanced manageability features developed as a direct result of IT customer feedback

gained through Intel market research. With the advent of powerful tools like the Intel®

System Defense Utility, the extensive feature set of Intel AMT easily integrates into any

network environment. Please see Section 1.3 for details on SKU feature availability.

Datasheet 49

Introduction

Manageability

In addition to Intel AMT the PCH integrates several functions designed to manage the

system and lower the total cost of ownership (TCO) of the system. These system

management functions are designed to report errors, diagnose the system, and recover

from system lockups without the aid of an external microcontroller.

•TCO Timer. The PCH’s integrated programmable TCO timer is used to detect

system locks. The first expiration of the timer generates an SMI# that the system

can use to recover from a software lock. The second expiration of the timer causes

a system reset to recover from a hardware lock.

•Processor Present Indicator. The PCH looks for the processor to fetch the first

instruction after reset. If the processor does not fetch the first instruction, the PCH

will reboot the system.

•ECC Error Reporting. When detecting an ECC error, the host controller has the

ability to send one of several messages to the PCH. The host controller can instruct

the PCH to generate either an SMI#, NMI, SERR#, or TCO interrupt.

•Function Disable. The PCH provides the ability to disable the following integrated

functions: LAN, USB, LPC, Intel HD Audio, SATA, PCI Express or SMBus. Once

disabled, these functions no longer decode I/O, memory, or PCI configuration

space. Also, no interrupts or power management events are generated from the

disabled functions.

•Intruder Detect. The PCH provides an input signal (INTRUDER#) that can be

attached to a switch that is activated by the system case being opened. The PCH

can be programmed to generate an SMI# or TCO interrupt due to an active

INTRUDER# signal.

System Management Bus (SMBus 2.0)

The PCH contains an SMBus Host interface that allows the processor to communicate

with SMBus slaves. This interface is compatible with most I2C devices. Special I2C

commands are implemented.

The PCH’s SMBus host controller provides a mechanism for the processor to initiate

communications with SMBus peripherals (slaves). Also, the PCH supports slave

functionality, including the Host Notify protocol. Hence, the host controller supports

eight command protocols of the SMBus interface (see System Management Bus

(SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write

Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.

The PCH’s SMBus also implements hardware-based Packet Error Checking for data

robustness and the Address Resolution Protocol (ARP) to dynamically provide address

to all SMBus devices.

Intel® High Definition Audio Controller

The Intel® High Definition Audio Specification defines a digital interface that can be

used to attach different types of codecs, such as audio and modem codecs. The PCH

Intel® HD Audio controller supports up to 4 codecs. The link can operate at either 3.3 V

or 1.5 V.

With the support of multi-channel audio stream, 32-bit sample depth, and sample rate

up to 192 kHz, the Intel HD Audio controller provides audio quality that can deliver CE

levels of audio experience. On the input side, the PCH adds support for an array of

microphones.

Introduction

50 Datasheet

Intel® Virtualization Technology for Directed I/O (Intel VT-d)

The PCH provides hardware support for implementation of Intel Virtualization

Technology with Directed I/O (Intel® VT-d). Intel VT-d Technology consists of

technology components that support the virtualization of platforms based on Intel®

Architecture processors. Intel VT-d technology enables multiple operating systems and

applications to run in independent partitions. A partition behaves like a virtual machine

(VM) and provides isolation and protection across partitions. Each partition is allocated

it’s own subset of host physical memory.

JTAG Boundary-Scan

The PCH implements the industry standard JTAG interface and enables Boundary-Scan

in place of the XOR chains used in previous generations of chipsets. Boundary-Scan can

be used to ensure device connectivity during the board manufacturing process. The

JTAG interface allows system manufacturers to improve efficiency by using industry

available tools to test the PCH on an assembled board. Since JTAG is a serial interface,

it eliminates the need to create probe points for every pin in an XOR chain. This eases

pin breakout and trace routing and simplifies the interface between the system and a

bed-of-nails tester.

Note: Contact your local Intel Field Sales Representative for additional information about

JTAG usage on the PCH.

Integrated Clock Controller

The PCH contains a Fully Integrated Clock Controller (ICC) generating various platform

clocks from a 25 MHz crystal source. The ICC contains up to eight PLLs and four Spread

Modulators for generating various clocks suited to the platform needs. The ICC supplies

up to ten 100 MHz PCI Express 2.0 Specification compliant clocks, one 100 MHz BCLK/

DMI to the processor, one 120 MHz for embedded DisplayPort on the processor, four

33 MHz clocks for SIO/EC/LPC/TPM devices and four Flex Clocks that can be configured

to various frequencies that include 14.318 MHz, 27 MHz, 33 MHz and 24/48 MHz for

use with SIO, EC, LPC, and discrete Graphics devices.

SOL Function

This function supports redirection of keyboard and text screens to a terminal window

on a remote console. The keyboard and text redirection enables the control of the client

machine through the network without the need to be physically near that machine. Text

and keyboard redirection allows the remote machine to control and configure a client

system. The SOL function emulates a standard PCI device and redirects the data from

the serial port to the management console using the integrated LAN.

KVM

KVM provides enhanced capabilities to its predecessor – SOL. In addition to the

features set provided by SOL, KVM provides mouse and graphic redirection across the

integrated LAN. Unlike SOL, KVM does not appear as a host accessible PCI device but is

instead almost completely performed by Intel AMT Firmware with minimal BIOS

interaction. The KVM feature is only available with internal graphics.

Datasheet 51

Introduction

IDE-R Function

The IDE-R function is an IDE Redirection interface that provides client connection to

management console ATA/ATAPI devices such as hard disk drives and optical disk

drives. A remote machine can setup a diagnostic SW or OS installation image and direct

the client to boot an IDE-R session. The IDE-R interface is the same as the IDE

interface although the device is not physically connected to the system and supports

the ATA/ATAPI-6 specification. IDE-R does not conflict with any other type of boot and

can instead be implemented as a boot device option. The Intel AMT solution will use

IDE-R when remote boot is required. The device attached through IDE-R is only visible

to software during a management boot session. During normal boot session, the IDE-R

controller does not appear as a PCI present device.

1.3 Intel® 6 Series Chipset and Intel® C200 Series

Chipset SKU Definition

NOTES:

1. Contact your local Intel Field Sales Representative for currently available PCH SKUs.

2. Table above shows feature differences between the PCH SKUs. If a feature is not listed in

the table it is considered a Base feature that is included in all SKUs

3. The PCH provides hardware support for AHCI functionality when enabled by appropriate

system configurations and software drivers.

4. SATA 6 Gb/s support on port 0 and port 1. SATA ports 0 and 1 also support 3 Gb/s and 1.5

Gb/s.

5. SATA 6 Gb/s support on port 0 only. SATA port 0 also supports 3 Gb/s and 1.5 Gb/s.

6. USB ports 6 and 7 are disabled.

7. USB ports 6, 7, 12 and 13 are disabled.

8. SATA ports 2 and 3 are disabled.

9. PCIe ports 7 and 8 are disabled.

10. PCI Legacy Mode may optionally be used allowing external PCI bus support through a

PCIe-to-PCI bridge. See Section 5.1.9 for more details.

11. Intel RST SSD Caching naming is not final at this time and is subject to change.

Table 1-2. Desktop Intel® 6 Series Chipset SKUs

Feature Set

SKU Name

Q67 Q65 B65 Z68 H67 P67 H61

PCI Express* 2.0 Ports 8888886

PCI Interface Yes Yes Yes No10 No10 No10 No10

USB 2.0 Ports 14 14 12614 14 14 107

Total number of SATA ports 6 6 6 6 6 6 4

• SATA Ports (6 Gb/s, 3 Gb/s, and 1.5 Gb/s) 2415152424240

• SATA Ports (3 Gb/s and 1.5 Gb/s only) 4 5 5 4 4 4 48

HDMI/DVI/VGA/DisplayPort*/eDP* Yes Yes Yes Yes Yes No Yes

Integrated Graphics Support with PAVP Yes Yes Yes Yes Yes No Yes

Intel® Rapid Storage

Techno lo gy

AHCI YesYesYesYesYesYesNo

RAID 0/1/5/10 Support Yes No No Yes Yes Yes No

Intel RST SSD Caching11 No No No Yes No No No

Intel® AT Yes Yes No No No No No

Intel® AMT 7.0 YesNoNoNoNoNoNo

Introduction

52 Datasheet

NOTES:

1. Contact your local Intel Field Sales Representative for currently available PCH SKUs

2. Table above shows feature difference between the PCH SKUs. If a feature is not listed in

the table it is considered a Base feature that is included in all SKUs

3. The PCH provides hardware support for AHCI functionality when enabled by appropriate

system configurations and software drivers.

4. SATA 6 Gb/s support on port 0 and port 1. SATA ports 0 and 1 also support 3 Gb/s and

1.5 Gb/s.

5. USB ports 6 and 7 are disabled on 12 port SKUs.

Table 1-3. Mobile Intel® 6 Series Chipset SKUs

Feature Set

SKU Name

QM67 UM67 HM67 HM65 QS67

PCI Express* 2.0 Ports 88888

PCI Interface No No No No No

USB* 2.0 Ports 14 14 14 12514

Total number of SATA ports 6 6 6 6 6

• SATA Ports (6 Gb/s, 3 Gb/s, and 1.5 Gb/s) 2424242424

• SATA Ports (3 Gb/s and 1.5 Gb/s only) 4 4 4 4 4

HDMI/DVI/VGA/SDVO/DisplayPort*/eDP*/LVDS Yes Yes Yes Yes Yes

Integrated Graphics Support with PAVP 2.0 Yes Yes Yes Yes Yes

Intel® Rapid

Storage

Technology

AHCI Yes Yes Yes Yes Yes

RAID 0/1/5/10 Support Yes No Yes No Yes

Intel® Anti-Theft Yes Yes Yes Yes Yes

Intel® AMT 7.0 Yes No No No Yes

Datasheet 53

Introduction

NOTES:

1. Contact your local Intel Field Sales Representative for currently available PCH SKUs.

2. Table above shows feature differences between the PCH SKUs. If a feature is not listed in

the table it is considered a Base feature that is included in all SKUs

3. The PCH provides hardware support for AHCI functionality when enabled by appropriate

system configurations and software drivers.

4. SATA 6 Gb/s support on port 0 and port 1. SATA ports 0 and 1 also support 3 Gb/s and

1.5 Gb/s.

5. USB ports 6 and 7 are disabled.

§ §

Table 1-4. Server/Workstation Intel® C200 Series Chipset SKUs

Feature Set

SKU Name

C206 C204 C202

PCI Express* 2.0 Ports 88 8

PCI Interface Yes Yes Yes

USB 2.0 Ports 14 125125

Total number of SATA Ports 6 6 6

• SATA Ports (6.0 Gb/s & 3.0 Gb/s & 1.5 Gb/s) 24240

• SATA Ports (3.0 Gb/s & 1.5 Gb/s only) 4 4 6

HDMI*/DVI*/VGA/eDP*/DisplayPort* Yes No No

Integrated Graphics Support with PAVP Yes No No

Intel® Rapid

Storage

Tec hno logy

AHCI Yes Yes Yes

RAID 0/1/5/10 Support Yes Yes Yes

Intel® Anti-Theft Technology Yes No No

Intel® Active Management Technology 7.0 Yes No No

Introduction

54 Datasheet

Datasheet 55

Signal Description

2 Signal Description

This chapter provides a detailed description of each signal. The signals are arranged in

functional groups according to their associated interface.

The “#” symbol at the end of the signal name indicates that the active, or asserted

state occurs when the signal is at a low voltage level. When “#” is not present, the

signal is asserted when at the high voltage level.

The following notations are used to describe the signal type:

IInput Pin

O Output Pin

OD O Open Drain Output Pin.

I/OD Bi-directional Input/Open Drain Output Pin.

I/O Bi-directional Input/Output Pin.

CMOS CMOS buffers. 1.5 V tolerant.

COD CMOS Open Drain buffers. 3.3 V tolerant.

HVCMOS High Voltage CMOS buffers. 3.3 V tolerant.

AAnalog reference or output.

The “Type” for each signal is indicative of the functional operating mode of the signal.

Unless otherwise noted in Section 3.2 or Section 3.3, a signal is considered to be in the

functional operating mode after RTCRST# deasserts for signals in the RTC well, after

RSMRST# deasserts for signals in the suspend well, after PWROK asserts for signals in

the core well, after DPWROK asserts for Signals in the Deep S4/S5 well, after APWROK

asserts for Signals in the Active Sleep well.

Signal Description

56 Datasheet

Figure 2-1. PCH Interface Signals Block Diagram (not all signals are on all SKUs)

AD[31:0]

C/BE[3:0]#

DEVSEL#

FRAME#

IRDY#

TRDY#

STOP#

PAR

PERR#

REQ0#

REQ1#/GPIO50

REQ2#/GPIO52

REQ3#/GPIO54

GNT0#

GNT1#/GPIO51

GNT2#/GPIO53

GNT3#/GPIO55

SERR#

PME#

CLKIN_PCILOOPBACK

PCIRST#

PLOCK#

PCI

Interface

Intel®Fle x ib le

Display

Interface

Power

Mgnt.

Inte rru p t

Interface

PMSYNCH

RCIN#

A20GATE

THRMPTRIP#

PROCPWRGD

Processor

Interface

USB

SERIRQ

PIRQ[D:A]#

PIRQ[H:E]#/GPIO[5:2]

USB[13:0][P,N]

OC0#/GPIO59; OC1#/GPIO40

OC2#/GPIO41; OC3#/GPIO42

OC4#/GPIO43; OC5#/GPIO9

OC6#/GPIO10; OC7#/GPIO14

USBRBIAS, USBRBIAS#

RTCX1

RTCX2

CLKIN_DMI_[P,N];CLKIN_DMI2_[P,N]

CLKIN_SATA_[P,N]/CKSSCD_[P,N]

CLKIN_DOT96[P,N]

XTAL25_IN;REF14CLKIN

PCIECLKRQ0#/GPIO73;PCIECLKRQ1#/GPIO18

PCIECLKRQ2#/GPIO20/SMI#;PCIECLKRQ3#/GPIO25

PCIECLKRQ4#/GPIO26;PCIECLKRQ5#/GPIO44

PCIECLKRQ6#/GPIO45;PCIECLKRQ7#/GPIO46

PEG_A_CLKRQ#/GPIO47;PEG_B_CLKRQ#/GPIO56

XCLK_RCOMP

RTC

Clock

Inputs

Misc.

Signals

INTVRMEN, DSWVRMEN

SPKR

SRTCRST#; RTCRST#

INIT3_3V#

TPn

GPIO35/NMI#

GPIO24/PROC_MISSING

General

Purpose

I/O

GPIO[72,57,32,28,27,15,8]

PWM[3:0]

TACH7/GPIO71;TACH6/GPIO70; TACH5/GPIO69;TACH4/GPIO68

TACH3/GPIO7; TACH2/GPIO6; TACH1/GPIO1;TACH0/GPIO17

SST

PECI

Direct

Media

Interface

LPC /

FWH

Interface

SMBus

Interface

Intel®

High

Definition

Audio

System

Mgnt.

LAD[3:0]/FWH[3:0]

LFRAME#/FWH4

LDRQ0#; LDRQ1#/GPIO23

Serial ATA

Interface

PCI Express*

Interface

SPI

S P I_ C S0#; S PI_CS 1 #

SPI_MISO

SPI_MOSI

SPI_CLK

JTAG

C o n tr o lle r

Link

Fan

Speed

Control

Digital

Display

Interface

Clock

Outputs

CLKOUT_DP_[P,N]

CLKOUT_DMI_[P,N]

XTAL25_OUT

CLKOUT_PEG_A_[P,N];CLKOUT_PEG_B_[P,N]

CLKOUT_PCIE[7:0]_[P,N]

CLKOUT_ITPXDP_[P,N]

CLKOUT_PCI[4:0]

CLKOUTFLEX0/GPIO64;CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66;CLKOUTFLEX3/GPIO67

Analog

Display

LVDS

FDI_RX[P,N][7:4]

FDI_RX[P,N[[3:0]

FDI_FSYNC[0:1];FDI_LSYNC[0:1];FDI_INIT

CL_CLK1 ; CL_DATA1

CL_RST1#

PET[p,n][8:1]

PER[p,n][8:1]

SATA[5:0]TX[P,N]

SATA[5:0]RX[P,N]

SATAICOMPO, SATA3COMP O

SATAICOMPI, SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

SATA2GP/GPIO36

SATA3GP/GPIO37

SATA4GP/GPIO16

SATA5GP/GPIO49/TEMP_ALERT#

SCLOCK/GPIO22, SLOAD/GPIO38

SDATAOUT0/GPIO39, SDATAOUT1/GPIO48

SUSWARN#/SUS_PWR_DN_ACK/GPIO30

DPWROK

SYS_RESET#

RSMRST#

SLP_S3#

SLP_S4#

SLP_S5#/GPIO63

SLP_A#

CLKRUN#/GPIO32

PWROK

AWROK

PWRBTN#

RI#

WAKE#

SUS_STAT#/GPIO61

SUSCLK/GPIO62

BATLOW#/GPIO72

PLTRST#

BMBUSY#/GPIO0

STP_PCI#/GPIO34

ACPRESENT/GPIO31

DRAMPWROK

LAN_PHY_PWR_CTRL/GPIO12

SLP_LAN#/GPIO29

SUSACK#

HDA_RST#

HDA_SYNC

HDA_BCLK

HDA_SDO

HDA_SDIN[3:0]

HDA_DOCK_EN#;HDA_DOCK_RST#

DMI[3:0]TX[P,N]

D MI[3: 0 ] RX[P,N]

DMI_ZCOMP

DMI_IRCOMP

SMBDATA; SMBCLK

SMBALERT#/GPIO11

INTRUDER#;

SML[1:0]DATA;SML[1:0]CLK

SML0ALERT#/GPIO60

SML1ALERT#/PCHHOT#/GPIO74

CRT_RED;CRT_GREEN;CRT_BLUE

DAC_IREF

CRT_HSYNC;CRT_VSYNC

CRT_DDC_CLK;CRT_DDC_DATA

CRT_IRTN

LVDS[A:B]_DATA[3:0]

LVDS[A:B]_DATA#[3:0]

LVDS[A:B]_CLK;LVDS[A:B]_CLK#

LVD _VR E F H ;LVD_VREFL; LVD_VBG

LVD_IBG

L_DDC_CLK;L_DDC_DATA

L_VDDEN;L_BLKTEN;L_BKLTCTL

DDPB_[3:0][P,N]

DDPC_[3:0][P,N]

DDPD_[3:0][P,N]

DDP[B:D]_AUX[P,N]

DDP[B:D]_HPD

SDVO_CTRLCLK;SDVO_CTRLDATA

DDPC_CTRLCLK;DDPC_CTRLDATA

DDPD_CTRLCLK;DDPD_CTRLDATA

SDVO_INT[P,N]

SDVO_TVCLKIN[P,N]

SDVO_STALL[P,N]

JTAGTCK

JTAGTMS

JTAGTDI

JTAGTDO

Datasheet 57

Signal Description

2.1 Direct Media Interface (DMI) to Host Controller

2.2 PCI Express*

Table 2-1. Direct Media Interface Signals

Name Type Description

DMI0TXP,

DMI0TXN ODirect Media Interface Differential Transmit Pair 0

DMI0RXP,

DMI0RXN IDirect Media Interface Differential Receive Pair 0

DMI1TXP,

DMI1TXN ODirect Media Interface Differential Transmit Pair 1

DMI1RXP,

DMI1RXN IDirect Media Interface Differential Receive Pair 1

DMI2TXP,

DMI2TXN ODirect Media Interface Differential Transmit Pair 2

DMI2RXP,

DMI2RXN IDirect Media Interface Differential Receive Pair 2

DMI3TXP,

DMI3TXN ODirect Media Interface Differential Transmit Pair 3

DMI3RXP,

DMI3RXN IDirect Media Interface Differential Receive Pair 3

DMI_ZCOMP IImpedance Compensation Input: Determines DMI input

impedance.

DMI_IRCOMP OImpedance/Current Compensation Output: Determines DMI

output impedance and bias current.

DMI2RBIAS I/O DMI2RBIAS: Analog connection point for 750  ±1% external

precision resistor.

Table 2-2. PCI Express* Signals (Sheet 1 of 2)

Name Type Description

PETp1, PETn1 OPCI Express* Differential Transmit Pair 1

PERp1, PERn1 IPCI Express Differential Receive Pair 1

PETp2, PETn2 OPCI Express Differential Transmit Pair 2

PERp2, PERn2 IPCI Express Differential Receive Pair 2

PETp3, PETn3 OPCI Express Differential Transmit Pair 3

PERp3, PERn3 IPCI Express Differential Receive Pair 3

PETp4, PETn4 OPCI Express Differential Transmit Pair 4

PERp4, PERn4 IPCI Express Differential Receive Pair 4

PETp5, PETn5 OPCI Express Differential Transmit Pair 5

PERp5, PERn5 IPCI Express Differential Receive Pair 5

PETp6, PETn6 OPCI Express Differential Transmit Pair 6

PERp6, PERn6 IPCI Express Differential Receive Pair 6

PETp7, PETn7 OPCI Express Differential Transmit Pair 7

Signal Description

58 Datasheet

2.3 PCI Interface

Note: PCI Interface is only available on PCI Interface-enabled SKUs. However, certain PCI

Interface signal functionality is available even on PCI Interface-disabled SKUS, as

described below (see Section 1.3 for full details on SKU definition).

PERp7, PERn7 IPCI Express Differential Receive Pair 7

PETp8, PETn8 OPCI Express Differential Transmit Pair 8

PERp8, PERn8 IPCI Express Differential Receive Pair 8

Table 2-3. PCI Interface Signals (Sheet 1 of 2)

Name Type Description

Functionality

Available on

PCI Interface-

disabled SKUs

AD[31:0] I/O PCI Address/Data: Reserved. No

BE[3:0]# I/O Bus Command and Byte Enables: Reserved. No

DEVSEL# I/O Device Select: Reserved. No

FRAME# I/O Cycle Frame: Reserved. No

IRDY# I/O Initiator Ready: Reserved. No

TRDY# I/O Target Ready: Reserved. No

STOP# I/O Stop: Reserved. No

PAR I/O Calculated/Checked Parity: Reserved. No

PERR# I/O Parity Error: Reserved. No

REQ0#

REQ1#/

GPIO50

REQ2#/

GPIO52

REQ3#/

GPIO54

PCI Requests: REQ functionality is Reserved.

REQ[3:1]# pins can instead be used as GPIO.

NOTES:

1. External pull-up resistor is required. When used as

native functionality, the pull-up resistor may be to

either 3.3 V or 5.0 V per PCI specification. When

used as GPIO or not used at all, the pull-up resistor

should be to the Vcc3_3 rail.

(GPIO only)

GNT0#

GNT1#/

GPIO51

GNT2#/

GPIO53

GNT3#/

GPIO55

PCI Grants: GNT functionality is Reserved. GNT[3:1]#

pins can instead be used as GPIO.

Pull-up resistors are not required on these signals. If

pull-ups are used, they should be tied to the Vcc3_3

power rail.

NOTES:

1. GNT[3:1]#/GPIO[55,53,51] are sampled as a

functional strap. See Section 2.27 for details.

(GPIO and strap

only)

Table 2-2. PCI Express* Signals (Sheet 2 of 2)

Name Type Description

Datasheet 59

Signal Description

CLKIN_PCI

LOOPBACK I

PCI Clock: This is a 33 MHz clock feedback input to

reduce skew between PCH PCI clock and clock observed

by connected PCI devices. This signal must be

connected to one of the pins in the group

CLKOUT_PCI[4:0]

Yes

PCIRST# OPCI Reset: Reserved. No

PLOCK# I/O PCI Lock: Reserved. No

SERR# I/OD System Error: Reserved. No

PME# I/OD

PCI Power Management Event: PCI peripherals drive

PME# to wake the system from low-power states S1–

S5. PME# assertion can also be enabled to generate an

SCI from the S0 state. In some cases the PCH may

drive PME# active due to an internal wake event. The

PCH will not drive PME# high, but it will be pulled up to

VccSus3_3 by an internal pull-up resistor.

Can be used with PCI legacy mode on platforms using a

PCIe-to-PCI bridge. Downstream PCI devices would

need to have PME# routed from the connector to the

PCH PME# pin.

Yes

Table 2-3. PCI Interface Signals (Sheet 2 of 2)

Name Type Description

Functionality

Available on

PCI Interface-

disabled SKUs

Signal Description

60 Datasheet

2.4 Serial ATA Interface

Table 2-4. Serial ATA Interface Signals (Sheet 1 of 3)

Name Type Description

SATA0TXP

SATA0TXN O

Serial ATA 0 Differential Transmit Pairs: These are outbound

high-speed differential signals to Port 0.

In compatible mode, SATA Port 0 is the primary master of SATA

Controller 1.

Supports up to 6 Gb/s, 3 Gb/s, and 1.5 Gb/s.

SATA0RXP

SATA0RXN I

Serial ATA 0 Differential Receive Pair: These are inbound high-

speed differential signals from Port 0.

In compatible mode, SATA Port 0 is the primary master of SATA

Controller 1.

Supports up to 6 Gb/s, 3 Gb/s, and 1.5 Gb/s.

SATA1TXP

SATA1TXN O

Serial ATA 1 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 1.

In compatible mode, SATA Port 1 is the secondary master of SATA

Controller 1.

Supports up to 6 Gb/s, 3 Gb/s, and 1.5 Gb/s.

SATA1RXP

SATA1RXN I

Serial ATA 1 Differential Receive Pair: These are inbound high-

speed differential signals from Port 1.

In compatible mode, SATA Port 1 is the secondary master of SATA

Controller 1.

Supports up to 6 Gb/s, 3 Gb/s, and 1.5 Gb/s.

SATA2TXP

SATA2TXN O

Serial ATA 2 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 2.

In compatible mode, SATA Port 2 is the primary slave of SATA

Controller 1.

Supports up to 3 Gb/s and 1.5 Gb/s.

NOTE: SATA Port 2 may not be available in all PCH SKUs.

SATA2RXP

SATA2RXN I

Serial ATA 2 Differential Receive Pair: These are inbound high-

speed differential signals from Port 2.

In compatible mode, SATA Port 2 is the primary slave of SATA

Controller 1

Supports up to 3 Gb/s and 1.5 Gb/s.

NOTE: SATA Port 2 may not be available in all PCH SKUs.

SATA3TXP

SATA3TXN O

Serial ATA 3 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 3

In compatible mode, SATA Port 3 is the secondary slave of SATA

Controller 1

Supports up to 3 Gb/s and 1.5 Gb/s.

NOTE: SATA Port 3 may not be available in all PCH SKUs.

Datasheet 61

Signal Description

SATA3RXP

SATA3RXN I

Serial ATA 3 Differential Receive Pair: These are inbound high-

speed differential signals from Port 3.

In compatible mode, SATA Port 3 is the secondary slave of SATA

Controller 1

Supports up to 3 Gb/s and 1.5 Gb/s.

NOTE: SATA Port 3 may not be available in all PCH SKUs.

SATA4TXP

SATA4TXN O

Serial ATA 4 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 4.

In compatible mode, SATA Port 4 is the primary master of SATA

Controller 2.

Supports up to 3 Gb/s and 1.5 Gb/s.

SATA4RXP

SATA4RXN I

Serial ATA 4 Differential Receive Pair: These are inbound high-

speed differential signals from Port 4.

In compatible mode, SATA Port 4 is the primary master of SATA

Controller 2.

Supports up to 3 Gb/s and 1.5 Gb/s.

SATA5TXP

SATA5TXN O

Serial ATA 5 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 5.

In compatible mode, SATA Port 5 is the secondary master of SATA

Controller 2.

Supports up to 3 Gb/s and 1.5 Gb/s.

SATA5RXP

SATA5RXN I

Serial ATA 5 Differential Receive Pair: These are inbound high-

speed differential signals from Port 5.

In compatible mode, SATA Port 5 is the secondary master of SATA

Controller 2.

Supports up to 3 Gb/s and 1.5 Gb/s.

SATAICOMPO O

Serial ATA Compensation Output: Connected to an external

precision resistor to VccCore. Must be connected to SATAICOMPI

on the board.

SATAICOMPI ISerial ATA Compensation Input: Connected to SATAICOMPO on

the board.

SATA0GP /

GPIO21 I

Serial ATA 0 General Purpose: This is an input pin which can be

configured as an interlock switch corresponding to SATA Port 0.

When used as an interlock switch status indication, this signal

should be drive to ‘0’ to indicate that the switch is closed and to ‘1’

to indicate that the switch is open.

If interlock switches are not required, this pin can be configured as

GPIO21.

SATA1GP /

GPIO19 I

Serial ATA 1 General Purpose: Same function as SATA0GP,

except for SATA Port 1.

If interlock switches are not required, this pin can be configured as

GPIO19.

SATA2GP /

GPIO36 I

Serial ATA 2 General Purpose: Same function as SATA0GP,

except for SATA Port 2.

If interlock switches are not required, this pin can be configured as

GPIO36.

Table 2-4. Serial ATA Interface Signals (Sheet 2 of 3)

Name Type Description

Signal Description

62 Datasheet

SATA3GP /

GPIO37 I

Serial ATA 3 General Purpose: Same function as SATA0GP,

except for SATA Port 3.

If interlock switches are not required, this pin can be configured as

GPIO37.

SATA4GP /

GPIO16 / I

Serial ATA 4 General Purpose: Same function as SATA0GP,

except for SATA Port 4.

If interlock switches are not required, this pin can be configured as

GPIO16 or MPGIO9.

SATA5GP /

GPIO49 /

TEMP_ALERT#

Serial ATA 5 General Purpose: Same function as SATA0GP,

except for SATA Port 5.

If interlock switches are not required, this pin can be configured as

GPIO49 or TEMP_ALERT#.

SATALED# OD O

Serial ATA LED: This signal is an open-drain output pin driven

during SATA command activity. It is to be connected to external

circuitry that can provide the current to drive a platform LED. When

active, the LED is on. When tri-stated, the LED is off. An external

pull-up resistor to Vcc3_3 is required.

SCLOCK/

GPIO22 OD O

SGPIO Reference Clock: The SATA controller uses rising edges of

this clock to transmit serial data, and the target uses the falling

edge of this clock to latch data. The SClock frequency supported is

32 kHz.

If SGPIO interface is not used, this signal can be used as GPIO22.

SLOAD/GPIO38 OD O

SGPIO Load: The controller drives a ‘1’ at the rising edge of

SCLOCK to indicate either the start or end of a bit stream. A 4-bit

vendor specific pattern will be transmitted right after the signal

assertion.

If SGPIO interface is not used, this signal can be used as GPIO38.

SDATAOUT0/

GPIO39

SDATAOUT1/

GPIO48

OD O

SGPIO Dataout: Driven by the controller to indicate the drive

status in the following sequence: drive 0, 1, 2, 3, 4, 5, 0, 1, 2...

If SGPIO interface is not used, the signals can be used as GPIO.

SATA3RBIAS I/O SATA3 RBIAS: Analog connection point for a 750  ±1% external

precision resistor.

SATA3COMPI IImpedance Compensation Input: Connected to a 50  (1%)

precision external pull-up resistor to VccIO.

SATA3RCOMPO OImpedance/Current Compensation Output: Connected to a

50  (1%) precision external pull-up resistor to VccIO

Table 2-4. Serial ATA Interface Signals (Sheet 3 of 3)

Name Type Description

Datasheet 63

Signal Description

2.5 LPC Interface

2.6 Interrupt Interface

NOTE: PIRQ Interrupts can only be shared if it is configured as level sensitive. They cannot be

shared if configured as edge triggered.

Table 2-5. LPC Interface Signals

Name Type Description

LAD[3:0] I/O LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pull-

ups are provided.

LFRAME# OLPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.

LDRQ0#,

LDRQ1# /

GPIO23

LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to

request DMA or bus master access. These signals are typically connected

to an external Super I/O device. An internal pull-up resistor is provided on

these signals.

LDRQ1# may optionally be used as GPIO23.

Table 2-6. Interrupt Signals

Name Type Description

SERIRQ I/OD Serial Interrupt Request: This pin implements the serial interrupt

protocol.

PIRQ[D:A]# I/OD

PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can

be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as

described in Section 5.8.6. Each PIRQx# line has a separate Route

Control register.

In APIC mode, these signals are connected to the internal I/O APIC in

the following fashion: PIRQA# is connected to IRQ16, PIRQB# to

IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the

legacy interrupts.

These signals are 5 V tolerant.

PIRQ[H:E]# /

GPIO[5:2] I/OD

PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can

be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as

described in Section 5.8.6. Each PIRQx# line has a separate Route

Control register.

In APIC mode, these signals are connected to the internal I/O APIC in

the following fashion: PIRQE# is connected to IRQ20, PIRQF# to

IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the

legacy interrupts. If not needed for interrupts, these signals can be

used as GPIO.

These signals are 5 V tolerant.

Signal Description

64 Datasheet

2.7 USB Interface

Table 2-7. USB Interface Signals (Sheet 1 of 2)

Name Type Description

USBP0P,

USBP0N,

USBP1P,

USBP1N

I/O

Universal Serial Bus Port [1:0] Differential: These differential

pairs are used to transmit Data/Address/Command signals for ports 0

and 1. These ports can be routed to EHCI Controller 1.

NOTE: No external resistors are required on these signals. The PCH

integrates 15 k pull-downs and provides an output driver

impedance of 45  which requires no external series resistor.

USBP2P,

USBP2N,

USBP3P,

USBP3N

I/O

Universal Serial Bus Port [3:2] Differential: These differential

pairs are used to transmit data/address/command signals for ports 2

and 3. These ports can be routed to EHCI Controller 1.

NOTE: No external resistors are required on these signals. The PCH

integrates 15 k pull-downs and provides an output driver

impedance of 45  which requires no external series resistor.

USBP4P,

USBP4N,

USBP5P,

USBP5N

I/O

Universal Serial Bus Port [5:4] Differential: These differential

pairs are used to transmit Data/Address/Command signals for ports 4

and 5. These ports can be routed to EHCI Controller 1.

NOTE: No external resistors are required on these signals. The PCH

integrates 15 k pull-downs and provides an output driver

impedance of 45  which requires no external series resistor.

USBP6P,

USBP6N,

USBP7P,

USBP7N

I/O

Universal Serial Bus Port [7:6] Differential: These differential

pairs are used to transmit Data/Address/Command signals for ports 6

and 7. These ports can be routed to EHCI Controller 1.

NOTE: No external resistors are required on these signals. The PCH

integrates 15 k pull-downs and provides an output driver

impedance of 45  which requires no external series resistor.

USBP8P,

USBP8N,

USBP9P,

USBP9N

I/O

Universal Serial Bus Port [9:8] Differential: These differential

pairs are used to transmit Data/Address/Command signals for ports 8

and 9. These ports can be routed to EHCI Controller 2.

NOTE: No external resistors are required on these signals. The PCH

integrates 15 k pull-downs and provides an output driver

impedance of 45  which requires no external series resistor.

USBP10P,

USBP10N,

USBP11P,

USBP11N

I/O

Universal Serial Bus Port [11:10] Differential: These differential

pairs are used to transmit Data/Address/Command signals for ports

10 and 11. These ports can be routed to EHCI Controller 2.

NOTE: No external resistors are required on these signals. The PCH

integrates 15 k pull-downs and provides an output driver

impedance of 45  which requires no external series resistor.

USBP12P,

USBP12N,

USBP13P,

USBP13N

I/O

Universal Serial Bus Port [13:12] Differential: These differential

pairs are used to transmit Data/Address/Command signals for ports

13 and 12. These ports can be routed to EHCI Controller 2.

NOTE: No external resistors are required on these signals. The PCH

integrates 15 k pull-downs and provides an output driver

impedance of 45  which requires no external series resistor.

Datasheet 65

Signal Description

2.8 Power Management Interface

OC0#/GPIO59

OC1#/GPIO40

OC2#/GPIO41

OC3#/GPIO42

OC4#/GPIO43

OC5#/GPIO9

OC6#/GPIO10

OC7#/GPIO14

Overcurrent Indicators: These signals set corresponding bits in the

USB controllers to indicate that an overcurrent condition has occurred.

OC[7:0]# may optionally be used as GPIOs.

NOTES:

1. OC# pins are not 5 V tolerant.

2. Depending on platform configuration, sharing of OC# pins may

be required.

3. OC[3:0]# can only be used for EHCI Controller 1

4. OC[4:7]# can only be used for EHCI Controller 2

USBRBIAS OUSB Resistor Bias: Analog connection point for an external resistor.

Used to set transmit currents and internal load resistors.

USBRBIAS# I

USB Resistor Bias Complement: Analog connection point for an

external resistor. Used to set transmit currents and internal load

resistors.

Table 2-8. Power Management Interface Signals (Sheet 1 of 4)

Name Type Description

ACPRESENT

/ GPIO31 I

ACPRESENT: This input pin indicates when the platform is plugged

into AC power or not. In addition to the previous Intel® ME to EC

communication, the PCH uses this information to implement the Deep

S4/S5 policies. For example, the platform may be configured to enter

Deep S4/S5 when in S4 or S5 and only when running on battery. This

is powered by Deep S4/S5 Well.

This signal is muxed with GPIO31.

APWROK IActive Sleep Well (ASW) Power OK: When asserted, indicates that

power to the ASW sub-system is stable.

BATLOW#

(Mobile Only)

/ GPIO72

Battery Low: An input from the battery to indicate that there is

insufficient power to boot the system. Assertion will prevent wake

from S3–S5 state. This signal can also be enabled to cause an SMI#

when asserted.

NOTE: See Ta b l e 2 . 2 4 for Desktop implementation pin requirements.

BMBUSY#

/ GPIO0 I

Bus Master Busy: Generic bus master activity indication driven into

the PCH. Can be configured to set the PM1_STS.BM_STS bit. Can also

be configured to assert indications transmitted from the PCH to the

processor using the PMSYNCH pin.

CLKRUN#

(Mobile Only)

/ GPIO32

(Desktop Only)

I/O

PCI Clock Run: Used to support PCI CLKRUN protocol. Connects to

peripherals that need to request clock restart or prevention of clock

stopping.

DPWROK I

DPWROK: Power OK Indication for the VccDSW3_3 voltage rail. This

input is tied together with RSMRST# on platforms that do not support

Deep S4/S5.

This signal is in the RTC well.

Table 2-7. USB Interface Signals (Sheet 2 of 2)

Name Type Description

Signal Description

66 Datasheet

DRAMPWROK OD O

DRAM Power OK: This signal should connect to the processor’s

SM_DRAMPWROK pin. The PCH asserts this pin to indicate when DRAM

power is stable.

This pin requires an external pull-up

LAN_PHY_PW

R_CTRL /

GPIO12

LAN PHY Power Control: LAN_PHY_PWR_CTRL should be connected

to LAN_DISABLE_N on the PHY. PCH will drive LAN_PHY_PWR_CTRL

low to put the PHY into a low power state when functionality is not

needed.

NOTES:

1. LAN_PHY_PWR_CTRL can only be driven low if SLP_LAN# is

deasserted.

2. Signal can instead be used as GPIO12.

PLTRST# O

Platform Reset: The PCH asserts PLTRST# to reset devices on the

platform (such as SIO, FWH, LAN, processor, etc.). The PCH asserts

PLTRST# during power-up and when S/W initiates a hard reset

sequence through the Reset Control register (I/O Register CF9h). The

PCH drives PLTRST# active a minimum of 1 ms when initiated through

the Reset Control register (I/O Register CF9h).

NOTE: PLTRST# is in the VccSus3_3 well.

PWRBTN# I

Power Button: The Power Button will cause SMI# or SCI to indicate a

system request to go to a sleep state. If the system is already in a

sleep state, this signal will cause a wake event. If PWRBTN# is pressed

for more than 4 seconds, this will cause an unconditional transition

(power button override) to the S5 state. Override will occur even if the

system is in the S1-S4 states. This signal has an internal pull-up

resistor and has an internal 16 ms de-bounce on the input. This signal

is in the DSW well.

PWROK I

Power OK: When asserted, PWROK is an indication to the PCH that all

of its core power rails have been stable for 10 ms. PWROK can be

driven asynchronously. When PWROK is negated, the PCH asserts

PLTRST#.

NOTES:

1. It is required that the power rails associated with PCI/PCIe

typically the 3.3 V, 5 V, and 12 V core well rails) have been

valid for 99 ms prior to PWROK assertion in order to comply

with the 100 ms PCI 2.3/PCIe 1.1 specification on PLTRST#

deassertion.

2. PWROK must not glitch, even if RSMRST# is low.

RI# IRing Indicate: This signal is an input from a modem. It can be

enabled as a wake event, and this is preserved across power failures.

RSMRST# I

Resume Well Reset: This signal is used for resetting the resume

power plane logic. This signal must be asserted for at least t201 after

the suspend power wells are valid. When deasserted, this signal is an

indication that the suspend power wells are stable.

SLP_A# OSLP_A#: Used to control power to the active sleep well (ASW) of the

PCH.

Table 2-8. Power Management Interface Signals (Sheet 2 of 4)

Name Type Description

Datasheet 67

Signal Description

SLP_LAN# /

GPIO29 O

LAN Sub-System Sleep Control: When SLP_LAN# is deasserted it

indicates that the PHY device must be powered. When SLP_LAN# is

asserted, power can be shut off to the PHY device. SLP_LAN# will

always be deasserted in S0 and anytime SLP_A# is deasserted.

A SLP_LAN#/GPIO Select Soft-Strap can be used for systems NOT

using SLP_LAN# functionality to revert to GPIO29 usage. When soft-

strap is 0 (default), pin function will be SLP_LAN#. When soft-strap is

set to 1, the pin returns to its regular GPIO mode.

The pin behavior is summarized in Section 5.13.10.5.

SLP_S3# O

S3 Sleep Control: SLP_S3# is for power plane control. This signal

shuts off power to all non-critical systems when in S3 (Suspend To

RAM), S4 (Suspend to Disk), or S5 (Soft Off) states.

SLP_S4# O

S4 Sleep Control: SLP_S4# is for power plane control. This signal

shuts power to all non-critical systems when in the S4 (Suspend to

Disk) or S5 (Soft Off) state.

NOTE: This pin must be used to control the DRAM power in order to

use the PCH’s DRAM power-cycling feature. Refer to

Chapter 5.13.10.2 for details

SLP_S5# /

GPIO63 O

S5 Sleep Control: SLP_S5# is for power plane control. This signal is

used to shut power off to all non-critical systems when in the S5 (Soft

Off) states.

Pin may also be used as GPIO63.

SLP_SUS# O

Deep S4/S5 Indication: When asserted low, this signal indicates

PCH is in Deep S4/S5 state where internal Sus power is shut off for

enhanced power saving. If Deep S4/S5 is not supported, then this pin

can be left unconnected.

This pin is in the DSW power well.

STP_PCI# /

GPIO34 OStop PCI Clock: This signal is an output to the clock generator for it

to turn off the PCI clock.

SUSACK# I

SUSACK#: If Deep S4/S5 is supported, the EC/motherboard

controlling logic must change SUSACK# to match SUSWARN# once

the EC/motherboard controlling logic has completed the preparations

discussed in the description for the SUSWARN# pin.

NOTE: SUSACK# is only required to change in response to

SUSWARN# if Deep S4/S5 is supported by the platform.

This pin is in the Sus power well.

SUS_STAT# /

GPIO61 O

Suspend Status: This signal is asserted by the PCH to indicate that

the system will be entering a low power state soon. This can be

monitored by devices with memory that need to switch from normal

refresh to suspend refresh mode. It can also be used by other

peripherals as an indication that they should isolate their outputs that

may be going to powered-off planes.

Pin may also be used as GPIO61.

SUSCLK /

GPIO62 O

Suspend Clock: This clock is an output of the RTC generator circuit to

use by other chips for refresh clock.

Pin may also be used as GPIO62.

Table 2-8. Power Management Interface Signals (Sheet 3 of 4)

Name Type Description

Signal Description

68 Datasheet

SUSWARN# /

SUSPWRDNACK

/ GPIO30

SUSWARN#: This pin asserts low when the PCH is planning to enter

the Deep S4/S5 power state and remove Suspend power (using

SLP_SUS#). The EC/motherboard controlling logic must observe

edges on this pin, preparing for SUS well power loss on a falling edge

and preparing for SUS well related activity (host/Intel ME wakes and

runtime events) on a rising edge. SUSACK# must be driven to match

SUSWARN# once the above preparation is complete. SUSACK# should

be asserted within a minimal amount of time from SUSWARN#

assertion as no wake events are supported if SUSWARN# is asserted

but SUSACK# is not asserted. Platforms supporting Deep S4/S5, but

not wishing to participate in the handshake during wake and Deep S4/

S5 entry may tie SUSACK# to SUSWARN#.

This pin may be muxed with a GPIO for use in systems that do not

support Deep S4/S5. This pin is muxed with SUSPWRDNACK since it is

not needed in Deep S4/S5 supported platforms.

Reset type: RSMRST#

This signal is multiplexed with GPIO30 and SUSPWRDNACK.

SUSPWRDNA

CK /

SUSWARN# /

GPIO30

SUSPWRDNACK: Active high. Asserted by the PCH on behalf of the

Intel ME when it does not require the PCH Suspend well to be

powered.

Platforms are not expected to use this signal when the PCH’s Deep S4/

S5 feature is used.

This signal is multiplexed with GPIO30 and SUSWARN#.

SYS_PWROK I

System Power OK: This generic power good input to the PCH is

driven and utilized in a platform-specific manner. While PWROK always

indicates that the core wells of the PCH are stable, SYS_PWROK is

used to inform the PCH that power is stable to some other system

component(s) and the system is ready to start the exit from reset.

SYS_RESET# I

System Reset: This pin forces an internal reset after being

debounced. The PCH will reset immediately if the SMBus is idle;

otherwise, it will wait up to 25 ms ±2 ms for the SMBus to idle before

forcing a reset on the system.

WAKE# IPCI Express* Wake Event: Sideband wake signal on PCI Express

asserted by components requesting wake up.

Table 2-8. Power Management Interface Signals (Sheet 4 of 4)

Name Type Description

Datasheet 69

Signal Description

2.9 Processor Interface

2.10 SMBus Interface

2.11 System Management Interface

Table 2-9. Processor Interface Signals

Name Type Description

RCIN# I

Keyboard Controller Reset Processor: The keyboard controller

can generate INIT# to the processor. This saves the external OR gate

with the PCH’s other sources of INIT#. When the PCH detects the

assertion of this signal, INIT# is generated using a VLW message to

the processor.

NOTE: The PCH will ignore RCIN# assertion during transitions to the

S3, S4, and S5 states.

A20GATE I

A20 Gate: A20GATE is from the keyboard controller. The signal acts

as an alternative method to force the A20M# VLW message to the

processor active.

PROCPWRGD O

Processor Power Good: This signal should be connected to the

processor’s UNCOREPWRGOOD input to indicate when the processor

power is valid.

PMSYNCH OPower Management Sync: Provides state information from the PCH

to the processor

THRMTRIP# I

Thermal Trip: When low, this signal indicates that a thermal trip

from the processor occurred, and the PCH will immediately transition

to a S5 state. The PCH will not wait for the processor stop grant cycle

since the processor has overheated.

Table 2-10. SM Bus Interface Signals

Name Type Description

SMBDATA I/OD SMBus Data: External pull-up resistor is required.

SMBCLK I/OD SMBus Clock: External pull-up resistor is required.

SMBALERT# /

GPIO11 I

SMBus Alert: This signal is used to wake the system or generate

SMI#.

This signal may be used as GPIO11.

Table 2-11. System Management Interface Signals (Sheet 1 of 2)

Name Type Description

INTRUDER# I

Intruder Detect: This signal can be set to disable the system if box

detected open. This signal’s status is readable, so it can be used like a

GPI if the Intruder Detection is not needed.

SML0DATA I/OD System Management Link 0 Data: SMBus link to external PHY.

External pull-up is required.

SML0CLK I/OD System Management Link 0 Clock: SMBus link to external PHY.

External pull-up is required.

SML0ALERT# /

GPIO60 O OD

SMLink Alert 0: Output of the integrated LAN controller to external

PHY. External pull-up resistor is required.

This signal can instead be used as GPIO60.

Signal Description

70 Datasheet

2.12 Real Time Clock Interface

2.13 Miscellaneous Signals

SML1ALERT# /

PCHHOT# /

GPIO74

O OD

SMLink Alert 1: Alert for the ME SMBus controller to optional

Embedded Controller or BMC. External pull-up resistor is required.

This signal can instead be used as PCHHOT# or GPIO74

NOTE: A soft-strap determines the native function SML1ALERT# or

PCHHOT# usage. When soft-strap is 0, function is

SML1ALERT#, when soft-strap is 1, function is PCHHOT#.

SML1CLK /

GPIO58 I/OD

System Management Link 1 Clock: SMBus link to optional

Embedded Controller or BMC. External pull-up resistor is required.

This signal can instead be used as GPIO58

SML1DATA /

GPIO75 I/OD

System Management Link 1 Data: SMBus link to optional

Embedded Controller or BMC. External pull-up resistor is required.

This signal can instead be used as GPIO75

Table 2-12. Real Time Clock Interface

Name Type Description

RTCX1 Special

Crystal Input 1: This signal is connected to the 32.768 kHz crystal. If

no external crystal is used, then RTCX1 can be driven with the desired

clock rate.

RTCX2 Special Crystal Input 2: This signal is connected to the 32.768 kHz crystal. If

no external crystal is used, then RTCX2 should be left floating.

Table 2-13. Miscellaneous Signals (Sheet 1 of 2)

Name Type Description

INTVRMEN I

Internal Voltage Regulator Enable: This signal enables the

internal 1.05 V regulators when pulled high.

This signal must be always pulled-up to VccRTC on desktop platforms

and may optionally be pulled low on mobile platforms if using an

external VR for the DcpSus rail.

NOTE: See VccCore signal description for behavior when INTVRMEN

is sampled low (external VR mode).

DSWVRMEN I

Deep S4/S5 Well Internal Voltage Regulator Enable: This signal

enables the internal DSW 1.05 V regulators.

This signal must be always pulled-up to VccRTC.

SPKR O

Speaker: The SPKR signal is the output of counter 2 and is internally

“ANDed” with Port 61h Bit 1 to provide Speaker Data Enable. This

signal drives an external speaker driver device, which in turn drives

the system speaker. Upon PLTRST#, its output state is 0.

NOTE: SPKR is sampled as a functional strap. See Section 2.27 for

more details. There is a weak integrated pull-down resistor on

SPKR pin.

Table 2-11. System Management Interface Signals (Sheet 2 of 2)

Name Type Description

Datasheet 71

Signal Description

RTCRST# I

RTC Reset: When asserted, this signal resets register bits in the RTC

well.

NOTES:

1. Unless CMOS is being cleared (only to be done in the G3

power state), the RTCRST# input must always be high when

all other RTC power planes are on.

2. In the case where the RTC battery is dead or missing on the

platform, the RTCRST# pin must rise before the RSMRST#

pin.

SRTCRST# I

Secondary RTC Reset: This signal resets the manageability register

bits in the RTC well when the RTC battery is removed.

NOTES:

1. The SRTCRST# input must always be high when all other RTC

power planes are on.

2. In the case where the RTC battery is dead or missing on the

platform, the SRTCRST# pin must rise before the RSMRST#

pin.

SML1ALERT#/

PCHHOT#/

GPIO74

PCHHOT#: This signal is used to indicate a PCH temperature out of

bounds condition to an external EC, when PCH temperature is greater

than value programmed by BIOS. An external pull-up resistor is

required on this signal.

NOTE: A soft-strap determines the native function SML1ALERT# or

PCHHOT# usage. When soft-strap is 0, function is

SML1ALERT#, when soft-strap is 1, function is PCHHOT#.

INIT3_3V# O

Initialization 3.3 V: INIT3_3V# is asserted by the PCH for 16 PCI

clocks to reset the processor. This signal is intended for Firmware

Hub.

GPIO35 / NMI#

(Server /

Workstation

Only)

OD O

NMI#: This is an NMI event indication to an external controller (such

as a BMC) on server/workstation platforms.

When operating as NMI event indication pin function (enabled when

"NMI SMI Event Native GPIO Enable" soft strap [PCHSTRP9:bit 16] is

set to 1), the pin is OD (open drain).

PCIECLKRQ2# /

GPIO20 / SMI#

(Server /

Workstation

Only)

OD O

SMI#: This is an SMI event indication to an external controller (such

as a BMC) on server/workstation platforms.

When operating as SMI event indication pin function (enabled when

"NMI SMI Event Native GPIO Enable" soft strap [PCHSTRP9:bit 16] is

set to 1), the pin is OD (open drain).

Table 2-13. Miscellaneous Signals (Sheet 2 of 2)

Name Type Description

Signal Description

72 Datasheet

2.14 Intel® High Definition Audio Link

Table 2-14. Intel® High Definition Audio Link Signals

Name Type Description

HDA_RST# OIntel® High Definition Audio Reset: Master hardware reset to

external codec(s).

HDA_SYNC O

Intel High Definition Audio Sync: 48 kHz fixed rate sample

sync to the codec(s). Also used to encode the stream number.

NOTE: This signal is sampled as a functional strap. See

Section 2.27 for more details. There is a weak integrated

pull-down resistor on this pin.

HDA_BCLK O

Intel High Definition Audio Bit Clock Output: 24.000 MHz

serial data clock generated by the Intel High Definition Audio

controller (the PCH).

HDA_SDO O

Intel High Definition Audio Serial Data Out: Serial TDM data

output to the codec(s). This serial output is double-pumped for a

bit rate of 48 Mb/s for Intel High Definition Audio.

NOTE: This signal is sampled as a functional strap. See

Section 2.27 for more details. There is a weak integrated

pull-down resistor on this pin.

HDA_SDIN[3:0] I

Intel High Definition Audio Serial Data In [3:0]: Serial TDM

data inputs from the codecs. The serial input is single-pumped

for a bit rate of 24 Mb/s for Intel High Definition Audio. These

signals have integrated pull-down resistors, which are always

enabled.

NOTE: During enumeration, the PCH will drive this signal. During

normal operation, the CODEC will drive it.

HDA_DOCK_EN#

/GPIO33 O

Intel High Definition Audio Dock Enable: This signal controls

the external Intel HD Audio docking isolation logic. This is an

active low signal. When deasserted the external docking switch is

in isolate mode. When asserted the external docking switch

electrically connects the Intel HD Audio dock signals to the

corresponding PCH signals.

This signal can instead be used as GPIO33.

HDA_DOCK_RST#

/ GPIO13 O

Intel High Definition Audio Dock Reset: This signal is a

dedicated HDA_RST# signal for the codec(s) in the docking

station. Aside from operating independently from the normal

HDA_RST# signal, it otherwise works similarly to the HDA_RST#

signal.

This signal is shared with GPIO13. This signal defaults to GPIO13

mode after PLTRST#. BIOS is responsible for configuring GPIO13

to HDA_DOCK_RST# mode.

Datasheet 73

Signal Description

2.15 Controller Link

2.16 Serial Peripheral Interface (SPI)

2.17 Thermal Signals

Table 2-15. Controller Link Signals

Signal Name Type Description

CL_RST1# O

Controller Link Reset: Controller Link reset that connects to a

Wireless LAN Device supporting Intel Active Management

Technology.

CL_CLK1 I/O

Controller Link Clock: Bi-directional clock that connects to a

Wireless LAN Device supporting Intel Active Management

Technology.

CL_DATA1 I/O

Controller Link Data: Bi-directional data that connects to a

Wireless LAN Device supporting Intel Active Management

Technology.

Table 2-16. Serial Peripheral Interface (SPI) Signals

Name Type Description

SPI_CS0# OSPI Chip Select 0: Used as the SPI bus request signal.

SPI_CS1# OSPI Chip Select 1: Used as the SPI bus request signal.

SPI_MISO ISPI Master IN Slave OUT: Data input pin for PCH.

SPI_MOSI I/O SPI Master OUT Slave IN: Data output pin for PCH.

SPI_CLK OSPI Clock: SPI clock signal, during idle the bus owner will drive the

clock signal low. 17.86 MHz and 31.25 MHz.

Table 2-17. Thermal Signals (Sheet 1 of 2)

Signal Name Type Description

PWM[3:0]

(Server/

Workstation Usage

Only); Not

available in Mobile

& Desktop)

OD O

Fan Pulse Width Modulation Outputs: Pulse Width Modulated

duty cycle output signals used for fan control.

These signals are 5 V tolerant.

TACH0 / GPIO17

TACH1 / GPIO1

TACH2 / GPIO6

TACH3 / GPIO7

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

(TACH* signals

used on Server/

Workstation Only;

not available in

Mobile & Desktop)

Fan Tachometer Inputs: Tachometer pulse input signal that is

used to measure fan speed. This signal is connected to the

“Sense” signal on the fan.

Can instead be used as a GPIO.

Signal Description

74 Datasheet

2.18 Testability Signals

NOTE: JTAG Pin definitions are from IEEE Standard Test Access Port and Boundary-Scan

Architecture (IEEE Std. 1149.1-2001)

2.19 Clock Signals

SST (Server/

Workstation Usage

Only; not

available in Mobile

& Desktop)

I/O

Simple Serial Transport: Single-wire, serial bus. Connect to

SST compliant devices such as SST thermal sensors or voltage

sensors.

PECI I/O Platform Environment Control Interface: Single-wire, serial

bus.

Table 2-18. Testability Signals

Name Type Description

JTAG_TCK ITest Clock Input (TCK): The test clock input provides the clock

for the JTAG test logic.

JTAG_TMS I

Test Mode Select (TMS): The signal is decoded by the Test

Access Port (TAP) controller to control test operations.

JTAG_TDI I

Test Data Input (TDI): Serial test instructions and data are

received by the test logic at TDI.

JTAG_TDO OD Test Data Output (TDO): TDO is the serial output for test

instructions and data from the test logic defined in this standard.

Table 2-17. Thermal Signals (Sheet 2 of 2)

Signal Name Type Description

Table 2-19. Clock Interface Signals (Sheet 1 of 3)

Name Type Description

CLKOUT_ITPXDP_P,

CLKOUT_ITPXDP_N O100 MHz Differential output to processor XDP/ITP connector on

platform

CLKOUT_DP_P,

CLKOUT_DP_N O 120 MHz Differential output for DisplayPort reference

CLKIN_DMI_P,

CLKIN_DMI_N IUnused.

NOTE: External pull-down input termination is required

CLKOUT_DMI_P,

CLKOUT_DMI_N O100 MHz PCIe Gen2 specification jitter tolerant differential

output to processor.

CLKIN_SATA_P,

CLKIN_SATA_N IUnused.

NOTE: External pull-down input termination is required

CLKIN_DOT96_P,

CLKIN_DOT96_N IUnused.

NOTE: External pull-down input termination is required

XTAL25_IN I Connection for 25 MHz crystal to PCH oscillator circuit.

XTAL25_OUT O Connection for 25 MHz crystal to PCH oscillator circuit.

REFCLK14IN IUnused.

NOTE: External pull-down input termination is required

Datasheet 75

Signal Description

CLKOUT_PEG_A_P,

CLKOUT_PEG_A_N O100 MHz Gen2 PCIe specification differential output to PCI

Express* Graphics device

CLKOUT_PEG_B_P,

CLKOUT_PEG_B_N O100 MHz Gen2 PCIe specification differential output to a

second PCI Express Graphics device

PEG_A_CLKRQ# /

GPIO47 (Mobile

Only),

PEG_B_CLKRQ# /

GPIO56

(Mobile Only)

Clock Request Signals for PCIe Graphics SLOTS

Can instead by used as GPIOs

NOTE: External pull-up resistor required if used for CLKREQ#

functionality

CLKOUT_PCIE[7:0]

_P,

CLKOUT_PCIE[7:0]

O100 MHz PCIe Gen2 specification differential output to PCI

Express devices

CLKIN_GND0_P,

CLKIN_GND0_N

(Desktop Only)

CLKIN_GND1_P,

CLKIN_GND1_N

IRequires external pull-down termination (can be shared

between P and N signals of the differential pair).

PCIECLKRQ0# /

GPIO73,

PCIECLKRQ1# /

GPIO18,

PCIECLKRQ3# /

GPIO25,

PCIECLKRQ4# /

GPIO26

(all the above

CLKRQ# signals are

Mobile Only)

Clock Request Signals for PCI Express 100 MHz Clocks

Can instead by used as GPIOs

NOTE: External pull-up resistor required if used for CLKREQ#

functionality

PCIECLKRQ2# /

GPIO20 / SMI#,

PCIECLKRQ5# /

GPIO44,

PCIECLKRQ6# /

GPIO45,

PCIECLKRQ7# /

GPIO46

(SMI# above is

server/workstation

only)

Clock Request Signals for PCI Express 100 MHz Clocks

Can instead by used as GPIOs

NOTE: External pull-up resistor required if used for CLKREQ#

functionality

CLKOUT_PCI[4:0] O

Single-Ended, 33 MHz outputs to PCI connectors/devices. One

of these signals must be connected to CLKIN_PCILOOPBACK

to function as a PCI clock loopback. This allows skew control

for variable lengths of CLKOUT_PCI[4:0].

CLKIN_PCILOOPBA

CK I

33 MHz PCI clock feedback input, to reduce skew between PCH

on-die PCI clock and PCI clock observed by connected PCI

devices

CLKOUTFLEX01 /

GPIO64 O

Configurable as a GPIO or as a programmable output clock

which can be configured as one of the following:

• 33 MHz

• 27 MHz (SSC/Non-SSC)

• 48/24 MHz

• 14.318 MHz

• DC Output logic ‘0’

Table 2-19. Clock Interface Signals (Sheet 2 of 3)

Name Type Description

Signal Description

76 Datasheet

NOTE:

1. It is highly recommended to prioritize 27/14.318/24/48 MHz clocks on CLKOUTFLEX1 and

CLKOUTFLEX3 outputs. Intel does not recommend configuring the 27/14.318/24/48 MHz

clocks on CLKOUTFLEX0 and CLKOUTFLEX2 if more than 2x 33 MHz clocks in addition to

the Feedback clock are used on the CLKOUT_PCI outputs.

CLKOUTFLEX11 /

GPIO65 O

Configurable as a GPIO or as a programmable output clock

which can be configured as one of the following:

• Non functional and unsupported clock output value (Default)

• 27 MHz (SSC/Non-SSC)

• 14.318 MHz output to SIO/EC

• 48/24 MHz

• DC Output logic ‘0’

CLKOUTFLEX21 /

GPIO66 O

Configurable as a GPIO or as a programmable output clock

which can be configured as one of the following:

• 33 MHz

• 25 MHz

• 27 MHz (SSC/Non-SSC)

• 48/24 MHz

• 14.318 MHz

• DC Output logic ‘0’

CLKOUTFLEX31 /

GPIO67 O

Configurable as a GPIO or as a programmable output clock

which can be configured as one of the following:

• 27 MHz (SSC/Non SSC)

• 14.318 MHz output to SIO

• 48/24 MHz (Default)

• DC Output logic ‘0’

XCLK_RCOMP I/O

Differential clock buffer Impedance Compensation:

Connected to an external precision resistor (90.9  ±1%) to

VccDIFFCLKN

Table 2-19. Clock Interface Signals (Sheet 3 of 3)

Name Type Description

Datasheet 77

Signal Description

2.20 LVDS Signals

All signals are Mobile Only, except as signals noted otherwise that are available in the

desktop package.

Table 2-20. LVDS Interface Signals

Name Type Description

LVDSA_DATA[3:0] O LVDS Channel A differential data output - positive

LVDSA_DATA#[3:0] O LVDS Channel A differential data output - negative

LVDSA_CLK O LVDS Channel A differential clock output - positive

LVDSA_CLK# O LVDS Channel A differential clock output - negative

LVDSB_DATA[3:0] O LVDS Channel B differential data output - positive

LVDSB_DATA#[3:0] O LVDS Channel B differential data output - negative

LVDSB_CLK O LVDS Channel B differential clock output - positive

LVDSB_CLK# O LVDS Channel B differential clock output - negative

L_DDC_CLK I/O EDID support for flat panel display

L_DDC_DATA I/O EDID support for flat panel display

L_CTRL_CLK I/O Control signal (clock) for external SSC clock chip control –

optional

L_CTRL_DATA I/O Control signal (data) for external SSC clock chip control –

optional

L_VDD_EN (available

in Desktop) O

LVDS Panel Power Enable: Panel power control enable

control for LVDS or embedded DisplayPort*.

This signal is also called VDD_DBL in the CPIS specification

and is used to control the VDC source to the panel logic.

L_BKLTEN (available in

Desktop) O

LVDS Backlight Enable: Panel backlight enable control for

LVDS or embedded DisplayPort.

This signal is also called ENA_BL in the CPIS specification

and is used to gate power into the backlight circuitry.

L_BKLTCTL (available

in Desktop) O

Panel Backlight Brightness Control: Panel brightness

control for LVDS or embedded DisplayPort.

This signal is also called VARY_BL in the CPIS specification

and is used as the PWM Clock input signal.

LVDS_VREFH O Test mode voltage reference.

LVDS_VREFL O Test mode voltage reference.

LVD_IBG I LVDS reference current.

LVD_VBG O Test mode voltage reference.

Signal Description

78 Datasheet

2.21 Analog Display /VGA DAC Signals

2.22 Intel® Flexible Display Interface (Intel® FDI)

Table 2-21. Analog Display Interface Signals

Name Type Description

VGA_RED O

RED Analog Video Output: This signal is a VGA Analog video

output from the internal color palette DAC.

VGA_GREEN O

GREEN Analog Video Output: This signal is a VGA Analog

video output from the internal color palette DAC.

VGA_BLUE O

BLUE Analog Video Output: This signal is a VGA Analog video

output from the internal color palette DAC.

DAC_IREF I/O

Resistor Set: Set point resistor for the internal color palette

DAC. A 1 k 1% resistor is required between DAC_IREF and

motherboard ground.

VGA_HSYNC O

HVCMOS

VGA Horizontal Synchronization: This signal is used as the

horizontal sync (polarity is programmable) or “sync interval”. 2.5

V output

VGA_VSYNC O

HVCMOS

VGA Vertical Synchronization: This signal is used as the

vertical sync (polarity is programmable). 2.5 V output.

VGA_DDC_CLK I/O

COD Monitor Control Clock

VGA_DDC_DATA I/O

COD Monitor Control Data

VGA_IRTN I/O

COD Monitor Interrupt Return

Table 2-22. Intel® Flexible Display Interface Signals

Signal Name Type Description

FDI_RXP[3:0] I Display Link 1 positive data in

FDI_RXN[3:0] I Display Link 1 negative data in

FDI_FSYNC[0] ODisplay Link 1 Frame sync

FDI_LSYNC[0] O Display Link 1 Line sync

FDI_RXP[7:4] I Display Link 2 positive data in

FDI_RXN[7:4] I Display Link 2 negative data in

FDI_FSYNC[1] ODisplay Link 2 Frame sync

FDI_LSYNC[1] O Display Link 2 Line sync

FDI_INT O Used for Display interrupts from PCH to processor.

Datasheet 79

Signal Description

2.23 Digital Display Signals

Table 2-23. Digital Display Interface Signals (Sheet 1 of 3)

Name Type Description

DDPB_[3:0]P O

Port B: Capable of SDVO / HDMI / DVI / DisplayPort

SDVO

DDPB_[0]P: red

DDPB_[1]P: green

DDPB_[2]P: blue

DDPB_[3]P: clock

HDMI / DVI Port B Data and Clock Lines

DDPB_[0]P: TMDSB_DATA2

DDPB_[1]P: TMDSB_DATA1

DDPB_[2]P: TMDSB_DATA0

DDPB_[3]P: TMDSB_CLK

DisplayPort Port B

DDPB_[0]P: Display Port Lane 0

DDPB_[1]P: Display Port Lane 1

DDPB_[2]P: Display Port Lane 2

DDPB_[3]P: Display Port Lane 3

DDPB_[3:0]N O

Port B: Capable of SDVO / HDMI / DVI / DisplayPort

SDVO

DDPB_[0]N: red complement

DDPB_[1]N: green complement

DDPB_[2]N: blue complement

DDPB_[3]N: clock complement

HDMI / DVI Port B Data and Clock Line Complements

DDPB_[0]N: TMDSB_DATA2B

DDPB_[1]N: TMDSB_DATA1B

DDPB_[2]N: TMDSB_DATA0B

DDPB_[3]N: TMDSB_CLKB

DisplayPort Port B

DDPB_[0]N: Display Port Lane 0 complement

DDPB_[1]N: Display Port Lane 1 complement

DDPB_[2]N: Display Port Lane 2 complement

DDPB_[3]N: Display Port Lane 3 complement

DDPB_AUXP I/O Port B: DisplayPort Aux

DDPB_AUXN I/O Port B: DisplayPort Aux Complement

DDPB_HPD IPort B: TMDSB_HPD Hot Plug Detect

SDVO_CTRLCLK I/O Port B: HDMI Control Clock. Shared with port B SDVO

Signal Description

80 Datasheet

SDVO_CTRLDATA I/O Port B: HDMI Control Data. Shared with Port B SDVO

SDVO_INTP ISDVO_INTP: Serial Digital Video Input Interrupt

SDVO_INTN ISDVO_INTN: Serial Digital Video Input Interrupt Complement.

SDVO_TVCLKINP ISDVO_TVCLKINP: Serial Digital Video TVOUT Synchronization

Clock.

SDVO_TVCLKINN ISDVO_TVCLKINN: Serial Digital Video TVOUT Synchronization

Clock Complement.

SDVO_STALLP ISDVO_STALLP: Serial Digital Video Field Stall.

SDVO_STALLN ISDVO_STALLN: Serial Digital Video Field Stall Complement.

DDPC_[3:0]P O

Port C: Capable of HDMI / DVI / DP

HDMI / DVI Port C Data and Clock Lines

DDPC_[0]P: TMDSC_DATA2

DDPC_[1]P: TMDSC_DATA1

DDPC_[2]P: TMDSC_DATA0

DDPC_[3]P: TMDSC_CLK

DisplayPort Port C

DDPC_[0]P: Display Port Lane 0

DDPC_[1]P: Display Port Lane 1

DDPC_[2]P: Display Port Lane 2

DDPC_[3]P: Display Port Lane 3

DDPC_[3:0]N O

Port C: Capable of HDMI / DVI / DisplayPort

HDMI / DVI Port C Data and Clock Line Complements

DDPC_[0]N: TMDSC_DATA2B

DDPC_[1]N: TMDSC_DATA1B

DDPC_[2]N: TMDSC_DATA0B

DDPC_[3]N: TMDSC_CLKB

DisplayPort Port C Complements

DDPC_[0]N: Lane 0 complement

DDPC_[1]N: Lane 1 complement

DDPC_[2]N: Lane 2 complement

DDPC_[3]N: Lane 3 complement

DDPC_AUXP I/O Port C: Display Port Aux

DDPC_AUXN I/O Port C: Display Port Aux Complement

DDPC_HPD IPort C: TMDSC_HPD Hot Plug Detect

DDPC_CTRLCLK I/O HDMI Port C Control Clock

DDPC_CTRLDATA I/O HDMI Port C Control Data

Table 2-23. Digital Display Interface Signals (Sheet 2 of 3)

Name Type Description

Datasheet 81

Signal Description

DDPD_[3:0]P O

Port D: Capable of HDMI / DVI / DP

HDMI / DVI Port D Data and Clock Lines

DDPD_[0]P: TMDSC_DATA2

DDPD_[1]P: TMDSC_DATA1

DDPD_[2]P: TMDSC_DATA0

DDPD_[3]P: TMDSC_CLK

DisplayPort Port D

DDPD_[0]P: Display Port Lane 0

DDPD_[1]P: Display Port Lane 1

DDPD_[2]P: Display Port Lane 2

DDPD_[3]P: Display Port Lane 3

DDPD_[3:0]N O

Port D: Capable of HDMI / DVI / DisplayPort

HDMI / DVI Port D Data and Clock Line Complements

DDPD_[0]N: TMDSC_DATA2B

DDPD_[1]N: TMDSC_DATA1B

DDPD_[2]N: TMDSC_DATA0B

DDPD_[3]N: TMDSC_CLKB

DisplayPort Port D Complements

DDPD_[0]N: Lane 0 complement

DDPD_[1]N: Lane 1 complement

DDPD_[2]N: Lane 2 complement

DDPD_[3]N: Lane 3 complement

DDPD_AUXP I/O Port D: DisplayPort Aux

DDPD_AUXN I/O Port D: DisplayPort Aux Complement

DDPD_HPD IPort D: TMDSD_HPD Hot Plug Detect

DDPD_CTRLCLK I/O HDMI Port D Control Clock

DDPD_CTRLDATA I/O HDMI Port D Control Data

Table 2-23. Digital Display Interface Signals (Sheet 3 of 3)

Name Type Description

Signal Description

82 Datasheet

2.24 General Purpose I/O Signals

Notes:

1. GPIO Configuration registers within the Core Well are reset whenever PWROK is

deasserted.

2. GPIO Configuration registers within the Suspend Well are reset when RSMRST# is

asserted, CF9h reset (06h or 0Eh), or SYS_RESET# is asserted. However, CF9h

reset and SYS_RESET# events can be masked from resetting the Suspend well

GPIO by programming appropriate GPIO Reset Select (GPIO_RST_SEL) registers.

3. GPIO24 is an exception to the other GPIO Signals in the Suspend Well and is not

reset by CF9h reset (06h or 0Eh)

Table 2-24. General Purpose I/O Signals (Sheet 1 of 4)

Name Type Tolerance Power

Well Default Blink

Capability Description

GPIO75 I/O 3.3 V Suspend Native No Multiplexed with SML1DATA

(Note 11)

GPIO74 I/O 3.3 V Suspend Native No

Multiplexed with SML1ALERT#/

PCHHOT#

(Note 11)

GPIO73

(Mobile Only) I/O 3.3 V Suspend Native No Multiplexed with PCIECLKRQ0#

GPIO72 I/O 3.3 V Suspend

Native

(Mobile

Only)

Mobile: Multiplexed with BATLOW#.

Desktop: Unmultiplexed; requires

pull-up resistor. (Note 4)

GPIO[71:70] I/O 3.3 V Core Native No

Desktop: Multiplexed with

TACH[7:6]

Mobile: Used as GPIO only

GPIO[69:68] I/O 3.3 V Core GPI No

Desktop: Multiplexed with

TACH[5:4]

Mobile: Used as GPIO only

GPIO67 I/O 3.3 V Core Native No Multiplexed with CLKOUTFLEX3

GPIO66 I/O 3.3 V Core Native No Multiplexed with CLKOUTFLEX2

GPIO65 I/O 3.3 V Core Native No Multiplexed with CLKOUTFLEX1

GPIO64 I/O 3.3 V Core Native No Multiplexed with CLKOUTFLEX0

GPIO63 I/O 3.3 V Suspend Native No Multiplexed with SLP_S5#

GPIO62 I/O 3.3 V Suspend Native No Multiplexed with SUSCLK

GPIO61 I/O 3.3 V Suspend Native No Multiplexed with SUS_STAT#

GPIO60 I/O 3.3 V Suspend Native No Multiplexed with SML0ALERT#

GPIO59 I/O 3.3 V Suspend Native No Multiplexed with OC0#

(Note 11)

GPIO58 I/O 3.3 V Suspend Native No Multiplexed with SML1CLK

GPIO57 I/O 3.3 V Suspend GPI No Unmultiplexed

GPIO56

(Mobile Only) I/O 3.3 V Suspend Native No Mobile: Multiplexed with

PEG_B_CLKRQ#

GPIO55 I/O 3.3 V Core Native No Desktop: Multiplexed with GNT3#

Mobile: Used as GPIO only

Datasheet 83

Signal Description

GPIO54 I/O 5.0 V Core Native No

Desktop: Multiplexed with REQ3#.

(Note 11)

Mobile: Used as GPIO only

GPIO53 I/O 3.3 V Core Native No Desktop: Multiplexed with GNT2#

Mobile: Used as GPIO only

GPIO52 I/O 5.0 V Core Native No

Desktop: Multiplexed with REQ2#.

(Note 11)

Mobile: Used as GPIO only

GPIO51 I/O 3.3 V Core Native No Desktop: Multiplexed with GNT1#

Mobile: Used as GPIO only

GPIO50 I/O 5.0 V Core Native No

Desktop: Multiplexed with REQ1#.

(Note 11)

Mobile: Used as GPIO only

GPIO49 I/O 3.3 V Core GPI No Multiplexed with SATA5GP and

TEMP_ALERT#

GPIO48 I/O 3.3 V Core GPI No Multiplexed with SDATAOUT1.

GPIO47

(Mobile Only) I/O 3.3 V Suspend Native No Multiplexed with PEG_A_CLKRQ#

GPIO46 I/O 3.3 V Suspend Native No Multiplexed with PCIECLKRQ7#

GPIO45 I/O 3.3 V Suspend Native No Multiplexed with PCIECLKRQ6#

GPIO44 I/O 3.3 V Suspend Native No Multiplexed with PCIECLKRQ5#

GPIO[43:

40] I/O 3.3 V Suspend Native No Multiplexed with OC[4:1]#

(Note 11)

GPIO39 I/O 3.3 V Core GPI No Multiplexed with SDATAOUT0.

GPIO38 I/O 3.3 V Core GPI No Multiplexed with SLOAD.

GPIO37 I/O 3.3 V Core GPI No Multiplexed with SATA3GP.

GPIO36 I/O 3.3 V Core GPI No Multiplexed with SATA2GP.

GPIO35 I/O 3.3 V Core GPO No Multiplexed with NMI#.

GPIO34 I/O 3.3 V Core GPI No Multiplexed with STP_PCI#

GPIO33 I/O 3.3 V Core GPO No

Mobile: Multiplexed with

HDA_DOCK_EN# (Mobile Only)

(Note 4)

Desktop: Used as GPIO only

GPIO32

(not available

in Mobile)

I/O 3.3 V Core

GPO,

Native

(Mobile

only)

Unmultiplexed (Desktop Only)

Mobile Only: Used as CLKRUN#,

unavailable as GPIO

(Note 4)

GPIO31 I/O 3.3 V DSW GPI Yes

Multiplexed with ACPRESENT(Mobile

Only) (Note 6)

Desktop: Used as GPIO31 only.

Unavailable as ACPRESENT

Table 2-24. General Purpose I/O Signals (Sheet 2 of 4)

Name Type Tolerance Power

Well Default Blink

Capability Description

Signal Description

84 Datasheet

GPIO30 I/O 3.3 V Suspend Native Yes

Multiplexed with SUSPWRDNACK,

SUSWARN#

Desktop: Can be configured as

SUSWARN# or GPIO30 only. Cannot

be used as SUSPWRDNACK.

Mobile: Used as SUSPWRDNACK,

SUSWARN#, or GPIO30

GPIO29 I/O 3.3 V Suspend GPI No

Multiplexed with SLP_LAN#

Pin usage as GPIO is determined by

SLP_LAN#/GPIO Select Soft-strap.

When soft-strap = 1, pin can be

used as GPIO and defaults to GP

Input (Note 10)

GPIO28 I/O 3.3 V Suspend GPO Yes Unmultiplexed

GPIO27 I/O 3.3 V DSW GPI Yes

Unmultiplexed. Can be configured

as wake input to allow wakes from

Deep S4/S5.

GPIO26

(Mobile Only) I/O 3.3 V Suspend Native Yes Mobile: Multiplexed with

PCIECLKRQ4#

GPIO25

(Mobile Only) I/O 3.3 V Suspend Native Yes Mobile: Multiplexed with

PCIECLKRQ3#

GPIO24 I/O 3.3 V Suspend GPO Yes

Desktop: Can be used as

PROC_MISSING configured using

Intel ME firmware.

Mobile: Unmultiplexed

NOTE: GPIO24 configuration

by CF9h reset event.

GPIO23 I/O 3.3 V Core Native Yes Multiplexed with LDRQ1#.

GPIO22 I/O 3.3 V Core GPI Yes Multiplexed with SCLOCK

GPIO21 I/O 3.3 V Core GPI Yes Multiplexed with SATA0GP

GPIO20 I/O 3.3 V Core Native Yes Multiplexed with PCIECLKRQ2#,

SMI#

GPIO19 I/O 3.3 V Core GPI Yes Multiplexed with SATA1GP

GPIO18

(Mobile Only) I/O 3.3 V Core Native Yes

(Note 7)

Mobile: Multiplexed with

PCIECLKRQ1#

GPIO17 I/O 3.3 V Core GPI Yes Desktop: Multiplexed with TACH0.

Mobile: Used as GPIO17 only.

GPIO16 I/O 3.3 V Core GPI Yes Multiplexed with SATA4GP

GPIO15 I/O 3.3 V Suspend GPO Yes Unmultiplexed

GPIO14 I/O 3.3 V Suspend Native Yes Multiplexed with OC7#

GPIO13 I/O 3.3 V Suspend GPI Yes

Multiplexed with HDA_DOCK_RST#

(Mobile Only) (Note 4)

Desktop: Used as GPIO only

Table 2-24. General Purpose I/O Signals (Sheet 3 of 4)

Name Type Tolerance Power

Well Default Blink

Capability Description

Datasheet 85

Signal Description

NOTES:

1. All GPIOs can be configured as either input or output.

2. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to

either an SMI# or an SCI, but not both.

3. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO

signals are not driven high into powered-down planes. Also, external devices should not be

driving powered down GPIOs high. Some GPIOs may be connected to pins on devices that

exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core

power (PWROK low) or a Power Button Override event will result in the PCH driving a pin to

a logic 1 to another device that is powered down.

4. The functionality that is multiplexed with the GPIO may not be used in desktop

configuration.

5. When this signal is configured as GPO the output stage is an open drain.

6. In an Intel® ME disabled system, GPIO31 may be used as ACPRESENT from the EC.

7. GPIO18 will toggle at a frequency of approximately 1 Hz when the signal is programmed as

a GPIO (when configured as an output) by BIOS.

8. For GPIOs where GPIO vs. Native Mode is configured using SPI Soft Strap, the

corresponding GPIO_USE_SEL bits for these GPIOs have no effect. The GPIO_USE_SEL

bits for these GPIOs may change to reflect the Soft-Strap configuration even though GPIO

Lockdown Enable (GLE) bit is set.

9. These pins are used as Functional straps. See Section 2.27 for more details.

10. Once Soft-strap is set to GPIO mode, this pin will default to GP Input. When Soft-strap is

SLP_LAN# usage and if Host BIOS does not configure as GP Output for SLP_LAN# control,

SLP_LAN# behavior will be based on the setting of the RTC backed SLP_LAN# Default Bit

(D31:F0:A4h:Bit 8).

11. When the multiplexed GPIO is used as GPIO functionality, care should be taken to ensure

the signal is stable in its inactive state of the native functionality, immediately after reset

until it is initialized to GPIO functionality.

GPIO12 I/O 3.3 V Suspend Native Yes

Multiplexed with

LAN_PHY_PWR_CTRL. GPIO / Native

functionality controlled using soft

strap

(Note 8)

GPIO11 I/O 3.3 V Suspend Native Yes Multiplexed with SMBALERT#.

(Note 11)

GPIO10 I/O 3.3 V Suspend Native Yes Multiplexed with OC6#

(Note 11)

GPIO9 I/O 3.3 V Suspend Native Yes Multiplexed with OC5#

(Note 11)

GPIO8 I/O 3.3 V Suspend GPO Yes Unmultiplexed

GPIO[7:6] I/O 3.3 V Core GPI Yes Multiplexed with TACH[3:2].

Mobile: Used as GPIO[7:6] only.

GPIO[5:2] I/OD 5 V Core GPI Yes Multiplexed PIRQ[H:E]# (Note 5).

GPIO1 I/O 3.3 V Core GPI Yes Multiplexed with TACH1.

Mobile: Used as GPIO1 only.

GPIO0 I/O 3.3 V Core GPI Yes Multiplexed with BMBUSY#

Table 2-24. General Purpose I/O Signals (Sheet 4 of 4)

Name Type Tolerance Power

Well Default Blink

Capability Description

Signal Description

86 Datasheet

2.25 Manageability Signals

The following signals can be optionally used by Intel Management Engine supported

applications and appropriately configured by Intel Management Engine firmware. When

configured and used as a manageability function, the associated host GPIO

functionality is no longer available. If the manageability function is not used in a

platform, the signal can be used as a host General Purpose I/O or a native function.

NOTE: SLP_LAN# may also be configured by Intel® ME FW in Sx/Moff. Please refer to SLP_LAN#/

GPIO29 signal description for details.

Table 2-25. Manageability Signals

Name Type Description

SUSWARN# /

SUSPWRDNACK /

GPIO30 (Mobile

Only)

I/O

Used by Intel® ME as either SUSWARN# in Deep S4/S5 state

supported platforms or as SUSPWRDNACK in non Deep S4/S5

state supported platforms.

NOTE: This signal is in the Suspend power well.

ACPRESENT /

GPIO31 (Mobile

Only)

I/O

Input signal from the Embedded Controller (EC) on Mobile

systems to indicate AC power source or the system battery.

Active High indicates AC power.

NOTE: This signal is in the Deep S4/S5 power well.

SATA5GP / GPIO49

/ TEMP_ALERT# I/O

Used as an alert (active low) to indicate to the external

controller (such as EC or SIO) that temperatures are out of

range for the PCH or Graphics/Memory Controller or the

processor core.

NOTE: This signal is in the Core power well.

GPIO24 /

PROC_MISSING

(Desktop Only)

I/O

Used to indicate Processor Missing to the Intel Management

Engine.

NOTE: This signal is in the Suspend power well.

Datasheet 87

Signal Description

2.26 Power and Ground Signals

Table 2-26. Power and Ground Signals (Sheet 1 of 2)

Name Description

DcpRTC Decoupling: This signal is for RTC decoupling only. This signal requires

decoupling.

DcpSST

Decoupling: Internally generated 1.5 V powered off of Suspend Well. This

signal requires decoupling. Decoupling is required even if this feature is not

used.

DcpSus

1.05 V Suspend well power.

Internal VR mode (INTVRMEN sampled high): Well generated internally. Pins

should be left No Connect

External VR mode (INTVRMEN sampled low): Well supplied externally. Pins

should be powered by 1.05 Suspend power supply. Decoupling capacitors are

required.

NOTE: External VR mode applies to Mobile Only.

DcpSusByp

Internally generated 1.05 V Deep S4/S5 well power. This rail should not be

supplied externally.

NOTE: No decoupling capacitors should be used on this rail.

V5REF Reference for 5 V tolerance on core well inputs. This power may be shut off in

S3, S4, S5 or G3 states.

V5REF_Sus Reference for 5 V tolerance on suspend well inputs. This power is not

expected to be shut off unless the system is unplugged.

VccCore

1.05 V supply for core well logic. This power may be shut off in S3, S4, S5 or

G3 states.

NOTE: In external VR mode (INTVRMEN sampled low), the voltage level of

VccCore may be indeterminate while DcpSus (1.05V Suspend Well

Power) supply ramps and prior to PWROK assertion.

Vcc3_3 3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4,

S5 or G3 states.

VccASW

1.05 V supply for the Active Sleep Well. Provides power to the Intel® ME and

integrated LAN. This plane must be on in S0 and other times the Intel ME or

integrated LAN is used.

VccDMI

Power supply for DMI.

1.05 V or 1.0 V based on the processor VCCIO voltage. Please refer to the

respective processor documentation to find the appropriate voltage level.

VccDIFFCLKN 1.05 V supply for Differential Clock Buffers. This power is supplied by the core

well.

VccRTC

3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power

is not expected to be shut off unless the RTC battery is removed or completely

drained.

NOTE: Implementations should not attempt to clear CMOS by using a jumper

to pull VccRTC low. Clearing CMOS can be done by using a jumper on

RTCRST# or GPI.

VccIO 1.05 V supply for core well I/O buffers. This power may be shut off in S3, S4,

S5 or G3 states.

VccSus3_3 3.3 V supply for suspend well I/O buffers. This power is not expected to be

shut off unless the system is unplugged.

VccSusHDA Suspend supply for Intel® HD Audio. This pin can be either 1.5 or 3.3 V.

Signal Description

88 Datasheet

VccVRM 1.5 V/1.8 V supply for internal PLL and VRMs

VccDFTERM 1.8 V or 3.3 V supply for DF_TVS. This pin should be pulled up to 1.8 V or 3.3

V core.

VccADPLLA 1.05 V supply for Display PLL A Analog Power. This power is supplied by the

core well.

VccADPLLB 1.05 V supply for Display PLL B Analog Power. This power is supplied by the

core well.

VccADAC 3.3 V supply for Display DAC Analog Power. This power is supplied by the core

well.

Vss Grounds.

VccAClk

1.05 V Analog power supply for internal clock PLL. This power is supplied by

the core well.

NOTE: This pin can be left as no connect

VccAPLLEXP 1.05 V Analog Power for DMI. This power is supplied by the core well.

NOTE: This pin can be left as no connect

VccAPLLDMI2 1.05 V Analog Power for internal PLL. This power is supplied by core well.

NOTE: This pin can be left as no connect

VccAFDIPLL

1.05 V analog power supply for the FDI PLL. This power is supplied by core

well.

NOTE: This pin can be left as no connect

VccAPLLSATA

1.05 V analog power supply for SATA PLL. This power is supplied by core well.

This rail requires an LC filter when power is supplied from an external VR.

NOTE: This pin can be left as no connect

VccALVDS

(Mobile Only) 3.3 V Analog power supply for LVDS, This power is supplied by core well.

VccTXLVDS

(Mobile Only) 1.8 V I/O power supply for LVDS. This power is supplied by core well.

V_PROC_IO

to drive the processor interface signals. Please refer to the respective

processor documentation to find the appropriate voltage level.

VccDSW3_3 3.3 V supply for Deep S4/S5 wells. If platform does not support Deep S4/S5

then tie to VccSus3_3.

VccSPI

3.3 V supply for SPI Controller Logic. This rail must be powered when VccASW

is powered.

NOTE: This rail can be optionally powered on 3.3 V Suspend power

(VccSus3_3) based on platform needs.

VccSSC 1.05 V supply for Integrated Clock Spread Modulators. This power is supplied

by core well.

VccClkDMI 1.05 V supply for DMI differential clock buffer

Table 2-26. Power and Ground Signals (Sheet 2 of 2)

Name Description

Datasheet 89

Signal Description

2.27 Pin Straps

The following signals are used for static configuration. They are sampled at the rising

edge of PWROK to select configurations (except as noted), and then revert later to their

normal usage. To invoke the associated mode, the signal should be driven at least four

PCI clocks prior to the time it is sampled.

The PCH implements Soft Straps, which are used to configure specific functions within

the PCH and processor very early in the boot process before BIOS or SW intervention.

When Descriptor Mode is enabled, the PCH will read Soft Strap data out of the SPI

device prior to the deassertion of reset to both the Intel Management Engine and the

Host system. Please refer to Section 5.24.2 for information on Descriptor Mode

Table 2-27. Functional Strap Definitions (Sheet 1 of 4)

Signal Usage When

Sampled Comment

SPKR No Reboot Rising edge

of PWROK

The signal has a weak internal pull-down. Note that the internal

pull-down is disabled after PLTRST# deasserts. If the signal is

sampled high, this indicates that the system is strapped to the “No

Reboot” mode (PCH will disable the TCO Timer system reboot

feature). The status of this strap is readable using the NO REBOOT

bit (Chipset Config Registers: Offset 3410h:Bit 5).

INIT3_3V# Reserved Rising edge

of PWROK

This signal has a weak internal pull-up. Note that the internal pull-

up is disabled after PLTRST# deasserts.

NOTE: This signal should not be pulled low

GNT3# /

GPIO55

Top -Bl oc k

Swap Override

Rising edge

of PWROK

The signal has a weak internal pull-up. Note that the internal pull-

up is disabled after PLTRST# deasserts. If the signal is sampled

low, this indicates that the system is strapped to the “topblock

swap” mode (PCH inverts A16 for all cycles targeting BIOS space).

The status of this strap is readable using the Top Swap bit (Chipset

Config Registers: Offset 3414h:Bit 0). Note that software will not

be able to clear the Top-Swap bit until the system is rebooted

without GNT3# being pulled down.

INTVRMEN

Integrated

1.05 V VRM

Enable /

Disable

Always

Integrated 1.05 V VRMs is enabled when high

External VR power source is used for DcpSus when sampled low.

NOTES:

1. External VR powering option is for Mobile Only. Other systems

should not pull the strap low.

2. See VccCore signal description for behavior when INTVRMEN is

sampled low (external VR mode).

Signal Description

90 Datasheet

GNT1#/

GPIO51

Boot BIOS

Strap bit 1

BBS1

Rising edge

of PWROK

This Signal has a weak internal pull-up.

Note that the internal pull-up is disabled after PLTRST#

deasserts.This field determines the destination of accesses to the

BIOS memory range. Also controllable using Boot BIOS Destination

bit (Chipset Config Registers: Offset 3410h:Bit 11). This strap is

used in conjunction with Boot BIOS Destination Selection 0 strap.

NOTES:

1. If option 00 (LPC) is selected, BIOS may still be placed on LPC,

but all platforms are required to have SPI flash connected

directly to the PCH's SPI bus with a valid descriptor in order to

boot.

2. Booting to PCI is intended for debut/testing only. Boot BIOS

Destination Select to LPC/PCI by functional strap or using Boot

BIOS Destination Bit will not affect SPI accesses initiated by

Intel® ME or Integrated GbE LAN.

3. PCI Boot BIOS destination is not supported on Mobile

SATA1GP/

GPIO19

Boot BIOS

Strap bit 0

BBS0

Rising edge

of PWROK

This Signal has a weak internal pull-up.

Note that the internal pull-up is disabled after PLTRST# deasserts.

This field determines the destination of accesses to the BIOS

memory range. Also controllable using Boot BIOS Destination bit

(Chipset Config Registers: Offset 3410h:Bit 10). This strap is used

in conjunction with Boot BIOS Destination Selection 1 strap.

NOTES:

1. If option 00 (LPC) is selected, BIOS may still be placed on LPC,

but all platforms are required to have SPI flash connected

directly to the PCH's SPI bus with a valid descriptor in order to

boot.

2. Booting to PCI is intended for debut/testing only. Boot BIOS

Destination Select to LPC/PCI by functional strap or using Boot

BIOS Destination Bit will not affect SPI accesses initiated by

Management Engine or Integrated GbE LAN.

3. PCI Boot BIOS destination is not supported on mobile.

GNT2#/

GPIO53

ESI Strap

(Server/

Workstation

Only)

Rising edge

of PWROK

This Signal has a weak internal pull-up.

Tying this strap low configures DMI for ESI compatible operation.

NOTES:

1. The internal pull-up is disabled after PLTRST# deasserts.

2. ESI compatible mode is for server platforms only. This signal

should not be pulled low for desktop and mobile.

Table 2-27. Functional Strap Definitions (Sheet 2 of 4)

Signal Usage When

Sampled Comment

Bit11 Bit 10 Boot BIOS

Destination

01 Reserved

10 PCI

11 SPI

00 LPC

Bit11 Bit 10 Boot BIOS

Destination

01 Reserved

10 PCI

11 SPI

00 LPC

Datasheet 91

Signal Description

HDA_SDO

Flash

Descriptor

Security

Override /

Intel ME

Debug Mode

Rising edge

of PWROK

Signal has a weak internal pull-down.

If strap is sampled low, the security measures defined in the Flash

Descriptor will be in effect (default) If sampled high, the Flash

Descriptor Security will be overridden.

This strap should only be asserted high using external pull-up in

manufacturing/debug environments ONLY.

NOTES:

1. The weak internal pull-down is disabled after PLTRST#

deasserts.

2. Asserting the HDA_SDO high on the rising edge of PWROK will

also halt Intel® Management Engine after chipset bring up and

disable runtime Intel ME features. This is a debug mode and

must not be asserted after manufacturing/debug.

DF_TVS

DMI and FDI

Tx/Rx

Ter minat ion

Voltage

Rising edge

of PWROK

This signal has a weak internal pull-down.

NOTE: The internal pull-down is disabled after PLTRST# deasserts.

GPIO28

On-Die PLL

Voltage

Regulator

Rising edge

of RSMRST#

This signal has a weak internal pull-up.

NOTE: The internal pull-up is disabled after RSMRST# deasserts.

The On-Die PLL voltage regulator is enabled when sampled high.

When sampled low the On-Die PLL Voltage Regulator is disabled.

HDA_SYNC

On-Die PLL

Voltage

Regulator

Voltage Select

Rising edge

of RSMRST#

This signal has a weak internal pull-down.

On Die PLL VR is supplied by 1.5 V from VccVRM when sampled

high, 1.8 V from VccVRM when sampled low.

GPIO15 TLS

Confidentiality

Rising edge

of RSMRST#

Low = Intel ME Crypto Transport Layer Security (TLS) cipher suite

with no confidentiality

High = Intel ME Crypto TLS cipher suite with confidentiality

This signal has a weak internal pull-down.

NOTES:

1. A strong pull-up may be needed for GPIO functionality

2. This signal must be pulled up to support Intel AMT with

TLS. Intel ME configuration parameters also need to be set

correctly to enable TLS.

L_DDC_DAT

ALVDS Detected Rising edge

of PWROK

When ‘1’- LVDS is detected; When ‘0’- LVDS is not detected.

NOTE: This signal has a weak internal pull-down. The internal pull-

down is disabled after PLTRST# deasserts.

SDVO_CTRL

DATA

Port B

Detected

Rising edge

of PWROK

When ‘1’- Port B is detected; When ‘0’- Port B is not detected

This signal has a weak internal pull-down.

NOTE: The internal pull-down is disabled after PLTRST# deasserts.

DDPC_CTRL

DATA

Port C

Detected

Rising edge

of PWROK

When ‘1’- Port C is detected; When ‘0’- Port C is not detected

This signal has a weak internal pull-down.

NOTE: The internal pull-down is disabled after PLTRST# deasserts.

DDPD_CTRL

DATA

Port D

Detected

Rising edge

of PWROK

When ‘1’- Port D is detected; When ‘0’- Port D is not detected

This signal has a weak internal pull-down.

NOTE: The internal pull-down is disabled after PLTRST# deasserts.

DSWVRMEN

Deep S4/S5

Well On-Die

Voltage

Regulator

Enable

Always If strap is sampled high, the Integrated Deep S4/S5 Well (DSW)

On-Die VR mode is enabled.

Table 2-27. Functional Strap Definitions (Sheet 3 of 4)

Signal Usage When

Sampled Comment

Signal Description

92 Datasheet

NOTE: See Section 3.1 for full details on pull-up/pull-down resistors.

2.28 External RTC Circuitry

The PCH implements an internal oscillator circuit that is sensitive to step voltage

changes in VccRTC. Figure 2-2 shows an example schematic recommended to ensure

correct operation of the PCH RTC.

NOTES:

1. The exact capacitor values for C1 and C2 must be based on the crystal maker

recommendations.

2. Reference designators are arbitrarily assigned.

3. For platforms not supporting Deep S4/S5, the VccDSW3_3 pins will be connected to the

VccSus3_3 pins.

4. Vbatt is voltage provided by the RTC battery (such as coin cell).

5. VccRTC, RTCX1, RTCX2, RTCRST#, and SRTCRST# are PCH pins.

6. VccRTC powers PCH RTC well.

7. RTCX1 is the input to the internal oscillator.

8. RTCX2 is the amplified feedback for the external crystal.

§ §

SATA2GP/

GPIO36 Reserved Rising edge

of PWROK

This signal has a weak internal pull-down.

NOTES:

1. The internal pull-down is disabled after PLTRST# deasserts.

2. This signal should not be pulled high when strap is sampled.

SATA3GP/

GPIO37 Reserved Rising edge

of PWROK

This signal has a weak internal pull-down.

NOTES:

1. The internal pull-down is disabled after PLTRST# deasserts.

2. This signal should not be pulled high when strap is sampled.

GPIO8 Reserved Rising edge

of RSMRST#

This signal has a weak internal pull-up.

NOTES:

1. The internal pull-up is disabled after RSMRST# deasserts.

2. This signal should not be pulled low when strap is sampled.

Table 2-27. Functional Strap Definitions (Sheet 4 of 4)

Signal Usage When

Sampled Comment

Figure 2-2. Example External RTC Circuit

32.768 KHz

Xtal 10M

VCCRTC

RTCX2

RTCX1

Vbatt

1uF

1 K

VccDSW3_3

(see note 3)

C1 C2

RTCRST#

1.0 uF

20 K

0.1uF

SRTCRST#

20 K

1.0 uF

Schottky Diodes

Datasheet 93

PCH Pin States

3 PCH Pin States

3.1 Integrated Pull-Ups and Pull-Downs

Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet 1 of 2)

Signal Resistor Type Nominal No tes

CL_CLK1 Pull-up/Pull-

down 32/100 8, 13

CL_DATA1 Pull-up/Pull-

down 32/100 8, 13

CLKOUTFLEX[3:0]/GPIO[67:64] Pull-down 20K 1, 10

GPIO15 Pull-down 20K 3

HDA_SDIN[3:0] Pull-down 20K 2

HDA_SYNC, HDA_SDO Pull-down 20K 2, 5

GNT[3:1]#/GPIO[55,53,51] Pull-up 20K 3, 6, 7

GPIO8 Pull-up 20K 3, 12

LAD[3:0]# / FWH[3:0]# Pull-up 20K 3

LDRQ0#, LDRQ1# / GPIO23 Pull-up 20K 3

DF_TVS Pull-down 20k 8

PME# Pull-up 20K 3

INIT3_3V# Pull-up 20K 3

PWRBTN# Pull-up 20K 3

SPI_MOSI Pull-down 20K 3, 5

SPI_MISO Pull-up 20K 3

SPKR Pull-down 20K 3, 9

TACH[7:0]/GPIO[71:68,7,6,1,17] Pull-up 20K 3 (only on

TACH[7:0])

USB[13:0] [P,N] Pull-down 20K 4

DDP[D:C]_CRTLDATA Pull-down 20K 3, 9

SDVO_CTRLDATA,L_DDC_DATA Pull-down 20K 3, 9

SDVO_INTP, SDVO_INTN Pull-down 50 18

SDVO_TVCLKINP, SDVO_TVCLKINN Pull-down 50 18

SDVO_STALLP, SDVO_STALLN Pull-down 50 18

BATLOW#/GPIO72 Pull-up 20K 3

CLKOUT_PCI[4:0] Pull-down 20K 1, 10

GPIO27 Pull-up 20K 3, 14

JTAG_TDI, JTAG_TMS Pull-up 20K 1, 11

JTAG_TCK Pull-down 20K 1, 11

GPIO28 Pull-up 20K 3, 12

PCH Pin States

94 Datasheet

NOTES:

1. Simulation data shows that these resistor values can range from 10 k to 40 k.

2. Simulation data shows that these resistor values can range from 9 k to 50 k.

3. Simulation data shows that these resistor values can range from 15 k to 40 k.

4. Simulation data shows that these resistor values can range from 14.25 k to 24.8 k.

5. The pull-up or pull-down on this signal is only enabled at boot/reset for strapping function.

6. The pull-up on this signal is not enabled when PCIRST# is high.

7. The pull-up on this signal is not enabled when PWROK is low.

8. Simulation data shows that these resistor values can range from 15 k to 31 k.

9. The pull-up or pull-down is not active when PLTRST# is NOT asserted.

10. The pull-down is enabled when PWROK is low.

11. External termination is also required on these signals for JTAG enabling.

12. Pull-up is disabled after RSMRST# is deasserted.

13. The Controller Link Clock and Data buffers use internal pull-up or pull-down resistors to

drive a logical 1 or 0.

14. Pull-up is enabled only in Deep S4/S5 state.

15. Pull-down is enabled only in Deep S4/S5 state.

16. When the interface is in BUS IDLE, the Internal Pull-down of 10 k is enabled. In normal

transmission, a 400  pull-down takes effect, the signal will be override to logic 1 with

pull-up resistor (37 ) to VCC 1.5 V.

17. This is a 350- normal pull-down, signal will be overridden to logic 1 with pull-up resistor

(31 ) to VCC 1.05 V.

18. Internal pull-down serves as Rx termination and is enabled after PLTRST# deasserts.

SATA[3:2]GP/GPIO[37:36] Pull-down 20K 3, 9

ACPRESENT/GPIO31 Pull-down 20K 3, 15

PCIECLKRQ5#/GPIO44 Pull-up 20K 1, 12

SST (Server/Workstation Only) Pull-down 10K 16

PCIECLKRQ7#/GPIO46 Pull-up 20K 1, 12

SATA1GP/GPIO19 Pull-up 20K 3, 9

SUSACK# Pull-up 20K 3

PECI Pull-down 350 17

Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet 2 of 2)

Signal Resistor Type Nominal Notes

Datasheet 95

PCH Pin States

3.2 Output and I/O Signals Planes and States

Tabl e 3 . 2 and Tab l e 3 -3 shows the power plane associated with the output and I/O

signals, as well as the state at various times. Within the table, the following terms are

used:

“High-Z” Tri-state. PCH not driving the signal high or low.

“High” PCH is driving the signal to a logic 1.

“Low” PCH is driving the signal to a logic 0.

“Defined” Driven to a level that is defined by the function or external pull-

up/pull-down resistor (will be high or low).

“Undefined” PCH is driving the signal, but the value is indeterminate.

“Running” Clock is toggling or signal is transitioning because function not

stopping.

“Off” The power plane is off; PCH is not driving when configured as an

output or sampling when configured as an input.

“Input” PCH is sampling and signal state determined by external driver.

Note: Signal levels are the same in S4 and S5, except as noted.

PCH suspend well signal states are indeterminate and undefined and may glitch prior to

RSMRST# deassertion. This does not apply to SLP_S3#, SLP_S4#, SLP_S5#, GPIO24,

and GPIO29. These signals are determinate and defined prior to RSMRST# deassertion.

PCH core well signal states are indeterminate and undefined and may glitch prior to

PWROK assertion. This does not apply to THRMTRIP#. This signal is determinate and

defined prior to PWROK assertion.

DSW indicates PCH Deep S4/S5 Well. This state provides a few wake events and critical

context to allow system to draw minimal power in S4 or S5 states.

ASW indicates PCH Active Sleep Well. This power well contains functionality associated

with active usage models while the host system is in Sx.

Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations

(Sheet 1 of 6)

Signal Name Power

Plane

During

Reset1

Immediately

after Reset1S0/S1 S3 S4/S5

PCI Express*

PETp[8:1], PETn[8:1] Core Low Low4Defined OFF OFF

DMI

DMI[3:0]TXP,

DMI[3:0]TXN Core Low Low Defined Off Off

PCI Bus

AD[31:0] Core Low Low Low Off Off

C/BE[3:0]# Core Low Low Low Off Off

DEVSEL# Core High-Z High-Z High-Z Off Off

PCH Pin States

96 Datasheet

FRAME# Core High-Z High-Z High-Z Off Off

GNT0#, GNT[3:1]#7/

GPIO[55, 53, 51] Core High High High Off Off

IRDY#, TRDY# Core High-Z High-Z High-Z Off Off

PAR Core Low Low Low Off Off

PCIRST# Suspend Low High High Low Low

PERR# Core High-Z High-Z High-Z Off Off

PLOCK# Core High-Z High-Z High-Z Off Off

STOP# Core High-Z High-Z High-Z Off Off

LPC/FWH Interface

LAD[3:0] / FWH[3:0] Core High High High Off Off

LFRAME# / FWH[4] Core High High High Off Off

INIT3_3V#7Core High High High Off Off

SATA Interface

SATA[5:0]TXP,

SATA[5:0]TXN Core High-Z High-Z Defined Off Off

SATALED# Core High-Z High-Z Defined Off Off

SATAICOMPO Core High High Defined Off Off

SCLOCK/GPIO22 Core High-Z (Input) High-Z (Input) Defined Off Off

SLOAD/GPIO38 Core High-Z (Input) High-Z (Input) Defined Off Off

SDATAOUT[1:0]/

GPIO[48,39] Core High-Z High-Z High-Z Off Off

SATA3RBIAS Core Te rmi na ted to

Vss

Terminated to

Vss

Term i nate d

to Vss Off Off

SATA3ICOMPO Core High-Z High-Z High-Z Off Off

SATA3RCOMPO Core High-Z High-Z High-Z Off Off

Interrupts

PIRQ[A:D]# Core High-Z High-Z High-Z Off Off

PIRQ[H:E]# /

GPIO[5:2] Core High-Z (Input) High-Z (Input) Defined Off Off

SERIRQ Core High-Z High-Z High-Z Off Off

USB Interface

USB[13:0][P,N] Suspend Low Low Defined Defined Defined

USBRBIAS Suspend High-Z High-Z High High High

Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations

(Sheet 2 of 6)

Signal Name Power

Plane

During

Reset1

Immediately

after Reset1S0/S1 S3 S4/S5

Datasheet 97

PCH Pin States

Power Management

LAN_PHY_PWR_CTRL10/

GPIO12 Suspend Low Low Defined Defined Defined

PLTRST# Suspend Low High High Low Low

SLP_A#5Suspend Low High High Defined Defined

SLP_S3# Suspend Low High High Low Low

SLP_S4# Suspend Low High High High Defined

SLP_S5#/GPIO63 Suspend Low High High High Defined2

SUS_STAT#/GPIO61 Suspend Low High High Low Low

SUSCLK/GPIO62 Suspend Low Running

DRAMPWROK Suspend Low High-Z High-Z High-Z Low

PMSYNCH Core Low Low Defined Off Off

STP_PCI#/GPIO34 Core High-Z (Input) High-Z (Input) Defined Off Off

SLP_LAN#/GPIO298

SLP_LAN# (using soft-

strap)

GPIO29 (using soft-

strap)

Suspend

Low

High-Z

Low8

High-Z

High

High-Z

Defined

High-Z

Defined

High-Z

Processor Interface

PROCPWRGD Processor Low High High Off Off

SMBus Interface

SMBCLK, SMBDATA Suspend High-Z High-Z Defined Defined Defined

System Management Interface

SML0ALERT# / GPIO60 Suspend High-Z High-Z11 Defined Defined Defined

SML0DATA Suspend High-Z High-Z Defined Defined Defined

SML0CLK Suspend High-Z High-Z Defined Defined Defined

SML1CLK/GPIO58 Suspend High-Z High-Z Defined Defined Defined

SML1ALERT#/PCHHOT#/

GPIO74 Suspend High-Z High-Z Defined Defined Defined

SML1DATA/GPIO75 Suspend High-Z High-Z Defined Defined Defined

Miscellaneous Signals

SPKR7Core Low Low Defined Off Off

JTAG_TDO Suspend High-Z High-Z High-Z High-Z High-Z

GPIO24 /

PROC_MISSING Suspend Low Low Defined Defined Defined

Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations

(Sheet 3 of 6)

Signal Name Power

Plane

During

Reset1

Immediately

after Reset1S0/S1 S3 S4/S5

PCH Pin States

98 Datasheet

Clocking Signals

CLKOUT_ITPXDP_P

CLKOUT_ITPXDP_N Core Running Running Running Off Off

CLKOUT_DP_P

CLKOUT_DP_N Core Running Running Running Off Off

CLKOUT_DMI_P,

CLKOUT_DMI_N Core Running Running Running Off Off

CLKOUT_PEG_A_P,

CLKOUT_PEG_A_N Core Running Running Running Off Off

CLKOUT_PEG_B_P,

CLKOUT_PEG_B_N Core Running Running Running Off Off

CLKOUT_PCIE[7:0]P,

CLKOUT_PCIE[7:0]N Core Running Running Running Off Off

CLKOUT_PCI[4:0] Core Running Running Running Off Off

CLKOUTFLEX[3:0]/

GPIO[67:64] Core Low Running Running Off Off

XTAL25_OUT Core Running Running Running Off Off

XCLK_RCOMP Core High-Z High-Z High-Z Off Off

Intel® High Definition Audio Interface

HDA_RST# Suspend Low Low3Defined Low Low

HDA_SDO7 Suspend Low Low Defined Low Low

HDA_SYNC7 Suspend Low Low Defined Low Low

HDA_BCLK13 Suspend Low Low Low Low Low

UnMultiplexed GPIO Signals

GPIO87Suspend High High Defined Defined Defined

GPIO157Suspend Low Low Defined Defined Defined

GPIO277(Non-Deep S4/

S5 mode) DSW High-Z High-Z High-Z High-Z High-Z

GPIO277(Deep S4/S5

mode) DSW High-Z High-Z High-Z High-Z High-Z

GPIO2812 Suspend High Low Low Low Low

GPIO32 Core High High Defined Off Off

GPIO57 Suspend Low High-Z (Input) Defined Defined Defined

GPIO729Suspend High High Defined Defined Defined

Multiplexed GPIO Signals used as GPIO only

GPIO0 Core High-Z (Input) High-Z (Input) Defined Off Off

GPIO139Suspend High-Z High-Z High-Z High-Z High-Z

GPIO309Suspend High-Z (Input) High-Z (Input) Defined Defined Defined

Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations

(Sheet 4 of 6)

Signal Name Power

Plane

During

Reset1

Immediately

after Reset1S0/S1 S3 S4/S5

Datasheet 99

PCH Pin States

GPIO319 (Non Deep-S4/

S5 mode) DSW High-Z (Input) High-Z (Input) Defined Defined Defined

GPIO319 (Deep-S4/S5

mode) DSW High-Z (Input) High-Z (Input) Defined Defined Defined

GPIO339Core High High High Off Off

GPIO35 / NMI#

(NMI# is Server/

Workstation Only)

Core Low Low Defined Off Off

SPI Interface

SPI_CS0# ASW High12 High Defined Defined Defined

SPI_CS1# ASW High12 High Defined Defined Defined

SPI_MOSI ASW Low12 Low Defined Defined Defined

SPI_CLK ASW Low12 Low Running Defined Defined

Controller Link

CL_CLK16Suspend High/Low15 High/Low15 Defined Defined Defined

CL_DATA16Suspend High/Low15 High/Low15 Defined Defined Defined

CL_RST1#6Suspend Low High High High High

Thermal Signals

PWM[3:0]

(Server/Workstation

Only)

Core Low Low Defined Off Off

SST

(Server/Workstation

Only)

Suspend Low Low Defined Off Off

PECI Processor Low Low Defined Off Off

Analog Display / CRT DAC Signals

VGA_RED, VGA_GREEN,

VGA_BLUE Core High-Z High-Z High-Z Off Off

DAC_IREF Core High-Z Low Low Off Off

VGA_HSYNC Core Low Low Low Off Off

VGA_VSYNC Core Low Low Low Off Off

VGA_DDC_CLK Core High-Z High-Z High-Z Off Off

VGA_DDC_DATA Core High-Z High-Z High-Z Off Off

VGA_IRTN Core High-Z High-Z High-Z Off Off

Intel® Flexible Display Interface

FDI_FSYNC[1:0] Core High-Z High-Z High-Z Off Off

FDI_LSYNC[1:0] Core High-Z High-Z High-Z Off Off

FDI_INT Core High-Z High-Z High-Z Off Off

Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations

(Sheet 5 of 6)

Signal Name Power

Plane

During

Reset1

Immediately

after Reset1S0/S1 S3 S4/S5

PCH Pin States

100 Datasheet

NOTES:

1. The states of Core and processor signals are evaluated at the times During PLTRST# and

Immediately after PLTRST#. The states of the Controller Link signals are taken at the

times during CL_RST1# and Immediately after CL_RST1#. The states of the Suspend

signals are evaluated at the times during RSMRST# and Immediately after RSMRST#, with

an exception to GPIO signals; refer to Section 2.24 for more details on GPIO state after

reset. The states of the HDA signals are evaluated at the times During HDA_RST# and

Immediately after HDA_RST#.

2. SLP_S5# signal will be high in the S4 state and low in the S5 state.

3. Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset

HDBAR+08h:bit 0), at which time HDA_RST# will be High and HDA_BIT_CLK will be

Running.

4. PETp/n[8:1] low until port is enabled by software.

5. The SLP_A# state will be determined by Intel ME Policies.

6. The state of signals in S3-5 will be defined by Intel ME Policies.

7. This signal is sampled as a functional strap during reset. Refer to Functional straps

definition table for usage.

8. SLP_LAN# behavior after reset is dependent on value of SLP_LAN# default value bit. A

soft-strap is used to select between SLP_LAN# and GPIO usage. When strap is set to 0

(default), pin is used as SLP_LAN#; when soft-strap is set to 1, pin is used as GPIO29.

9. Native functionality multiplexed with these GPIOs are not used in Desktop Configurations.

10. Native/GPIO functionality controlled using soft straps. Default to Native functionality until

soft straps are loaded.

11. State of the pins depend on the source of VccASW power.

12. Pin is tri-stated prior to APWROK assertion during Reset.

13. When Controller Reset Bit of Global Control Register (D27:F0 Offset HDBAR 08h bit 0) gets

set, this pin will start toggling.

14. Not all signals or pin functionalities may be available on a given SKU. See Section 1.3 and

Chapter 2 for details.

15. Controller Link Clock and Data buffers use internal pull-up and pull-down resistors to drive

a logical 1 or a 0.

Digital Display Interface

DDP[D:B]_[3:0]P,

DDP[D:B]_[3:0]N Core Low Low Defined Off Off

DDP[D:B]_AUXP,

DDP[D:B]_AUXN Core Low Low Defined Off Off

SDVO_CTRLCLK Core High-Z High-Z Defined Off Off

SDVO_CTRLDATA Core Low High-Z Defined Off Off

DDPC_CTRLCLK,

DDPD_CTRLCLK Core High-Z High-Z Defined Off Off

DDPC_CTRLDATA

DDPD_CTRLDATA Core Low High-Z Defined Off Off

Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations

(Sheet 6 of 6)

Signal Name Power

Plane

During

Reset1

Immediately

after Reset1S0/S1 S3 S4/S5

Datasheet 101

PCH Pin States

Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations

(Sheet 1 of 6)

Signal Name Power

Plane

During

Reset1

Immediately

after Reset1

C-x

states S0/S1 S3 S4/S5

PCI Express*

PET[8:1]p, PET[8:1]n Core Low Low4Defined Defined Off Off

DMI

DMI[3:0]TXP,

DMI[3:0]TXN Core Low Low Defined Defined Off Off

LPC/FWH Interface

LAD[3:0] / FWH[3:0] Core High High High High Off Off

LFRAME# / FWH[4] Core High High High High Off Off

INIT3_3V#7Core High High High High Off Off

SATA Interface

SATA[5:0]TXP,

SATA[5:0]TXN Core High-Z High-Z Defined Defined Off Off

SATALED# Core High-Z High-Z Defined Defined Off Off

SATAICOMPO Core High-Z High-Z Defined Defined Off Off

SCLOCK/GPIO22 Core High-Z

(Input) High-Z (Input) Defined Defined Off Off

SLOAD/GPIO38 Core High-Z

(Input) High-Z (Input) Defined Defined Off Off

SDATAOUT[1:0]/

GPIO[48,39] Core High-Z

(Input) High-Z (Input) Defined Defined Off Off

SATA3RBIAS Core Te rmina ted

to Vss

Ter min ated t o

Vss

Ter minat e

d to Vss

Termi nat e

d to Vss Off Off

SATA3ICOMPO Core High-Z High-Z High-Z High-Z Off Off

SATA3RCOMPO Core High-Z High-Z High-Z High-Z Off Off

Interrupts

PIRQ[A:D]# Core High-Z High-Z Defined Defined Off Off

PIRQ[H:E]# /

GPIO[5:2] Core High-Z

(Input) High-Z (Input) Defined Defined Off Off

SERIRQ Core High-Z High-Z Running High-Z Off Off

USB Interface

USB[13:0][P,N] Suspend Low Low Defined Defined Defined Defined

USBRBIAS Suspend High-Z High-Z Defined Defined Defined Defined

PCH Pin States

102 Datasheet

Power Management

CLKRUN#19 Core Low Low Defined Defined Off Off

PLTRST# Suspend Low High High High Low Low

SLP_A#5Suspend Low High High High Defined Defined

SLP_S3# Suspend Low High High High Low Low

SLP_S4# Suspend Low High High High High Defined

SLP_S5#/GPIO63 Suspend Low High High High High Defined2

SUS_STAT#/GPIO61 Suspend Low High High High Low Low

SUSCLK/GPIO62 Suspend Low Running

SUSWARN#/

SUSPWRDNACK/

GPIO30 (note 20)

Suspend 0 1 Defined Defined Defined Defined

SUSWARN#/

SUSPWRDNACK/

GPIO30 (note 21)

Suspend 0 1 1 1 1 1

DRAMPWROK Suspend Low High-Z High-Z High-Z High-Z Low

LAN_PHY_PWR_CTRL

9/GPIO12 Suspend Low Low Defined Defined Defined Defined

PMSYNCH Core Low Low Defined/

Low10 Defined Off Off

STP_PCI#/GPIO34 Core High-Z

(Input) High-Z (Input) Defined Defined Off Off

SLP_LAN#14/GPIO29

SLP_LAN# (using

soft-strap)

GPIO29 (using soft-

strap)

Suspend

Low

Low14

High-Z

High

High-Z

High

High-Z

Defined

High-Z

Defined

High-Z

Processor Interface

PROCPWRGD Processor Low High High High Off Off

SMBus Interface

SMBCLK, SMBDATA Suspend High-Z High-Z Defined Defined Defined Defined

Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations

(Sheet 2 of 6)

Signal Name Power

Plane

During

Reset1

Immediately

after Reset1

C-x

states S0/S1 S3 S4/S5

Datasheet 103

PCH Pin States

System Management Interface

SML0ALERT#/

GPIO60 Suspend High-Z High-Z Defined Defined Defined Defined

SML0DATA Suspend High-Z High-Z Defined Defined Defined Defined

SML0CLK Suspend High-Z High-Z Defined Defined Defined Defined

SML1CLK/GPIO58 Suspend High-Z High-Z Defined Defined Defined Defined

SML1ALERT#/

PCHHOT#/GPIO74 Suspend High-Z High-Z Defined Defined Defined Defined

SML1DATA/GPIO75 Suspend High-Z High-Z Defined Defined Defined Defined

Miscellaneous Signals

SPKR7Core Low Low Defined Defined Off Off

JTAG_TDO Suspend High-Z High-Z High-Z High-Z High-Z High-Z

Clocking Signals

CLKOUT_ITPXDP_P,

CLKOUT_ITPXDP_N Core Running Running Running Running Off Off

CLKOUT_DP_P,

CLKOUT_DP_N Core Running Running Running Running Off Off

CLKOUT_DMI_P,

CLKOUT_DMI_N Core Running Running Running Running Off Off

XTAL25_OUT Core High-Z High-Z High-Z High-Z Off Off

XCLK_RCOMP Core High-Z High-Z High-Z High-Z Off Off

CLKOUT_PEG_A_P,

CLKOUT_PEG_A_N Core Running Running Running Running Off Off

CLKOUT_PEG_B_P,

CLKOUT_PEG_B_N Core Running Running Running Running Off Off

CLKOUT_PCIE[7:0] P,

CLKOUT_PCIE[7:0] N Core Running Running Running Running Off Off

CLKOUT_PCI[4:0] Core Running Running Running Running Off Off

CLKOUTFLEX[3:0]/

GPIO[67:64] Core Low Running Running/

Low Running Off Off

Intel® High Definition Audio Interface

HDA_RST# Suspend Low Low3Defined Defined Low Low

HDA_SDO7Suspend Low Low Low Low Low Low

HDA_SYNC7Suspend Low Low Low Low Low Low

HDA_BCLK22 Suspend Low Low Low Low Low Low

HDA_DOCK_EN#/

GPIO33 Core High High11 High11 High11 Off Off

HDA_DOCK_RST#/

GPIO13 Suspend High-Z High-Z High-Z High-Z High-Z High-Z

Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations

(Sheet 3 of 6)

Signal Name Power

Plane

During

Reset1

Immediately

after Reset1

C-x

states S0/S1 S3 S4/S5

PCH Pin States

104 Datasheet

UnMultiplexed GPIO Signals

GPIO87Suspend High High Defined Defined Defined Defined

GPIO157Suspend Low Low Defined Defined Defined Defined

GPIO24 Suspend Low Low Defined Defined Defined Defined

GPIO277(Non-Deep

S4/S5 mode) DSW High-Z High-Z High-Z High-Z High-Z High-Z

GPIO277(Deep S4/S5

mode) DSW High-Z High-Z High-Z High-Z High-Z High-Z

GPIO28 Suspend High Low Low Low Low Low

GPIO57 Suspend Low High-Z (Input) Defined Defined Defined Defined

Multiplexed GPIO Signals used as GPIO only

GPIO0 Core High-Z

(Input) High-Z (Input) Defined Defined Off Off

GPIO[17,7,6,1]8Core High-Z High-Z High-Z High-Z Off Off

GPIO35 Core Low Low Defined Defined Off Off

GPIO50 Core High-Z High-Z High-Z High-Z Off Off

GPIO[55,53,51] Core High High High High Off Off

GPIO52 Core High-Z High-Z High-Z High-Z Off Off

GPIO54 Core High-Z High-Z High-Z High-Z Off Off

GPIO[71:68] Core High-Z High-Z High-Z High-Z Off Off

SPI Interface

SPI_CS0# ASW High18 High Defined Defined Defined Defined

SPI_CS1# ASW High18 High Defined Defined Defined Defined

SPI_MOSI ASW Low18 Low Defined Defined Defined Defined

SPI_CLK ASW Low18 Low Running Running Defined Defined

Controller Link

CL_CLK16Suspend High/Low13 High/Low13 Defined Defined Defined Defined

CL_DATA16Suspend High/Low13 High/Low13 Defined Defined Defined Defined

CL_RST1#6Suspend Low High Defined High High High

Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations

(Sheet 4 of 6)

Signal Name Power

Plane

During

Reset1

Immediately

after Reset1

C-x

states S0/S1 S3 S4/S5

Datasheet 105

PCH Pin States

LVDS Signals

LVDSA_DATA[3:0],

LVDSA_DATA#[3:0] Core High-Z High-Z Defined/

High-Z12

Defined/

High-Z12 Off Off

LVDSA_CLK,

LVDSA_CLK# Core High-Z High-Z Defined/

High-Z12

Defined/

High-Z12 Off Off

LVDSB_DATA[3:0],

LVDSB_DATA#[3:0] Core High-Z High-Z Defined/

High-Z12

Defined/

High-Z12 Off Off

LVDSB_CLK,

LVDSB_CLK# Core High-Z High-Z Defined/

High-Z12

Defined/

High-Z12 Off Off

L_DDC_CLK Core High-Z High-Z High-Z High-Z Off Off

L_DDC_DATA Core Low High-Z High-Z High-Z Off Off

L_VDD_EN Core Low Low Low/

High-Z12

Low/

High-Z12 Off Off

L_BKLTEN Core Low Low Low/

High-Z12

Low/

High-Z12 Off Off

L_BKLTCTL Core Low Low Low/

High-Z12

Low/

High-Z12 Off Off

L_CTRL_CLK Core High-Z High-Z High-Z High-Z Off Off

L_CTRL_DATA Core High-Z High-Z High-Z High-Z Off Off

LVD_VBG,

LVD_VREFH,

LVD_VREFL

Core High-Z High-Z High-Z High-Z Off Off

Analog Display / CRT DAC Signals

CRT_RED,

CRT_GREEN,

CRT_BLUE

Core High-Z High-Z Defined Defined Off Off

DAC_IREF Core High-Z Low Low Low Off Off

CRT_HSYNC Core Low Low Low Low Off Off

CRT_VSYNC Core Low Low Low Low Off Off

CRT_DDC_CLK Core High-Z High-Z High-Z High-Z Off Off

CRT_DDC_DATA Core High-Z High-Z High-Z High-Z Off Off

CRT_IRTN Core High-Z High-Z High-Z High-Z Off Off

Intel® Flexible Display Interface

FDI_FSYNC[1:0] Core High-Z High-Z Defined Defined Off Off

FDI_LSYNC[1:0] Core High-Z High-Z Defined Defined Off Off

FDI_INT Core High-Z High-Z Defined Defined Off Off

Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations

(Sheet 5 of 6)

Signal Name Power

Plane

During

Reset1

Immediately

after Reset1

C-x

states S0/S1 S3 S4/S5

PCH Pin States

106 Datasheet

NOTES:

1. The states of Core and processor signals are evaluated at the times During PLTRST# and

Immediately after PLTRST#. The states of the Controller Link signals are taken at the

times During CL_RST1# and Immediately after CL_RST1#. The states of the Suspend

signals are evaluated at the times During RSMRST# and Immediately after RSMRST#, with

an exception to GPIO signals; refer to Section 2.24 for more details on GPIO state after

reset. The states of the HDA signals are evaluated at the times During HDA_RST# and

Immediately after HDA_RST#.

2. SLP_S5# signal will be high in the S4 state and low in the S5 state.

3. Low until Intel® High Definition Audio Controller Reset bit set (D27:F0:Offset

HDBAR+08h:bit 0), at which time HDA_RST# will be High and HDA_BIT_CLK will be

Running.

4. PETp/n[8:1] low until port is enabled by software.

5. The SLP_A# state will be determined by Intel ME Policies.

6. The state of signals in S3-5 will be defined by Intel ME Policies.

7. This signal is sampled as a functional strap During Reset. Refer to Functional straps

definition table for usage.

8. Native functionality multiplexed with these GPIOs is not utilized in Mobile Configurations.

9. Native/GPIO functionality controlled using soft straps. Default to Native functionality until

soft straps are loaded.

10. This pin will be driven to a High when Dock Attach bit is set (Docking Control Register

D27:F0 Offset 4Ch)

11. This pin will be driven to a Low when Dock Attach bit is set (Docking Control Register

D27:F0 Offset 4Ch)

12. PCH tri-states these signals when LVDS port is disabled.

13. Controller Link Clock and Data buffers use internal pull-up and pull-down resistors to drive

a logical 1 or a 0.

14. SLP_LAN# behavior after reset is dependent on value of SLP_LAN# default value bit. A

soft-strap is used to select between SLP_LAN# and GPIO usage. When strap is set to 0

(default), pin is used as SLP_LAN#, when soft-strap is set to 1, pin is used as GPIO29.

15. State of the pins depend on the source of VccASW power.

16. Pin state reflected when SPI2 enable RTC power backed soft strap is enabled, for Mobile

configurations using a Finger-Print Sensor device. When soft strap is not enabled, signal

defaults to GP Input.

17. Based on Intel ME wake events and Intel ME state. SUSPWRDNACK is the default mode of

operation. If system supports Deep S4/S5, subsequent boots will default to SUSWARN#

18. Pins are tri-stated prior to APWROK assertion During Reset.

19. CLKRUN# is driven to a logic 1 During Reset for Mobile configurations (default is native

function) to ensure that PCI clocks can toggle before devices come out of Reset.

Digital Display Interface

DDP[D:B]_[3:0]P,

DDP[D:B]_[3:0]N, Core Low Low Defined Defined Off Off

DDP[D:B]_AUXP,

DDP[D:B]_AUXN Core Low Low Defined Defined Off Off

SDVO_CTRLCLK Core High-Z High-Z Defined Defined Off Off

SDVO_CTRLDATA Core Low High-Z Defined Defined Off Off

DDPC_CTRLCLK,

DDPD_CTRLCLK Core High-Z High-Z Defined Defined Off Off

DDPC_CTRLDATA,

DDPD_CTRLDATA Core Low High-Z Defined Defined Off Off

Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations

(Sheet 6 of 6)

Signal Name Power

Plane

During

Reset1

Immediately

after Reset1

C-x

states S0/S1 S3 S4/S5

Datasheet 107

PCH Pin States

20. Pin-state indicates SUSPWRDNACK in Non-Deep S4/S5, Deep S4/S5 after RTC power

failure.

21. Pin-state indicates SUSWARN# in Deep S4/S5 supported platforms.

22. When Controller Reset Bit of Global Control Register (D27:F0 Offset HDBAR 08h Bit 0) gets

set, this pin will start toggling.

23. Not all signals or pin functionalities may be available on a given SKU. See Section 1.3 and

Chapter 2 for details.

3.3 Power Planes for Input Signals

Ta b l e 3 - 4 and Ta ble 3 - 5 shows the power plane associated with each input signal, as

well as what device drives the signal at various times. Valid states include:

High

Low

Static: Will be high or low, but will not change

Driven: Will be high or low, and is allowed to change

Running: For input clocks

PCH suspend well signal states are indeterminate and undefined and may glitch prior to

RSMRST# deassertion. This does not apply to SLP_S3#, SLP_S4#, and SLP_S5#.

These signals are determinate and defined prior to RSMRST# deassertion.

PCH core well signal states are indeterminate and undefined and may glitch prior to

PWROK assertion. This does not apply to THRMTRIP#. This signal is determinate and

defined prior to PWROK assertion.

DSW indicates PCH Deep S4/S5 Well. This state provides a few wake events and critical

context to allow system to draw minimal power in S4 or S5 states.

ASW indicates PCH Active Sleep Well. This power well contains functionality associated

with active usage models while the host system is in Sx.

Table 3-4. Power Plane for Input Signals for Desktop Configurations (Sheet 1 of 3)

Signal Name Power Well Driver During Reset S0/S1 S3 S4/S5

DMI

DMI[3:0]RXP,

DMI[3:0]RXN Core Processor Driven Off Off

PCI Express*

PER[8:1]p, PERn[8:1]n Core PCI Express Device Driven Off Off

PCI Bus

REQ0#,

REQ1# / GPIO501

REQ2# / GPIO521

REQ3# / GPIO541

Core External Pull-up Driven Off Off

PME# Suspend Internal Pull-up Driven Driven Driven

SERR# Core PCI Bus Peripherals Driven Off Off

LPC Interface

LDRQ0# Core LPC Devices Driven Off Off

LDRQ1# / GPIO231Core LPC Devices Driven Off Off

PCH Pin States

108 Datasheet

SATA Interface

SATA[5:0]RXP,

SATA[5:0]RXN Core SATA Drive Driven Off Off

SATAICOMPI Core High-Z Driven Off Off

SATA4GP/GPIO161Core External Device or External

Pull-up/Pull-down Driven Off Off

SATA5GP/GPIO491/

TEMP_ALERT# Core External Device or External

Pull-up/Pull-down Driven Off Off

SATA0GP / GPIO[21]1Core External Device or External

Pull-up/Pull-down Driven Off Off

SATA1GP/GPIO19 Core Internal Pull-up Driven Off Off

SATA[3:2]GP/

GPIO[37:36] Core Internal Pull-down Driven Off Off

SATA3COMPI Core External Pull-up Driven Off Off

USB Interface

OC[7:0]#/

GPIO[14,10,9,43:40,59]1Suspend External Pull-ups Driven Driven Driven

USBRBIAS# Suspend External Pull-down Driven Driven Driven

Power Management

APWROK Suspend External Circuit High Driven Driven

PWRBTN# DSW Internal Pull-up Driven Driven Driven

PWROK RTC External Circuit Driven Driven Driven

DPWROK RTC External Circuit Driven Driven Driven

RI# Suspend Serial Port Buffer Driven Driven Driven

RSMRST# RTC External RC Circuit High High High

SYS_RESET# Core External Circuit Driven Off Off

SYS_PWROK Suspend External Circuit High Driven Driven

THRMTRIP# Core

(Processor) External Thermal Sensor Driven Off Off

WAKE# Suspend External Pull-up Driven Driven Driven

Processor Interface

A20GATE Core External Micro controller Static Off Off

RCIN# Core External Micro controller High Off Off

System Management Interface

SMBALERT# / GPIO11 Suspend External Pull-up Driven Driven Driven

INTRUDER# RTC External Switch Driven Driven Driven

JTAG Interface

JTAG_TDI3Suspend Internal Pull-up High High High

JTAG_TMS3Suspend Internal Pull-up High High High

JTAG_TCK3Suspend Internal pull-down Low Low Low

Table 3-4. Power Plane for Input Signals for Desktop Configurations (Sheet 2 of 3)

Signal Name Power Well Driver During Reset S0/S1 S3 S4/S5

Datasheet 109

PCH Pin States

NOTE:

1. These signals can be configured as outputs in GPIO mode.

2. This signal is sampled as a functional strap during Reset. Refer to Functional straps

definition table for usage.

3. External termination is also required for JTAG enabling.

4. Not all signals or pin functionalities may be available on a given SKU. See Section 1.3 and

Chapter 2 for details.

Miscellaneous Signals

INTVRMEN2RTC External Pull-up High High High

RTCRST# RTC External RC Circuit High High High

SRTCRST# RTC External RC Circuit High High High

Digital Display Interface

DDP[B:C:D]_HPD Core External Pull-down Driven Off Off

SDVO_INTP,

SDVO_INTN Core SDVO controller device Driven Off Off

SDVO_TVCLKINP,

SDVO_TVCLKINN Core SDVO controller device Driven Off Off

SDVO_STALLP,

SDVO_STALLN Core SDVO controller device Driven Off Off

Intel® Flexible Display Interface

FDI_RXP[7:0],

FDI_RXN[7:0] Core Processor Driven Off Off

Clock Interface

CLKIN_SATA_N,

CLKIN_SATA_P Core External pull-down Low Off Off

CLKIN_DOT_96P,

CLKIN_DOT_96N Core External pull-down Low Off Off

CLKIN_DMI_P,

CLKIN_DMI_N Core External pull-down Low Off Off

CLKIN_PCILOOPBACK Core Clock Generator Running Off Off

PCIECLKRQ[7:5]#/

GPIO[46:44]1Suspend External Pull-up Driven Driven Driven

PCIECLKRQ2#/GPIO201/

SMI# (SMI# is Server/

Workstation Only)

Core External Pull-up Driven Off Off

REFCLK14IN Core External Pull-down Low Off Off

XTAL25_IN Core Clock Generator High-Z High-Z High-Z

Intel® High Definition Audio Interface

SPI Interface

SPI_MISO ASW Internal Pull-up Driven Driven Driven

Thermal (Server/Workstation Only)

TACH[7:0]/

GPIO[71:68,7,6,1,17]1Core Internal Pull-up Driven Off Off

Table 3-4. Power Plane for Input Signals for Desktop Configurations (Sheet 3 of 3)

Signal Name Power Well Driver During Reset S0/S1 S3 S4/S5

PCH Pin States

110 Datasheet

Table 3-5. Power Plane for Input Signals for Mobile Configurations (Sheet 1 of 3)

Signal Name Power Well Driver During Reset C-x

states S0/S1 S3 S4/S5

DMI

DMI[3:0]RXP,

DMI[3:0]RXN Core Processor Driven Driven Off Off

PCI Express*

PER[8:1]p, PER[8:1]n Core PCI Express* Device Driven Driven Off Off

LPC Interface

LDRQ0# Core Internal Pull-up Driven High Off Off

LDRQ1# / GPIO231Core Internal Pull-up Driven High Off Off

SATA Interface

SATA[5:0]RXP,

SATA[5:0]RXN Core SATA Drive Driven Driven Off Off

SATAICOMPI Core High-Z High-Z Defined Off Off

SATA4GP/GPIO161Core External Device or

External Pull-up/Pull-down Driven Driven Off Off

SATA5GP/GPIO491/

TEMP_ALERT# Core External Device or

External Pull-up/Pull-down Driven Driven Off Off

SATA[0]GP /

GPIO[21]1Core External Device or

External Pull-up/Pull-down Driven Driven Off Off

SATA1GP/GPIO19 Core Internal Pull-up Driven Driven Off Off

SATA[3:2]GP/

GPIO[37:36] Core Internal Pull-down Driven Driven Off Off

SATA3COMPI Core External Pull-up Driven Driven Off Off

USB Interface

OC[7:0]#/

GPIO[14,10,9,43:40,

59]

Suspend External Pull-ups Driven Driven Driven Driven

USBRBIAS# Suspend External Pull-down Driven Driven Driven Driven

Power Management

ACPRESENT (Mobile

Only) /GPIO311(Non-

Deep S4/S5 mode)

DSW External Microcontroller Driven Driven Driven Driven

ACPRESENT (Mobile

Only) /GPIO311(Deep

S4/S5 mode)

DSW External Microcontroller Driven Driven Driven Driven

BATLOW# (Mobile

Only) /GPIO721Suspend External Pull-up High High Driven Driven

APWROK Suspend External Circuit Driven Driven Driven Driven

PWRBTN# DSW Internal Pull-up Driven Driven Driven Driven

PWROK RTC External Circuit Driven Driven Off Off

Datasheet 111

PCH Pin States

RI# Suspend Serial Port Buffer Driven Driven Driven Driven

RSMRST# RTC External RC Circuit High High High High

SYS_RESET# Core External Circuit Driven Driven Off Off

THRMTRIP# CORE

(Processor) Thermal Sensor Driven Driven Off Off

WAKE# Suspend External Pull-up Driven Driven Driven Driven

Processor Interface

A20GATE Core External Microcontroller Static Static Off Off

RCIN# Core External Microcontroller High High Off Off

System Management Interface

SMBALERT# / GPIO11 Suspend External Pull-up Driven Driven Driven Driven

INTRUDER# RTC External Switch Driven Driven High High

JTAG Interface

JTAG_TDI Suspend Internal Pull-up4High High High High

JTAG_TMS Suspend Internal Pull-up4High High High High

JTAG_TCK Suspend Internal Pull-down4 Low Low Low Low

Miscellaneous Signals

INTVRMEN2RTC External Pull-up or Pull-

down High High High High

RTCRST# RTC External RC Circuit High High High High

SRTCRST# RTC External RC Circuit High High High High

Intel® High Definition Audio Interface

HDA_SDIN[3:0] Suspend Intel® High Definition

Audio Codec Driven Low Low Low

SPI Interface

SPI_MISO ASW Internal Pull-up Driven Driven Driven Driven

Table 3-5. Power Plane for Input Signals for Mobile Configurations (Sheet 2 of 3)

Signal Name Power Well Driver During Reset C-x

states S0/S1 S3 S4/S5

PCH Pin States

112 Datasheet

NOTES:

1. These signals can be configured as outputs in GPIO mode.

2. This signal is sampled as a functional strap during Reset. Refer to Functional straps

definition table for usage.

3. External Termination is required for JTAG enabling.

4. Not all signals or pin functionalities may be available on a given SKU. See Section 1.3 and

Chapter 2 for details.

§ §

Clock Interface

CLKIN_DMI_P,

CLKIN_DMI_N Core External pull-down Low Low Off Off

CLKIN_SATA_N/

CLKIN_SATA_P/ Core External pull-down Low Low Off Off

CLKIN_DOT_96P,

CLKIN_DOT_96N Core External pull-down Low Low Off Off

CLKIN_PCILOOPBACK Core Clock Generator Running Running Off Off

PCIECLKRQ[7:3]#/

GPIO[46:44,26:25]1,

PCIECLKRQ0#/

GPIO731

Suspend External Pull-up Driven Driven Driven Driven

PCIECLKRQ[2:1]#/

GPIO[20:18]1Core External Pull-up Driven Driven Off Off

PEG_A_CLKRQ#/

GPIO471,

PEG_B_CLKRQ#/

GPIO561

Suspend External Pull-up Driven Driven Driven Driven

XTAL25_IN Core Clock Generator High-Z High-Z Off Off

REFCLK14IN Core External pull-down Low Low Off Off

CLKIN_PCILOOPBACK Core Clock Generator High-Z High-Z Off Off

Intel® Flexible Display Interface

FDI_RXP[7:0],

FDI_RXN[7:0] Core Processor Driven Driven Off Off

Digital Display Interface

DDP[B:C:D]_HPD Core External Pull-down Driven Driven Off Off

SDVO_INTP,

SDVO_INTN Core SDVO controller device Driven Driven Off Off

SDVO_TVCLKINP,

SDVO_TVCLKINN Core SDVO controller device Driven Driven Off Off

SDVO_STALLP,

SDVO_STALLN Core SDVO controller device Driven Driven Off Off

Table 3-5. Power Plane for Input Signals for Mobile Configurations (Sheet 3 of 3)

Signal Name Power Well Driver During Reset C-x

states S0/S1 S3 S4/S5

Datasheet 113

PCH and System Clocks

4 PCH and System Clocks

PCH provides a complete system clocking solution through Integrated Clocking.

PCH based platforms require several single-ended and differential clocks to synchronize

signal operation and data propagation system-wide between interfaces, and across

clock domains. In Integrated Clock mode, all the system clocks will be provided by PCH

from a 25 MHz crystal generated clock input.

The output signals from PCH are:

• One 100 MHz differential source for BCLK and DMI (PCI Express 2.0 jitter tolerant)

• One 120 MHz differential source for embedded DisplayPort (Mobile Only) on

Integrated Graphics processors.

• Ten 100 MHz differential sources for PCI Express 2.0

• One 100 MHz differential clock for XDP/ITP

• Five 33 MHz single-ended source for PCI/other devices (One of these is reserved as

loopback clock)

• Four flexible single-ended outputs that can be used for 14.31818/24/27/33/48 MHz

for legacy platform functions, discrete graphics devices, external USB controllers,

etc.

4.1 Platform Clocking Requirements

Providing a platform-level clocking solution uses multiple system components

including:

•The PCH

• 25 MHz Crystal source

Ta b l e 4 - 1 shows the system clock input to PCH. Tabl e 4 -2 shows system clock outputs

generated by PCH.

NOTES:

1. CLKIN_GND0_[P:N] (Desktop pins only) is NOT used and requires external termination on

Desktop platforms.

2. CLKIN_GND1_[P:N] is NOT used and requires external termination on Mobile and Desktop

platforms.

Table 4-1. PCH Clock Inputs

Clock Domain Frequency Usage description

CLKIN_DMI_P,

CLKIN_DMI_N 100 MHz Unused. External Termination required.

CLKIN_DOT96_P,

CLKIN_DOT96_N 96 MHz Unused. External Termination required.

CLKIN_SATA_P/

CLKIN_SATA_N 100 MHz Unused. External Termination required.

CLKIN_PCILOOPB

ACK 33 MHz

33 MHz clock feedback input to reduce skew between

PCH PCI clock and clock observed by connected PCI

devices. This signal must be connected to one of the

pins in the group CLKOUT_PCI[4:0]

REFCLK14IN 14.31818 MHz Unused. External Termination required.

XTAL25_IN 25 MHz Crystal input source used by PCH.

PCH and System Clocks

114 Datasheet

Figure 4-1 shows the high level block diagram of PCH clocking.

Table 4-2. Clock Outputs

Clock Domain Frequency Spread

Spectrum Usage

CLKOUT_PCI[4:0] 33 MHz Yes

Single Ended 33 MHz outputs to PCI connectors/

devices. One of these signals must be connected

to CLKIN_PCILOOPBACK to function as a PCI

clock loopback. This allows skew control for

variable lengths of CLKOUT_PCI[4:0].

NOTE: Not all SKUs may support PCI devices.

See Section 1.3 for details.

CLKOUT_DMI_P,

CLKOUT_DMI_N 100 MHz Yes 100 MHz PCIe* Gen2.0 differential output to the

processor for DMI/BCLK.

CLKOUT_PCIE[7:0]_P,

CLKOUT_PCIE[7:0]_N 100 MHz Yes 100 MHz PCIe Gen2.0 specification differential

output to PCI Express devices.

CLKOUT_PEG_A_P,

CLKOUT_PEG_A_N,

CLKOUT_PEG_B_P,

CLKOUT_PEG_B_N,

100 MHz Yes 100 MHz PCIe Gen2 specification differential

output to PCI Express Graphics devices.

CLKOUT_ITPXDP_P,

CLKOUT_ITPXDP_N 100 MHz Yes Used as 100 MHz Clock to processor XDP/ITP on

the platform.

CLKOUT_DP_P,

CLKOUT_DP_N 120 MHz Yes 120 MHz Differential output to processor for

embedded DisplayPort

CLKOUTFLEX0/ GPIO64

33 MHz /

14.31818 MHz /

27 MHz (SSC/

non-SSC) /48

MHz / 24MHz

33 MHz, 48/24 MHz or 14.31818 MHz outputs for

various platform devices such as PCI/LPC or

SIO/EC devices, 27 MHz (SSC/non-SSC) clock

for discrete graphics devices.

CLKOUTFLEX1/ GPIO65,

CLKOUTFLEX3/ GPIO67

14.31818 MHz /

27 MHz (SSC/

non-SSC) /

48 MHz / 24 MHz

48/24 MHz or 14.31818 MHz outputs for various

platform devices such as PCI/LPC or SIO/EC

devices, 27 MHz (SSC/non-SSC) clock for

discrete graphics devices.

CLKOUTFLEX2/ GPIO64

33 MHz / 25 MHz

/ 14.31818 MHz

/ 27MHz (SSC/

non-SSC) /

48 MHz / 24 MHz

33 MHz, 25MHz, 48/24 MHz or 14.31818 MHz

outputs for various platform devices such as PCI/

LPC or SIO/EC devices, 27 MHz (SSC/non-SSC)

clock for discrete graphics devices.

SPI_CLK 17.86 MHz/

31.25 MHz No Drive SPI devices connected to the PCH.

Generated by the PCH.

Datasheet 115

PCH and System Clocks

Figure 4-1. PCH High-Level Clock Diagram

PCH

Processor

Display

120M

USB

2.0/1.0

SATA

100 M Legacy

14 M

PCIe Graphics

PCI/LPC/33M Endpoint

PCIe * Endpoint

SIO, TPM, etc.

DMI/FDI

PCIe*

PCIe* 100 M Gen 2

Loopback

33 M

25 M

Xtal

DMI 100 M

DP 120 M

33 M

PCIe * 100 M Gen2

FLEX 14.318/33/27/48/24M

RTC

Xtal

RTC

32.768 M

SPI

(Var)

Int

OSC

Intel

XDP/ITP connector

100 M

DMI/

Intel FDI

PCIe

2.0

PLL

SSC

Block

PCH and System Clocks

116 Datasheet

4.2 Functional Blocks

The PCH has up to 8 PLLs, 4 Spread Modulators, and a numbers of dividers to provide

great flexibility in clock source selection, configuration, and better power management.

Table 4 - 3 describes the PLLs on the PCH and the clock domains that are driven from the

PLLs.

NOTES:

1. Indicates the source clock frequencies driven to other internal logic for delivering functionality needed.

Does not indicate external outputs

2. Powered in sub-S0 states by a Suspend well Ring oscillator.

Table 4 - 4 provides a basic description of the Spread modulators. The spread

modulators each operate on the XCK PLL’s 2.4 GHz outputs. Spread Spectrum tuning

and adjustment can be made on the fly without a platform reboot using specific

programming sequence to the clock registers.

Table 4-3. PCH PLLs

PLL Outputs1Description/Usage

XCK_PLL

Eight 2.4 GHz 45° phase

shifted. Outputs are routed to

each of the Spread Modulator

blocks before hitting the

various dividers and the other

PLLs to provide appropriate

clocks to all of the I/O

interface logic.

Main Reference PLL. Always enabled in Integrated Clocking

mode. Resides in core power well and is not powered in S3 and

below states.

DMI_PLL 2.5 GHz/625 MHz/250 MHz

DMI Gen2 clocks

Source clock is 100 MHz from XCK_PLL (post-dividers). It is the

primary PLL resource to generate the DMI port clocks.

Resides in core power well and is not powered in S3 and below

states.

FDI_PLL 2.7 GHz/270 MHz/450 MHz

FDI logic and link clocks

Source clock is 100 MHz from XCK_PLL (post-dividers).

Resides in the core power well and is not powered in S3 and

below states.

PCIEPXP_PLL

2.5 GHz/625 MHz/

500 MHz/250 MHz/125 MHz

clocks for PCI Express* 2.0

interface.

Source clock is from XCK_PLL. PCIEPXP_PLL drives clocks to

PCIe ports and Intel® ME engine2 (in S0 state). Can be

optionally used to supply DMI clocks.

Resides in the core power well and is not powered in S3 and

below states.

SATA_PLL

3.0 GHz/1.5 GHz/300 MHz/

150 MHz clocks for SATA logic

(serial clock, Tx/Rx clocks)

Source clock is 100 MHz from XCK_PLL (post-divider).

This PLL generates all the required SATA Gen2 and SATA Gen3

clocks.

Resides in core power well and is not powered in S3 and below

states.

USB_PLL

24-/48-/240-/480 MHz clocks

for legacy USB 2.0/USB 1.0

logic

Source clock is from XCK_PLL (post-divider).

Resides in core power well and is not powered in S3 and below

states.

DPLL_A/B Runs with a wide variety of

frequency and divider options.

Source clock is 120 MHz from XCK_PLL (post-divider).

Provides Reference clocks required for Integrated Graphics

Display.

Resides in core power well and is not powered in S3 and below

states.

Datasheet 117

PCH and System Clocks

4.3 Clock Configuration Access Overview

The PCH provides increased flexibility of host equivalent configurability of clocks, using

Intel ME FW.

In the Intel ME FW assisted configuration mode, Control settings for PLLs, Spread

Modulators and other clock configuration registers will be handled by the Intel ME

engine. The parameters to be loaded will reside in the Intel ME data region of the SPI

Flash device. BIOS would only have access to the register set through a set of Intel MEI

commands to the Intel ME.

4.4 Straps Related to Clock Configuration

There are no functional (pin) straps required for clock configuration.

The following soft-straps are implemented on PCH for Clock Configuration: Integrated

Clocking Profile Select: 3 Profile select bits allow up to 8 different clock profiles to be

specified in the SPI flash device. In addition, 3 RTC well backed host register bits are

also defined for Integrated Clocking Profile Selection through BIOS.

§ §

Table 4-4. SSC Blocks

Modulator Description

SSC1 Used for 120 MHz fixed frequency Spread Spectrum Clock. Supports up to

0.5% spread

SSC2 Used for 100 MHz Spread Spectrum Clock. Supports up to 0.5% spread.

SSC3 Used for 100 MHz fixed frequency SSC Clock. Supports up to 0.5% spread.

SSC4

Used for 120 MHz fixed-frequency super-spread clocks. Supports 0.5% spread

for the 100 MHz and up to 2.5% super-spread for the 120 MHz display clock for

Integrated Graphics.

PCH and System Clocks

118 Datasheet

Datasheet 119

Functional Description

5 Functional Description

This chapter describes the functions and interfaces of the PCH.

5.1 DMI-to-PCI Bridge (D30:F0)

The DMI-to-PCI bridge resides in PCI Device 30, Function 0 on Bus 0. This portion of

the PCH implements the buffering and control logic between PCI and Direct Media

Interface (DMI). The arbitration for the PCI bus is handled by this PCI device. The PCI

decoder in this device must decode the ranges for the DMI. All register contents are

lost when core well power is removed.

Direct Media Interface (DMI) is the chip-to-chip connection between the processor and

the PCH. This high-speed interface integrates advanced priority-based servicing

allowing for concurrent traffic and true isochronous transfer capabilities. Base

functionality is completely software transparent permitting current and legacy software

to operate normally.

To provide for true isochronous transfers and configurable Quality of Service (QoS)

transactions, the PCH supports two virtual channels on DMI—VC0 and VC1. These two

channels provide a fixed arbitration scheme where VC1 is always the highest priority.

VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be

specifically enabled and configured at both ends of the DMI link (that is, the PCH and

processor).

Configuration registers for DMI, virtual channel support, and DMI active state power

management (ASPM) are in the RCRB space in the Chipset Config Registers

(Chapter 10).

DMI is also capable of operating in an Enterprise Southbridge Interface (ESI)

compatible mode. ESI is a chip-to-chip connection for server/workstation chipsets. In

this ESI-compatible mode, the DMI signals require AC coupling. A hardware strap is

used to configure DMI in ESI-compatible mode see Section 2.27 for details.

5.1.1 PCI Bus Interface

The PCH PCI interface supports PCI Local Bus Specification, Revision 2.3, at 33 MHz.

The PCH integrates a PCI arbiter that supports up to four external PCI bus masters in

addition to the internal PCH requests.

Note: PCI Bus Interface is not available on any Mobile PCH SKUs. PCI Bus Interface is also not

available on certain Desktop PCH SKUs. See Section 5.1.9 for alternative methods for

supporting PCI devices.

Functional Description

120 Datasheet

5.1.2 PCI Bridge As an Initiator

The bridge initiates cycles on the PCI bus when granted by the PCI arbiter. The bridge

generates the following cycle types:

5.1.2.1 Memory Reads and Writes

The bridge bursts memory writes on PCI that are received as a single packet from DMI.

5.1.2.2 I/O Reads and Writes

The bridge generates single DW I/O read and write cycles. When the cycle completes

on the PCI bus, the bridge generates a corresponding completion on DMI. If the cycle is

retried, the cycle is kept in the down bound queue and may be passed by a postable

cycle.

5.1.2.3 Configuration Reads and Writes

The bridge generates single DW configuration read and write cycles. When the cycle

completes on the PCI bus, the bridge generates a corresponding completion on DMI. If

the cycle is retried, the cycle is kept in the down bound queue and may be passed by a

postable cycle.

5.1.2.4 Locked Cycles

The bridge propagates locks from DMI per the PCI Local Bus Specification. The PCI

bridge implements bus lock, which means the arbiter will not grant to any agent except

DMI while locked.

If a locked read results in a target or master abort, the lock is not established (as per

the PCI Local Bus Specification). Agents north of the PCH must not forward a

subsequent locked read to the bridge if they see the first one finish with a failed

completion.

5.1.2.5 Target / Master Aborts

When a cycle initiated by the bridge is master/target aborted, the bridge will not re-

attempt the same cycle. For multiple DW cycles, the bridge increments the address and

attempts the next DW of the transaction. For all non-postable cycles, a target abort

response packet is returned for each DW that was master or target aborted on PCI. The

bridge drops posted writes that abort.

5.1.2.6 Secondary Master Latency Timer

The bridge implements a Master Latency Timer using the SMLT register which, upon

expiration, causes the deassertion of FRAME# at the next legal clock edge when there

is another active request to use the PCI bus.

Table 5-1. PCI Bridge Initiator Cycle Types

Command C/BE# Notes

I/O Read/Write 2h/3h Non-posted

Memory Read/Write 6h/7h Writes are posted

Configuration Read/Write Ah/Bh Non-posted

Special Cycles 1h Posted

Datasheet 121

Functional Description

5.1.2.7 Dual Address Cycle (DAC)

The bridge will issue full 64-bit dual address cycles for device memory-mapped

registers above 4 GB.

5.1.2.8 Memory and I/O Decode to PCI

The PCI bridge in the PCH is a subtractive decode agent that follows the following

rules when forwarding a cycle from DMI to the PCI interface:

• The PCI bridge will positively decode any memory/IO address within its window

registers, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set for memory

windows and PCICMD.IOSE (D30:F0:Offset 04h:bit 0) is set for I/O windows.

• The PCI bridge will subtractively decode any 64-bit memory address not claimed

by another agent, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set.

• The PCI bridge will subtractively decode any 16-bit I/O address not claimed by

another agent assuming PCICMD.IOSE (D30:F0:Offset 04h:bit 0) is set.

• If BCTRL.IE (D30:F0:Offset 3Eh:bit 2) is set, the PCI bridge will not positively

forward from primary to secondary called out ranges in the I/O window per PCI

Local Bus Specification (I/O transactions addressing the last 768 bytes in each,

1 KB block: offsets 100h to 3FFh). The PCI bridge will still take them subtractively

assuming the above rules.

• If BCTRL.VGAE (D30:F0:Offset 3Eh:bit 3) is set, the PCI bridge will positively

forward from primary to secondary I/O and memory ranges as called out in the PCI

Bridge Specification, assuming the above rules are met.

5.1.3 Parity Error Detection and Generation

PCI parity errors can be detected and reported. The following behavioral rules apply:

• When a parity error is detected on PCI, the bridge sets the SECSTS.DPE

(D30:F0:Offset 1Eh:Bit 15).

• If the bridge is a master and BCTRL.PERE (D30:F0:Offset 3Eh:Bit 0) is set and one

of the parity errors defined below is detected on PCI, then the bridge will set

SECSTS.DPD (D30:F0:Offset 1Eh:Bit 8) and will also generate an internal SERR#.

— During a write cycle, the PERR# signal is active, or

— A data parity error is detected while performing a read cycle

• If an address or command parity error is detected on PCI and PCICMD.SEE

(D30:F0:Offset 04h:Bit 8), BCTRL.PERE, and BCTRL.SEE (D30:F0:Offset 3Eh:bit 1)

are all set, the bridge will set PSTS.SSE (D30:F0:Offset 06h:Bit 14) and generate

an internal SERR#.

• If the PSTS.SSE is set because of an address parity error and the PCICMD.SEE is

set, the bridge will generate an internal SERR#.

• When bad parity is detected from DMI, bad parity will be driven on all data from the

bridge.

• When an address parity error is detected on PCI, the PCI bridge will never claim the

cycle. This is a slight deviation from the PCI bridge specification that says that a

cycle should be claimed if BCTRL.PERE is not set. However, DMI does not have a

concept of address parity error, so claiming the cycle could result in the rest of the

system seeing a bad transaction as a good transaction.

Functional Description

122 Datasheet

5.1.4 PCIRST#

The PCIRST# pin is generated under two conditions:

•PLTRST# active

• BCTRL.SBR (D30:F0:Offset 3Eh:Bit 6) set to 1

The PCIRST# pin is in the suspend well. PCIRST# should be tied to PCI bus agents, but

not other agents in the system.

5.1.5 Peer Cycles

The PCI bridge may be the initiator of peer cycles. Peer cycles include memory, I/O,

and configuration cycle types. Peer cycles are only allowed through VC0, and are

enabled with the following bits:

• BPC.PDE (D30:F0:Offset 4Ch:Bit 2) – Memory and I/O cycles

• BPC.CDE (D30:F0:Offset 4Ch:Bit 1) – Configuration cycles

When enabled for peer for one of the above cycle types, the PCI bridge will perform a

peer decode to see if a peer agent can receive the cycle. When not enabled, memory

cycles (posted and/or non-posted) are sent to DMI, and I/O and/or configuration cycles

are not claimed.

Configuration cycles have special considerations. Under the PCI Local Bus Specification,

these cycles are not allowed to be forwarded upstream through a bridge. However, to

enable things such as manageability, BPC.CDE can be set. When set, type 1 cycles are

allowed into the part. The address format of the type 1 cycle is slightly different from a

standard PCI configuration cycle to allow addressing of extended PCI space. The format

is shown in Table 5 - 2.

Note: The PCH USB controllers cannot perform peer-to-peer traffic.

5.1.6 PCI-to-PCI Bridge Model

From a software perspective, the PCH contains a PCI-to-PCI bridge. This bridge

connects DMI to the PCI bus. By using the PCI-to-PCI bridge software model, the PCH

can have its decode ranges programmed by existing plug-and-play software such that

PCI ranges do not conflict with graphics aperture ranges in the Host controller.

Table 5-2. Type 1 Address Format

Bits Definition

31:27 Reserved (same as the PCI Local Bus Specification)

26:24 Extended Configuration Address – allows addressing of up to 4 KB. These bits are

combined with Bits 7:2 to get the full register.

23:16 Bus Number (same as the PCI Local Bus Specification)

15:11 Device Number (same as the PCI Local Bus Specification)

10:8 Function Number (same as the PCI Local Bus Specification)

7:2 Register (same as the PCI Local Bus Specification)

0 Must be 1 to indicate a type 1 cycle. Type 0 cycles are not decoded.

Datasheet 123

Functional Description

5.1.7 IDSEL to Device Number Mapping

When addressing devices on the external PCI bus (with the PCI slots), the PCH asserts

one address signal as an IDSEL. When accessing Device 0, the PCH asserts AD16.

When accessing Device 1, the PCH asserts AD17. This mapping continues all the way

up to Device 15 where the PCH asserts AD31. Note that the PCH internal functions

(Intel® High Definition Audio, USB, SATA and PCI Bridge) are enumerated like they are

off of a separate PCI bus (DMI) from the external PCI bus.

5.1.8 Standard PCI Bus Configuration Mechanism

The PCI Bus defines a slot based “configuration space” that allows each device to

contain up to eight functions with each function containing up to 256, 8-bit

configuration registers. The PCI Local Bus Specification, Revision 2.3 defines two bus

cycles to access the PCI configuration space: Configuration Read and Configuration

Write. Memory and I/O spaces are supported directly by the processor. Configuration

space is supported by a mapping mechanism implemented within the PCH. The PCI

Local Bus Specification, Revision 2.3 defines two mechanisms to access configuration

space, Mechanism 1 and Mechanism 2. The PCH only supports Mechanism 1.

Warning: Configuration writes to internal devices, when the devices are disabled, are illegal and

may cause undefined results.

5.1.9 PCI Legacy Mode

For some PCH SKUs, native PCI functionality is not supported requiring methods such

as using PCIe*-to-PCI bridges to enable external PCI I/O devices. To be able to use

PCIe-to-PCI bridges and attached legacy PCI devices, the PCH provides PCI Legacy

Mode. PCI Legacy Mode allows both the PCI Express* root port and PCIe-to-PCI bridge

look like subtractive PCI-to-PCI bridges. This allows the PCI Express root port to

subtractively decode and forward legacy cycles to the bridge, and the PCIe-to-PCI

bridge continues forwarding legacy cycles to downstream PCI devices. For designs that

would like to utilize PCI Legacy Mode, BIOS must program registers in the DMI-to-PCI

bridge (Device 30:Function 0) and in the desired PCI Express Root Port (Device

28:Functions 0-7) to enable subtractive decode.

Note: Software must ensure that only one PCH device is enabled for Subtractive decode at a

time.

Functional Description

124 Datasheet

5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5,

F6, F7)

There are eight root ports available in the PCH. The root ports are compliant to the PCI

Express 2.0 specification running at 5.0 GT/s. The ports all reside in Device 28, and

take Function 0 – 7. Port 1 is Function 0, Port 2 is Function 1, Port 3 is Function 2,

Port 4 is Function 3, Port 5 is Function 4, Port 6 is Function 5, Port 7 is Function 6, and

Port 8 is Function 7.

Note: This section assumes the default PCI Express Function Number-to-Root Port mapping is

used. Function numbers for a given root port are assignable through the Root Port

Function Number and Hide for PCI Express Root Ports register (RCBA+0404h).

PCI Express Root Ports 1–4 or Ports 5–8 can independently be configured as four x1s,

two x2s, one x2 and two x1s, or one x4 port widths. The port configuration is set by

soft straps in the Flash Descriptor.

5.2.1 Interrupt Generation

The root port generates interrupts on behalf of Hot-Plug and power management

events, when enabled. These interrupts can either be pin based, or can be MSIs, when

enabled.

When an interrupt is generated using the legacy pin, the pin is internally routed to the

PCH interrupt controllers. The pin that is driven is based upon the setting of the chipset

configuration registers. Specifically, the chipset configuration registers used are the

D28IP (Base address + 310Ch) and D28IR (Base address + 3146h) registers.

Table 5 - 3 summarizes interrupt behavior for MSI and wire-modes. In the table “bits”

refers to the Hot-Plug and PME interrupt bits.

Table 5-3. MSI versus PCI IRQ Actions

Interrupt Register Wire-Mode Action MSI Action

All bits 0 Wire inactive No action

One or more bits set to 1 Wire active Send message

One or more bits set to 1, new bit gets set to 1 Wire active Send message

One or more bits set to 1, software clears some (but not

all) bits Wire active Send message

One or more bits set to 1, software clears all bits Wire inactive No action

Software clears one or more bits, and one or more bits

are set on the same clock Wire active Send message

Datasheet 125

Functional Description

5.2.2 Power Management

5.2.2.1 S3/S4/S5 Support

Software initiates the transition to S3/S4/S5 by performing an I/O write to the Power

Management Control register in the PCH. After the I/O write completion has been

returned to the processor, each root port will send a PME_Turn_Off TLP (Transaction

Layer Packet) message on its downstream link. The device attached to the link will

eventually respond with a PME_TO_Ack TLP message followed by sending a

PM_Enter_L23 DLLP (Data Link Layer Packet) request to enter the L2/L3 Ready state.

When all of the PCH root ports links are in the L2/L3 Ready state, the PCH power

management control logic will proceed with the entry into S3/S4/S5.

Prior to entering S3, software is required to put each device into D3HOT

. When a device

is put into D3HOT

, it will initiate entry into a L1 link state by sending a PM_Enter_L1

DLLP. Thus, under normal operating conditions when the root ports sends the

PME_Turn_Off message, the link will be in state L1. However, when the root port is

instructed to send the PME_Turn_Off message, it will send it whether or not the link

was in L1. Endpoints attached to PCH can make no assumptions about the state of the

link prior to receiving a PME_Turn_Off message.

5.2.2.2 Resuming from Suspended State

The root port contains enough circuitry in the suspend well to detect a wake event

through the WAKE# signal and to wake the system. When WAKE# is detected asserted,

an internal signal is sent to the power management controller of the PCH to cause the

system to wake up. This internal message is not logged in any register, nor is an

interrupt/GPE generated due to it.

5.2.2.3 Device Initiated PM_PME Message

When the system has returned to a working state from a previous low power state, a

device requesting service will send a PM_PME message continuously, until

acknowledged by the root port. The root port will take different actions depending upon

whether this is the first PM_PME that has been received, or whether a previous

message has been received but not yet serviced by the operating system.

If this is the first message received (RSTS.PS - D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset

60h:bit 16 is cleared), the root port will set RSTS.PS, and log the PME Requester ID

into RSTS.RID (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 60h:bits 15:0). If an interrupt is

enabled using RCTL.PIE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 5Ch:bit 3), an interrupt

will be generated. This interrupt can be either a pin or an MSI if MSI is enabled using

MC.MSIE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 82h:Bit 0). See Section 5.2.2.4 for

SMI/SCI generation.

If this is a subsequent message received (RSTS.PS is already set), the root port will set

RSTS.PP (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 60h:Bit 17) and log the PME Requester

ID from the message in a hidden register. No other action will be taken.

When the first PME event is cleared by software clearing RSTS.PS, the root port will set

RSTS.PS, clear RSTS.PP, and move the requester ID from the hidden register into

RSTS.RID.

If RCTL.PIE is set, an interrupt will be generated. If RCTL.PIE is not set, a message will

be sent to the power management controller so that a GPE can be set. If messages

have been logged (RSTS.PS is set), and RCTL.PIE is later written from a 0 to a 1, an

interrupt will be generated. This last condition handles the case where the message

was received prior to the operating system re-enabling interrupts after resuming from

a low power state.

Functional Description

126 Datasheet

5.2.2.4 SMI/SCI Generation

Interrupts for power management events are not supported on legacy operating

systems. To support power management on non-PCI Express aware operating systems,

PM events can be routed to generate SCI. To generate SCI, MPC.PMCE must be set.

When set, a power management event will cause SMSCS.PMCS (D28:F0/F1/F2/F3/F4/

F5/F6/F7:Offset DCh:Bit 31) to be set.

Additionally, BIOS workarounds for power management can be supported by setting

MPC.PMME (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset D8h:Bit 0). When this bit is set,

power management events will set SMSCS.PMMS (D28:F0/F1/F2/F3/F4/F5/F6/

F7:Offset DCh:Bit 0), and SMI # will be generated. This bit will be set regardless of

whether interrupts or SCI is enabled. The SMI# may occur concurrently with an

interrupt or SCI.

5.2.3 SERR# Generation

SERR# may be generated using two paths – through PCI mechanisms involving bits in

the PCI header, or through PCI Express* mechanisms involving bits in the PCI Express

capability structure.

5.2.4 Hot-Plug

Each root port implements a Hot-Plug controller that performs the following:

• Messages to turn on/off/blink LEDs

• Presence and attention button detection

• Interrupt generation

The root port only allows Hot-Plug with modules (such as, ExpressCard*). Edge-

connector based Hot-Plug is not supported.

5.2.4.1 Presence Detection

When a module is plugged in and power is supplied, the physical layer will detect the

presence of the device, and the root port sets SLSTS.PDS (D28:F0/F1/F2/F3/F4/

F5:Offset 5Ah:Bit 6) and SLSTS.PDC (D28:F0/F1/F2/F3:Offset 6h:Bit 3). If SLCTL.PDE

(D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:Bit 3) and SLCTL.HPE (D28:F0/F1/F2/F3/

F4/F5/F6/F7:Offset 58h:Bit 5) are both set, the root port will also generate an

interrupt.

Figure 5-1. Generation of SERR# to Platform

PSTS.SSE

SERR#

PCICMD.SEE

Secondary Parity Error

Primary Parity Error

Secondary SERR#

Correctable SERR#

Fatal SERR#

Non-Fatal SERR#

PCI

PCI Express

Datasheet 127

Functional Description

When a module is removed (using the physical layer detection), the root port clears

SLSTS.PDS and sets SLSTS.PDC. If SLCTL.PDE and SLCTL.HPE are both set, the root

port will also generate an interrupt.

5.2.4.2 Message Generation

When system software writes to SLCTL.AIC (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset

58h:Bits 7:6) or SLCTL.PIC (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:Bits 9:8), the

root port will send a message down the link to change the state of LEDs on the module.

Writes to these fields are non-postable cycles, and the resulting message is a postable

cycle. When receiving one of these writes, the root port performs the following:

• Changes the state in the register.

• Generates a completion into the upstream queue

• Formulates a message for the downstream port if the field is written to regardless

of if the field changed.

• Generates the message on the downstream port

• When the last message of a command is transmitted, sets SLSTS.CCE (D28:F0/F1/

F2/F3/F4/F5/F6/F7:Offset 58h:Bit 4) to indicate the command has completed. If

SLCTL.CCE and SLCTL.HPE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:Bit 5) are

set, the root port generates an interrupt.

The command completed register (SLSTS.CC) applies only to commands issued by

software to control the Attention Indicator (SLCTL.AIC), Power Indicator (SLCTL.PIC),

or Power Controller (SLCTL.PCC). However, writes to other parts of the Slot Control

Hence, any write to the Slot Control Register is considered a command and if enabled,

will result in a command complete interrupt. The only exception to this rule is a write to

disable the command complete interrupt which will not result in a command complete

interrupt.

A single write to the Slot Control register is considered to be a single command, and

hence receives a single command complete, even if the write affects more than one

field in the Slot Control Register.

5.2.4.3 Attention Button Detection

When an attached device is ejected, an attention button could be pressed by the user.

This attention button press will result in a the PCI Express message

“Attention_Button_Pressed” from the device. Upon receiving this message, the root

port will set SLSTS.ABP (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 5Ah:Bit 0).

If SLCTL.ABE (D28:F0/F1/F2/F3/F4/F5:Offset 58h:bit 0) and SLCTL.HPE (D28:F0/F1/

F2/F3/F4/F5/F6/F7:Offset 58h:Bit 5) are set, the Hot-Plug controller will also generate

an interrupt. The interrupt is generated on an edge-event. For example, if SLSTS.ABP is

already set, a new interrupt will not be generated.

5.2.4.4 SMI/SCI Generation

Interrupts for Hot-Plug events are not supported on legacy operating systems. To

support Hot-Plug on n on-PCI Express aware operating systems, Hot-Plug events can

be routed to generate SCI. To generate SCI, MPC.HPCE (D28:F0/F1/F2/F3/F4/F5/F6/

F7:Offset D8h:Bit 30) must be set. When set, enabled Hot-Plug events will cause

SMSCS.HPCS (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset DCh:Bit 30) to be set.

Functional Description

128 Datasheet

Additionally, BIOS workarounds for Hot-Plug can be supported by setting MPC.HPME

(D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset D8h:Bit 1). When this bit is set, Hot-Plug events

can cause SMI status bits in SMSCS to be set. Supported Hot-Plug events and their

corresponding SMSCS bit are:

• Command Completed – SCSCS.HPCCM (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset

DCh:Bit 3)

• Presence Detect Changed – SMSCS.HPPDM (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset

DCh:Bit 1)

• Attention Button Pressed – SMSCS.HPABM (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset

DCh:Bit 2)

• Link Active State Changed – SMSCS.HPLAS (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset

DCh:Bit 4)

When any of these bits are set, SMI# will be generated. These bits are set regardless of

whether interrupts or SCI is enabled for Hot-Plug events. The SMI# may occur

concurrently with an interrupt or SCI.

5.3 Gigabit Ethernet Controller (B0:D25:F0)

The PCH integrates a Gigabit Ethernet (GbE) controller. The integrated GbE controller is

compatible with the Intel® 82579 Platform LAN Connect device. The integrated GbE

controller provides two interfaces for 10/100/1000 Mb/s and manageability operation:

• Based on PCI Express – A high-speed SerDes interface using PCI Express electrical

signaling at half speed while keeping the custom logical protocol for active state

operation mode.

• System Management Bus (SMBus) – A very low speed connection for low power

state mode for manageability communication only. At this low power state mode

the Ethernet link speed is reduced to 10 Mb/s.

The 82579 can be connected to any available PCI Express port in the PCH. The 82579

only runs at a speed of 1250 Mb/s, which is 1/2 of the 2.5 Gb/s PCI Express frequency.

Each of the PCI Express root ports in the PCH have the ability to run at the 1250 Mb/s

rate. There is no need to implement a mechanism to detect that the 82579 LAN device

is connected. The port configuration (if any), attached to the 82579 LAN device, is pre-

loaded from the NVM. The selected port adjusts the transmitter to run at the

1250 Mb/s rate and does not need to be PCI Express compliant.

Note: PCIe validation tools cannot be used for electrical validation of this interface; however,

PCIe layout rules apply for on-board routing.

The integrated GbE controller operates at full-duplex at all supported speeds or half-

duplex at 10/100 Mb/s. It also adheres to the IEEE 802.3x Flow Control Specification.

Note: GbE operation (1000 Mb/s) is only supported in S0 mode. In Sx modes, SMBus is the

only active bus and is used to support manageability/remote wake-up functionality.

The integrated GbE controller provides a system interface using a PCI Express function.

A full memory-mapped or I/O-mapped interface is provided to the software, along with

DMA mechanisms for high performance data transfer.

Datasheet 129

Functional Description

The integrated GbE controller features are:

•Network Features

— Compliant with the 1 Gb/s Ethernet 802.3 802.3u 802.3ab specifications

— Multi-speed operation: 10/100/1000 Mb/s

— Full-duplex operation at 10/100/1000 Mb/s: Half-duplex at 10/100 Mb/s

— Flow control support compliant with the 802.3X specification

— VLAN support compliant with the 802.3q specification

— MAC address filters: perfect match unicast filters; multicast hash filtering,

broadcast filter and promiscuous mode

— PCI Express/SMBus interface to GbE PHYs

• Host Interface Features

— 64-bit address master support for systems using more than 4 GB of physical

memory

— Programmable host memory receive buffers (256 Bytes to 16 KB)

— Intelligent interrupt generation features to enhance driver performance

— Descriptor ring management hardware for transmit and receive

— Software controlled reset (resets everything except the configuration space)

— Message Signaled Interrupts

• Performance Features

— Configurable receive and transmit data FIFO, programmable in 1 KB increments

— TCP segmentation capability compatible with Windows NT* 5.x off loading

features

— Fragmented UDP checksum offload for packet reassembly

— IPv4 and IPv6 checksum offload support (receive, transmit, and TCP

segmentation offload)

— Split header support to eliminate payload copy from user space to host space

— Receive Side Scaling (RSS) with two hardware receive queues

— Supports 9018 bytes of jumbo packets

—Packet buffer size

— LinkSec offload compliant with 802.3ae specification

— TimeSync offload compliant with 802.1as specification

• Virtualization Technology Features

— Warm function reset – function level reset (FLR)

—VMDq1

• Power Management Features

— Magic Packet* wake-up enable with unique MAC address

— ACPI register set and power down functionality supporting D0 and D3 states

— Full wake up support (APM, ACPI)

— MAC power down at Sx, DMoff with and without WoL

Functional Description

130 Datasheet

5.3.1 GbE PCI Express* Bus Interface

The GbE controller has a PCI Express interface to the host processor and host memory.

The following sections detail the bus transactions.

5.3.1.1 Transaction Layer

The upper layer of the host architecture is the transaction layer. The transaction layer

connects to the device core using an implementation specific protocol. Through this

core-to-transaction-layer protocol, the application-specific parts of the device interact

with the subsystem and transmit and receive requests to or from the remote agent,

respectively.

5.3.1.2 Data Alignment

5.3.1.2.1 4-KB Boundary

PCI requests must never specify an address/length combination that causes a memory

space access to cross a 4 KB boundary. It is hardware’s responsibility to break requests

into 4 KB-aligned requests (if needed). This does not pose any requirement on

software. However, if software allocates a buffer across a 4-KB boundary, hardware

issues multiple requests for the buffer. Software should consider aligning buffers to a

4-KB boundary in cases where it improves performance.

The alignment to the 4-KB boundaries is done in the core. The transaction layer does

not do any alignment according to these boundaries.

5.3.1.2.2 64 Bytes

PCI requests are multiples of 64 bytes and aligned to make better use of memory

controller resources. Writes, however, can be on any boundary and can cross a 64-byte

alignment boundary.

5.3.1.3 Configuration Request Retry Status

The integrated GbE controller might have a delay in initialization due to an NVM read. If

the NVM configuration read operation is not completed and the device receives a

configuration request, the device responds with a configuration request retry

completion status to terminate the request, and thus effectively stalls the configuration

request until such time that the sub-system has completed local initialization and is

ready to communicate with the host.

Datasheet 131

Functional Description

5.3.2 Error Events and Error Reporting

5.3.2.1 Data Parity Error

The PCI host bus does not provide parity protection, but it does forward parity errors

from bridges. The integrated GbE controller recognizes parity errors through the

internal bus interface and sets the Parity Error bit in PCI configuration space. If parity

errors are enabled in configuration space, a system error is indicated on the PCI host

bus. The offending cycle with a parity error is dropped and not processed by the

integrated GbE controller.

5.3.2.2 Completion with Unsuccessful Completion Status

A completion with unsuccessful completion status (any status other than 000) is

dropped and not processed by the integrated GbE controller. Furthermore, the request

that corresponds to the unsuccessful completion is not retried. When this unsuccessful

completion status is received, the System Error bit in the PCI configuration space is set.

If the system errors are enabled in configuration space, a system error is indicated on

the PCI host bus.

5.3.3 Ethernet Interface

The integrated GbE controller provides a complete CSMA/CD function supporting IEEE

802.3 (10 Mb/s), 802.3u (100 Mb/s) implementations. It also supports the IEEE 802.3z

and 802.3ab (1000 Mb/s) implementations. The device performs all of the functions

required for transmission, reception, and collision handling called out in the standards.

The mode used to communicate between the PCH and the 82579 PHY supports 10/100/

1000 Mb/s operation, with both half- and full-duplex operation at 10/100 Mb/s, and

full-duplex operation at 1000 Mb/s.

5.3.3.1 82579 LAN PHY Interface

The integrated GbE controller and the 82579 PHY communicate through the PCIe and

SMBus interfaces. All integrated GbE controller configuration is performed using device

control registers mapped into system memory or I/O space. The 82579 device is

configured using the PCI Express or SMBus interface.

The integrated GbE controller supports various modes as listed in Ta b l e 5 - 4 .

Table 5-4. LAN Mode Support

Mode System State Interface Active Connections

Normal 10/100/1000 Mb/s S0 PCI Express or

SMBus1

NOTES:

1. GbE operation is not supported in Sx states.

82579

Manageability and Remote Wake-up Sx SMBus 82579

Functional Description

132 Datasheet

5.3.4 PCI Power Management

The integrated GbE controller supports the Advanced Configuration and Power Interface

(ACPI) specification as well as Advanced Power Management (APM). This enables the

network-related activity (using an internal host wake signal) to wake up the host. For

example, from Sx (S3–S5) to S0.

The integrated GbE controller contains power management registers for PCI and

supports D0 and D3 states. PCIe transactions are only allowed in the D0 state, except

for host accesses to the integrated GbE controller’s PCI configuration registers.

5.3.4.1 Wake Up

The integrated GbE controller supports two types of wake-up mechanisms:

1. Advanced Power Management (APM) Wake Up

2. ACPI Power Management Wake Up

Both mechanisms use an internal logic signal to wake the system up. The wake-up

steps are as follows:

1. Host wake event occurs (note that packet is not delivered to host).

2. The 82579 receives a WoL packet/link status change.

3. The 82579 wakes up the integrated GbE controller using an SMBus message.

4. The integrated GbE controller sets the PME_STATUS bit.

5. System wakes from Sx state to S0 state.

6. The host LAN function is transitioned to D0.

7. The host clears the PME_STATUS bit.

5.3.4.1.1 Advanced Power Management Wake Up

Advanced Power Management Wake Up or APM Wake Up was previously known as

Wake on LAN (WoL). It is a feature that has existed in the 10/100 Mb/s NICs for several

generations. The basic premise is to receive a broadcast or unicast packet with an

explicit data pattern and then to assert a signal to wake up the system. In earlier

generations, this was accomplished by using a special signal that ran across a cable to

a defined connector on the motherboard. The NIC would assert the signal for

approximately 50 ms to signal a wake up. The integrated GbE controller uses (if

configured to) an in-band PM_PME message for this.

At power up, the integrated GbE controller reads the APM Enable bits from the NVM PCI

Init Control Word into the APM Enable (APME) bits of the Wake Up Control (WUC)

When APM wake up is enabled, the integrated GbE controller checks all incoming

packets for Magic Packets.

Once the integrated GbE controller receives a matching Magic Packet, it:

• Sets the Magic Packet Received bit in the Wake Up Status (WUS) register.

• Sets the PME_Status bit in the Power Management Control/Status Register

(PMCSR).

APM wake up is supported in all power states and only disabled if a subsequent NVM

read results in the APM Wake Up bit being cleared or the software explicitly writes a 0b

to the APM Wake Up (APM) bit of the WUC register.

Datasheet 133

Functional Description

Note: APM wake up settings will be restored to NVM default by the PCH when LAN connected

Device (PHY) power is turned off and subsequently restored. Some example host WOL

flows are:

• When system transitions to G3 after WOL is disabled from the BIOS, APM host WOL

would get enabled.

• Anytime power to the LAN Connected Device (PHY) is cycled while in S4/S5 after

WOL is disabled from the BIOS, APM host WOL would get enabled. Anytime power

to the LAN Connected Device (PHY) is cycled while in S3, APM host WOL

configuration is lost.

5.3.4.1.2 ACPI Power Management Wake Up

The integrated GbE controller supports ACPI Power Management based Wake ups. It

can generate system wake-up events from three sources:

• Receiving a Magic Packet.

• Receiving a Network Wake Up Packet.

• Detecting a link change of state.

Activating ACPI Power Management Wakeup requires the following steps:

• The software device driver programs the Wake Up Filter Control (WUFC) register to

indicate the packets it needs to wake up from and supplies the necessary data to

the IPv4 Address Table (IP4AT) and the Flexible Filter Mask Table (FFMT), Flexible

Filter Length Table (FFLT), and the Flexible Filter Value Table (FFVT). It can also set

the Link Status Change Wake Up Enable (LNKC) bit in the Wake Up Filter Control

(WUFC) register to cause wake up when the link changes state.

• The operating system (at configuration time) writes a 1b to the PME_EN bit of the

Power Management Control/Status Register (PMCSR.8).

Normally, after enabling wake up, the operating system writes a 11b to the lower two

bits of the PMCSR to put the integrated GbE controller into low-power mode.

Once wake up is enabled, the integrated GbE controller monitors incoming packets,

first filtering them according to its standard address filtering method, then filtering

them with all of the enabled wake-up filters. If a packet passes both the standard

address filtering and at least one of the enabled wake-up filters, the integrated GbE

controller:

• Sets the PME_Status bit in the PMCSR

• Sets one or more of the Received bits in the Wake Up Status (WUS) register. (More

than one bit is set if a packet matches more than one filter.)

If enabled, a link state change wake up causes similar results, setting the Link Status

Changed (LNKC) bit in the Wake Up Status (WUS) register when the link goes up or

down.

After receiving a wake-up packet, the integrated GbE controller ignores any subsequent

wake-up packets until the software device driver clears all of the Received bits in the

Wake Up Status (WUS) register. It also ignores link change events until the software

device driver clears the Link Status Changed (LNKC) bit in the Wake Up Status (WUS)

Note: ACPI wake up settings are not preserved when the LAN Connected Device (PHY) power

is turned off and subsequently restored. Some example host WOL flows are:

• Anytime power to the LAN Connected Device (PHY) is cycled while in S3 or S4,

ACPI host WOL configuration is lost.

Functional Description

134 Datasheet

5.3.5 Configurable LEDs

The integrated GbE controller supports three controllable and configurable LEDs that

are driven from the 82579 LAN device. Each of the three LED outputs can be

individually configured to select the particular event, state, or activity that is indicated

on that output. In addition, each LED can be individually configured for output polarity

as well as for blinking versus non-blinking (steady-state) indication.

The configuration for LED outputs is specified using the LEDCTL register. Furthermore,

the hardware-default configuration for all the LED outputs, can be specified using NVM

fields; thereby, supporting LED displays configurable to a particular OEM preference.

Each of the three LEDs might be configured to use one of a variety of sources for output

indication. The MODE bits control the LED source:

• LINK_100/1000 is asserted when link is established at either 100 or 1000 Mb/s.

• LINK_10/1000 is asserted when link is established at either 10 or 1000 Mb/s.

• LINK_UP is asserted when any speed link is established and maintained.

• ACTIVITY is asserted when link is established and packets are being transmitted or

received.

• LINK/ACTIVITY is asserted when link is established AND there is NO transmit or

receive activity

• LINK_10 is asserted when a 10 Mb/ps link is established and maintained.

• LINK_100 is asserted when a 100 Mb/s link is established and maintained.

• LINK_1000 is asserted when a 1000 Mb/s link is established and maintained.

• FULL_DUPLEX is asserted when the link is configured for full duplex operation.

• COLLISION is asserted when a collision is observed.

• PAUSED is asserted when the device's transmitter is flow controlled.

• LED_ON is always asserted; LED_OFF is always deasserted.

The IVRT bits enable the LED source to be inverted before being output or observed by

the blink-control logic. LED outputs are assumed to normally be connected to the

negative side (cathode) of an external LED.

The BLINK bits control whether the LED should be blinked while the LED source is

asserted, and the blinking frequency (either 200 ms on and 200 ms off or 83 ms on and

83 ms off). The blink control can be especially useful for ensuring that certain events,

such as ACTIVITY indication, cause LED transitions, which are sufficiently visible to a

human eye. The same blinking rate is shared by all LEDs.

Datasheet 135

Functional Description

5.3.6 Function Level Reset Support (FLR)

The integrated GbE controller supports FLR capability. FLR capability can be used in

conjunction with Intel® Virtualization Technology. FLR allows an operating system in a

Virtual Machine to have complete control over a device, including its initialization,

without interfering with the rest of the platform. The device provides a software

interface that enables the operating system to reset the entire device as if a PCI reset

was asserted.

5.3.6.1 FLR Steps

5.3.6.1.1 FLR Initialization

1. FLR is initiated by software by writing a 1b to the Initiate FLR bit.

2. All subsequent requests targeting the function are not claimed and will be master

aborted immediately on the bus. This includes any configuration, I/O or memory

cycles. However, the function will continue to accept completions targeting the

function.

5.3.6.1.2 FLR Operation

Function resets all configuration, I/O, and memory registers of the function except

those indicated otherwise and resets all internal states of the function to the default or

initial condition.

5.3.6.1.3 FLR Completion

The Initiate FLR bit is reset (cleared) when the FLR reset completes. This bit can be

used to indicate to the software that the FLR reset completed.

Note: From the time the Initiate FLR bit is written to 1b, software must wait at least 100 ms

before accessing the function.

Functional Description

136 Datasheet

5.4 LPC Bridge (with System and Management

Functions) (D31:F0)

The LPC bridge function of the PCH resides in PCI Device 31:Function 0. In addition to

the LPC bridge function, D31:F0 contains other functional units including DMA,

Interrupt controllers, Timers, Power Management, System Management, GPIO, and

RTC. In this chapter, registers and functions associated with other functional units

(power management, GPIO, USB, etc.) are described in their respective sections.

Note: The LPC bridge cannot be configured as a subtractive decode agent.

5.4.1 LPC Interface

The PCH implements an LPC interface as described in the Low Pin Count Interface

Specification, Revision 1.1. The LPC interface to the PCH is shown in Figure 5-2. Note

that the PCH implements all of the signals that are shown as optional, but peripherals

are not required to do so.

Figure 5-2. LPC Interface Diagram

PCH

LPC Device

PCI Bus

PCI

CLK PCI

RST# PCI

SERIRQ PCI

PME#

LAD [3 :0]

LFRAME#

LPCPD#

(Optional)

SUS_STAT#

LDRQ [1 :0 ]#

(Optional)

LSMI#

(Optional)

GPI

Datasheet 137

Functional Description

5.4.1.1 LPC Cycle Types

The PCH implements all of the cycle types described in the Low Pin Count Interface

Specification, Revision 1.1. Tabl e 5 -5 shows the cycle types supported by the PCH.

NOTES:

1. The PCH provides a single generic memory range (LGMR) for decoding memory cycles and

forwarding them as LPC Memory cycles on the LPC bus. The LGMR memory decode range

is 64 KB in size and can be defined as being anywhere in the 4 GB memory space. This

range needs to be configured by BIOS during POST to provide the necessary memory

resources. BIOS should advertise the LPC Generic Memory Range as Reserved to the OS in

order to avoid resource conflict. For larger transfers, the PCH performs multiple 8-bit

transfers. If the cycle is not claimed by any peripheral, it is subsequently aborted, and the

PCH returns a value of all 1s to the processor. This is done to maintain compatibility with

ISA memory cycles where pull-up resistors would keep the bus high if no device responds.

2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer

can be to any address. However, the 2-byte transfer must be word-aligned (that is, with an

address where A0=0). A DWord transfer must be DWord-aligned (that is, with an address

where A1 and A0 are both 0).

5.4.1.2 Start Field Definition

NOTE: All other encodings are RESERVED.

Table 5-5. LPC Cycle Types Supported

Cycle Type Comment

Memory Read 1 byte only. (See Note 1 below)

Memory Write 1 byte only. (See Note 1 below)

I/O Read 1 byte only. The PCH breaks up 16- and 32-bit processor cycles into

multiple 8-bit transfers.

I/O Write 1 byte only. The PCH breaks up 16- and 32-bit processor cycles into

multiple 8-bit transfers.

DMA Read Can be 1, or 2 bytes

DMA Write Can be 1, or 2 bytes

Bus Master Read Can be 1, 2, or 4 bytes. (See Note 2 below)

Bus Master Write Can be 1, 2, or 4 bytes. (See Note 2 below)

Table 5-6. Start Field Bit Definitions

Bits[3:0]

Encoding Definition

0000 Start of cycle for a generic target

0010 Grant for bus master 0

0011 Grant for bus master 1

1111 Stop/Abort: End of a cycle for a target.

Functional Description

138 Datasheet

5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR)

The PCH always drives Bit 0 of this field to 0. Peripherals running bus master cycles

must also drive Bit 0 to 0. Ta b l e 5 - 7 shows the valid bit encodings.

5.4.1.4 Size

Bits[3:2] are reserved. The PCH always drives them to 00. Peripherals running bus

master cycles are also supposed to drive 00 for Bits 3:2; however, the PCH ignores

those bits. Bits[1:0] are encoded as listed in Ta b le 5-8 .

5.4.1.5 SYNC

Valid values for the SYNC field are shown in Tabl e 5 -9.

Table 5-7. Cycle Type Bit Definitions

Bits[3:2] Bit1 Definition

00 0 I/O Read

00 1 I/O Write

01 0 Memory Read

01 1 Memory Read

10 0 DMA Read

10 1 DMA Write

11 x Reserved. If a peripheral performing a bus master cycle generates this

value, the PCH aborts the cycle.

Table 5-8. Transfer Size Bit Definition

Bits[1:0] Size

00 8-bit transfer (1 byte)

01 16-bit transfer (2 bytes)

10 Reserved. The PCH never drives this combination. If a peripheral running a bus

master cycle drives this combination, the PCH may abort the transfer.

11 32-bit transfer (4 bytes)

Table 5-9. SYNC Bit Definition (Sheet 1 of 2)

Bits[3:0] Indication

0000 Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA

request deassertion and no more transfers desired for that channel.

0101

Short Wait: Part indicating wait-states. For bus master cycles, the PCH does not

use this encoding. Instead, the PCH uses the Long Wait encoding (see next

encoding below).

0110

Long Wait: Part indicating wait-states, and many wait-states will be added. This

encoding driven by the PCH for bus master cycles, rather than the Short Wait

(0101).

1001

Ready More (Used only by peripheral for DMA cycle): SYNC achieved with no

error and more DMA transfers desired to continue after this transfer. This value is

valid only on DMA transfers and is not allowed for any other type of cycle.

Datasheet 139

Functional Description

NOTES:

1. All other combinations are RESERVED.

2. If the LPC controller receives any SYNC returned from the device other than short (0101),

long wait (0110), or ready (0000) when running a FWH cycle, indeterminate results may

occur. A FWH device is not allowed to assert an Error SYNC.

5.4.1.6 SYNC Time-Out

There are several error cases that can occur on the LPC interface. The PCH responds as

defined in section 4.2.1.9 of the Low Pin Count Interface Specification, Revision 1.1 to

the stimuli described therein. There may be other peripheral failure conditions;

however, these are not handled by the PCH.

5.4.1.7 SYNC Error Indication

The PCH responds as defined in section 4.2.1.10 of the Low Pin Count Interface

Specification, Revision 1.1.

Upon recognizing the SYNC field indicating an error, the PCH treats this as a SERR by

reporting this into the Device 31 Error Reporting Logic.

5.4.1.8 LFRAME# Usage

The PCH follows the usage of LFRAME# as defined in the Low Pin Count Interface

Specification, Revision 1.1.

The PCH performs an abort for the following cases (possible failure cases):

• The PCH starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC

after four consecutive clocks.

• The PCH starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid

SYNC pattern.

• A peripheral drives an illegal address when performing bus master cycles.

• A peripheral drives an invalid value.

5.4.1.9 I/O Cycles

For I/O cycles targeting registers specified in the PCH’s decode ranges, the PCH

performs I/O cycles as defined in the Low Pin Count Interface Specification, Revision

1.1. These are 8-bit transfers. If the processor attempts a 16-bit or 32-bit transfer, the

PCH breaks the cycle up into multiple 8-bit transfers to consecutive I/O addresses.

Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the PCH

returns a value of all 1s (FFh) to the processor. This is to maintain compatibility with

ISA I/O cycles where pull-up resistors would keep the bus high if no device responds.

1010

Error: Sync achieved with error. This is generally used to replace the SERR# or

IOCHK# signal on the PCI/ISA bus. It indicates that the data is to be transferred,

but there is a serious error in this transfer. For DMA transfers, this not only indicates

an error, but also indicates DMA request deassertion and no more transfers desired

for that channel.

Table 5-9. SYNC Bit Definition (Sheet 2 of 2)

Bits[3:0] Indication

Functional Description

140 Datasheet

5.4.1.10 Bus Master Cycles

The PCH supports Bus Master cycles and requests (using LDRQ#) as defined in the Low

Pin Count Interface Specification, Revision 1.1. The PCH has two LDRQ# inputs, and

thus supports two separate bus master devices. It uses the associated START fields for

Bus Master 0 (0010b) or Bus Master 1 (0011b).

Note: The PCH does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters

should only perform memory read or memory write cycles.

5.4.1.11 LPC Power Management

LPCPD# Protocol

Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals drive

LDRQ# low or tri-state it. The PCH shuts off the LDRQ# input buffers. After driving

SUS_STAT# active, the PCH drives LFRAME# low, and tri-states (or drives low)

LAD[3:0].

Note: The Low Pin Count Interface Specification, Revision 1.1 defines the LPCPD# protocol

where there is at least 30 µs from LPCPD# assertion to LRST# assertion. This

specification explicitly states that this protocol only applies to entry/exit of low power

states which does not include asynchronous reset events. The PCH asserts both

SUS_STAT# (connects to LPCPD#) and PLTRST# (connects to LRST#) at the same time

during a global reset. This is not inconsistent with the LPC LPCPD# protocol.

5.4.1.12 Configuration and PCH Implications

LPC I/F Decoders

To allow the I/O cycles and memory mapped cycles to go to the LPC interface, the PCH

includes several decoders. During configuration, the PCH must be programmed with the

same decode ranges as the peripheral. The decoders are programmed using the Device

31:Function 0 configuration space.

Note: The PCH cannot accept PCI write cycles from PCI-to-PCI bridges or devices with similar

characteristics (specifically those with a “Retry Read” feature which is enabled) to an

LPC device if there is an outstanding LPC read cycle towards the same PCI device or

bridge. These cycles are not part of normal system operation, but may be encountered

as part of platform validation testing using custom test fixtures.

Bus Master Device Mapping and START Fields

Bus Masters must have a unique START field. In the case of the PCH that supports two

LPC bus masters, it drives 0010 for the START field for grants to Bus Master 0

(requested using LDRQ0#) and 0011 for grants to Bus Master 1 (requested using

LDRQ1#.). Thus, no registers are needed to configure the START fields for a particular

bus master.

Datasheet 141

Functional Description

5.5 DMA Operation (D31:F0)

The PCH supports LPC DMA using the PCH’s DMA controller. The DMA controller has

registers that are fixed in the lower 64 KB of I/O space. The DMA controller is

configured using registers in the PCI configuration space. These registers allow

configuration of the channels for use by LPC DMA.

The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with

seven independently programmable channels (Figure 5-3). DMA Controller 1 (DMA-1)

corresponds to DMA Channels 0–3 and DMA Controller 2 (DMA-2) corresponds to

Channels 5–7. DMA Channel 4 is used to cascade the two controllers and defaults to

cascade mode in the DMA Channel Mode (DCM) Register. Channel 4 is not available for

any other purpose. In addition to accepting requests from DMA slaves, the DMA

controller also responds to requests that software initiates. Software may initiate a

DMA service request by setting any bit in the DMA Channel Request Register to a 1.

Each DMA channel is hardwired to the compatible settings for DMA device size:

Channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and Channels [7:5]

are hardwired to 16-bit, count-by-words (address shifted) transfers.

The PCH provides 24-bit addressing in compliance with the ISA-Compatible

specification. Each channel includes a 16-bit ISA-Compatible Current Register which

holds the sixteen least-significant bits of the 24-bit address, an ISA-Compatible Page

The DMA controller also features refresh address generation, and auto-initialization

following a DMA termination.

5.5.1 Channel Priority

For priority resolution, the DMA consists of two logical channel groups: Channels 0–3

and Channels 4–7. Each group may be in either fixed or rotate mode, as determined by

the DMA Command Register.

DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However,

a software request for DMA service can be presented through each channel's DMA

Request Register. A software request is subject to the same prioritization as any

hardware request. See the detailed register description for Request Register

programming information in Section 13.2.

5.5.1.1 Fixed Priority

The initial fixed priority structure is as follows:

The fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. In this scheme, channel 0 has the

highest priority, and channel 7 has the lowest priority. Channels [3:0] of DMA-1 assume

the priority position of channel 4 in DMA-2, thus taking priority over Channels 5, 6, and

Figure 5-3. PCH DMA Controller

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

DMA-1 DMA-2

High priority Low priority

0, 1, 2, 3 5, 6, 7

Functional Description

142 Datasheet

5.5.1.2 Rotating Priority

Rotation allows for “fairness” in priority resolution. The priority chain rotates so that the

last channel serviced is assigned the lowest priority in the channel group (0–3, 5–7).

Channels 0–3 rotate as a group of 4. They are always placed between Channel 5 and

Channel 7 in the priority list.

Channel 5–7 rotate as part of a group of 4. That is, Channels (5–7) form the first three

positions in the rotation, while Channel Group (0–3) comprises the fourth position in

the arbitration.

5.5.2 Address Compatibility Mode

When the DMA is operating, the addresses do not increment or decrement through the

High and Low Page Registers. Therefore, if a 24-bit address is 01FFFFh and increments,

the next address is 010000h, not 020000h. Similarly, if a 24-bit address is 020000h

and decrements, the next address is 02FFFFh, not 01FFFFh. However, when the DMA is

operating in 16-bit mode, the addresses still do not increment or decrement through

the High and Low Page Registers but the page boundary is now 128 K. Therefore, if a

24-bit address is 01FFFEh and increments, the next address is 000000h, not

0100000h. Similarly, if a 24-bit address is 020000h and decrements, the next address

is 03FFFEh, not 02FFFEh. This is compatible with the 82C37 and Page Register

implementation used in the PC-AT. This mode is set after CPURST is valid.

5.5.3 Summary of DMA Transfer Sizes

Table 5 - 10 lists each of the DMA device transfer sizes. The column labeled “Current

Byte/Word Count Register” indicates that the register contents represents either the

number of bytes to transfer or the number of 16-bit words to transfer. The column

labeled “Current Address Increment/Decrement” indicates the number added to or

taken from the Current Address register after each DMA transfer cycle. The DMA

Channel Mode Register determines if the Current Address Register will be incremented

or decremented.

5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count

by Words

The PCH maintains compatibility with the implementation of the DMA in the PC AT that

used the 82C37. The DMA shifts the addresses for transfers to/from a 16-bit device

count-by-words.

Note: The least significant bit of the Low Page Register is dropped in 16-bit shifted mode.

When programming the Current Address Register (when the DMA channel is in this

mode), the Current Address must be programmed to an even address with the address

value shifted right by one bit.

Table 5-10. DMA Transfer Size

DMA Device Date Size And Word Count Current Byte/Word

Count Register

Current Address

Increment/

Decrement

8-Bit I/O, Count By Bytes Bytes 1

16-Bit I/O, Count By Words (Address

Shifted) Words 1

Datasheet 143

Functional Description

The address shifting is shown in Tab l e 5 -11.

NOTE: The least significant bit of the Page Register is dropped in 16-bit shifted mode.

5.5.4 Autoinitialize

By programming a bit in the DMA Channel Mode Register, a channel may be set up as

an autoinitialize channel. When a channel undergoes autoinitialization, the original

values of the Current Page, Current Address and Current Byte/Word Count Registers

are automatically restored from the Base Page, Address, and Byte/Word Count

Registers of that channel following TC. The Base Registers are loaded simultaneously

with the Current Registers by the microprocessor when the DMA channel is

programmed and remain unchanged throughout the DMA service. The mask bit is not

set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to

perform another DMA service, without processor intervention, as soon as a valid DREQ

is detected.

5.5.5 Software Commands

There are three additional special software commands that the DMA controller can

execute. The three software commands are:

• Clear Byte Pointer Flip-Flop

•Master Clear

• Clear Mask Register

They do not depend on any specific bit pattern on the data bus.

Table 5-11. Address Shifting in 16-Bit I/O DMA Transfers

Output

Address

8-Bit I/O Programmed

Address (Ch 0–3)

16-Bit I/O Programmed

Address (Ch 5–7)

(Shifted)

A[16:1]

A[23:17]

A[16:1]

A[23:17]

A[15:0]

A[23:17]

Functional Description

144 Datasheet

5.6 LPC DMA

DMA on LPC is handled through the use of the LDRQ# lines from peripherals and

special encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment

modes are supported on the LPC interface. Channels 0–3 are 8-bit channels. Channels

5–7 are 16-bit channels. Channel 4 is reserved as a generic bus master request.

5.6.1 Asserting DMA Requests

Peripherals that need DMA service encode their requested channel number on the

LDRQ# signal. To simplify the protocol, each peripheral on the LPC I/F has its own

dedicated LDRQ# signal (they may not be shared between two separate peripherals).

The PCH has two LDRQ# inputs, allowing at least two devices to support DMA or bus

mastering.

LDRQ# is synchronous with LCLK (PCI clock). As shown in Figure 5-4, the peripheral

uses the following serial encoding sequence:

• Peripheral starts the sequence by asserting LDRQ# low (start bit). LDRQ# is high

during idle conditions.

• The next three bits contain the encoded DMA channel number (MSB first).

• The next bit (ACT) indicates whether the request for the indicated DMA channel is

active or inactive. The ACT bit is 1 (high) to indicate if it is active and 0 (low) if it is

inactive. The case where ACT is low is rare, and is only used to indicate that a

previous request for that channel is being abandoned.

• After the active/inactive indication, the LDRQ# signal must go high for at least one

clock. After that one clock, LDRQ# signal can be brought low to the next encoding

sequence.

If another DMA channel also needs to request a transfer, another sequence can be sent

on LDRQ#. For example, if an encoded request is sent for Channel 2, and then Channel

3 needs a transfer before the cycle for Channel 2 is run on the interface, the peripheral

can send the encoded request for Channel 3. This allows multiple DMA agents behind

an I/O device to request use of the LPC interface, and the I/O device does not need to

self-arbitrate before sending the message.

Figure 5-4. DMA Request Assertion through LDRQ#

Start MSB LSB ACT Start

LCLK

LDRQ#

Datasheet 145

Functional Description

5.6.2 Abandoning DMA Requests

DMA Requests can be deasserted in two fashions: on error conditions by sending an

LDRQ# message with the ‘ACT’ bit set to 0, or normally through a SYNC field during the

DMA transfer. This section describes boundary conditions where the DMA request needs

to be removed prior to a data transfer.

There may be some special cases where the peripheral desires to abandon a DMA

transfer. The most likely case of this occurring is due to a floppy disk controller which

has overrun or underrun its FIFO, or software stopping a device prematurely.

In these cases, the peripheral wishes to stop further DMA activity. It may do so by

sending an LDRQ# message with the ACT bit as 0. However, since the DMA request was

seen by the PCH, there is no assurance that the cycle has not been granted and will

shortly run on LPC. Therefore, peripherals must take into account that a DMA cycle may

still occur. The peripheral can choose not to respond to this cycle, in which case the

host will abort it, or it can choose to complete the cycle normally with any random data.

This method of DMA deassertion should be prevented whenever possible, to limit

boundary conditions both on the PCH and the peripheral.

5.6.3 General Flow of DMA Transfers

Arbitration for DMA channels is performed through the 8237 within the host. Once the

host has won arbitration on behalf of a DMA channel assigned to LPC, it asserts

LFRAME# on the LPC I/F and begins the DMA transfer. The general flow for a basic DMA

transfer is as follows:

1. The PCH starts transfer by asserting 0000b on LAD[3:0] with LFRAME# asserted.

2. The PCH asserts ‘cycle type’ of DMA, direction based on DMA transfer direction.

3. The PCH asserts channel number and, if applicable, terminal count.

4. The PCH indicates the size of the transfer: 8 or 16 bits.

5. If a DMA read…

— The PCH drives the first 8 bits of data and turns the bus around.

— The peripheral acknowledges the data with a valid SYNC.

— If a 16-bit transfer, the process is repeated for the next 8 bits.

6. If a DMA write…

— The PCH turns the bus around and waits for data.

— The peripheral indicates data ready through SYNC and transfers the first byte.

— If a 16-bit transfer, the peripheral indicates data ready and transfers the next

byte.

7. The peripheral turns around the bus.

5.6.4 Terminal Count

Terminal count is communicated through LAD[3] on the same clock that DMA channel is

communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates

the last byte of transfer, based upon the size of the transfer.

For example, on an 8-bit transfer size (SIZE field is 00b), if the TC bit is set, then this is

the last byte. On a 16-bit transfer (SIZE field is 01b), if the TC bit is set, then the

second byte is the last byte. The peripheral, therefore, must internalize the TC bit when

the CHANNEL field is communicated, and only signal TC when the last byte of that

transfer size has been transferred.

Functional Description

146 Datasheet

5.6.5 Verify Mode

Verify mode is supported on the LPC interface. A verify transfer to the peripheral is

similar to a DMA write, where the peripheral is transferring data to main memory. The

indication from the host is the same as a DMA write, so the peripheral will be driving

data onto the LPC interface. However, the host will not transfer this data into main

memory.

5.6.6 DMA Request Deassertion

An end of transfer is communicated to the PCH through a special SYNC field

transmitted by the peripheral. An LPC device must not attempt to signal the end of a

transfer by deasserting LDREQ#. If a DMA transfer is several bytes (such as, a transfer

from a demand mode device) the PCH needs to know when to deassert the DMA

request based on the data currently being transferred.

The DMA agent uses a SYNC encoding on each byte of data being transferred, which

indicates to the PCH whether this is the last byte of transfer or if more bytes are

requested. To indicate the last byte of transfer, the peripheral uses a SYNC value of

0000b (ready with no error), or 1010b (ready with error). These encodings tell the PCH

that this is the last piece of data transferred on a DMA read (PCH to peripheral), or the

byte that follows is the last piece of data transferred on a DMA write (peripheral to the

PCH).

When the PCH sees one of these two encodings, it ends the DMA transfer after this byte

and deasserts the DMA request to the 8237. Therefore, if the PCH indicated a 16-bit

transfer, the peripheral can end the transfer after one byte by indicating a SYNC value

of 0000b or 1010b. The PCH does not attempt to transfer the second byte, and

deasserts the DMA request internally.

If the peripheral indicates a 0000b or 1010b SYNC pattern on the last byte of the

indicated size, then the PCH only deasserts the DMA request to the 8237 since it does

not need to end the transfer.

If the peripheral wishes to keep the DMA request active, then it uses a SYNC value of

1001b (ready plus more data). This tells the 8237 that more data bytes are requested

after the current byte has been transferred, so the PCH keeps the DMA request active

to the 8237. Therefore, on an 8-bit transfer size, if the peripheral indicates a SYNC

value of 1001b to the PCH, the data will be transferred and the DMA request will remain

active to the 8237. At a later time, the PCH will then come back with another START–

CYCTYPE–CHANNEL–SIZE etc. combination to initiate another transfer to the

peripheral.

The peripheral must not assume that the next START indication from the PCH is

another grant to the peripheral if it had indicated a SYNC value of 1001b. On a single

mode DMA device, the 8237 will re-arbitrate after every transfer. Only demand mode

DMA devices can be assured that they will receive the next START indication from the

PCH.

Note: Indicating a 0000b or 1010b encoding on the SYNC field of an odd byte of a 16-bit

channel (first byte of a 16-bit transfer) is an error condition.

Note: The host stops the transfer on the LPC bus as indicated, fills the upper byte with

random data on DMA writes (peripheral to memory), and indicates to the 8237 that the

DMA transfer occurred, incrementing the 8237’s address and decrementing its byte

count.

Datasheet 147

Functional Description

5.6.7 SYNC Field / LDRQ# Rules

Since DMA transfers on LPC are requested through an LDRQ# assertion message, and

are ended through a SYNC field during the DMA transfer, the peripheral must obey the

following rule when initiating back-to-back transfers from a DMA channel.

The peripheral must not assert another message for eight LCLKs after a deassertion is

indicated through the SYNC field. This is needed to allow the 8237, that typically runs

off a much slower internal clock, to see a message deasserted before it is re-asserted

so that it can arbitrate to the next agent.

Under default operation, the host only performs 8-bit transfers on 8-bit channels and

16-bit transfers on 16-bit channels.

The method by which this communication between host and peripheral through system

BIOS is performed is beyond the scope of this specification. Since the LPC host and LPC

peripheral are motherboard devices, no “plug-n-play” registry is required.

The peripheral must not assume that the host is able to perform transfer sizes that are

larger than the size allowed for the DMA channel, and be willing to accept a SIZE field

that is smaller than what it may currently have buffered.

To that end, it is recommended that future devices that may appear on the LPC bus,

that require higher bandwidth than 8-bit or 16-bit DMA allow, do so with a bus

mastering interface and not rely on the 8237.

5.7 8254 Timers (D31:F0)

The PCH contains three counters that have fixed uses. All registers and functions

associated with the 8254 timers are in the core well. The 8254 unit is clocked by a

14.31818 MHz clock.

Counter 0, System Timer

This counter functions as the system timer by controlling the state of IRQ0 and is

typically programmed for Mode 3 operation. The counter produces a square wave with

a period equal to the product of the counter period (838 ns) and the initial count value.

The counter loads the initial count value 1 counter period after software writes the

count value to the counter I/O address. The counter initially asserts IRQ0 and

decrements the count value by two each counter period. The counter negates IRQ0

when the count value reaches 0. It then reloads the initial count value and again

decrements the initial count value by two each counter period. The counter then

asserts IRQ0 when the count value reaches 0, reloads the initial count value, and

repeats the cycle, alternately asserting and negating IRQ0.

Counter 1, Refresh Request Signal

This counter provides the refresh request signal and is typically programmed for Mode

2 operation and only impacts the period of the REF_TOGGLE bit in Port 61. The initial

count value is loaded one counter period after being written to the counter I/O address.

The REF_TOGGLE bit will have a square wave behavior (alternate between 0 and 1) and

will toggle at a rate based on the value in the counter. Programming the counter to

anything other than Mode 2 will result in undefined behavior for the REF_TOGGLE bit.

Counter 2, Speaker Tone

This counter provides the speaker tone and is typically programmed for Mode 3

operation. The counter provides a speaker frequency equal to the counter clock

frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled

by a write to port 061h (see NMI Status and Control ports).

Functional Description

148 Datasheet

5.7.1 Timer Programming

The counter/timers are programmed in the following fashion:

1. Write a control word to select a counter.

2. Write an initial count for that counter.

3. Load the least and/or most significant bytes (as required by Control Word Bits 5, 4)

of the 16-bit counter.

4. Repeat with other counters.

Only two conventions need to be observed when programming the counters. First, for

each counter, the control word must be written before the initial count is written.

Second, the initial count must follow the count format specified in the control word

(least significant byte only, most significant byte only, or least significant byte and then

most significant byte).

A new initial count may be written to a counter at any time without affecting the

counter's programmed mode. Counting is affected as described in the mode definitions.

The new count must follow the programmed count format.

If a counter is programmed to read/write two-byte counts, the following precaution

applies: A program must not transfer control between writing the first and second byte

to another routine which also writes into that same counter. Otherwise, the counter will

be loaded with an incorrect count.

The Control Word Register at port 43h controls the operation of all three counters.

Several commands are available:

•Control Word Command. Specifies which counter to read or write, the operating

mode, and the count format (binary or BCD).

•Counter Latch Command. Latches the current count so that it can be read by the

system. The countdown process continues.

•Read Back Command. Reads the count value, programmed mode, the current

state of the OUT pins, and the state of the Null Count Flag of the selected counter.

Table 5 - 12 lists the six operating modes for the interval counters.

Table 5-12. Counter Operating Modes

Mode Function Description

0 Out signal on end of count (=0) Output is 0. When count goes to 0, output goes to

1 and stays at 1 until counter is reprogrammed.

1 Hardware retriggerable one-shot Output is 0. When count goes to 0, output goes to

1 for one clock time.

2Rate generator (divide by n

counter)

Output is 1. Output goes to 0 for one clock time,

then back to 1 and counter is reloaded.

3Square wave output

Output is 1. Output goes to 0 when counter rolls

over, and counter is reloaded. Output goes to 1

when counter rolls over, and counter is reloaded,

etc.

4 Software triggered strobe Output is 1. Output goes to 0 when count expires

for one clock time.

5 Hardware triggered strobe Output is 1. Output goes to 0 when count expires

for one clock time.

Datasheet 149

Functional Description

5.7.2 Reading from the Interval Timer

It is often desirable to read the value of a counter without disturbing the count in

progress. There are three methods for reading the counters: a simple read operation,

counter Latch command, and the Read-Back command. Each is explained below.

With the simple read and counter latch command methods, the count must be read

according to the programmed format; specifically, if the counter is programmed for two

byte counts, two bytes must be read. The two bytes do not have to be read one right

after the other. Read, write, or programming operations for other counters may be

inserted between them.

5.7.2.1 Simple Read

The first method is to perform a simple read operation. The counter is selected through

Port 40h (Counter 0), 41h (Counter 1), or 42h (Counter 2).

Note: Performing a direct read from the counter does not return a determinate value,

because the counting process is asynchronous to read operations. However, in the case

of Counter 2, the count can be stopped by writing to the GATE bit in Port 61h.

5.7.2.2 Counter Latch Command

The Counter Latch command, written to Port 43h, latches the count of a specific

counter at the time the command is received. This command is used to ensure that the

count read from the counter is accurate, particularly when reading a two-byte count.

The count value is then read from each counter’s Count register as was programmed by

the Control register.

The count is held in the latch until it is read or the counter is reprogrammed. The count

is then unlatched. This allows reading the contents of the counters on the fly without

affecting counting in progress. Multiple Counter Latch Commands may be used to latch

more than one counter. Counter Latch commands do not affect the programmed mode

of the counter in any way.

If a Counter is latched and then, some time later, latched again before the count is

read, the second Counter Latch command is ignored. The count read is the count at the

time the first Counter Latch command was issued.

5.7.2.3 Read Back Command

The Read Back command, written to Port 43h, latches the count value, programmed

mode, and current states of the OUT pin and Null Count flag of the selected counter or

counters. The value of the counter and its status may then be read by I/O access to the

counter address.

The Read Back command may be used to latch multiple counter outputs at one time.

This single command is functionally equivalent to several counter latch commands, one

for each counter latched. Each counter's latched count is held until it is read or

reprogrammed. Once read, a counter is unlatched. The other counters remain latched

until they are read. If multiple count Read Back commands are issued to the same

counter without reading the count, all but the first are ignored.

The Read Back command may additionally be used to latch status information of

selected counters. The status of a counter is accessed by a read from that counter's

I/O port address. If multiple counter status latch operations are performed without

reading the status, all but the first are ignored.

Functional Description

150 Datasheet

Both count and status of the selected counters may be latched simultaneously. This is

functionally the same as issuing two consecutive, separate Read Back commands. If

multiple count and/or status Read Back commands are issued to the same counters

without any intervening reads, all but the first are ignored.

If both count and status of a counter are latched, the first read operation from that

counter returns the latched status, regardless of which was latched first. The next one

or two reads, depending on whether the counter is programmed for one or two type

counts, returns the latched count. Subsequent reads return unlatched count.

5.8 8259 Interrupt Controllers (PIC) (D31:F0)

The PCH incorporates the functionality of two 8259 interrupt controllers that provide

system interrupts for the ISA compatible interrupts. These interrupts are: system

timer, keyboard controller, serial ports, parallel ports, floppy disk, mouse, and DMA

channels. In addition, this interrupt controller can support the PCI based interrupts, by

mapping the PCI interrupt onto the compatible ISA interrupt line. Each 8259 core

supports eight interrupts, numbered 0–7. Ta ble 5- 1 3 shows how the cores are

connected.

The PCH cascades the slave controller onto the master controller through master

controller interrupt input 2. This means there are only 15 possible interrupts for the

PCH PIC.

Table 5-13. Interrupt Controller Core Connections

8259 8259

Input

Typical Interrupt

Source Connected Pin / Function

Master

0 Internal Internal Timer / Counter 0 output / HPET #0

1 Keyboard IRQ1 using SERIRQ

2 Internal Slave controller INTR output

3 Serial Port A IRQ3 using SERIRQ, PIRQ#

4 Serial Port B IRQ4 using SERIRQ, PIRQ#

5 Parallel Port / Generic IRQ5 using SERIRQ, PIRQ#

6 Floppy Disk IRQ6 using SERIRQ, PIRQ#

7 Parallel Port / Generic IRQ7 using SERIRQ, PIRQ#

Slave

0Internal Real Time

Clock Internal RTC / HPET #1

1 Generic IRQ9 using SERIRQ, SCI, TCO, or PIRQ#

2 Generic IRQ10 using SERIRQ, SCI, TCO, or PIRQ#

3Generic IRQ11 using SERIRQ, SCI, TCO, or PIRQ#, or HPET

4PS/2 Mouse IRQ12 using SERIRQ, SCI, TCO, or PIRQ#, or HPET

5Internal

State Machine output based on processor FERR#

assertion. May optionally be used for SCI or TCO

interrupt if FERR# not needed.

6SATA SATA Primary (legacy mode), or using SERIRQ or

PIRQ#

7SATA SATA Secondary (legacy mode) or using SERIRQ or

PIRQ#

Datasheet 151

Functional Description

Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2,

IRQ8#, and IRQ13.

Note: Active-low interrupt sources (such as, the PIRQ#s) are inverted inside the PCH. In the

following descriptions of the 8259s, the interrupt levels are in reference to the signals

at the internal interface of the 8259s, after the required inversions have occurred.

Therefore, the term “high” indicates “active,” which means “low” on an originating

PIRQ#.

5.8.1 Interrupt Handling

5.8.1.1 Generating Interrupts

The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each

interrupt level. These bits are used to determine the interrupt vector returned, and

status of any other pending interrupts. Tab le 5-14 defines the IRR, ISR, and IMR.

5.8.1.2 Acknowledging Interrupts

The processor generates an interrupt acknowledge cycle that is translated by the host

bridge into a PCI Interrupt Acknowledge Cycle to the PCH. The PIC translates this

command into two internal INTA# pulses expected by the 8259 cores. The PIC uses the

first internal INTA# pulse to freeze the state of the interrupts for priority resolution. On

the second INTA# pulse, the master or slave sends the interrupt vector to the

processor with the acknowledged interrupt code. This code is based upon Bits [7:3] of

the corresponding ICW2 register, combined with three bits representing the interrupt

within that controller.

Table 5-14. Interrupt Status Registers

Bit Description

IRR

Interrupt Request Register. This bit is set on a low to high transition of the interrupt

line in edge mode, and by an active high level in level mode. This bit is set whether or

not the interrupt is masked. However, a masked interrupt will not generate INTR.

ISR

Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared,

when an interrupt acknowledge cycle is seen, and the vector returned is for that

interrupt.

IMR Interrupt Mask Register. This bit determines whether an interrupt is masked.

Masked interrupts will not generate INTR.

Table 5-15. Content of Interrupt Vector Byte

Master, Slave Interrupt Bits [7:3] Bits [2:0]

IRQ7,15

ICW2[7:3]

111

IRQ6,14 110

IRQ5,13 101

IRQ4,12 100

IRQ3,11 011

IRQ2,10 010

IRQ1,9 001

IRQ0,8 000

Functional Description

152 Datasheet

5.8.1.3 Hardware/Software Interrupt Sequence

1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or

seen high in level mode, setting the corresponding IRR bit.

2. The PIC sends INTR active to the processor if an asserted interrupt is not masked.

3. The processor acknowledges the INTR and responds with an interrupt acknowledge

cycle. The cycle is translated into a PCI interrupt acknowledge cycle by the host

bridge. This command is broadcast over PCI by the PCH.

4. Upon observing its own interrupt acknowledge cycle on PCI, the PCH converts it

into the two cycles that the internal 8259 pair can respond to. Each cycle appears

as an interrupt acknowledge pulse on the internal INTA# pin of the cascaded

interrupt controllers.

5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR

bit is set and the corresponding IRR bit is reset. On the trailing edge of the first

pulse, a slave identification code is broadcast by the master to the slave on a

private, internal three bit wide bus. The slave controller uses these bits to

determine if it must respond with an interrupt vector during the second INTA#

pulse.

6. Upon receiving the second internally generated INTA# pulse, the PIC returns the

interrupt vector. If no interrupt request is present because the request was too

short in duration, the PIC returns vector 7 from the master controller.

7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of

the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate

EOI command is issued at the end of the interrupt subroutine.

5.8.2 Initialization Command Words (ICWx)

Before operation can begin, each 8259 must be initialized. In the PCH, this is a four

byte sequence. The four initialization command words are referred to by their

acronyms: ICW1, ICW2, ICW3, and ICW4.

The base address for each 8259 initialization command word is a fixed location in the

I/O memory space: 20h for the master controller, and A0h for the slave controller.

5.8.2.1 ICW1

An I/O write to the master or slave controller base address with data bit 4 equal to 1 is

interpreted as a write to ICW1. Upon sensing this write, the PCH’s PIC expects three

more byte writes to 21h for the master controller, or A1h for the slave controller, to

complete the ICW sequence.

A write to ICW1 starts the initialization sequence during which the following

automatically occur:

1. Following initialization, an interrupt request (IRQ) input must make a low-to-high

transition to generate an interrupt.

2. The Interrupt Mask Register is cleared.

3. IRQ7 input is assigned priority 7.

4. The slave mode address is set to 7.

5. Special mask mode is cleared and Status Read is set to IRR.

Datasheet 153

Functional Description

5.8.2.2 ICW2

The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the

interrupt vector that will be released during an interrupt acknowledge. A different base

is selected for each interrupt controller.

5.8.2.3 ICW3

The third write in the sequence (ICW3) has a different meaning for each controller.

• For the master controller, ICW3 is used to indicate which IRQ input line is used to

cascade the slave controller. Within the PCH, IRQ2 is used. Therefore, Bit 2 of ICW3

on the master controller is set to a 1, and the other bits are set to 0s.

• For the slave controller, ICW3 is the slave identification code used during an

interrupt acknowledge cycle. On interrupt acknowledge cycles, the master

controller broadcasts a code to the slave controller if the cascaded interrupt won

arbitration on the master controller. The slave controller compares this

identification code to the value stored in its ICW3, and if it matches, the slave

controller assumes responsibility for broadcasting the interrupt vector.

5.8.2.4 ICW4

The final write in the sequence (ICW4) must be programmed for both controllers. At

the very least, Bit 0 must be set to a 1 to indicate that the controllers are operating in

an Intel Architecture-based system.

5.8.3 Operation Command Words (OCW)

These command words reprogram the Interrupt controller to operate in various

interrupt modes.

• OCW1 masks and unmasks interrupt lines.

• OCW2 controls the rotation of interrupt priorities when in rotating priority mode,

and controls the EOI function.

• OCW3 sets up ISR/IRR reads, enables/disables the special mask mode (SMM), and

enables/disables polled interrupt mode.

5.8.4 Modes of Operation

5.8.4.1 Fully Nested Mode

In this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being

the highest. When an interrupt is acknowledged, the highest priority request is

determined and its vector placed on the bus. Additionally, the ISR for the interrupt is

set. This ISR bit remains set until: the processor issues an EOI command immediately

before returning from the service routine; or if in AEOI mode, on the trailing edge of

the second INTA#. While the ISR bit is set, all further interrupts of the same or lower

priority are inhibited, while higher levels generate another interrupt. Interrupt priorities

can be changed in the rotating priority mode.

Functional Description

154 Datasheet

5.8.4.2 Special Fully-Nested Mode

This mode is used in the case of a system where cascading is used, and the priority has

to be conserved within each slave. In this case, the special fully-nested mode is

programmed to the master controller. This mode is similar to the fully-nested mode

with the following exceptions:

• When an interrupt request from a certain slave is in service, this slave is not locked

out from the master's priority logic and further interrupt requests from higher

priority interrupts within the slave are recognized by the master and initiate

interrupts to the processor. In the normal-nested mode, a slave is masked out

when its request is in service.

• When exiting the Interrupt Service routine, software has to check whether the

interrupt serviced was the only one from that slave. This is done by sending a Non-

Specific EOI command to the slave and then reading its ISR. If it is 0, a non-

specific EOI can also be sent to the master.

5.8.4.3 Automatic Rotation Mode (Equal Priority Devices)

In some applications, there are a number of interrupting devices of equal priority.

Automatic rotation mode provides for a sequential 8-way rotation. In this mode, a

device receives the lowest priority after being serviced. In the worst case, a device

requesting an interrupt has to wait until each of seven other devices are serviced at

most once.

There are two ways to accomplish automatic rotation using OCW2; the Rotation on

Non-Specific EOI Command (R=1, SL=0, EOI=1) and the rotate in automatic EOI mode

which is set by (R=1, SL=0, EOI=0).

5.8.4.4 Specific Rotation Mode (Specific Priority)

Software can change interrupt priorities by programming the bottom priority. For

example, if IRQ5 is programmed as the bottom priority device, then IRQ6 is the highest

priority device. The Set Priority Command is issued in OCW2 to accomplish this, where:

R=1, SL=1, and LO–L2 is the binary priority level code of the bottom priority device.

In this mode, internal status is updated by software control during OCW2. However, it

is independent of the EOI command. Priority changes can be executed during an EOI

command by using the Rotate on Specific EOI Command in OCW2 (R=1, SL=1, EOI=1

and LO–L2=IRQ level to receive bottom priority.

5.8.4.5 Poll Mode

Poll mode can be used to conserve space in the interrupt vector table. Multiple

interrupts that can be serviced by one interrupt service routine do not need separate

vectors if the service routine uses the poll command. Poll mode can also be used to

expand the number of interrupts. The polling interrupt service routine can call the

appropriate service routine, instead of providing the interrupt vectors in the vector

table. In this mode, the INTR output is not used and the microprocessor internal

Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is

achieved by software using a Poll command.

The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as

an interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads

the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte

returned during the I/O read contains a 1 in Bit 7 if there is an interrupt, and the binary

code of the highest priority level in Bits 2:0.

Datasheet 155

Functional Description

5.8.4.6 Cascade Mode

The PIC in the PCH has one master 8259 and one slave 8259 cascaded onto the master

through IRQ2. This configuration can handle up to 15 separate priority levels. The

master controls the slaves through a three bit internal bus. In the PCH, when the

master drives 010b on this bus, the slave controller takes responsibility for returning

the interrupt vector. An EOI command must be issued twice: once for the master and

once for the slave.

5.8.4.7 Edge and Level Triggered Mode

In ISA systems this mode is programmed using Bit 3 in ICW1, which sets level or edge

for the entire controller. In the PCH, this bit is disabled and a new register for edge and

level triggered mode selection, per interrupt input, is included. This is the Edge/Level

control Registers ELCR1 and ELCR2.

If an ELCR bit is 0, an interrupt request will be recognized by a low-to-high transition

on the corresponding IRQ input. The IRQ input can remain high without generating

another interrupt. If an ELCR bit is 1, an interrupt request will be recognized by a high

level on the corresponding IRQ input and there is no need for an edge detection. The

interrupt request must be removed before the EOI command is issued to prevent a

second interrupt from occurring.

In both the edge and level triggered modes, the IRQ inputs must remain active until

after the falling edge of the first internal INTA#. If the IRQ input goes inactive before

this time, a default IRQ7 vector is returned.

5.8.4.8 End of Interrupt (EOI) Operations

An EOI can occur in one of two fashions: by a command word write issued to the PIC

before returning from a service routine, the EOI command; or automatically when AEOI

bit in ICW4 is set to 1.

5.8.4.9 Normal End of Interrupt

In normal EOI, software writes an EOI command before leaving the interrupt service

routine to mark the interrupt as completed. There are two forms of EOI commands:

Specific and

Non-Specific. When a Non-Specific EOI command is issued, the PIC clears the highest

ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of operation of

the PIC within the PCH, as the interrupt being serviced currently is the interrupt

entered with the interrupt acknowledge. When the PIC is operated in modes that

preserve the fully nested structure, software can determine which ISR bit to clear by

issuing a Specific EOI. An ISR bit that is masked is not cleared by a Non-Specific EOI if

the PIC is in the special mask mode. An EOI command must be issued for both the

master and slave controller.

5.8.4.10 Automatic End of Interrupt Mode

In this mode, the PIC automatically performs a Non-Specific EOI operation at the

trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this

mode should be used only when a nested multi-level interrupt structure is not required

within a single PIC. The AEOI mode can only be used in the master controller and not

the slave controller.

Functional Description

156 Datasheet

5.8.5 Masking Interrupts

5.8.5.1 Masking on an Individual Interrupt Request

Each interrupt request can be masked individually by the Interrupt Mask Register

(IMR). This register is programmed through OCW1. Each bit in the IMR masks one

interrupt channel. Masking IRQ2 on the master controller masks all requests for service

from the slave controller.

5.8.5.2 Special Mask Mode

Some applications may require an interrupt service routine to dynamically alter the

system priority structure during its execution under software control. For example, the

routine may wish to inhibit lower priority requests for a portion of its execution but

enable some of them for another portion.

The special mask mode enables all interrupts not masked by a bit set in the Mask

issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower priority

requests. In the special mask mode, any interrupts may be selectively enabled by

loading the Mask Register with the appropriate pattern. The special mask mode is set

by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1, SMM=0.

5.8.6 Steering PCI Interrupts

The PCH can be programmed to allow PIRQA#-PIRQH# to be routed internally to

interrupts 3–7, 9–12, 14 or 15. The assignment is programmable through the PIRQx

Route Control registers, located at 60–63h and 68–6Bh in Device 31:Function 0. One or

more PIRQx# lines can be routed to the same IRQx input. If interrupt steering is not

required, the Route registers can be programmed to disable steering.

The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts

on a PCI board to share a single line across the connector. When a PIRQx# is routed to

specified IRQ line, software must change the IRQ's corresponding ELCR bit to level

sensitive mode. The PCH internally inverts the PIRQx# line to send an active high level

to the PIC. When a PCI interrupt is routed onto the PIC, the selected IRQ can no longer

be used by an active high device (through SERIRQ). However, active low interrupts can

share their interrupt with PCI interrupts.

Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external

PIRQ to be asserted. The PCH receives the PIRQ input, like all of the other external

sources, and routes it accordingly.

Datasheet 157

Functional Description

5.9 Advanced Programmable Interrupt Controller

(APIC) (D31:F0)

In addition to the standard ISA-compatible PIC described in the previous chapter, the

PCH incorporates the APIC. While the standard interrupt controller is intended for use

in a uni-processor system, APIC can be used in either a uni-processor or multi-

processor system.

5.9.1 Interrupt Handling

The I/O APIC handles interrupts very differently than the 8259. Briefly, these

differences are:

•Method of Interrupt Transmission. The I/O APIC transmits interrupts through

memory writes on the normal data path to the processor, and interrupts are

handled without the need for the processor to run an interrupt acknowledge cycle.

•Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the

interrupt number. For example, interrupt 10 can be given a higher priority than

interrupt 3.

•More Interrupts. The I/O APIC in the PCH supports a total of 24 interrupts.

•Multiple Interrupt Controllers. The I/O APIC architecture allows for multiple I/O

APIC devices in the system with their own interrupt vectors.

5.9.2 Interrupt Mapping

The I/O APIC within the PCH supports 24 APIC interrupts. Each interrupt has its own

unique vector assigned by software. The interrupt vectors are mapped as follows, and

match “Config 6” of the Multi-Processor Specification.

Table 5-16. APIC Interrupt Mapping1 (Sheet 1 of 2)

IRQ # Using

SERIRQ

Direct

from Pin

Using PCI

Message Internal Modules

0 No No No Cascade from 8259 #1

1Yes No Yes

2 No No No 8254 Counter 0, HPET #0 (legacy mode)

3Yes No Yes

4Yes No Yes

5Yes No Yes

6Yes No Yes

7Yes No Yes

8No No NoRTC, HPET #1 (legacy mode)

9 Yes No Yes Option for SCI, TCO

10 Yes No Yes Option for SCI, TCO

11 Yes No Yes HPET #2, Option for SCI, TCO (Note2)

12 Yes No Yes HPET #3 (Note 3)

13 No No No FERR# logic

14 Yes No Yes SATA Primary (legacy mode)

15 Yes No Yes SATA Secondary (legacy mode)

Functional Description

158 Datasheet

NOTES:

1. When programming the polarity of internal interrupt sources on the APIC, interrupts 0

through 15 receive active-high internal interrupt sources, while interrupts 16 through 23

receive active-low internal interrupt sources.

2. If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other

devices to ensure the proper operation of HPET #2. The PCH hardware does not prevent

sharing of IRQ 11.

3. If IRQ 12 is used for HPET #3, software should ensure IRQ 12 is not shared with any other

devices to ensure the proper operation of HPET #3. The PCH hardware does not prevent

sharing of IRQ 12.

4. PIRQ[E:H] are Multiplexed with GPIO pins. Interrupts PIRQ[E:H] will not be exposed if they

are configured as GPIOs.

5.9.3 PCI / PCI Express* Message-Based Interrupts

When external devices through PCI/PCI Express wish to generate an interrupt, they will

send the message defined in the PCI Express* Base Specification, Revision 1.0a for

generating INTA# – INTD#. These will be translated internal assertions/deassertions of

INTA# – INTD#.

5.9.4 IOxAPIC Address Remapping

To support Intel® Virtualization Technology, interrupt messages are required to go

through similar address remapping as any other memory request. Address remapping

allows for domain isolation for interrupts, so a device assigned in one domain is not

allowed to generate an interrupt to another domain.

The address remapping is based on the Bus: Device: Function field associated with the

requests. The internal APIC is required to initiate the interrupt message using a unique

Bus: Device: function.

The PCH allows BIOS to program the unique Bus: Device: Function address for the

internal APIC. This address field does not change the APIC functionality and the APIC is

not promoted as a stand-alone PCI device. See Device 31: Function 0 Offset 6Ch for

additional information.

5.9.5 External Interrupt Controller Support

The PCH supports external APICs off of PCI Express ports but does not support APICs

on the PCI bus. The EOI special cycle is only forwarded to PCI Express ports.

16 PIRQA# PIRQA#

Yes Internal devices are routable; see

Section 10.1.20 though Section 10.1.34.

17 PIRQB# PIRQB#

18 PIRQC# PIRQC#

19 PIRQD# PIRQD#

20 N/A PIRQE#4

Yes

Option for SCI, TCO, HPET #0,1,2, 3. Other

internal devices are routable; see

Section 10.1.20 though Section 10.1.34.

21 N/A PIRQF#4

22 N/A PIRQG#4

23 N/A PIRQH#4

Table 5-16. APIC Interrupt Mapping1 (Sheet 2 of 2)

IRQ # Using

SERIRQ

Direct

from Pin

Using PCI

Message Internal Modules

Datasheet 159

Functional Description

5.10 Serial Interrupt (D31:F0)

The PCH supports a serial IRQ scheme. This allows a single signal to be used to report

interrupt requests. The signal used to transmit this information is shared between the

host, the PCH, and all peripherals that support serial interrupts. The signal line,

SERIRQ, is synchronous to PCI clock, and follows the sustained tri-state protocol that is

used by all PCI signals. This means that if a device has driven SERIRQ low, it will first

drive it high synchronous to PCI clock and release it the following PCI clock. The serial

IRQ protocol defines this sustained tri-state signaling in the following fashion:

•S – Sample Phase. Signal driven low

•R – Recovery Phase. Signal driven high

•T – Turn-around Phase. Signal released

The PCH supports a message for 21 serial interrupts. These represent the 15 ISA

interrupts (IRQ0–1, 2–15), the four PCI interrupts, and the control signals SMI# and

IOCHK#. The serial IRQ protocol does not support the additional APIC interrupts

(20–23).

Note: When the SATA controller is configured for legacy IDE mode, IRQ14 and IRQ15 are

expected to behave as ISA legacy interrupts that cannot be shared (that is, through the

Serial Interrupt pin). If IRQ14 and IRQ15 are shared with Serial Interrupt pin then

abnormal system behavior may occur. For example, IRQ14/15 may not be detected by

the PCH's interrupt controller. When the SATA controller is not running in Native IDE

mode, IRQ14 and IRQ15 are used as special interrupts. If the SATA controller is in

native mode, these interrupts can be mapped to other devices accordingly.

5.10.1 Start Frame

The serial IRQ protocol has two modes of operation which affect the start frame. These

two modes are: Continuous, where the PCH is solely responsible for generating the

start frame; and Quiet, where a serial IRQ peripheral is responsible for beginning the

start frame.

The mode that must first be entered when enabling the serial IRQ protocol is

continuous mode. In this mode, the PCH asserts the start frame. This start frame is 4,

6, or 8 PCI clocks wide based upon the Serial IRQ Control Register, bits 1:0 at 64h in

Device 31:Function 0 configuration space. This is a polling mode.

When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the

SERIRQ line remains inactive and pulled up between the Stop and Start Frame until a

peripheral drives the SERIRQ signal low. The PCH senses the line low and continues to

drive it low for the remainder of the Start Frame. Since the first PCI clock of the start

frame was driven by the peripheral in this mode, the PCH drives the SERIRQ line low for

1 PCI clock less than in continuous mode. This mode of operation allows for a quiet,

and therefore lower power, operation.

Functional Description

160 Datasheet

5.10.2 Data Frames

Once the Start frame has been initiated, all of the SERIRQ peripherals must start

counting frames based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has

exactly 3 phases of 1 clock each:

•Sample Phase. During this phase, the SERIRQ device drives SERIRQ low if the

corresponding interrupt signal is low. If the corresponding interrupt is high, then

the SERIRQ devices tri-state the SERIRQ signal. The SERIRQ line remains high due

to pull-up resistors (there is no internal pull-up resistor on this signal, an external

pull-up resistor is required). A low level during the IRQ0–1 and IRQ2–15 frames

indicates that an active-high ISA interrupt is not being requested, but a low level

during the PCI INT[A:D], SMI#, and IOCHK# frame indicates that an active-low

interrupt is being requested.

•Recovery Phase. During this phase, the device drives the SERIRQ line high if in

the Sample Phase it was driven low. If it was not driven in the sample phase, it is

tri-stated in this phase.

•Turn-around Phase. The device tri-states the SERIRQ line

5.10.3 Stop Frame

After all data frames, a Stop Frame is driven by the PCH. The SERIRQ signal is driven

low by the PCH for 2 or 3 PCI clocks. The number of clocks is determined by the

SERIRQ configuration register. The number of clocks determines the next mode.

5.10.4 Specific Interrupts Not Supported Using SERIRQ

There are three interrupts seen through the serial stream that are not supported by the

PCH. These interrupts are generated internally, and are not sharable with other devices

within the system. These interrupts are:

• IRQ0. Heartbeat interrupt generated off of the internal 8254 counter 0.

• IRQ8#. RTC interrupt can only be generated internally.

• IRQ13. Floating point error interrupt generated off of the processor assertion of

FERR#.

The PCH ignores the state of these interrupts in the serial stream, and does not adjust

their level based on the level seen in the serial stream.

Table 5-17. Stop Frame Explanation

Stop Frame Width Next Mode

2 PCI clocks Quiet Mode. Any SERIRQ device may initiate a Start Frame

3 PCI clocks Continuous Mode. Only the host (the PCH) may initiate a Start Frame

Datasheet 161

Functional Description

5.10.5 Data Frame Format

Ta b l e 5 - 1 8 shows the format of the data frames. For the PCI interrupts (A–D), the

output from the PCH is AND’d with the PCI input signal. This way, the interrupt can be

signaled using both the PCI interrupt input signal and using the SERIRQ signal (they

are shared).

Table 5-18. Data Frame Format

Data

Frame

Interrupt

Clocks Past

Start

Frame

Comment

1IRQ0 2

Ignored. IRQ0 can only be generated using the internal

8524

2IRQ1 5

3 SMI# 8 Causes SMI# if low. Will set the SERIRQ_SMI_STS bit.

4IRQ3 11

5IRQ4 14

6IRQ5 17

7IRQ6 20

8IRQ7 23

9 IRQ8 26 Ignored. IRQ8# can only be generated internally.

10 IRQ9 29

11 IRQ10 32

12 IRQ11 35

13 IRQ12 38

14 IRQ13 41 Ignored. IRQ13 can only be generated from FERR#

15 IRQ14 44 Not attached to SATA logic

16 IRQ15 47 Not attached to SATA logic

17 IOCHCK# 50 Same as ISA IOCHCK# going active.

18 PCI INTA# 53 Drive PIRQA#

19 PCI INTB# 56 Drive PIRQB#

20 PCI INTC# 59 Drive PIRQC#

21 PCI INTD# 62 Drive PIRQD#

Functional Description

162 Datasheet

5.11 Real Time Clock (D31:F0)

The Real Time Clock (RTC) module provides a battery backed-up date and time keeping

device with two banks of static RAM with 128 bytes each, although the first bank has

114 bytes for general purpose usage. Three interrupt features are available: time of

day alarm with once a second to once a month range, periodic rates of 122 µs to

500 ms, and end of update cycle notification. Seconds, minutes, hours, days, day of

week, month, and year are counted. Daylight savings compensation is no longer

supported. The hour is represented in twelve or twenty-four hour format, and data can

be represented in BCD or binary format. The design is functionally compatible with the

Motorola MS146818B. The time keeping comes from a 32.768 kHz oscillating source,

which is divided to achieve an update every second. The lower 14 bytes on the lower

RAM block has very specific functions. The first ten are for time and date information.

The next four (0Ah to 0Dh) are registers, which configure and report RTC functions.

The time and calendar data should match the data mode (BCD or binary) and hour

mode (12 or 24 hour) as selected in register B. It is up to the programmer to make

sure that data stored in these locations is within the reasonable values ranges and

represents a possible date and time. The exception to these ranges is to store a value

of C0–FFh in the Alarm bytes to indicate a don’t care situation. All Alarm conditions

must match to trigger an Alarm Flag, which could trigger an Alarm Interrupt if enabled.

The SET bit must be 1 while programming these locations to avoid clashes with an

update cycle. Access to time and date information is done through the RAM locations. If

a RAM read from the ten time and date bytes is attempted during an update cycle, the

value read do not necessarily represent the true contents of those locations. Any RAM

writes under the same conditions are ignored.

Note: The leap year determination for adding a 29th day to February does not take into

account the end-of-the-century exceptions. The logic simply assumes that all years

divisible by 4 are leap years. According to the Royal Observatory Greenwich, years that

are divisible by 100 are typically not leap years. In every fourth century (years divisible

by 400, like 2000), the 100-year-exception is over-ridden and a leap-year occurs. Note

that the year 2100 will be the first time in which the current RTC implementation would

incorrectly calculate the leap-year.

The PCH does not implement month/year alarms.

5.11.1 Update Cycles

An update cycle occurs once a second, if the SET bit of register B is not asserted and

the divide chain is properly configured. During this procedure, the stored time and date

are incremented, overflow is checked, a matching alarm condition is checked, and the

time and date are rewritten to the RAM locations. The update cycle will start at least

488 µs after the UIP bit of register A is asserted, and the entire cycle does not take

more than 1984 µs to complete. The time and date RAM locations (0–9) are

disconnected from the external bus during this time.

To avoid update and data corruption conditions, external RAM access to these locations

can safely occur at two times. When a updated-ended interrupt is detected, almost

999 ms is available to read and write the valid time and date data. If the UIP bit of

Warning: The overflow conditions for leap years adjustments are based on more than one date or

time item. To ensure proper operation when adjusting the time, the new time and data

values should be set at least two seconds before leap year occurs.

Datasheet 163

Functional Description

5.11.2 Interrupts

The real-time clock interrupt is internally routed within the PCH both to the I/O APIC

and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the PCH,

nor is it shared with any other interrupt. IRQ8# from the SERIRQ stream is ignored.

However, the High Performance Event Timers can also be mapped to IRQ8#; in this

case, the RTC interrupt is blocked.

5.11.3 Lockable RAM Ranges

The RTC battery-backed RAM supports two 8-byte ranges that can be locked using the

configuration space. If the locking bits are set, the corresponding range in the RAM will

not be readable or writable. A write cycle to those locations will have no effect. A read

cycle to those locations will not return the location’s actual value (resultant value is

undefined).

Once a range is locked, the range can be unlocked only by a hard reset, which will

invoke the BIOS and allow it to relock the RAM range.

5.11.4 Century Rollover

The PCH detects a rollover when the Year byte (RTC I/O space, index Offset 09h)

transitions form 99 to 00. Upon detecting the rollover, the PCH sets the

NEWCENTURY_STS bit (TCOBASE + 04h, Bit 7). If the system is in an S0 state, this

causes an SMI#. The SMI# handler can update registers in the RTC RAM that are

associated with century value. If the system is in a sleep state (S1–S5) when the

century rollover occurs, the PCH also sets the NEWCENTURY_STS bit, but no SMI# is

generated. When the system resumes from the sleep state, BIOS should check the

NEWCENTURY_STS bit and update the century value in the RTC RAM.

5.11.5 Clearing Battery-Backed RTC RAM

Clearing CMOS RAM in a PCH-based platform can be done by using a jumper on

RTCRST# or GPI. Implementations should not attempt to clear CMOS by using a

jumper to pull VccRTC low.

Using RTCRST# to Clear CMOS

A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default,

the state of those configuration bits that reside in the RTC power well. When the

RTCRST# is strapped to ground, the RTC_PWR_STS bit (D31:F0:A4h Bit 2) will be set

and those configuration bits in the RTC power well will be set to their default state.

BIOS can monitor the state of this Bit, and manually clear the RTC CMOS array once

the system is booted. The normal position would cause RTCRST# to be pulled up

through a weak pull-up resistor. Tab l e 5 -19 shows which bits are set to their default

state when RTCRST# is asserted. This RTCRST# jumper technique allows the jumper to

be moved and then replaced—all while the system is powered off. Then, once booted,

the RTC_PWR_STS can be detected in the set state.

Functional Description

164 Datasheet

Using a GPI to Clear CMOS

A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the

setting of this GPI on system boot-up, and manually clear the CMOS array.

Note: The GPI strap technique to clear CMOS requires multiple steps to implement. The

system is booted with the jumper in new position, then powered back down. The

jumper is replaced back to the normal position, then the system is rebooted again.

Warning: Do not implement a jumper on VccRTC to clear CMOS.

Table 5-19. Configuration Bits Reset by RTCRST# Assertion

Bit Name Register Location Bit(s) Default

State

Alarm Interrupt

Enable (AIE)

Configuration) (RTC_REGB)

I/O space (RTC Index

+ 0Bh) 5X

Alarm Flag (AF) Register C (Flag Register)

(RTC_REGC)

I/O space (RTC Index

+ 0Ch) 5X

SWSMI_RATE_SEL General PM Configuration 3

SLP_S4# Minimum

Assertion Width

General PM Configuration 3

SLP_S4# Assertion

Stretch Enable

General PM Configuration 3

RTC Power Status

(RTC_PWR_STS)

General PM Configuration 3

Power Failure

(PWR_FLR)

General PM Configuration 3

AFTERG3_EN General PM Configuration 3

Power Button

Override Status

(PRBTNOR_STS)

Power Management 1 Status

RTC Event Enable

(RTC_EN)

Power Management 1 Enable

Sleep Type

(SLP_TYP)

Power Management 1 Control

(PM1_CNT) PMBase + 04h 12:10 0

PME_EN General Purpose Event 0

Enables Register (GPE0_EN) PMBase + 2Ch 11 0

BATLOW_EN General Purpose Event 0

Enables Register (GPE0_EN) PMBase + 2Ch 10 0

RI_EN General Purpose Event 0

Enables Register (GPE0_EN) PMBase + 2Ch 8 0

NEWCENTURY_ST

TCO1 Status Register

(TCO1_STS) TCOBase + 04h 7 0

Intruder Detect

(INTRD_DET)

TCO2 Status Register

(TCO2_STS) TCOBase + 06h 0 0

Top Sw ap ( TS) Backed Up Control Register

(BUC)

Chipset Config

Registers:Offset 3414h 0X

Datasheet 165

Functional Description

5.12 Processor Interface (D31:F0)

The PCH interfaces to the processor with following pin-based signals other than DMI:

• Standard Outputs to processor: PROCPWRGD, PMSYNCH, PECI

• Standard Input from processor: THRMTRIP#

Most PCH outputs to the processor use standard buffers. The PCH has separate

V_PROC_IO signals that are pulled up at the system level to the processor voltage, and

thus determines VOH for the outputs to the processor.

The following processor interface legacy pins were removed from the PCH:

• IGNNE#, STPCLK#, DPSLP#, are DPRSLPVR are no longer required on PCH based

systems.

• A20M#, SMI#, NMI, INIT#, INTR, FERR#: Functionality has been replaced by in-

band Virtual Legacy Wire (VLW) messages. See Section 5.12.3.

5.12.1 Processor Interface Signals and VLW Messages

This section describes each of the signals that interface between the PCH and the

processor(s). Note that the behavior of some signals may vary during processor reset,

as the signals are used for frequency strapping.

5.12.1.1 A20M# (Mask A20) / A20GATE

The A20M# VLW message is asserted when both of the following conditions are true:

• The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a 0

• The A20GATE input signal is a 0

The A20GATE input signal is expected to be generated by the external microcontroller

(KBC).

Functional Description

166 Datasheet

5.12.1.2 INIT (Initialization)

The INIT# VLW Message is asserted based on any one of several events described in

Table 5 - 20. When any of these events occur, INIT# is asserted for 16 PCI clocks, then

driven high.

Note: INIT3_3V# is functionally identical to INIT# VLW but it is a physical signal at 3.3 V on

desktop SKUs only.

5.12.1.3 FERR# (Numeric Coprocessor Error)

The PCH supports the coprocessor error function with the FERR# message. The

function is enabled using the COPROC_ERR_EN bit. If FERR# is driven active by the

processor, IRQ13 goes active (internally). When it detects a write to the COPROC_ERR

active. IGNNE# remains active until FERR# is driven inactive. IGNNE# is never driven

active unless FERR# is active.

Note: IGNNE# (Ignore Numeric Error is now internally generated by the processor.

Table 5-20. INIT# Going Active

Cause of INIT3_3V# Going Active Comment

Shutdown special cycle from processor observed

on PCH-processor interconnect.

INIT assertion based on value of Shutdown

Policy Select register (SPS)

PORT92 write, where INIT_NOW (Bit 0) transitions

from a 0 to a 1.

PORTCF9 write, where SYS_RST (Bit 1) was a 0

and RST_CPU (Bit 2) transitions from 0 to 1.

RCIN# input signal goes low. RCIN# is expected

to be driven by the external microcontroller

(KBC).

0 to 1 transition on RCIN# must occur

before the PCH will arm INIT3_3V# to be

generated again.

NOTE: RCIN# signal is expected to be low

during S3, S4, and S5 states.

Transition on the RCIN# signal in

those states (or the transition to

those states) may not necessarily

cause the INIT3_3V# signal to be

generated to the processor.

Processor BIST

To enter BIST, software sets CPU_BIST_EN

bit and then does a full processor reset

using the CF9 register.

Datasheet 167

Functional Description

5.12.1.4 NMI (Non-Maskable Interrupt)

Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in

Ta b l e 5 - 2 1 .

5.12.1.5 Processor Power Good (PROCPWRGD)

This signal is connected to the processor’s UNCOREPWRGOOD input to indicate when

the processor power is valid.

5.12.2 Dual-Processor Issues

5.12.2.1 Usage Differences

In dual-processor designs, some of the processor signals are unused or used differently

than for uniprocessor designs.

• A20M#/A20GATE and FERR# are generally not used, but still supported.

• I/O APIC and SMI# are assumed to be used.

5.12.3 Virtual Legacy Wire (VLW) Messages

The PCH supports VLW messages as alternative method of conveying the status of the

following legacy sideband interface signals to the processor:

• A20M#, INTR, SMI#, INIT#, NMI

Note: IGNNE# VLW message is not required to be generated by the PCH as it is internally

emulated by the processor.

VLW are inbound messages to the processor. They are communicated using Vendor

Defined Message over the DMI link.

Legacy processor signals can only be delivered using VLW in the PCH. Delivery of

legacy processor signals (A20M#, INTR, SMI#, INIT# or NMI) using I/O APIC controller

is not supported.

Table 5-21. NMI Sources

Cause of NMI Comment

SERR# goes active (either internally,

externally using SERR# signal, or using

message from processor)

Can instead be routed to generate an SCI, through

the NMI2SCI_EN bit (Device 31:Function 0, TCO

Base + 08h, Bit 11).

IOCHK# goes active using SERIRQ#

stream (ISA system Error)

Can instead be routed to generate an SCI, through

the NMI2SCI_EN bit (Device 31:Function 0, TCO

Base + 08h, Bit 11).

SECSTS Register Device 31: Function F0

Offset 1Eh, bit 8.

This is enabled by the Parity Error Response Bit

(PER) at Device 30: Function 0 Offset 04, bit 6.

DEV_STS Register Device 31:Function F0

Offset 06h, bit 8

This is enabled by the Parity Error Response Bit

(PER) at Device 30: Function 0 Offset 04, bit 6.

GPIO[15:0] when configured as a General

Purpose input and routed as NMI (by

GPIO_ROUT at Device 31: Function 0

Offset B8)

This is enabled by GPI NMI Enable (GPI_NMI_EN)

bits at Device 31: Function 0 Offset: GPIOBASE +

28h bits 15:0

Functional Description

168 Datasheet

5.13 Power Management

5.13.1 Features

• Support for Advanced Configuration and Power Interface, Version 4.0a (ACPI)

providing power and thermal management

— ACPI 24-Bit Timer SCI and SMI# Generation

• PCI PME# signal for Wake Up from Low-Power states

• System Sleep State Control

— ACPI S3 state – Suspend to RAM (STR)

— ACPI S4 state – Suspend-to-Disk (STD)

— ACPI G2/S5 state – Soft Off (SOFF)

— Power Failure Detection and Recovery

— Deep S4/S5

•Intel

® Management Engine Power Management Support

— Wake events from the Intel Management Engine (enabled from all S-States

including Catastrophic S5 conditions)

5.13.2 PCH and System Power States

Table 5 - 22 shows the power states defined for PCH-based platforms. The state names

generally match the corresponding ACPI states.

Table 5-22. General Power States for Systems Using the PCH (Sheet 1 of 2)

State/

Substates Legacy Name / Description

G0/S0/C0 Full On: Processor operating. Individual devices may be shut down or be placed

into lower power states to save power.

G0/S0/Cx

Cx State: Cx states are processor power states within the S0 system state that

provide for various levels of power savings. The processor initiates C-state entry

and exit while interacting with the PCH. The PCH will base its behavior on the

processor state.

G1/S1 S1: The PCH provides the S1 messages and the S0 messages on a wake event.

It is preferred for systems to use C-states than S1.

G1/S3

Suspend-To-RAM (STR): The system context is maintained in system DRAM,

but power is shut off to non-critical circuits. Memory is retained and refreshes

continue. All external clocks stop except RTC.

G1/S4 Suspend-To-Disk (STD): The context of the system is maintained on the disk.

All power is then shut off to the system except for the logic required to resume.

G2/S5 Soft Off (SOFF): System context is not maintained. All power is shut off except

for the logic required to restart. A full boot is required when waking.

Deep S4/S5

Deep S4/S5: An optional low power state where system context may or may

not be maintained depending upon entry condition. All power is shut off except

for minimal logic that allows exiting Deep S4/S5. If Deep S4/S5 state was

entered from S4 state, then the resume path will place system back into S4. If

Deep S4/S5 state was entered from S5 state, then the resume path will place

system back into S5.

Datasheet 169

Functional Description

Ta b l e 5 - 2 3 shows the transitions rules among the various states. Note that transitions

among the various states may appear to temporarily transition through intermediate

states. For example, in going from S0 to S3, it may appear to pass through the G1/S1

states. These intermediate transitions and states are not listed in the table.

NOTES:

1. Some wake events can be preserved through power failure.

2. Transitions from the S1–S5 or G3 states to the S0 state are deferred until BATLOW# is

inactive in mobile configurations.

3. Includes all other applicable types of events that force the host into and stay in G2/S5.

4. If the system was in G1/S4 before G3 entry, then the system will go to S0/C0 or G1/S4.

Mechanical OFF (MOFF): System context not maintained. All power is shut off

except for the RTC. No “Wake” events are possible. This state occurs if the user

removes the main system batteries in a mobile system, turns off a mechanical

switch, or if the system power supply is at a level that is insufficient to power the

“waking” logic. When system power returns, transition will depend on the state

just prior to the entry to G3 and the AFTERG3_EN bit in the GEN_PMCON3

Table 5-22. General Power States for Systems Using the PCH (Sheet 2 of 2)

State/

Substates Legacy Name / Description

Table 5-23. State Transition Rules for the PCH

Present

State Transition Trigger Next State

G0/S0/C0

•DMI Msg

•SLP_EN bit set

• Power Button Override3

• Mechanical Off/Power Failure

•G0/S0/Cx

• G1/Sx or G2/S5 state

•G2/S5

•G3

G0/S0/Cx

•DMI Msg

• Power Button Override3

• Mechanical Off/Power Failure

•G0/S0/C0

•S5

•G3

G1/S1 or

G1/S3

•Any Enabled Wake Event

• Power Button Override3

• Mechanical Off/Power Failure

•G0/S0/C0

•G2/S5

•G3

G1/S4

• Any Enabled Wake Event • G0/S0/C02

• Power Button Override3•G2/S5

• Conditions met as described in

Section 5.13.7.6.1 and

Section 5.13.7.6.2

•Deep S4/S5

• Mechanical Off/Power Failure • G3

G2/S5

• Any Enabled Wake Event • G0/S0/C02

• Conditions met as described in

Section 5.13.7.6.1 and

Section 5.13.7.6.2

•Deep S4/S5

• Mechanical Off/Power Failure • G3

G2/Deep

S4/S5

•Any Enabled Wake Event

• ACPRESENT Assertion

• Mechanical Off/Power Failure

•G0/S0/C0

• G1/S4 or G2/S5 (see Section 5.13.7.6.2)

•G3

G3 • Power Returns

• S0/C0 (reboot) or G2/S54 (stay off until

power button pressed or other wake

event)1,2

Functional Description

170 Datasheet

5.13.3 System Power Planes

The system has several independent power planes, as described in Tabl e 5 -24. Note

that when a particular power plane is shut off, it should go to a 0 V level.

Table 5-24. System Power Plane

Plane Controlled By Description

Processor SLP_S3# signal The SLP_S3# signal can be used to cut the power to the

processor completely.

Main SLP_S3# signal

When SLP_S3# goes active, power can be shut off to any circuit

not required to wake the system from the S3 state. Since the S3

state requires that the memory context be preserved, power

must be retained to the main memory.

The processor, devices on the PCI bus, LPC I/F, and graphics will

typically be shut off when the Main power plane is off, although

there may be small subsections powered.

Memory SLP_S4# signal

SLP_S5# signal

When SLP_S4# goes active, power can be shut off to any circuit

not required to wake the system from the S4. Since the memory

context does not need to be preserved in the S4 state, the power

to the memory can also be shut down.

When SLP_S5# goes active, power can be shut off to any circuit

not required to wake the system from the S5 state. Since the

memory context does not need to be preserved in the S5 state,

the power to the memory can also be shut.

Intel® ME SLP_A#

This signal is asserted when the manageability platform goes to

MOff. Depending on the platform, this pin may be used to control

the Intel Management Engine power planes, LAN subsystem

power, and the SPI flash power.

LAN SLP_LAN#

This signal is asserted in Sx/Moff when both host and Intel ME

WOL are not supported. This signal can be use to control power

to the Intel GbE PHY.

Deep S4/

S5 Well SLP_SUS# This signal that the Sus rails externally can be shut off for

enhanced power saving.

DEVICE[n] Implementation

Specific

Individual subsystems may have their own power plane. For

example, GPIO signals may be used to control the power to disk

drives, audio amplifiers, or the display screen.

Datasheet 171

Functional Description

5.13.4 SMI#/SCI Generation

Upon any enabled SMI event taking place while the End of SMI (EOS) bit is set, the PCH

will clear the EOS bit and assert SMI to the processor, which will cause it to enter SMM

space. SMI assertion is performed using a Virtual Legacy Wire (VLW) message. Prior

system generations (those based upon legacy processors) used an actual SMI# pin.

Once the SMI VLW has been delivered, the PCH takes no action on behalf of active SMI

events until Host software sets the End of SMI (EOS) bit. At that point, if any SMI

events are still active, the PCH will send another SMI VLW message.

The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating

system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the

8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed

to level mode for that interrupt.

In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or

23. The interrupt polarity changes depending on whether it is on an interrupt shareable

with a PIRQ or not (see Section 13.1.13). The interrupt remains asserted until all SCI

sources are removed.

Ta b l e 5 - 2 5 shows which events can cause an SMI and SCI. Note that some events can

be programmed to cause either an SMI or SCI. The usage of the event for SCI (instead

of SMI) is typically associated with an ACPI-based system. Each SMI or SCI source has

a corresponding enable and status bit.

Table 5-25. Causes of SMI and SCI (Sheet 1 of 2)

Cause SCI SMI Additional Enables Where Reported

PME# Yes Yes PME_EN=1 PME_STS

PME_B0 (Internal, Bus 0, PME-

Capable Agents) Yes Yes PME_B0_EN=1 PME_B0_STS

PCI Express* PME Messages Yes Yes PCI_EXP_EN=1

(Not enabled for SMI) PCI_EXP_STS

PCI Express Hot Plug Message Yes Yes HOT_PLUG_EN=1

(Not enabled for SMI) HOT_PLUG_STS

Power Button Press Yes Yes PWRBTN_EN=1 PWRBTN_STS

Power Button Override (Note 7) Yes No None PRBTNOR_STS

RTC Alarm Yes Yes RTC_EN=1 RTC_STS

Ring Indicate Yes Yes RI_EN=1 RI_STS

ACPI Timer overflow (2.34 sec.) Yes Yes TMROF_EN=1 TMROF_STS

Any GPI[15:0] Yes Yes

GPI[x]_Route=10;

GPI[x]_EN=1

(SCI)

GPI[x]_Route=01;

ALT_GPI_SMI[x]_EN=1

(SMI)

GPI[x]_STS

ALT_GPI_SMI[x]_STS

GPIO[27] Yes Yes GP27_EN=1 GP27_STS

TCO SCI Logic Yes No TCOSCI_EN=1 TCOSCI_STS

TCO SCI message from processor Yes No none CPUSCI_STS

TCO SMI Logic No Yes TCO_EN=1 TCO_STS

TCO SMI –No Yes none NEWCENTURY_STS

TCO SMI – TCO TIMEROUT No Yes none TIMEOUT

TCO SMI – OS writes to TCO_DAT_IN

Functional Description

172 Datasheet

NOTES:

1. SCI_EN must be 1 to enable SCI, except for BIOS_RLS. SCI_EN must be 0 to enable SMI.

2. SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode).

3. GBL_SMI_EN must be 1 to enable SMI.

4. EOS must be written to 1 to re-enable SMI for the next 1.

5. The PCH must have SMI fully enabled when the PCH is also enabled to trap cycles. If SMI is not enabled in

conjunction with the trap enabling, then hardware behavior is undefined.

6. Only GPI[15:0] may generate an SMI or SCI.

7. When a power button override first occurs, the system will transition immediately to S5. The SCI will only

occur after the next wake to S0 if the residual status bit (PRBTNOR_STS) is not cleared prior to setting

SCI_EN.

8. GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set. Software must take great care not

to set the BIOS_RLS bit (which causes GBL_STS to be set) if the SCI handler is not in place.

TCO SMI – Message from processor No Yes none CPUSMI_STS

TCO SMI – NMI occurred (and NMIs

mapped to SMI) No Yes NMI2SMI_EN=1 NMI2SMI_STS

TCO SMI – INTRUDER# signal goes

active No Yes INTRD_SEL=10 INTRD_DET

TCO SMI – Change of the BIOSWE

(D31:F0:DCh, Bit 0) bit from 0 to 1 No Yes BLE=1 BIOSWR_STS

TCO SMI – Write attempted to BIOS No Yes BIOSWE=1 BIOSWR_STS

BIOS_RLS written to Yes No GBL_EN=1 GBL_STS

GBL_RLS written to No Yes BIOS_EN=1 BIOS_STS

Write to B2h register No Yes APMC_EN = 1 APM_STS

Periodic timer expires No Yes PERIODIC_EN=1 PERIODIC_STS

64 ms timer expires No Yes SWSMI_TMR_EN=1 SWSMI_TMR_STS

Enhanced USB Legacy Support Event No Yes LEGACY_USB2_EN = 1 LEGACY_USB2_STS

Enhanced USB Intel Specific Event No Yes INTEL_USB2_EN = 1 INTEL_USB2_STS

Serial IRQ SMI reported No Yes none SERIRQ_SMI_STS

Device monitors match address in its

range No Yes none DEVTRAP_STS

SMBus Host Controller No Yes SMB_SMI_EN

Host Controller Enabled SMBus host status reg.

SMBus Slave SMI message No Yes none SMBUS_SMI_STS

SMBus SMBALERT# signal active No Yes none SMBUS_SMI_STS

SMBus Host Notify message received No Yes HOST_NOTIFY_INTREN SMBUS_SMI_STS

HOST_NOTIFY_STS

(Mobile Only) BATLOW# assertion Yes Yes BATLOW_EN=1 BATLOW_STS

Access microcontroller 62h/66h No Yes MCSMI_EN MCSMI_STS

SLP_EN bit written to 1 No Yes SMI_ON_SLP_EN=1 SMI_ON_SLP_EN_STS

SPI Command Completed No Yes None SPI_SMI_STS

Software Generated GPE Yes Yes SWGPE=1 SWGPE_STS

USB Per-Port Registers Write Enable

bit changes to 1 No Yes USB2_EN=1,

Write_Enable_SMI_Enable=1

USB2_STS, Write Enable

Status

GPIO Lockdown Enable bit changes

from ‘1’ to ‘0’ No Yes GPIO_UNLOCK_SMI_EN=1 GPIO_UNLOCK_SMI_STS

Table 5-25. Causes of SMI and SCI (Sheet 2 of 2)

Cause SCI SMI Additional Enables Where Reported

Datasheet 173

Functional Description

5.13.4.1 PCI Express* SCI

PCI Express ports and the processor (using DMI) have the ability to cause PME using

messages. When a PME message is received, the PCH will set the PCI_EXP_STS bit. If

the PCI_EXP_EN bit is also set, the PCH can cause an SCI using the GPE1_STS register.

5.13.4.2 PCI Express* Hot-Plug

PCI Express has a Hot-Plug mechanism and is capable of generating a SCI using the

GPE1 register. It is also capable of generating an SMI. However, it is not capable of

generating a wake event.

5.13.5 C-States

PCH-based systems implement C-states by having the processor control the states. The

chipset exchanges messages with the processor as part of the C-state flow, but the

chipset does not directly control any of the processor impacts of C-states, such as

voltage levels or processor clocking. In addition to the new messages, the PCH also

provides additional information to the processor using a sideband pin (PMSYNCH). All of

the legacy C-state related pins (STPCLK#, STP_CPU#, DPRSLP#, DPRSLPVR#, etc.) do

not exist on the PCH.

5.13.6 Dynamic PCI Clock Control (Mobile Only)

The PCI clock can be dynamically controlled independent of any other low-power state.

This control is accomplished using the CLKRUN# protocol as described in the PCI Mobile

Design Guide, and is transparent to software.

The Dynamic PCI Clock control is handled using the following signals:

• CLKRUN#: Used by PCI and LPC peripherals to request the system PCI clock to run

• STP_PCI#: Used to stop the system PCI clock

Note: The 33-MHz clock to the PCH is “free-running” and is not affected by the STP_PCI#

signal.

Note: STP_PCI# is only used if PCI/LPC clocks are distributed from clock synthesizer rather

than PCH.

5.13.6.1 Conditions for Checking the PCI Clock

When there is a lack of PCI activity the PCH has the capability to stop the PCI clocks to

conserve power. “PCI activity” is defined as any activity that would require the PCI

clock to be running.

Any of the following conditions will indicate that it is not okay to stop the PCI clock:

•Cycles on PCI or LPC

• Cycles of any internal device that would need to go on the PCI bus

• SERIRQ activity

Behavioral Description

• When there is a lack of activity (as defined above) for 29 PCI clocks, the PCH

deasserts (drive high) CLKRUN# for 1 clock and then tri-states the signal.

Functional Description

174 Datasheet

5.13.6.2 Conditions for Maintaining the PCI Clock

PCI masters or LPC devices that wish to maintain the PCI clock running will observe the

CLKRUN# signal deasserted, and then must re-assert if (drive it low) within 3 clocks.

• When the PCH has tri-stated the CLKRUN# signal after deasserting it, the PCH then

checks to see if the signal has been re-asserted (externally).

• After observing the CLKRUN# signal asserted for 1 clock, the PCH again starts

asserting the signal.

• If an internal device needs the PCI bus, the PCH asserts the CLKRUN# signal.

5.13.6.3 Conditions for Stopping the PCI Clock

• If no device re-asserts CLKRUN# once it has been deasserted for at least 6 clocks,

the PCH stops the PCI clock by asserting the STP_PCI# signal to the clock

synthesizer.

• For case when PCH distribute PCI clock, PCH stop PCI clocks without the

involvement of STP_PCI#.

5.13.6.4 Conditions for Re-Starting the PCI Clock

• A peripheral asserts CLKRUN# to indicate that it needs the PCI clock re-started.

• When the PCH observes the CLKRUN# signal asserted for 1 (free running) clock,

the PCH deasserts the STP_PCI# signal to the clock synthesizer within 4 (free

running) clocks.

• Observing the CLKRUN# signal asserted externally for 1 (free running) clock, the

PCH again starts driving CLKRUN# asserted.

If an internal source requests the clock to be re-started, the PCH re-asserts CLKRUN#,

and simultaneously deasserts the STP_PCI# signal. For case when PCH distribute PCI

clock, PCH start PCI clocks without the involvement of STP_PCI#.

5.13.6.5 LPC Devices and CLKRUN#

If an LPC device (of any type) needs the 33 MHz PCI clock, such as for LPC DMA or LPC

serial interrupt, then it can assert CLKRUN#. Note that LPC devices running DMA or bus

master cycles will not need to assert CLKRUN#, since the PCH asserts it on their behalf.

The LDRQ# inputs are ignored by the PCH when the PCI clock is stopped to the LPC

devices in order to avoid misinterpreting the request. The PCH assumes that only one

more rising PCI clock edge occurs at the LPC device after the assertion of STP_PCI#.

Upon deassertion of STP_PCI#, the PCH assumes that the LPC device receives its first

clock rising edge corresponding to the PCH’s second PCI clock rising edge after the

deassertion.

5.13.7 Sleep States

5.13.7.1 Sleep State Overview

The PCH directly supports different sleep states (S1–S5), which are entered by

methods such as setting the SLP_EN bit or due to a Power Button press. The entry to

the Sleep states is based on several assumptions:

• The G3 state cannot be entered using any software mechanism. The G3 state

indicates a complete loss of power.

Datasheet 175

Functional Description

5.13.7.2 Initiating Sleep State

Sleep states (S1–S5) are initiated by:

• Masking interrupts, turning off all bus master enable bits, setting the desired type

in the SLP_TYP field, and then setting the SLP_EN bit. The hardware then attempts

to gracefully put the system into the corresponding Sleep state.

• Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button

Override event. In this case the transition to the S5 state is less graceful, since

there are no dependencies on DMI messages from the processor or on clocks other

than the RTC clock.

• Assertion of the THRMTRIP# signal will cause a transition to the S5 state. This can

occur when system is in S0 or S1 state.

• Shutdown by integrated manageability functions (ASF/Intel AMT)

• Internal watchdog timer time-out events

5.13.7.3 Exiting Sleep States

Sleep states (S1–S5) are exited based on Wake events. The Wake events forces the

system to a full on state (S0), although some non-critical subsystems might still be

shut off and have to be brought back manually. For example, the hard disk may be shut

off during a sleep state and have to be enabled using a GPIO pin before it can be used.

Upon exit from the PCH-controlled Sleep states, the WAK_STS bit is set. The possible

causes of Wake Events (and their restrictions) are shown in Tabl e 5 -27.

Note: (Mobile Only) If the BATLOW# signal is asserted, the PCH does not attempt to wake

from an S1–S5 state, even if the power button is pressed. This prevents the system

from waking when the battery power is insufficient to wake the system. Wake events

that occur while BATLOW# is asserted are latched by the PCH, and the system wakes

after BATLOW# is deasserted.

Table 5-26. Sleep Types

Sleep Type Comment

S1 System lowers the processor’s power consumption. No snooping is possible in this

state.

The PCH asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical

circuits. Power is only retained to devices needed to wake from this sleeping

state, as well as to the memory.

The PCH asserts SLP_S3# and SLP_S4#. The SLP_S4# signal shuts off the power

to the memory subsystem. Only devices needed to wake from this state should be

powered.

S5 The PCH asserts SLP_S3#, SLP_S4# and SLP_S5#.

Functional Description

176 Datasheet

Table 5-27. Causes of Wake Events (Sheet 1 of 2)

Cause How Enabled Wake from

S1, Sx

Wake from

Deep S4/S5

Wake from

S1, Sx After

Power Loss

(Note 1)

Wake from

“Reset”

Types

(Note 2)

RTC Alarm Set RTC_EN bit in PM1_EN

Power Button Always enabled as Wake

event. YY YY

GPI[15:0]

GPE0_EN register

NOTE: GPIs that are in the

core well are not

capable of waking the

system from sleep

states when the core

well is not powered.

GPIO27 Set GP27_EN in GPE0_EN

LAN Will use PME#. Wake enable

set with LAN logic. YY

RI# Set RI_EN bit in GPE0_EN

Intel® High

Definition Audio

Event sets PME_B0_STS bit;

PM_B0_EN must be enabled.

Can not wake from S5 state if

it was entered due to power

failure or power button

override.

Primary PME# PME_B0_EN bit in GPE0_EN

Secondary PME# Set PME_EN bit in GPE0_EN

PCI_EXP_WAKE# PCI_EXP_WAKE bit. (Note 3) Y Y

SATA Set PME_EN bit in GPE0_EN

PCI_EXP PME

Message

Must use the PCI Express*

WAKE# pin rather than

messages for wake from S3,

S4, or S5.

S1 S1

SMBALERT# Always enabled as Wake

event. YYY

SMBus Slave

Wake Message

(01h)

Wake/SMI# command always

enabled as a Wake event.

NOTE: SMBus Slave Message

can wake the system

from S1–S5, as well as

from S5 due to Power

Button Override.

YYY

Datasheet 177

Functional Description

NOTES:

1. This column represents what the PCH would honor as wake events but there may be

enabling dependencies on the device side which are not enabled after a power loss.

2. Reset Types include: Power Button override, Intel ME initiated power button override, Intel

ME initiated host partition reset with power down, Intel ME Watchdog Timer, SMBus

unconditional power down, processor thermal trip, PCH catastrophic temperature event.

3. When the WAKE# pin is active and the PCI Express device is enabled to wake the system,

the PCH will wake the platform.

4. SATA can only trigger a wake event in S1, but if PME is asserted prior to S3/S4/S5 entry

and software does not clear the PME_B0_STS, a wake event would still result.

It is important to understand that the various GPIs have different levels of functionality

when used as wake events. The GPIs that reside in the core power well can only

generate wake events from sleep states where the core well is powered. Also, only

certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits reside in

ACPI I/O space. Tabl e 5 - 28 summarizes the use of GPIs as wake events.

The latency to exit the various Sleep states varies greatly and is heavily dependent on

power supply design, so much so that the exit latencies due to the PCH are

insignificant.

5.13.7.4 PCI Express* WAKE# Signal and PME Event Message

PCI Express ports can wake the platform from any sleep state (S1, S3, S4, or S5) using

the WAKE# pin. WAKE# is treated as a wake event, but does not cause any bits to go

active in the GPE_STS register.

PCI Express ports and the processor (using DMI) have the ability to cause PME using

messages. When a PME message is received, the PCH will set the PCI_EXP_STS bit.

SMBus Host

Notify message

received

HOST_NOTIFY_WKEN bit

SMBus Slave Command

SMB_WAK_STS bit in the

GPEO_STS register.

YYY

Intel® ME Non-

Maskable Wake

Always enabled as a wake

event. YYY

Integrated WOL

Enable Override

WOL Enable Override bit (in

Configuration Space). Y Y Y

Table 5-27. Causes of Wake Events (Sheet 2 of 2)

Cause How Enabled Wake from

S1, Sx

Wake from

Deep S4/S5

Wake from

S1, Sx After

Power Loss

(Note 1)

Wake from

“Reset”

Types

(Note 2)

Table 5-28. GPI Wake Events

GPI Power Well Wake From Notes

GPI[7:0] Core S1 ACPI

Compliant

GPI[15:8] Suspend S1–S5 ACPI

Compliant

Functional Description

178 Datasheet

5.13.7.5 Sx-G3-Sx, Handling Power Failures

Depending on when the power failure occurs and how the system is designed, different

transitions could occur due to a power failure.

The AFTERG3_EN bit provides the ability to program whether or not the system should

boot once power returns after a power loss event. If the policy is to not boot, the

system remains in an S5 state (unless previously in S4). There are only three possible

events that will wake the system after a power failure.

1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low

(G3 state), the PWRBTN_STS bit is reset. When the PCH exits G3 after power

returns (RSMRST# goes high), the PWRBTN# signal is already high (because VCC-

standby goes high before RSMRST# goes high) and the PWRBTN_STS bit is 0.

2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a

wake event, it is important to keep this signal powered during the power loss

event. If this signal goes low (active), when power returns the RI_STS bit is set and

the system interprets that as a wake event.

3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss.

Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.

The PCH monitors both PCH PWROK and RSMRST# to detect for power failures. If PCH

PWROK goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set.

Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power

loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#.

NOTE:

1. Entry state to Deep S4/S5 is preserved through G3 allowing resume from Deep S4/S5 to

take appropriate path (that is, return to S4 or S5).

Table 5-29. Transitions Due to Power Failure

State at Power Failure AFTERG3_EN bit Transition When Power Returns

S0, S1, S3 1

S4 1

S5 1

Deep S4/S5 1

Deep S4/S51

Datasheet 179

Functional Description

5.13.7.6 Deep S4/S5

To minimize power consumption while in S4/S5, the PCH supports a lower power, lower

featured version of these power states known as Deep S4/S5. In the Deep S4/S5 state,

the Suspend wells are powered off, while the Deep S4/S5 Well (DSW) remains

powered. A limited set of wake events are supported by the logic located in the DSW.

The Deep S4/S5 capability and the SUSPWRDNACK pin functionality are mutually

exclusive.

5.13.7.6.1 Entry Into Deep S4/S5

A combination of conditions is required for entry into Deep S4/S5.

All of the following must be met:

• Intel ME in Moff

• AND either a or b as defined below:

a. ((DPS4_EN_AC AND S4) OR (DPS5_EN_AC AND S5)) (desktop only)

b. ((AC_PRESENT = 0) AND ((DPS4_EN_DC AND S4) OR (DPS5_EN_DC AND S5)))

The PCH also performs a SUSWARN#/SUSACK# handshake to ensure the platform is

ready to enter Deep S4/S5. The PCH asserts SUSWARN# as notification that it is about

to enter Deep S4/S5. Before the PCH proceeds and asserts SLP_SUS#, the PCH waits

for SUSACK# to assert.

5.13.7.6.2 Exit from Deep S4/S5

While in Deep S4/S5, the PCH monitors and responds to a limited set of wake events

(RTC Alarm, Power Button, and GPIO27). Upon sensing an enabled Deep S4/S5 wake

event, the PCH brings up the Suspend well by deasserting SLP_SUS#.

Table 5-30. Supported Deep S4/S5 Policy Configurations

Configuration DPS4_EN_DC DPS4_EN_AC DPS5_EN_DC DPS5_EN_AC

1: Enabled in S5 when on

Battery (ACPRESENT = 0) 0010

2: Enabled in S5 (ACPRESENT

not considered) (desktop only) 0011

3: Enabled in S4 and S5 when

on Battery (ACPRESENT = 0) 1010

4: Enabled in S4 and S5

(ACPRESENT not

considered) (desktop only 1111

5: Deep S4 / S5 disabled 0000

Table 5-31. Deep S4/S5 Wake Events

Event Enable

RTC Alarm RTC_DS_WAKE_DIS (RCBA+3318h:Bit 21)

Power Button Always enabled

GPIO27 GPIO27_EN (PMBASE+28h:Bit 35)

Functional Description

180 Datasheet

Note that ACPRESENT has some behaviors that are different from the other Deep S4/

S5 wake events. If the Intel ME has enabled ACPRESENT as a wake event then it

behaves just like any other Intel ME Deep S4/S5 wake event. However, even if

ACPRESENT wakes are not enabled, if the Host policies indicate that Deep S4/S5 is only

supported when on battery, then ACPRESENT going high will cause the PCH to exit

Deep S4/S5. In this case, the Suspend wells gets powered up and the platform remains

in S4/MOFF or S5/MOFF. If ACPRESENT subsequently drops (before any Host or Intel

ME wake events are detected), the PCH will re-enter Deep S4/S5.

5.13.8 Event Input Signals and Their Usage

The PCH has various input signals that trigger specific events. This section describes

those signals and how they should be used.

5.13.8.1 PWRBTN# (Power Button)

The PCH PWRBTN# signal operates as a “Fixed Power Button” as described in the

Advanced Configuration and Power Interface, Version 2.0b. PWRBTN# signal has a

16 ms de-bounce on the input. The state transition descriptions are included in

Table 5 - 32. Note that the transitions start as soon as the PWRBTN# is pressed (but

after the debounce logic), and does not depend on when the Power Button is released.

Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width

(if enabled), the Power Button is not a wake event. Refer to the following Power Button

Override Function section for further details.

Power Button Override Function

If PWRBTN# is observed active for at least four consecutive seconds, the state machine

should unconditionally transition to the G2/S5 state, regardless of present state (S0–

S4), even if the PCH PWROK is not active. In this case, the transition to the G2/S5 state

should not depend on any particular response from the processor (such as, a DMI

Messages), nor any similar dependency from any other subsystem.

The PWRBTN# status is readable to check if the button is currently being pressed or

has been released. The status is taken after the de-bounce, and is readable using the

PWRBTN_LVL bit.

Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has

occurred. The 4-second timer starts counting when the PCH is in a S0 state. If the

PWRBTN# signal is asserted and held active when the system is in a suspend state

Table 5-32. Transitions Due to Power Button

Present

State Event Transition/Action Comment

S0/Cx PWRBTN# goes low

SMI or SCI generated

(depending on SCI_EN,

PWRBTN_EN and

GLB_SMI_EN)

Software typically initiates a

Sleep state

S1–S5 PWRBTN# goes low Wake Event. Transitions to

S0 state Standard wakeup

G3 PWRBTN# pressed None No effect since no power

Not latched nor detected

S0–S4

PWRBTN# held low

for at least 4

consecutive seconds

Unconditional transition to

S5 state

No dependence on processor

(DMI Messages) or any other

subsystem

Datasheet 181

Functional Description

(S1–S5), the assertion causes a wake event. Once the system has resumed to the S0

state, the 4-second timer starts.

Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width

(if enabled by D31:F0:A4h Bit 3), the Power Button is not a wake event. As a result, it

is conceivable that the user will press and continue to hold the Power Button waiting for

the system to awake. Since a 4-second press of the Power Button is already defined as

an Unconditional Power down, the power button timer will be forced to inactive while

the power-cycle timer is in progress. Once the power-cycle timer has expired, the

Power Button awakes the system. Once the minimum SLP_S4# power cycle expires,

the Power Button must be pressed for another 4 to 5 seconds to create the Override

condition to S5.

Sleep Button

The Advanced Configuration and Power Interface, Version 2.0b defines an optional

Sleep button. It differs from the power button in that it only is a request to go from S0

to S1–S4 (not S5). Also, in an S5 state, the Power Button can wake the system, but the

Sleep Button cannot.

Although the PCH does not include a specific signal designated as a Sleep Button, one

of the GPIO signals can be used to create a “Control Method” Sleep Button. See the

Advanced Configuration and Power Interface, Version 2.0b for implementation details.

5.13.8.2 RI# (Ring Indicator)

The Ring Indicator can cause a wake event (if enabled) from the S1–S5 states.

Ta b l e 5 - 3 3 shows when the wake event is generated or ignored in different states. If in

the G0/S0/Cx states, the PCH generates an interrupt based on RI# active, and the

interrupt will be set up as a Break event.

Note: Filtering/Debounce on RI# will not be done in PCH. Can be in modem or external.

5.13.8.3 PME# (PCI Power Management Event)

The PME# signal comes from a PCI device to request that the system be restarted. The

PME# signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs

when the PME# signal goes from high to low. No event is caused when it goes from low

to high.

There is also an internal PME_B0 bit. This is separate from the external PME# signal

and can cause the same effect.

Table 5-33. Transitions Due to RI# Signal

Present State Event RI_EN Event

S0 RI# Active X Ignored

S1–S5 RI# Active 0

Ignored

Wake Event

Functional Description

182 Datasheet

5.13.8.4 SYS_RESET# Signal

When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, the

PCH attempts to perform a “graceful” reset, by waiting up to 25 ms for the SMBus to go

idle. If the SMBus is idle when the pin is detected active, the reset occurs immediately;

otherwise, the counter starts. If at any point during the count the SMBus goes idle the

reset occurs. If, however, the counter expires and the SMBus is still active, a reset is

forced upon the system even though activity is still occurring.

Once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the

SYS_RESET# input remains asserted or not. It cannot occur again until SYS_RESET#

has been detected inactive after the debounce logic, and the system is back to a full S0

state with PLTRST# inactive. Note that if bit 3 of the CF9h I/O register is set then

SYS_RESET# will result in a full power cycle reset.

5.13.8.5 THRMTRIP# Signal

If THRMTRIP# goes active, the processor is indicating an overheat condition, and the

PCH immediately transitions to an S5 state, driving SLP_S3#, SLP_S4#, SLP_S5# low,

and setting the CTS bit. The transition looks like a power button override.

When a THRMTRIP# event occurs, the PCH will power down immediately without

following the normal S0 -> S5 path. The PCH will immediately drive SLP_S3#,

SLP_S4#, and SLP_S5# low after sampling THRMTRIP# active.

If the processor is running extremely hot and is heating up, it is possible (although very

unlikely) that components around it, such as the PCH, are no longer executing cycles

properly. Therefore, if THRMTRIP# goes active, and the PCH is relying on state machine

logic to perform the power down, the state machine may not be working, and the

system will not power down.

The PCH provides filtering for short low glitches on the THRMTRIP# signal in order to

prevent erroneous system shut downs from noise. Glitches shorter than 25nsec are

ignored.

During boot, THRMTRIP# is ignored until SLP_S3#, PWROK, and PLTRST# are all ‘1’.

During entry into a powered-down state (due to S3, S4, S5 entry, power cycle reset,

etc.) THRMTRIP# is ignored until either SLP_S3# = 0, or PCH PWROK = 0, or

SYS_PWROK = 0.

Note: A thermal trip event will:

• Clear the PWRBTN_STS bit

• Clear all the GPE0_EN register bits

• Clear the SMB_WAK_STS bit only if SMB_SAK_STS was set due to SMBus slave

receiving message and not set due to SMBAlert

Datasheet 183

Functional Description

5.13.9 ALT Access Mode

Before entering a low power state, several registers from powered down parts may

need to be saved. In the majority of cases, this is not an issue, as registers have read

and write paths. However, several of the ISA compatible registers are either read only

or write only. To get data out of write-only registers, and to restore data into read-only

registers, the PCH implements an ALT access mode.

If the ALT access mode is entered and exited after reading the registers of the PCH

timer (8254), the timer starts counting faster (13.5 ms). The following steps listed

below can cause problems:

1. BIOS enters ALT access mode for reading the PCH timer related registers.

2. BIOS exits ALT access mode.

3. BIOS continues through the execution of other needed steps and passes control to

the operating system.

After getting control in step #3, if the operating system does not reprogram the system

timer again, the timer ticks may be happening faster than expected. For example

Microsoft MS-DOS* and its associated software assume that the system timer is

running at 54.6 ms and as a result the time-outs in the software may be happening

faster than expected.

Operating systems (such as Microsoft Windows* 98 and Windows* 2000) reprogram

the system timer and therefore do not encounter this problem.

For other operating systems (such as Microsoft MS-DOS*) the BIOS should restore the

timer back to 54.6 ms before passing control to the operating system. If the BIOS is

entering ALT access mode before entering the suspend state it is not necessary to

restore the timer contents after the exit from ALT access mode.

Functional Description

184 Datasheet

5.13.9.1 Write Only Registers with Read Paths in ALT Access Mode

The registers described in Tabl e 5 -34 have read paths in ALT access mode. The access

number field in the table indicates which register will be returned per access to that

port.

Table 5-34. Write Only Registers with Read Paths in ALT Access Mode (Sheet 1 of 2)

Restore Data Restore Data

I/O

Addr

# of

Rds Access Data I/O

Addr

# of

Rds Access Data

00h 2

1DMA Chan 0 base address

low byte

40h 7

1Timer Counter 0 status, bits

[5:0]

2DMA Chan 0 base address

high byte 2Timer Counter 0 base count

low byte

01h 2

1DMA Chan 0 base count low

byte 3Timer Counter 0 base count

high byte

2DMA Chan 0 base count high

byte 4Timer Counter 1 base count

low byte

02h 2

1DMA Chan 1 base address

low byte 5Timer Counter 1 base count

high byte

2DMA Chan 1 base address

high byte 6Timer Counter 2 base count

low byte

03h 2

1DMA Chan 1 base count low

byte 7Timer Counter 2 base count

high byte

2DMA Chan 1 base count high

byte 41h 1 Timer Counter 1 status, bits

[5:0]

04h 2

1DMA Chan 2 base address

low byte 42h 1 Timer Counter 2 status, bits

[5:0]

2DMA Chan 2 base address

high byte 70h 1 Bit 7 = NMI Enable,

Bits [6:0] = RTC Address

05h 2

1DMA Chan 2 base count low

byte C4h 2

1DMA Chan 5 base address

low byte

2DMA Chan 2 base count high

byte 2DMA Chan 5 base address

high byte

06h 2

1DMA Chan 3 base address

low byte C6h 2

1DMA Chan 5 base count low

byte

2DMA Chan 3 base address

high byte 2DMA Chan 5 base count

high byte

07h 2

1DMA Chan 3 base count low

byte C8h 2

1DMA Chan 6 base address

low byte

2DMA Chan 3 base count high

byte 2DMA Chan 6 base address

high byte

Datasheet 185

Functional Description

NOTES:

1. The OCW1 register must be read before entering ALT access mode.

2. Bits 5, 3, 1, and 0 return 0.

08h 6

1 DMA Chan 0–3 Command2

CAh 2

1DMA Chan 6 base count low

byte

2 DMA Chan 0–3 Request 2 DMA Chan 6 base count

high byte

3DMA Chan 0 Mode:

Bits(1:0) = 00 CCh 2

1DMA Chan 7 base address

low byte

4DMA Chan 1 Mode:

Bits(1:0) = 01 2DMA Chan 7 base address

high byte

5DMA Chan 2 Mode:

Bits(1:0) = 10 CEh 2

1DMA Chan 7 base count low

byte

6DMA Chan 3 Mode: Bits(1:0)

= 11. 2DMA Chan 7 base count

high byte

20h 12

1 PIC ICW2 of Master controller

D0h 6

1 DMA Chan 4–7 Command2

2 PIC ICW3 of Master controller 2 DMA Chan 4–7 Request

3 PIC ICW4 of Master controller 3 DMA Chan 4 Mode:

Bits(1:0) = 00

4PIC OCW1 of Master

controller14DMA Chan 5 Mode:

Bits(1:0) = 01

5PIC OCW2 of Master

controller 5DMA Chan 6 Mode:

Bits(1:0) = 10

6PIC OCW3 of Master

controller 6DMA Chan 7 Mode:

Bits(1:0) = 11.

7 PIC ICW2 of Slave controller

8 PIC ICW3 of Slave controller

9 PIC ICW4 of Slave controller

10 PIC OCW1 of Slave

controller1

11 PIC OCW2 of Slave controller

12 PIC OCW3 of Slave controller

Table 5-34. Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of 2)

Restore Data Restore Data

I/O

Addr

# of

Rds Access Data I/O

Addr

# of

Rds Access Data

Functional Description

186 Datasheet

5.13.9.2 PIC Reserved Bits

Many bits within the PIC are reserved, and must have certain values written in order for

the PIC to operate properly. Therefore, there is no need to return these values in ALT

access mode. When reading PIC registers from 20h and A0h, the reserved bits shall

return the values listed in Tab le 5-35 .

5.13.9.3 Read Only Registers with Write Paths in ALT Access Mode

The registers described in Tabl e 5 -36 have write paths to them in ALT access mode.

Software restores these values after returning from a powered down state. These

registers must be handled special by software. When in normal mode, writing to the

base address/count register also writes to the current address/count register.

Therefore, the base address/count must be written first, then the part is put into ALT

access mode and the current address/count register is written.

Table 5-35. PIC Reserved Bits Return Values

PIC Reserved Bits Value Returned

ICW2(2:0) 000

ICW4(7:5) 000

ICW4(3:2) 00

ICW4(0) 0

OCW2(4:3) 00

OCW3(7) 0

OCW3(5) Reflects bit 6

OCW3(4:3) 01

Table 5-36. Register Write Accesses in ALT Access Mode

I/O Address Register Write Value

08h DMA Status Register for Channels 0–3

D0h DMA Status Register for Channels 4–7

Datasheet 187

Functional Description

5.13.10 System Power Supplies, Planes, and Signals

5.13.10.1 Power Plane Control with SLP_S3#,

SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN#

The SLP_S3# output signal can be used to cut power to the system core supply, since it

only goes active for the Suspend-to-RAM state (typically mapped to ACPI S3). Power

must be maintained to the PCH suspend well, and to any other circuits that need to

generate Wake signals from the Suspend-to-RAM state. During S3 (Suspend-to-RAM)

all signals attached to powered down plans will be tri-stated or driven low, unless they

are pulled using a pull-up resistor.

Cutting power to the core may be done using the power supply, or by external FETs on

the motherboard.

The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core

supply, as well as power to the system memory, since the context of the system is

saved on the disk. Cutting power to the memory may be done using the power supply,

or by external FETs on the motherboard.

The SLP_S4# output signal is used to remove power to additional subsystems that are

powered during SLP_S3#.

SLP_S5# output signal can be used to cut power to the system core supply, as well as

power to the system memory, since the context of the system is saved on the disk.

Cutting power to the memory may be done using the power supply, or by external FETs

on the motherboard.

SLP_A# output signal can be used to cut power to the Intel Management Engine and

SPI flash on a platform that supports the M3 state (for example, certain power policies

in Intel AMT).

SLP_LAN# output signal can be used to cut power to the external Intel 82579 GbE PHY

device.

5.13.10.2 SLP_S4# and Suspend-To-RAM Sequencing

The system memory suspend voltage regulator is controlled by the Glue logic. The

SLP_S4# signal should be used to remove power to system memory rather than the

SLP_S5# signal. The SLP_S4# logic in the PCH provides a mechanism to fully cycle the

power to the DRAM and/or detect if the power is not cycled for a minimum time.

Note: To use the minimum DRAM power-down feature that is enabled by the SLP_S4#

Assertion Stretch Enable bit (D31:F0:A4h Bit 3), the DRAM power must be controlled

by the SLP_S4# signal.

5.13.10.3 PWROK Signal

When asserted, PWROK is an indication to the PCH that its core well power rails are

powered and stable. PWROK can be driven asynchronously. When PCH PWROK is low,

the PCH asynchronously asserts PLTRST#. PWROK must not glitch, even if RSMRST# is

low.

It is required that the power associated with PCI/PCIe have been valid for 99 ms prior

to PWROK assertion in order to comply with the 100 ms PCI 2.3 / PCIe 2.0 specification

on PLTRST# deassertion.

Note: SYS_RESET# is recommended for implementing the system reset button. This saves

external logic that is needed if the PWROK input is used. Additionally, it allows for

Functional Description

188 Datasheet

better handling of the SMBus and processor resets and avoids improperly reporting

power failures.

5.13.10.4 BATLOW# (Battery Low) (Mobile Only)

The BATLOW# input can inhibit waking from S3, S4, and S5 states if there is not

sufficient power. It also causes an SMI if the system is already in an S0 state.

5.13.10.5 SLP_LAN# Pin Behavior

Table 5 - 37 summarizes SLP_LAN# pin behavior.

5.13.10.6 RTCRST# and SRTCRST#

The basic behavior of the SRTCRST# and RTCRST# signals can be summarized by the

following:

1. RTC coin cell removal: both SRTCRST# and RTCRST# assert and reset logic

2. Clear CMOS board capability: only RTCRST# asserts

It is imperative that SRTCRST# is only asserted when RTCRST# is also asserted. A

jumper on the SRTCRST# signal should not be implemented.

5.13.11 Clock Generators

The clock generator is expected to provide the frequencies shown in Ta b l e 4 - 1 .

Table 5-37. SLP_LAN# Pin Behavior

Functionality

(Determined

by soft strap)

SLP_LAN

Default Value

Bit

GPIO29 Input /

Output

(Determined by

GP_IO_SEL bit)

Pin Value In S0

or M3

Value in S3-S5/

Moff

SLP_LAN#

0 (Default)

In (Default) 1 0

Out 1

Depends on

GPIO29 output

data value

In (Default) 1 1

Out 1

Depends on

GPIO29 output

data value

GPIO29

0 (Default) In Z (tri-state) 0

1 In Z (tri-state) 1

N/A Out

Depends on

GPIO29 output

data value

Depends on

GPIO29 output

data value

Datasheet 189

Functional Description

5.13.12 Legacy Power Management Theory of Operation

Instead of relying on ACPI software, legacy power management uses BIOS and various

hardware mechanisms. The scheme relies on the concept of detecting when individual

subsystems are idle, detecting when the whole system is idle, and detecting when

accesses are attempted to idle subsystems.

However, the operating system is assumed to be at least APM enabled. Without APM

calls, there is no quick way to know when the system is idle between keystrokes. The

PCH does not support burst modes.

5.13.12.1 APM Power Management (Desktop Only)

The PCH has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and

Enable register, generates an SMI once per minute. The SMI handler can check for

system activity by reading the DEVTRAP_STS register. If none of the system bits are

set, the SMI handler can increment a software counter. When the counter reaches a

sufficient number of consecutive minutes with no activity, the SMI handler can then put

the system into a lower power state.

If there is activity, various bits in the DEVTRAP_STS register will be set. Software clears

the bits by writing a 1 to the bit position.

The DEVTRAP_STS register allows for monitoring various internal devices, or Super I/O

devices (SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions

on LPC or PCI. Other PCI activity can be monitored by checking the PCI interrupts.

5.13.12.2 Mobile APM Power Management (Mobile Only)

In mobile systems, there are additional requirements associated with device power

management. To handle this, the PCH has specific SMI traps available. The following

algorithm is used:

1. The periodic SMI timer checks if a device is idle for the require time. If so, it puts

the device into a low-power state and sets the associated SMI trap.

2. When software (not the SMI handler) attempts to access the device, a trap occurs

(the cycle doesn’t really go to the device and an SMI is generated).

3. The SMI handler turns on the device and turns off the trap.

4. The SMI handler exits with an I/O restart. This allows the original software to

continue.

5.13.13 Reset Behavior

When a reset is triggered, the PCH will send a warning message to the processor to

allow the processor to attempt to complete any outstanding memory cycles and put

memory into a safe state before the platform is reset. When the processor is ready, it

will send an acknowledge message to the PCH. Once the message is received the PCH

asserts PLTRST#.

The PCH does not require an acknowledge message from the processor to trigger

PLTRST#. A global reset will occur after 4 seconds if an acknowledge from the

processor is not received.

When the PCH causes a reset by asserting PLTRST# its output signals will go to their

reset states as defined in Chapter 3.

Functional Description

190 Datasheet

A reset in which the host platform is reset and PLTRST# is asserted is called a Host

Reset or Host Partition Reset. Depending on the trigger a host reset may also result in

power cycling see Ta b l e 5 - 3 8 for details. If a host reset is triggered and the PCH times

out before receiving an acknowledge message from the processor a Global Reset with

power cycle will occur.

A reset in which the host and Intel ME partitions of the platform are reset is called a

Global Reset. During a Global Reset, all PCH functionality is reset except RTC Power

Well backed information and Suspend well status, configuration, and functional logic for

controlling and reporting the reset. Intel ME and Host power back up after the power

cycle period.

Straight to S5 is another reset type where all power wells that are controlled by the

SLP_S3#, SLP_S4#, and SLP_A# pins, as well as SLP_S5# and SLP_LAN# (if pins are

not configured as GPIOs), are turned off. All PCH functionality is reset except RTC

Power Well backed information and Suspend well status, configuration, and functional

logic for controlling and reporting the reset. The host stays there until a valid wake

event occurs.

Table 5 - 38 shows the various reset triggers.

Table 5-38. Causes of Host and Global Resets (Sheet 1 of 2)

Trigger

Host Reset

without

Power Cycle1

Host Reset

with Power

Cycle2

Global Reset

with Power

Cycle3

Straight to S5

(Host Stays

there)

Write of 0Eh to CF9h (RST_CNT Register) No Yes No (Note 4)

Write of 06h to CF9h (RST_CNT Register) Yes No No (Note 4)

SYS_RESET# Asserted and CF9h (RST_CNT

SMBus Slave Message received for Reset with

Power Cycle No Yes No (Note 4)

SMBus Slave Message received for Reset without

Power Cycle Yes No No (Note 4)

SMBus Slave Message received for unconditional

Power Down No No No Yes

TCO Watchdog Timer reaches zero two times Yes No No (Note 4)

Power Failure: PWROK signal goes inactive in

S0/S1 or DPWROK drops No No Yes

SYS_PWROK Failure: SYS_PWROK signal goes

inactive in S0/S1 No No Yes

Processor Thermal Trip (THRMTRIP#) causes

transition to S5 and reset asserts No No No Yes

PCH internal thermal sensors signals a

catastrophic temperature condition No No No Yes

Power Button 4 second override causes

transition to S5 and reset asserts No No No Yes

Special shutdown cycle from processor causes

CF9h-like PLTRST# and CF9h (RST_CNT

No Yes No (Note 4)

Special shutdown cycle from processor causes

CF9h-like PLTRST# and CF9h (RST_CNT

Yes No No (Note 4)

Intel® Management Engine Triggered Host Reset

without power cycle Yes No No (Note 4)

Intel Management Engine Triggered Host Reset

with power cycle No Yes No (Note 4)

Datasheet 191

Functional Description

NOTES:

1. The PCH drops this type of reset request if received while the system is in S3/S4/S5.

2. PCH does not drop this type of reset request if received while system is in a software-

entered S3/S4/S5 state. However, the PCH will perform the reset without executing the

RESET_WARN protocol in these states.

3. The PCH does not send warning message to processor; reset occurs without delay.

4. Trigger will result in Global Reset with power cycle if the acknowledge message is not

received by the PCH.

5. The PCH waits for enabled wake event to complete reset.

Intel Management Engine Triggered Power

Button Override No No No Yes

Intel Management Engine Watchdog Timer Time-

out No No No Yes

Intel Management Engine Triggered Global Reset No No Yes

Intel Management Engine Triggered Host Reset

with power down (host stays there) No Yes (Note 5) No (Note 4)

PLTRST# Entry Time-out No No Yes

S3/4/5 Entry Time-out No No No Yes

PROCPWRGD Stuck Low No No Yes

Power Management Watchdog Timer No No No Yes

Intel Management Engine Hardware

Uncorrectable Error No No No Yes

Table 5-38. Causes of Host and Global Resets (Sheet 2 of 2)

Trigger

Host Reset

without

Power Cycle1

Host Reset

with Power

Cycle2

Global Reset

with Power

Cycle3

Straight to S5

(Host Stays

there)

Functional Description

192 Datasheet

5.14 System Management (D31:F0)

The PCH provides various functions to make a system easier to manage and to lower

the Total Cost of Ownership (TCO) of the system. Features and functions can be

augmented using external A/D converters and GPIO, as well as an external

microcontroller.

The following features and functions are supported by the PCH:

• Processor present detection

— Detects if processor fails to fetch the first instruction after reset

• Various Error detection (such as ECC Errors) indicated by host controller

— Can generate SMI#, SCI, SERR, NMI, or TCO interrupt

• Intruder Detect input

— Can generate TCO interrupt or SMI# when the system cover is removed

— INTRUDER# allowed to go active in any power state, including G3

• Detection of bad BIOS Flash (FWH or Flash on SPI) programming

— Detects if data on first read is FFh (indicates that BIOS flash is not

programmed)

• Ability to hide a PCI device

— Allows software to hide a PCI device in terms of configuration space through

the use of a device hide register (See Section 10.1.45)

Note: Voltage ID from the processor can be read using GPI signals.

5.14.1 Theory of Operation

The System Management functions are designed to allow the system to diagnose failing

subsystems. The intent of this logic is that some of the system management

functionality can be provided without the aid of an external microcontroller.

5.14.1.1 Detecting a System Lockup

When the processor is reset, it is expected to fetch its first instruction. If the processor

fails to fetch the first instruction after reset, the TCO timer times out twice and the PCH

asserts PLTRST#.

Datasheet 193

Functional Description

5.14.1.2 Handling an Intruder

The PCH has an input signal, INTRUDER#, that can be attached to a switch that is

activated by the system’s case being open. This input has a two RTC clock debounce. If

INTRUDER# goes active (after the debouncer), this will set the INTRD_DET bit in the

TCO2_STS register. The INTRD_SEL bits in the TCO_CNT register can enable the PCH to

cause an SMI# or interrupt. The BIOS or interrupt handler can then cause a transition

to the S5 state by writing to the SLP_EN bit.

The software can also directly read the status of the INTRUDER# signal (high or low) by

clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI

if the intruder function is not required.

If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written

as a 1, then the INTRD_DET bit will go to a 0 when INTRUDER# input signal goes

inactive. Note that this is slightly different than a classic sticky bit, since most sticky

bits would remain active indefinitely when the signal goes active and would

immediately go inactive when a 1 is written to the bit.

Note: The INTRD_DET bit resides in the PCH’s RTC well, and is set and cleared synchronously

with the RTC clock. Thus, when software attempts to clear INTRD_DET (by writing a 1

to the bit location) there may be as much as two RTC clocks (about 65 µs) delay before

the bit is actually cleared. Also, the INTRUDER# signal should be asserted for a

minimum of 1 ms to ensure that the INTRD_DET bit will be set.

Note: If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET

bit, the bit remains set and the SMI is generated again immediately. The SMI handler

can clear the INTRD_SEL bits to avoid further SMIs. However, if the INTRUDER# signal

goes inactive and then active again, there will not be further SMIs, since the

INTRD_SEL bits would select that no SMI# be generated.

5.14.1.3 Detecting Improper Flash Programming

The PCH can detect the case where the BIOS flash is not programmed. This results in

the first instruction fetched to have a value of FFh. If this occurs, the PCH sets the

BAD_BIOS bit. The BIOS flash may reside in FWH or flash on the SPI bus.

5.14.1.4 Heartbeat and Event Reporting using SMLink/SMBus

Heartbeat and event reporting using SMLink/SMBus is no longer supported. The Intel

AMT logic in PCH can be programmed to generate an interrupt to the Intel Management

Engine when an event occurs. The Intel Management Engine will poll the TCO registers

to gather appropriate bits to send the event message to the Gigabit Ethernet controller,

if Intel Management Engine is programmed to do so.

Functional Description

194 Datasheet

5.14.2 TCO Modes

5.14.2.1 TCO Legacy/Compatible Mode

In TCO Legacy/Compatible mode, only the host SMBus is utilized. The TCO Slave is

connected to the host SMBus internally by default. In this mode, the Intel Management

Engine SMBus controllers are not used and should be disabled by soft strap.

In TCO Legacy/Compatible mode the PCH can function directly with an external LAN

controller or equivalent external LAN controller to report messages to a network

management console without the aid of the system processor. This is crucial in cases

where the processor is malfunctioning or cannot function due to being in a low-power

state. Table 5 - 3 9 includes a list of events that will report messages to the network

management console.

NOTE: The GPIO11/SMBALERT# pin will trigger an event message (when enabled by the

GPIO11_ALERT_DISABLE bit) regardless of whether it is configured as a GPI or not.

Figure 5-5. TCO Legacy/Compatible Mode SMBus Configuration

Host SM Bu s

TCO Slave

SPD

(Slave) uCtrl

Legacy Sensors

(Master or Slave

with ALERT)

TCO Legacy/Compatible Mode

SMBus

Intel ME SMBus

Contro ll e r 3 X

XPCI/PCIe*

Device

3rd Party

NIC

PCH

Intel ME SMBus

Control l er 1

Intel ME SMBus

Control l er 2

Table 5-39. Event Transitions that Cause Messages

Event Assertion? deassertion? Comments

INTRUDER# pin yes no Must be in “S1 or hung S0” state

THRM# pin yes yes

Must be in “S1 or hung S0” state. Note that

the THRM# pin is isolated when the core

power is off, thus preventing this event in

S3–S5.

Watchdog Timer

Expired yes no (NA) “S1 or hung S0” state entered

GPIO[11]/

SMBALERT# pin yes yes Must be in “S1 or hung S0” state

BATLOW# yes yes Must be in “S1 or hung S0” state

CPU_PWR_FLR yes no “S1 or hung S0” state entered

Datasheet 195

Functional Description

5.14.2.2 Advanced TCO Mode

The PCH supports the Advanced TCO mode in which SMLink0 and SMLink1 are used in

addition to the host SMBus. See Figure 5-6 for more details. In this mode, the Intel ME

SMBus controllers must be enabled by soft strap in the flash descriptor.

SMLink0 is dedicated to integrated LAN use and when an Intel PHY 82579 is connected

to SMLink0, a soft strap must be set to indicate that the PHY is connected to SMLink0.

The interface will be running at the frequency of 300 kHz - 400 kHz depending on

different factors such as board routing or bus loading when the Fast Mode is enabled

using a soft strap.

SMLink1 is dedicated to Embedded Controller (EC) or Baseboard Management

Controller (BMC) use. In the case where a BMC is connected to SMLink1, the BMC

communicates with the Intel Management Engine through the Intel ME SMBus

connected to SMLink1. The host and TCO slave communicate with BMC through SMBus.

Figure 5-6. Advanced TCO Mode

Host SM Bus

TCO Slave

SPD

(Slave)

Legacy Sensors

(Master or Slave

with ALERT)

Advanced TCO M ode

SMBus

SMLink0

Inte l M E S MB u s

Co n tro ller 3 EC or

BMC

In tel

82579

SMLink1

PCH

Intel M E SMBus

Co n troller 2

Intel M E SMBus

Co n troller 1 PCI/PCIe*

Device

Functional Description

196 Datasheet

5.15 General Purpose I/O (D31:F0)

The PCH contains up to 70 General Purpose Input/Output (GPIO) signals for Desktop

PCH and 75 General Purpose Input/Output (GPIO) for Mobile PCH. Each GPIO can be

configured as an input or output signal. The number of inputs and outputs varies

depending on the configuration. Following is a brief summary of new GPIO features.

— Capability to mask Suspend well GPIOs from CF9h events (configured using

GP_RST_SEL registers)

— Added capability to program GPIO prior to switching to output

5.15.1 Power Wells

Some GPIOs exist in the suspend power plane. Care must be taken to make sure GPIO

signals are not driven high into powered-down planes. Some PCH GPIOs may be

connected to pins on devices that exist in the core well. If these GPIOs are outputs,

there is a danger that a loss of core power (PWROK low) or a Power Button Override

event results in the PCH driving a pin to a logic 1 to another device that is powered

down.

5.15.2 SMI# SCI and NMI Routing

The routing bits for GPIO[15:0] allow an input to be routed to SMI#, SCI, NMI or

neither. Note that a bit can be routed to either an SMI# or an SCI, but not both.

5.15.3 Triggering

GPIO[15:0] have “sticky” bits on the input. Refer to the GPE0_STS register and the

ALT_GPI_SMI_STS register. As long as the signal goes active for at least 2 clock cycles,

the PCH keeps the sticky status bit active. The active level can be selected in the

GP_INV register. This does not apply to GPI_NMI_STS residing in GPIO I/O space.

If the system is in an S0 or an S1 state, the GPI inputs are sampled at 33 MHz, so the

signal only needs to be active for about 60 ns to be latched. In the S3–S5 states, the

GPI inputs are sampled at 32.768 kHz, and thus must be active for at least

61 microseconds to be latched.

Note: GPIs that are in the core well are not capable of waking the system from sleep states

where the core well is not powered.

If the input signal is still active when the latch is cleared, it will again be set. Another

edge trigger is not required. This makes these signals “level” triggered inputs.

5.15.4 GPIO Registers Lockdown

The following GPIO registers are locked down when the GPIO Lockdown Enable (GLE)

bit is set. The GLE bit resides in D31:F0:GPIO Control (GC) register.

• Offset 00h: GPIO_USE_SEL[31:0]

• Offset 04h: GP_IO_SEL[31:0]

• Offset 0Ch: GP_LVL[31:0]

• Offset 28h: GPI_NMI_EN[15:0]

• Offset 2Ch: GPI_INV[31:0]

• Offset 30h: GPIO_USE_SEL2[63:32]

• Offset 34h: GPI_IO_SEL2[63:32]

• Offset 38h: GP_LVL2[63:32]

• Offset 40h: GPIO_USE_SEL3[95:64]

• Offset 44h: GPI_IO_SEL3[95:64]

• Offset 48h: GP_LVL3[95:64]

• Offset 60h: GP_RST_SEL[31:0]

• Offset 64h: GP_RST_SEL2[63:32]

• Offset 68h: GP_RST_SEL3[95:64]

Datasheet 197

Functional Description

Once these registers are locked down, they become Read-Only registers and any

software writes to these registers will have no effect. To unlock the registers, the GPIO

Lockdown Enable (GLE) bit is required to be cleared to ‘0’. When the GLE bit changes

from a ‘1’ to a ‘0’ a System Management Interrupt (SMI#) is generated if enabled.

Once the GPIO_UNLOCK_SMI bit is set, it can not be changed until a PLTRST# occurs.

This ensures that only BIOS can change the GPIO configuration. If the GLE bit is

cleared by unauthorized software, BIOS will set the GLE bit again when the SMI# is

triggered and these registers will continue to be locked down.

5.15.5 Serial POST Codes over GPIO

The PCH adds the extended capability allowing system software to serialize POST or

other messages on GPIO. This capability negates the requirement for dedicated

diagnostic LEDs on the platform. Additionally, based on the newer BTX form factors, the

PCI bus as a target for POST codes is increasingly difficult to support as the total

number of PCI devices supported are decreasing.

5.15.5.1 Theory of Operation

For the PCH generation POST code serialization logic will be shared with GPIO. These

GPIOs will likely be shared with LED control offered by the Super I/O (SIO) component.

Figure 5-7 shows a likely configuration.

The anticipated usage model is that either the PCH or the SIO can drive a pin low to

turn off an LED. In the case of the power LED, the SIO would normally leave its

corresponding pin in a high-Z state to allow the LED to turn on. In this state, the PCH

can blink the LED by driving its corresponding pin low and subsequently tri-stating the

buffer. The I/O buffer should not drive a ‘1’ when configured for this functionality and

should be capable of sinking 24 mA of current.

An external optical sensing device can detect the on/off state of the LED. By externally

post-processing the information from the optical device, the serial bit stream can be

recovered. The hardware will supply a ‘sync’ byte before the actual data transmission

to allow external detection of the transmit frequency. The frequency of transmission

should be limited to 1 transition every 1 s to ensure the detector can reliably sample

Figure 5-7. Serial Post over GPIO Reference Circuit

SIO

V_3P3_STBY

LED

N ote: The pull-up value is based on the brightness required.

PCH

Functional Description

198 Datasheet

the on/off state of the LED. To allow flexibility in pull-up resistor values for power

optimization, the frequency of the transmission is programmable using the DRS field in

the GP_GB_CMDSTS register.

The serial bit stream is Manchester encoded. This choice of transmission ensures that a

transition will be seen on every clock. The 1 or 0 data is based on the transmission

happening during the high or low phase of the clock.

As the clock will be encoded within the data stream, hardware must ensure that the Z-

0 and 0-Z transitions are glitch-free. Driving the pin directly from a flop or through

glitch-free logic are possible methods to meet the glitch-free requirement.

A simplified hardware/software register interface provides control and status

information to track the activity of this block. Software enabling the serial blink

capability should implement an algorithm referenced below to send the serialized

message on the enabled GPIO.

1. Read the Go/Busy status bit in the GP_GB_CMDSTS register and verify it is cleared.

This will ensure that the GPIO is idled and a previously requested message is still

not in progress.

2. Write the data to serialize into the GP_GB_DATA register.

3. Write the DLS and DRS values into the GP_GB_CMDSTS register and set the Go bit.

This may be accomplished using a single write.

The reference diagram shows the LEDs being powered from the suspend supply. By

providing a generic capability that can be used both in the main and the suspend power

planes maximum flexibility can be achieved. A key point to make is that the PCH will

not unintentionally drive the LED control pin low unless a serialization is in progress.

System board connections utilizing this serialization capability are required to use the

same power plane controlling the LED as the PCH GPIO pin. Otherwise, the PCH GPIO

may float low during the message and prevent the LED from being controlled from the

SIO. The hardware will only be serializing messages when the core power well is

powered and the processor is operational.

Care should be taken to prevent the PCH from driving an active ‘1’ on a pin sharing the

serial LED capability. Since the SIO could be driving the line to 0, having the PCH drive

a 1 would create a high current path. A recommendation to avoid this condition

involves choosing a GPIO defaulting to an input. The GP_SER_BLINK register should be

set first before changing the direction of the pin to an output. This sequence ensures

the open-drain capability of the buffer is properly configured before enabling the pin as

an output.

5.15.5.2 Serial Message Format

To serialize the data onto the GPIO, an initial state of high-Z is assumed. The SIO is

required to have its LED control pin in a high-Z state as well to allow the PCH to blink

the LED (refer to the reference diagram).

The three components of the serial message include the sync, data, and idle fields. The

sync field is 7 bits of ‘1’ data followed by 1 bit of ‘0’ data. Starting from the high-Z state

(LED on) provides external hardware a known initial condition and a known pattern. In

case one or more of the leading 1 sync bits are lost, the 1s followed by 0 provide a

clear indication of ‘end of sync’. This pattern will be used to ‘lock’ external sampling

logic to the encoded clock.

The data field is shifted out with the highest byte first (MSB). Within each byte, the

most significant bit is shifted first (MSb).

Datasheet 199

Functional Description

The idle field is enforced by the hardware and is at least 2 bit times long. The hardware

will not clear the Busy and Go bits until this idle time is met. Supporting the idle time in

hardware prevents time-based counting in BIOS as the hardware is immediately ready

for the next serial code when the Go bit is cleared. Note that the idle state is

represented as a high-Z condition on the pin. If the last transmitted bit is a 1, returning

to the idle state will result in a final 0-1 transition on the output Manchester data. Two

full bit times of idle correspond to a count of 4 time intervals (the width of the time

interval is controlled by the DRS field).

The following waveform shows a 1-byte serial write with a data byte of 5Ah. The

internal clock and bit position are for reference purposes only. The Manchester D is the

resultant data generated and serialized onto the GPIO. Since the buffer is operating in

open-drain mode the transitions are from high-Z to 0 and back.

5.16 SATA Host Controller (D31:F2, F5)

The SATA function in the PCH has three modes of operation to support different

operating system conditions. In the case of Native IDE enabled operating systems, the

PCH uses two controllers to enable all six ports of the bus. The first controller

(Device 31: Function 2) supports ports 0 – 3 and the second controller (Device 31:

Function 5) supports ports 4 and 5. When using a legacy operating system, only one

controller (Device 31: Function 2) is available that supports ports 0 – 3. In AHCI or

RAID mode, only one controller (Device 31: Function 2) is utilized enabling all six ports

and the second controller (Device 31: Function 5) shall be disabled.

The MAP register, Section 15.1.25, provides the ability to share PCI functions. When

sharing is enabled, all decode of I/O is done through the SATA registers. Device 31,

Function 1 (IDE controller) is hidden by software writing to the Function Disable

The PCH SATA controllers feature six sets of interface signals (ports) that can be

independently enabled or disabled (they cannot be tri-stated or driven low). Each

interface is supported by an independent DMA controller.

The PCH SATA controllers interact with an attached mass storage device through a

The host software follows existing standards and conventions when accessing the

Note: SATA interface transfer rates are independent of UDMA mode settings. SATA interface

transfer rates will operate at the bus’s maximum speed, regardless of the UDMA mode

reported by the SATA device or the system BIOS.

I nt ernal C l ock

M anchest e r D

8-bi t sync field

(1111_1110)

Bit 7 0123456

5A data byte 2 clk

idle

Functional Description

200 Datasheet

5.16.1 SATA 6 Gb/s Support

The PCH supports SATA 6 Gb/s transfers with all capable SATA devices. SATA 6 Gb/s

support is available on PCH Ports 0 and 1 only.

Note: PCH ports 0 and 1 also support SATA 1.5 Gb/s and 3.0 Gb/s device transfers.

5.16.2 SATA Feature Support

Feature

PCH

(AHCI/RAID

Disabled)

PCH

(AHCI/RAID

Enabled)

Native Command Queuing (NCQ) N/A Supported

Auto Activate for DMA N/A Supported

Hot Plug Support N/A Supported

Asynchronous Signal Recovery N/A Supported

3 Gb/s Transfer Rate Supported Supported

ATAPI Asynchronous Notification N/A Supported

Host & Link Initiated Power Management N/A Supported

Staggered Spin-Up Supported Supported

Command Completion Coalescing N/A N/A

External SATA N/A Supported

Feature Description

Native Command Queuing

(NCQ)

Allows the device to reorder commands for more efficient data

transfers

Auto Activate for DMA Collapses a DMA Setup then DMA Activate sequence into a DMA

Setup only

Hot Plug Support

Allows for device detection without power being applied and

ability to connect and disconnect devices without prior

notification to the system

Asynchronous Signal

Recovery

Provides a recovery from a loss of signal or establishing

communication after hot plug

6 Gb/s Transfer Rate Capable of data transfers up to 6 Gb/s

ATAPI Asynchronous

Notification

A mechanism for a device to send a notification to the host that

the device requires attention

Host & Link Initiated Power

Management

Capability for the host controller or device to request Partial and

Slumber interface power states

Staggered Spin-Up Enables the host the ability to spin up hard drives sequentially

to prevent power load problems on boot

Command Completion

Coalescing

Reduces interrupt and completion overhead by allowing a

specified number of commands to complete and then generating

an interrupt to process the commands

External SATA Technology that allows for an outside the box connection of up

to 2 meters (when using the cable defined in SATA-IO)

Datasheet 201

Functional Description

5.16.3 Theory of Operation

5.16.3.1 Standard ATA Emulation

The PCH contains a set of registers that shadow the contents of the legacy IDE

registers. The behavior of the Command and Control Block registers, PIO, and DMA

data transfers, resets, and interrupts are all emulated.

Note: The PCH will assert INTR when the master device completes the EDD command

regardless of the command completion status of the slave device. If the master

completes EDD first, an INTR is generated and BSY will remain '1' until the slave

completes the command. If the slave completes EDD first, BSY will be '0' when the

master completes the EDD command and asserts INTR. Software must wait for busy to

clear (0) before completing an EDD command, as required by the ATA5 through ATA7

(T13) industry standards.

5.16.3.2 48-Bit LBA Operation

The SATA host controller supports 48-bit LBA through the host-to-device register FIS

when accesses are performed using writes to the task file. The SATA host controller will

ensure that the correct data is put into the correct byte of the host-to-device FIS.

There are special considerations when reading from the task file to support 48-bit LBA

operation. Software may need to read all 16-bits. Since the registers are only 8-bits

wide and act as a FIFO, a bit must be set in the device/control register, which is at

offset 3F6h for primary and 376h for secondary (or their native counterparts).

If software clears Bit 7 of the control register before performing a read, the last item

written will be returned from the FIFO. If software sets Bit 7 of the control register

before performing a read, the first item written will be returned from the FIFO.

5.16.4 SATA Swap Bay Support

The PCH provides for basic SATA swap bay support using the PSC register configuration

bits and power management flows. A device can be powered down by software and the

port can then be disabled, allowing removal and insertion of a new device.

Note: This SATA swap bay operation requires board hardware (implementation specific),

BIOS, and operating system support.

5.16.5 Hot Plug Operation

The PCH supports Hot Plug Surprise removal and Insertion Notification in the PARTIAL,

SLUMBER and Listen Mode states when used with Low Power Device Presence

Detection. Software can take advantage of power savings in the low power states while

enabling hot plug operation. Refer to chapter 7 of the AHCI specification for details.

5.16.5.1 Low Power Device Presence Detection

Low Power Device Presence Detection enables SATA Link Power Management to co-

exist with hot plug (insertion and removal) without interlock switch or cold presence

detect. The detection mechanism allows Hot Plug events to be detectable by hardware

across all link power states (Active, PARTIAL, SLUMBER) as well as AHCI Listen Mode.

If the Low Power Device Presence Detection circuit is disabled the PCH reverts to Hot

Plug Surprise Removal Notification (without an interlock switch) mode that is mutually

exclusive of the PARTIAL and SLUMBER power management states.

Functional Description

202 Datasheet

5.16.6 Function Level Reset Support (FLR)

The SATA Host Controller supports the Function Level Reset (FLR) capability. The FLR

capability can be used in conjunction with Intel Virtualization Technology. FLR allows an

operating system in a Virtual Machine to have complete control over a device, including

its initialization, without interfering with the rest of the platform. The device provides a

software interface that enables the Operating System to reset the whole device as if a

PCI reset was asserted.

5.16.6.1 FLR Steps

5.16.6.1.1 FLR Initialization

1. A FLR is initiated by software writing a ‘1’ to the Initiate FLR bit.

2. All subsequent requests targeting the Function will not be claimed and will be

Master Abort Immediate on the bus. This includes any configuration, I/O or

Memory cycles, however, the Function shall continue to accept completions

targeting the Function.

5.16.6.1.2 FLR Operation

The Function will Reset all configuration, I/O and memory registers of the Function

except those indicated otherwise and reset all internal states of the Function to the

default or initial condition.

5.16.6.1.3 FLR Completion

The Initiate FLR bit is reset (cleared) when the FLR reset is completed. This bit can be

used to indicate to the software that the FLR reset is completed.

Note: From the time Initiate FLR bit is written to 1 software must wait at least 100 ms before

accessing the function.

5.16.7 Intel® Rapid Storage Technology Configuration

The Intel Rapid Storage Technology offers several diverse options for RAID (redundant

array of independent disks) to meet the needs of the end user. AHCI support provides

higher performance and alleviates disk bottlenecks by taking advantage of the

independent DMA engines that each SATA port offers in the PCH.

• RAID Level 0 performance scaling up to 4 drives, enabling higher throughput for

data intensive applications such as video editing.

• Data security is offered through RAID Level 1, which performs mirroring.

• RAID Level 10 provides high levels of storage performance with data protection,

combining the fault-tolerance of RAID Level 1 with the performance of RAID Level

0. By striping RAID Level 1 segments, high I/O rates can be achieved on systems

that require both performance and fault-tolerance. RAID Level 10 requires 4 hard

drives, and provides the capacity of two drives.

• RAID Level 5 provides highly efficient storage while maintaining fault-tolerance on

3 or more drives. By striping parity, and rotating it across all disks, fault tolerance

of any single drive is achieved while only consuming 1 drive worth of capacity. That

is, a 3 drive RAID 5 has the capacity of 2 drives, or a 4 drive RAID 5 has the

capacity of 3 drives. RAID 5 has high read transaction rates, with a medium write

rate. RAID 5 is well suited for applications that require high amounts of storage

while maintaining fault tolerance.

Datasheet 203

Functional Description

By using the PCH’s built-in Intel Rapid Storage Technology, there is no loss of PCI

resources (request/grant pair) or add-in card slot.

Intel® Rapid Storage Technology functionality requires the following items:

1. The PCH SKU enabled for Intel® Rapid Storage Technology

2. Intel Rapid Storage Manager RAID Option ROM must be on the platform

3. Intel Rapid Storage Manager drivers, most recent revision.

4. At least two SATA hard disk drives (minimum depends on RAID configuration).

Intel Rapid Storage Technology is not available in the following configurations:

1. The SATA controller is in compatible mode.

5.16.7.1 Intel® Rapid Storage Manager RAID Option ROM

The Intel Rapid Storage Manager RAID Option ROM is a standard PnP Option ROM that

is easily integrated into any System BIOS. When in place, it provides the following

three primary functions:

• Provides a text mode user interface that allows the user to manage the RAID

configuration on the system in a pre-operating system environment. Its feature set

is kept simple to keep size to a minimum, but allows the user to create & delete

RAID volumes and select recovery options when problems occur.

• Provides boot support when using a RAID volume as a boot disk. It does this by

providing Int13 services when a RAID volume needs to be accessed by MS-DOS

applications (such as NTLDR) and by exporting the RAID volumes to the System

BIOS for selection in the boot order.

• At each boot up, provides the user with a status of the RAID volumes and the

option to enter the user interface by pressing CTRL-I.

5.16.8 Intel® Smart Response Technology

Intel® Smart Response Technology is a disk caching solution that can provide improved

computer system performance with improved power savings. It allows configuration of

a computer systems with the advantage of having HDDs for maximum storage capacity

with system performance at or near SSD performance levels.

5.16.9 Power Management Operation

Power management of the PCH SATA controller and ports will cover operations of the

host controller and the SATA wire.

5.16.9.1 Power State Mappings

The D0 PCI power management state for device is supported by the PCH SATA

controller.

SATA devices may also have multiple power states. From parallel ATA, three device

states are supported through ACPI. They are:

•D0 – Device is working and instantly available.

•D1 – Device enters when it receives a STANDBY IMMEDIATE command. Exit latency

from this state is in seconds

•D3 – From the SATA device’s perspective, no different than a D1 state, in that it is

entered using the STANDBY IMMEDIATE command. However, an ACPI method is

also called which will reset the device and then cut its power.

Each of these device states are subsets of the host controller’s D0 state.

Functional Description

204 Datasheet

Finally, SATA defines three PHY layer power states, which have no equivalent mappings

to parallel ATA. They are:

•PHY READY – PHY logic and PLL are both on and active

•Partial – PHY logic is powered, but in a reduced state. Exit latency is no longer

than 10 ns

•Slumber – PHY logic is powered, but in a reduced state. Exit latency can be up to

10 ms.

Since these states have much lower exit latency than the ACPI D1 and D3 states, the

SATA controller defines these states as sub-states of the device D0 state.

5.16.9.2 Power State Transitions

5.16.9.2.1 Partial and Slumber State Entry/Exit

The partial and slumber states save interface power when the interface is idle. It would

be most analogous to PCI CLKRUN# (in power savings, not in mechanism), where the

interface can have power saved while no commands are pending. The SATA controller

defines PHY layer power management (as performed using primitives) as a driver

operation from the host side, and a device proprietary mechanism on the device side.

The SATA controller accepts device transition types, but does not issue any transitions

as a host. All received requests from a SATA device will be ACKed.

When an operation is performed to the SATA controller such that it needs to use the

SATA cable, the controller must check whether the link is in the Partial or Slumber

states, and if so, must issue a COM_WAKE to bring the link back online. Similarly, the

SATA device must perform the same action.

5.16.9.2.2 Device D1, D3 States

These states are entered after some period of time when software has determined that

no commands will be sent to this device for some time. The mechanism for putting a

device in these states does not involve any work on the host controller, other then

sending commands over the interface to the device. The command most likely to be

used in ATA/ATAPI is the “STANDBY IMMEDIATE” command.

5.16.9.2.3 Host Controller D3HOT State

After the interface and device have been put into a low power state, the SATA host

controller may be put into a low power state. This is performed using the PCI power

management registers in configuration space. There are two very important aspects to

note when using PCI power management.

1. When the power state is D3, only accesses to configuration space are allowed. Any

attempt to access the memory or I/O spaces will result in master abort.

2. When the power state is D3, no interrupts may be generated, even if they are

enabled. If an interrupt status bit is pending when the controller transitions to D0,

an interrupt may be generated.

When the controller is put into D3, it is assumed that software has properly shut down

the device and disabled the ports. Therefore, there is no need to sustain any values on

the port wires. The interface will be treated as if no device is present on the cable, and

power will be minimized.

When returning from a D3 state, an internal reset will not be performed.

Datasheet 205

Functional Description

5.16.9.2.4 Non-AHCI Mode PME# Generation

When in non-AHCI mode (legacy mode) of operation, the SATA controller does not

generate PME#. This includes attach events (since the port must be disabled), or

interlock switch events (using the SATAGP pins).

5.16.9.3 SMI Trapping (APM)

Device 31:Function2:Offset C0h (see Section 14.1.39) contain control for generating

SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges (1F0–

1F7h, 3F6h, 170–177h, and 376h) and native IDE ranges defined by PCMDBA, PCTLBA,

SCMDBA an SCTLBA. If the SATA controller is in legacy mode and is using these

addresses, accesses to one of these ranges with the appropriate bit set causes the

cycle to not be forwarded to the SATA controller, and for an SMI# to be generated. If an

access to the Bus-Master IDE registers occurs while trapping is enabled for the device

being accessed, then the register is updated, an SMI# is generated, and the device

activity status bits (Section 14.1.40) are updated indicating that a trap occurred.

5.16.10 SATA Device Presence

In legacy mode, the SATA controller does not generate interrupts based on hot plug/

unplug events. However, the SATA PHY does know when a device is connected (if not in

a partial or slumber state), and it s beneficial to communicate this information to host

software as this will greatly reduce boot times and resume times.

The flow used to indicate SATA device presence is shown in Figure 5-8. The ‘PxE’ bit

refers to PCS.P[3:0]E bits, depending on the port being checked and the ‘PxP’ bits refer

to the PCS.P[3:0]P bits, depending on the port being checked. If the PCS/PxP bit is set

a device is present, if the bit is cleared a device is not present. If a port is disabled,

software can check to see if a new device is connected by periodically re-enabling the

port and observing if a device is present, if a device is not present it can disable the

port and check again later. If a port remains enabled, software can periodically poll

PCS.PxP to see if a new device is connected.

Figure 5-8. Flow for Port Enable / Device Present Bits

Functional Description

206 Datasheet

5.16.11 SATA LED

The SATALED# output is driven whenever the BSY bit is set in any SATA port. The

SATALED# is an active-low open-drain output. When SATALED# is low, the LED should

be active. When SATALED# is high, the LED should be inactive.

5.16.12 AHCI Operation

The PCH provides hardware support for Advanced Host Controller Interface (AHCI), a

programming interface for SATA host controllers developed through a joint industry

effort. AHCI defines transactions between the SATA controller and software and enables

advanced performance and usability with SATA. Platforms supporting AHCI may take

advantage of performance features such as no master/slave designation for SATA

devices—each device is treated as a master—and hardware assisted native command

queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires

appropriate software support (such as, an AHCI driver) and for some features,

hardware support in the SATA device or additional platform hardware.

The PCH supports all of the mandatory features of the Serial ATA Advanced Host

Controller Interface Specification, Revision 1.2 and many optional features, such as

hardware assisted native command queuing, aggressive power management, LED

indicator support, and Hot-Plug through the use of interlock switch support (additional

platform hardware and software may be required depending upon the implementation).

Note: For reliable device removal notification while in AHCI operation without the use of

interlock switches (surprise removal), interface power management should be disabled

for the associated port. See Section 7.3.1 of the AHCI Specification for more

information.

5.16.13 SGPIO Signals

The SGPIO signals, in accordance to the SFF-8485 specification, support per-port LED

signaling. These signals are not related to SATALED#, which allows for simplified

indication of SATA command activity. The SGPIO group interfaces with an external

controller chip that fetches and serializes the data for driving across the SGPIO bus.

The output signals then control the LEDs. This feature is only valid in AHCI/RAID mode.

5.16.13.1 Mechanism

The enclosure management for SATA Controller 1 (Device 31: Function 2) involves

sending messages that control LEDs in the enclosure. The messages for this function

are stored after the normal registers in the AHCI BAR, at Offset 580h bytes for the PCH

from the beginning of the AHCI BAR as specified by the EM_LOC global register

(Section 14.4.1.6).

Software creates messages for transmission in the enclosure management message

buffer. The data in the message buffer should not be changed if CTL.TM bit is set by

software to transmit an update message. Software should only update the message

buffer when CTL.TM bit is cleared by hardware otherwise the message transmitted will

be indeterminate. Software then writes a register to cause hardware to transmit the

message or take appropriate action based on the message content. The software

should only create message types supported by the controller, which is LED messages

for the PCH. If the software creates other non LED message types (such as, SAF-TE,

SES-2), the SGPIO interface may hang and the result is indeterminate.

During reset all SGPIO pins will be in tri-state. The interface will continue to be in tri-

state after reset until the first transmission occurs when software programs the

message buffer and sets the transmit bit CTL.TM. The SATA Host controller will initiate

the transmission by driving SCLOCK and at the same time drive the SLOAD to ‘0’ prior

Datasheet 207

Functional Description

to the actual bit stream transmission. The Host will drive SLOAD low for at least 5

SCLOCK then only start the bit stream by driving the SLOAD to high. SLOAD will be

driven high for 1 SCLOCK follow by vendor specific pattern that is default to “0000” if

software has yet to program the value. A total of 21-bit stream from 7 ports (Port0,

Port1, Port2, Port3, Port4 Port5 and Port6) of 3-bit per port LED message will be

transmitted on SDATAOUT0 pin after the SLOAD is driven high for 1 SCLOCK. Only 3

ports (Port4, Port5 and Port6) of 9 bit total LED message follow by 12 bits of tri-state

value will be transmitted out on SDATAOUT1 pin.

All the default LED message values will be high prior to software setting them, except

the Activity LED message that is configured to be hardware driven that will be

generated based on the activity from the respective port. All the LED message values

will be driven to ‘1’ for the port that is unimplemented as indicated in the Port

Implemented register regardless of the software programmed value through the

message buffer.

There are 2 different ways of resetting the PCH’s SGPIO interface, asynchronous reset

and synchronous reset. Asynchronous reset is caused by platform reset to cause the

SGPIO interface to be tri-state asynchronously. Synchronous reset is caused by setting

the CTL.RESET bit, clearing the GHC.AE bit or HBA reset, where Host Controller will

complete the existing full bit stream transmission then only tri-state all the SGPIO pins.

After the reset, both synchronous and asynchronous, the SGPIO pins will stay tri-

stated.

Note: The PCH Host Controller does not ensure that it will cause the target SGPIO device or

controller to be reset. Software is responsible to keep the PCH SGPIO interface in tri-

state for 2 second to cause a reset on the target of the SGPIO interface.

5.16.13.2 Message Format

Messages shall be constructed with a one DWord header that describes the message to

be sent followed by the actual message contents. The first DWord shall be constructed

as follows:

Bit Description

31:28 Reserved

27:24

Message Type (MTYPE): Specifies the type of the message.

The message types are:

0h = LED

1h = SAF-TE

2h = SES-2

3h = SGPIO (register based interface)

All other values reserved

23:16

Data Size (DSIZE): Specifies the data size in bytes. If the message (enclosure

services command) has a data buffer that is associated with it that is transferred, the

size of that data buffer is specified in this field. If there is no separate data buffer, this

field shall have a value of ‘0’. The data directly follows the message in the message

buffer. For the PCH, this value should always be ‘0’.

15:8

Message Size (MSIZE): Specifies the size of the message in bytes. The message size

does not include the one DWord header. A value of ‘0’ is invalid. For the PCH, the

message size is always 4 bytes.

7:0 Reserved

Functional Description

208 Datasheet

The SAF-TE, SES-2, and SGPIO message formats are defined in the corresponding

specifications, respectively. The LED message type is defined in Section 5.16.13.3. It is

the responsibility of software to ensure the content of the message format is correct. If

the message type is not programmed as 'LED' for this controller, the controller shall not

take any action to update its LEDs. Note that for LED message type, the message size

is always consisted of 4 bytes.

5.16.13.3 LED Message Type

The LED message type specifies the status of up to three LEDs. Typically, the usage for

these LEDs is activity, fault, and locate. Not all implementations necessarily contain all

LEDs (for example, some implementations may not have a locate LED). The message

identifies the HBA port number and the Port Multiplier port number that the slot status

applies to. If a Port Multiplier is not in use with a particular device, the Port Multiplier

port number shall be ‘0’. The format of the LED message type is defined in Ta b l e 5 - 4 0 .

The LEDs shall retain their values until there is a following update for that particular

slot.

Table 5-40. Multi-activity LED Message Type

Byte Description

3-2

Value (VAL): This field describes the state of each LED for a particular location. There

are three LEDs that may be supported by the HBA. Each LED has 3 bits of control.

LED values are:

000b – LED shall be off

001b – LED shall be solid on as perceived by human eye

All other values reserved

The LED bit locations are:

Bits 2:0 – Activity LED (may be driven by hardware)

Bits 5:3 – Vendor Specific LED (such as locate)

Bits 8:6 - Vendor Specific LED (such as fault)

Bits 15:9 – Reserved

Vendor specific message is:

Bit 3:0 – Vendor Specific Pattern

Bit 15:4 – Reserved

NOTE: If Activity LED Hardware Driven (ATTR.ALHD) bit is set, host will output the

hardware LED value sampled internally and will ignore software written activity

value on bit [2:0]. Since the PCH Enclosure Management does not support port

multiplier based LED message, the LED message will be generated

independently based on respective port’s operation activity. Vendor specific LED

values Locate (Bits 5:3) and Fault (Bits 8:6) always are driven by software.

Port Multiplier Information: Specifies slot specific information related to Port

Multiplier.

Bits 3:0 specify the Port Multiplier port number for the slot that requires the status

update. If a Port Multiplier is not attached to the device in the affected slot, the Port

Multiplier port number shall be '0'. Bits 7:4 are reserved. The PCH does not support LED

messages for devices behind a Port MUltiplier. This byte should be 0.

HBA Information: Specifies slot specific information related to the HBA.

Bits 4:0 – HBA port number for the slot that requires the status update.

Bit 5 – If set to '1', value is a vendor specific message that applies to the entire

enclosure. If cleared to '0', value applies to the port specified in bits 4:0.

Bits 7:6 – Reserved

Datasheet 209

Functional Description

5.16.13.4 SGPIO Waveform

Figure 5-9. Serial Data transmitted over the SGPIO Interface

Functional Description

210 Datasheet

5.16.14 External SATA

The PCH supports external SATA. External SATA utilizes the SATA interface outside of

the system box. The usage model for this feature must comply with the Serial ATA II

Cables and Connectors Volume 2 Gold specification at www.sata-io.org. Intel validates

two configurations:

1. The cable-up solution involves an internal SATA cable that connects to the SATA

motherboard connector and spans to a back panel PCI bracket with an eSATA

connector. A separate eSATA cable is required to connect an eSATA device.

2. The back-panel solution involves running a trace to the I/O back panel and

connecting a device using an external SATA connector on the board.

5.17 High Precision Event Timers

This function provides a set of timers that can be used by the operating system. The

timers are defined such that in the future, the operating system may be able to assign

specific timers to used directly by specific applications. Each timer can be configured to

cause a separate interrupt.

The PCH provides eight timers. The timers are implemented as a single counter, each

with its own comparator and value register. This counter increases monotonically. Each

individual timer can generate an interrupt when the value in its value register matches

the value in the main counter.

The registers associated with these timers are mapped to a memory space (much like

the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS

reports to the operating system the location of the register space. The hardware can

support an assignable decode space; however, the BIOS sets this space prior to

handing it over to the operating system. It is not expected that the operating system

will move the location of these timers once it is set by the BIOS.

5.17.1 Timer Accuracy

1. The timers are accurate over any 1 ms period to within 0.05% of the time specified

in the timer resolution fields.

2. Within any 100 microsecond period, the timer reports a time that is up to two ticks

too early or too late. Each tick is less than or equal to 100 ns, so this represents an

error of less than 0.2%.

3. The timer is monotonic. It does not return the same value on two consecutive

reads (unless the counter has rolled over and reached the same value).

The main counter is clocked by the 14.31818 MHz clock, synchronized into the

66.666 MHz domain. This results in a non-uniform duty cycle on the synchronized

clock, but does have the correct average period. The accuracy of the main counter is as

accurate as the 14.31818 MHz clock.

Datasheet 211

Functional Description

5.17.2 Interrupt Mapping

Mapping Option #1 (Legacy Replacement Option)

In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is set. This forces the

mapping found in Table 5 - 4 1.

NOTE: The Legacy Option does not preclude delivery of IRQ0/IRQ8 using direct FSB interrupt

messages.

Mapping Option #2 (Standard Option)

In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is 0. Each timer has its

own routing control. The interrupts can be routed to various interrupts in the 8259 or

I/O APIC. A capabilities field indicates which interrupts are valid options for routing. If a

timer is set for edge-triggered mode, the timers should not be shared with any PCI

interrupts.

For the PCH, the only supported interrupt values are as follows:

Timer 0 and 1: IRQ20, 21, 22 & 23 (I/O APIC only).

Timer 2: IRQ11 (8259 or I/O APIC) and IRQ20, 21, 22 & 23 (I/O APIC only).

Timer 3: IRQ12 (8259 or I/O APIC) and IRQ 20, 21, 22 & 23 (I/O APIC only).

Interrupts from Timer 4, 5, 6, 7 can only be delivered using direct FSB interrupt

messages.

Table 5-41. Legacy Replacement Routing

Timer 8259 Mapping APIC Mapping Comment

0IRQ0 IRQ2

In this case, the 8254 timer will

not cause any interrupts

1IRQ8 IRQ8

In this case, the RTC will not cause

any interrupts.

2 & 3 Per IRQ Routing

Field. Per IRQ Routing Field

4, 5, 6, 7 not available not available

Functional Description

212 Datasheet

5.17.3 Periodic versus Non-Periodic Modes

Non-Periodic Mode

Timer 0 is configurable to 32 (default) or 64-bit mode, whereas Timers 1, 2 and 3 only

support 32-bit mode (See Section 20.1.5).

All of the timers support non-periodic mode.

Refer to Section 2.3.9.2.1 of the IA-PC HPET Specification for a description of this

mode.

Periodic Mode

Timer 0 is the only timer that supports periodic mode. Refer to Section 2.3.9.2.2 of the

IA-PC HPET Specification for a description of this mode.

The following usage model is expected:

1. Software clears the ENABLE_CNF bit to prevent any interrupts.

2. Software Clears the main counter by writing a value of 00h to it.

3. Software sets the TIMER0_VAL_SET_CNF bit.

4. Software writes the new value in the TIMER0_COMPARATOR_VAL register.

5. Software sets the ENABLE_CNF bit to enable interrupts.

The Timer 0 Comparator Value register cannot be programmed reliably by a single

64-bit write in a 32-bit environment except if only the periodic rate is being changed

during run-time. If the actual Timer 0 Comparator Value needs to be reinitialized, then

the following software solution will always work regardless of the environment:

1. Set TIMER0_VAL_SET_CNF bit.

2. Set the lower 32 bits of the Timer0 Comparator Value register.

3. Set TIMER0_VAL_SET_CNF bit.

4. Set the upper 32 bits of the Timer0 Comparator Value register.

5.17.4 Enabling the Timers

The BIOS or operating system PnP code should route the interrupts. This includes the

Legacy Rout bit, Interrupt Rout bit (for each timer), interrupt type (to select the edge

or level type for each timer)

The Device Driver code should do the following for an available timer:

1. Set the Overall Enable bit (Offset 10h, bit 0).

2. Set the timer type field (selects one-shot or periodic).

3. Set the interrupt enable.

4. Set the comparator value.

Datasheet 213

Functional Description

5.17.5 Interrupt Levels

Interrupts directed to the internal 8259s are active high. See Section 5.9 for

information regarding the polarity programming of the I/O APIC for detecting internal

interrupts.

If the interrupts are mapped to the 8259 or I/O APIC and set for level-triggered mode,

they can be shared with PCI interrupts. They may be shared although it is unlikely for

the operating system to attempt to do this.

If more than one timer is configured to share the same IRQ (using the

TIMERn_INT_ROUT_CNF fields), then the software must configure the timers to level-

triggered mode. Edge-triggered interrupts cannot be shared.

5.17.6 Handling Interrupts

If each timer has a unique interrupt and the timer has been configured for edge-

triggered mode, then there are no specific steps required. No read is required to

process the interrupt.

If a timer has been configured to level-triggered mode, then its interrupt must be

cleared by the software. This is done by reading the interrupt status register and

writing a 1 back to the bit position for the interrupt to be cleared.

Independent of the mode, software can read the value in the main counter to see how

time has passed between when the interrupt was generated and when it was first

serviced.

If Timer 0 is set up to generate a periodic interrupt, the software can check to see how

much time remains until the next interrupt by checking the timer value register.

5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors

A 32-bit timer can be read directly using processors that are capable of 32-bit or 64-bit

instructions. However, a 32-bit processor may not be able to directly read 64-bit timer.

A race condition comes up if a 32-bit processor reads the 64-bit register using two

separate 32-bit reads. The danger is that just after reading one half, the other half rolls

over and changes the first half.

If a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before

reading both the upper and lower 32-bits of the timer. If a 32-bit processor does not

want to halt the timer, it can use the 64-bit timer as a 32-bit timer by setting the

TIMERn_32MODE_CNF bit. This causes the timer to behave as a 32-bit timer. The upper

32-bits are always 0.

Alternatively, software may do a multiple read of the counter while it is running.

Software can read the high 32 bits, then the low 32 bits, the high 32 bits again. If the

high 32 bits have not changed between the two reads, then a rollover has not

happened and the low 32 bits are valid. If the high 32 bits have changed between

reads, then the multiple reads are repeated until a valid read is performed.

Note: On a 64-bit platform, if software attempts a 64 bit read of the 64-bit counter, software

must be aware that some platforms may split the 64 bit read into two 32 bit reads. The

read maybe inaccurate if the low 32 bits roll over between the high and low reads.

Functional Description

214 Datasheet

5.18 USB EHCI Host Controllers (D29:F0 and D26:F0)

The PCH contains two Enhanced Host Controller Interface (EHCI) host controllers which

support up to fourteen USB 2.0 high-speed root ports. USB 2.0 allows data transfers up

to 480 Mb/s. USB 2.0 based Debug Port is also implemented in the PCH.

5.18.1 EHC Initialization

The following descriptions step through the expected PCH Enhanced Host Controller

(EHC) initialization sequence in chronological order, beginning with a complete power

cycle in which the suspend well and core well have been off.

5.18.1.1 BIOS Initialization

BIOS performs a number of platform customization steps after the core well has

powered up. Contact your Intel Field Representative for additional PCH BIOS

information.

5.18.1.2 Driver Initialization

See Chapter 4 of the Enhanced Host Controller Interface Specification for Universal

Serial Bus, Revision 1.0.

5.18.1.3 EHC Resets

In addition to the standard PCH hardware resets, portions of the EHC are reset by the

HCRESET bit and the transition from the D3HOT device power management state to the

D0 state. The effects of each of these resets are:

If the detailed register descriptions give exceptions to these rules, those exceptions

override these rules. This summary is provided to help explain the reasons for the reset

policies.

5.18.2 Data Structures in Main Memory

See Section 3 and Appendix B of the Enhanced Host Controller Interface Specification

for Universal Serial Bus, Revision 1.0 for details.

Reset Doe s Reset Does Not Reset Comments

HCRESET bit set.

Memory space registers

except Structural

Parameters (which is

written by BIOS).

Configuration

registers.

The HCRESET must only affect registers that

the EHCI driver controls. PCI Configuration

space and BIOS-programmed parameters

cannot be reset.

Software writes

the Device Power

State from D3HOT

(11b) to D0 (00b).

Core well registers

(except BIOS-

programmed registers).

Suspend well

registers; BIOS-

programmed core

well registers.

The D3-to-D0 transition must not cause

wake information (suspend well) to be lost.

It also must not clear BIOS-programmed

registers because BIOS may not be invoked

following the D3-to-D0 transition.

Datasheet 215

Functional Description

5.18.3 USB 2.0 Enhanced Host Controller DMA

The PCH USB 2.0 EHC implements three sources of USB packets. They are, in order of

priority on USB during each microframe:

1. The USB 2.0 Debug Port (see Section USB 2.0 Based Debug Port),

2. The Periodic DMA engine, and

3. The Asynchronous DMA engine.

The PCH always performs any currently-pending debug port transaction at the

beginning of a microframe, followed by any pending periodic traffic for the current

microframe. If there is time left in the microframe, then the EHC performs any pending

asynchronous traffic until the end of the microframe (EOF1). Note that the debug port

traffic is only presented on Port 1 and Port 9, while the other ports are idle during this

time.

5.18.4 Data Encoding and Bit Stuffing

See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.

5.18.5 Packet Formats

See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.

The PCH EHCI allows entrance to USB test modes, as defined in the USB 2.0

specification, including Test J, Test Packet, etc. However note that the PCH Test Packet

test mode interpacket gap timing may not meet the USB 2.0 specification.

5.18.6 USB 2.0 Interrupts and Error Conditions

Section 4 of the Enhanced Host Controller Interface Specification for Universal Serial

Bus, Revision 1.0 goes into detail on the EHC interrupts and the error conditions that

cause them. All error conditions that the EHC detects can be reported through the EHCI

Interrupt status bits. Only PCH-specific interrupt and error-reporting behavior is

documented in this section. The EHCI Interrupts Section must be read first, followed by

this section of the datasheet to fully comprehend the EHC interrupt and error-reporting

functionality.

• Based on the EHC Buffer sizes and buffer management policies, the Data Buffer

Error can never occur on the PCH.

• Master Abort and Target Abort responses from hub interface on EHC-initiated read

packets will be treated as Fatal Host Errors. The EHC halts when these conditions

are encountered.

• The PCH may assert the interrupts which are based on the interrupt threshold as

soon as the status for the last complete transaction in the interrupt interval has

been posted in the internal write buffers. The requirement in the Enhanced Host

Controller Interface Specification for Universal Serial Bus, Revision 1.0 (that the

status is written to memory) is met internally, even though the write may not be

seen on DMI before the interrupt is asserted.

• Since the PCH supports the 1024-element Frame List size, the Frame List Rollover

interrupt occurs every 1024 milliseconds.

• The PCH delivers interrupts using PIRQH#.

• The PCH does not modify the CERR count on an Interrupt IN when the “Do

Complete-Split” execution criteria are not met.

• For complete-split transactions in the Periodic list, the “Missed Microframe” bit does

not get set on a control-structure-fetch that fails the late-start test. If subsequent

accesses to that control structure do not fail the late-start test, then the “Missed

Microframe” bit will get set and written back.

Functional Description

216 Datasheet

5.18.6.1 Aborts on USB 2.0-Initiated Memory Reads

If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The

following actions are taken when this occurs:

• The Host System Error status bit is set.

• The DMA engines are halted after completing up to one more transaction on the

USB interface.

• If enabled (by the Host System Error Enable), then an interrupt is generated.

• If the status is Master Abort, then the Received Master Abort bit in configuration

space is set.

• If the status is Target Abort, then the Received Target Abort bit in configuration

space is set.

• If enabled (by the SERR Enable bit in the function’s configuration space), then the

Signaled System Error bit in configuration bit is set.

5.18.7 USB 2.0 Power Management

5.18.7.1 Pause Feature

This feature allows platforms to dynamically enter low-power states during brief

periods when the system is idle (that is, between keystrokes). This is useful for

enabling power management features in the PCH. The policies for entering these states

typically are based on the recent history of system bus activity to incrementally enter

deeper power management states. Normally, when the EHC is enabled, it regularly

accesses main memory while traversing the DMA schedules looking for work to do; this

activity is viewed by the power management software as a non-idle system, thus

preventing the power managed states to be entered. Suspending all of the enabled

ports can prevent the memory accesses from occurring, but there is an inherent

latency overhead with entering and exiting the suspended state on the USB ports that

makes this unacceptable for the purpose of dynamic power management. As a result,

the EHCI software drivers are allowed to pause the EHC DMA engines when it knows

that the traffic patterns of the attached devices can afford the delay. The pause only

prevents the EHC from generating memory accesses; the SOF packets continue to be

generated on the USB ports (unlike the suspended state).

5.18.7.2 Suspend Feature

The Enhanced Host Controller Interface (EHCI) For Universal Serial Bus Specification,

Section 4.3 describes the details of Port Suspend and Resume.

5.18.7.3 ACPI Device States

The USB 2.0 function only supports the D0 and D3 PCI Power Management states.

Notes regarding the PCH implementation of the Device States:

1. The EHC hardware does not inherently consume any more power when it is in the

D0 state than it does in the D3 state. However, software is required to suspend or

disable all ports prior to entering the D3 state such that the maximum power

consumption is reduced.

2. In the D0 state, all implemented EHC features are enabled.

3. In the D3 state, accesses to the EHC memory-mapped I/O range will master abort.

Note that, since the Debug Port uses the same memory range, the Debug Port is

only operational when the EHC is in the D0 state.

4. In the D3 state, the EHC interrupt must never assert for any reason. The internal

PME# signal is used to signal wake events, etc.

5. When the Device Power State field is written to D0 from D3, an internal reset is

generated. See section EHC Resets for general rules on the effects of this reset.

6. Attempts to write any other value into the Device Power State field other than 00b

(D0 state) and 11b (D3 state) will complete normally without changing the current

value in this field.

Datasheet 217

Functional Description

5.18.7.4 ACPI System States

The EHC behavior as it relates to other power management states in the system is

summarized in the following list:

• The System is always in the S0 state when the EHC is in the D0 state. However,

when the EHC is in the D3 state, the system may be in any power management

state (including S0).

• When in D0, the Pause feature (See Section 5.18.7.1) enables dynamic processor

low-power states to be entered.

• The PLL in the EHC is disabled when entering the S3/S4/S5 states (core power

turns off).

• All core well logic is reset in the S3/S4/S5 states.

5.18.8 USB 2.0 Legacy Keyboard Operation

The PCH must support the possibility of a keyboard downstream from either a full-

speed/low-speed or a high-speed port. The description of the legacy keyboard support

is unchanged from USB 1.1.

The EHC provides the basic ability to generate SMIs on an interrupt event, along with

more sophisticated control of the generation of SMIs.

5.18.9 USB 2.0 Based Debug Port

The PCH supports the elimination of the legacy COM ports by providing the ability for

new debugger software to interact with devices on a USB 2.0 port.

High-level restrictions and features are:

• Operational before USB 2.0 drivers are loaded.

• Functions even when the port is disabled.

• Allows normal system USB 2.0 traffic in a system that may only have one USB port.

• Debug Port device (DPD) must be high-speed capable and connect directly to Port 1

and Port 9 on PCH-based systems (such as, the DPD cannot be connected to

Port 1/Port 9 through a hub. When a DPD is detected the PCH EHCI will bypass the

integrated Rate Matching Hub and connect directly to the port and the DPD.).

• Debug Port FIFO always makes forward progress (a bad status on USB is simply

presented back to software).

• The Debug Port FIFO is only given one USB access per microframe.

The Debug port facilitates operating system and device driver debug. It allows the

software to communicate with an external console using a USB 2.0 connection.

Because the interface to this link does not go through the normal USB 2.0 stack, it

allows communication with the external console during cases where the operating

system is not loaded, the USB 2.0 software is broken, or where the USB 2.0 software is

being debugged. Specific features of this implementation of a debug port are:

• Only works with an external USB 2.0 debug device (console)

• Implemented for a specific port on the host controller

• Operational anytime the port is not suspended AND the host controller is in D0

power state.

• Capability is interrupted when port is driving USB RESET

Functional Description

218 Datasheet

5.18.9.1 Theory of Operation

There are two operational modes for the USB debug port:

1. Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard

host controller driver. In Mode 1, the Debug Port controller is required to generate a

“keepalive” packets less than 2 ms apart to keep the attached debug device from

suspending. The keepalive packet should be a standalone 32-bit SYNC field.

2. Mode 2 is when the host controller is running (that is, host controller’s Run/Stop#

bit is 1). In Mode 2, the normal transmission of SOF packets will keep the debug

device from suspending.

Behavioral Rules

1. In both modes 1 and 2, the Debug Port controller must check for software

requested debug transactions at least every 125 microseconds.

2. If the debug port is enabled by the debug driver, and the standard host controller

driver resets the USB port, USB debug transactions are held off for the duration of

the reset and until after the first SOF is sent.

3. If the standard host controller driver suspends the USB port, then USB debug

transactions are held off for the duration of the suspend/resume sequence and until

after the first SOF is sent.

4. The ENABLED_CNT bit in the debug register space is independent of the similar

port control bit in the associated Port Status and Control register.

Table 5 - 42 shows the debug port behavior related to the state of bits in the debug

registers as well as bits in the associated Port Status and Control register.

Table 5-42. Debug Port Behavior

OWNER_CNT ENABLED_CT Port

Enable

Run /

Stop Suspend De bug Port Behavior

0XXXX

Debug port is not being used. Normal

operation.

10XXX

Debug port is not being used. Normal

operation.

1100X

Debug port in Mode 1. SYNC keepalives sent

plus debug traffic

1101X

Debug port in Mode 2. SOF (and only SOF) is

sent as keepalive. Debug traffic is also sent.

Note that no other normal traffic is sent out

this port, because the port is not enabled.

11100

Invalid. Host controller driver should never

put controller into this state (enabled, not

running and not suspended).

1 1 1 0 1 Port is suspended. No debug traffic sent.

11110

Debug port in Mode 2. Debug traffic is

interspersed with normal traffic.

1 1 1 1 1 Port is suspended. No debug traffic sent.

Datasheet 219

Functional Description

5.18.9.1.1 OUT Transactions

An Out transaction sends data to the debug device. It can occur only when the

following are true:

• The debug port is enabled

• The debug software sets the GO_CNT bit

• The WRITE_READ#_CNT bit is set

The sequence of the transaction is:

1. Software sets the appropriate values in the following bits:

—USB_ADDRESS_CNF

—USB_ENDPOINT_CNF

— DATA_BUFFER[63:0]

— TOKEN_PID_CNT[7:0]

— SEND_PID_CNT[15:8]

—DATA_LEN_CNT

— WRITE_READ#_CNT: (Note: This will always be 1 for OUT transactions.)

— GO_CNT: (Note: This will always be 1 to initiate the transaction.)

2. The debug port controller sends a token packet consisting of:

—SYNC

— TOKEN_PID_CNT field

— USB_ADDRESS_CNT field

—USB_ENDPOINT_CNT field

— 5-bit CRC field

3. After sending the token packet, the debug port controller sends a data packet

consisting of:

—SYNC

— SEND_PID_CNT field

— The number of data bytes indicated in DATA_LEN_CNT from the DATA_BUFFER

— 16-bit CRC

NOTE: A DATA_LEN_CNT value of 0 is valid in which case no data bytes would be

included in the packet.

4. After sending the data packet, the controller waits for a handshake response from

the debug device.

— If a handshake is received, the debug port controller:

a. Places the received PID in the RECEIVED_PID_STS field

b. Resets the ERROR_GOOD#_STS bit

c. Sets the DONE_STS bit

— If no handshake PID is received, the debug port controller:

a. Sets the EXCEPTION_STS field to 001b

b. Sets the ERROR_GOOD#_STS bit

c. Sets the DONE_STS bit

Functional Description

220 Datasheet

5.18.9.1.2 IN Transactions

An IN transaction receives data from the debug device. It can occur only when the

following are true:

• The debug port is enabled

• The debug software sets the GO_CNT bit

• The WRITE_READ#_CNT bit is reset

The sequence of the transaction is:

1. Software sets the appropriate values in the following bits:

— USB_ADDRESS_CNF

—USB_ENDPOINT_CNF

— TOKEN_PID_CNT[7:0]

—DATA_LEN_CNT

— WRITE_READ#_CNT: (Note: This will always be 0 for IN transactions.)

— GO_CNT: (Note: This will always be 1 to initiate the transaction.)

2. The debug port controller sends a token packet consisting of:

—SYNC

— TOKEN_PID_CNT field

— USB_ADDRESS_CNT field

— USB_ENDPOINT_CNT field

— 5-bit CRC field.

3. After sending the token packet, the debug port controller waits for a response from

the debug device.

If a response is received:

— The received PID is placed into the RECEIVED_PID_STS field

— Any subsequent bytes are placed into the DATA_BUFFER

— The DATA_LEN_CNT field is updated to show the number of bytes that were

received after the PID.

4. If a valid packet was received from the device that was one byte in length

(indicating it was a handshake packet), then the debug port controller:

— Resets the ERROR_GOOD#_STS bit

— Sets the DONE_STS bit

5. If a valid packet was received from the device that was more than one byte in

length (indicating it was a data packet), then the debug port controller:

— Transmits an ACK handshake packet

— Resets the ERROR_GOOD#_STS bit

— Sets the DONE_STS bit

6. If no valid packet is received, then the debug port controller:

— Sets the EXCEPTION_STS field to 001b

— Sets the ERROR_GOOD#_STS bit

— Sets the DONE_STS bit.

Datasheet 221

Functional Description

5.18.9.1.3 Debug Software

Enabling the Debug Port

There are two mutually exclusive conditions that debug software must address as part

of its startup processing:

• The EHCI has been initialized by system software

• The EHCI has not been initialized by system software

Debug software can determine the current ‘initialized’ state of the EHCI by examining

the Configure Flag in the EHCI USB 2.0 Command Register. If this flag is set, then

system software has initialized the EHCI. Otherwise, the EHCI should not be considered

initialized. Debug software will initialize the debug port registers depending on the

state of the EHCI. However, before this can be accomplished, debug software must

determine which root USB port is designated as the debug port.

Determining the Debug Port

Debug software can easily determine which USB root port has been designated as the

debug port by examining bits 20:23 of the EHCI Host Controller Structural Parameters

is, 0001=port 1).

Debug Software Startup with Non-Initialized EHCI

Debug software can attempt to use the debug port if after setting the OWNER_CNT bit,

the Current Connect Status bit in the appropriate (See Determining the Debug Port

Presence) PORTSC register is set. If the Current Connect Status bit is not set, then

debug software may choose to terminate or it may choose to wait until a device is

connected.

If a device is connected to the port, then debug software must reset/enable the port.

Debug software does this by setting and then clearing the Port Reset bit the PORTSC

clearing the Port Reset bit. Due to possible delays, this bit may not change to 0

immediately; reset is complete when this bit reads as 0. Software must not continue

until this bit reads 0.

If a high-speed device is attached, the EHCI will automatically set the Port Enabled/

Disabled bit in the PORTSC register and the debug software can proceed. Debug

software should set the ENABLED_CNT bit in the Debug Port Control/Status register,

and then reset (clear) the Port Enabled/Disabled bit in the PORTSC register (so that the

system host controller driver does not see an enabled port when it is first loaded).

Debug Software Startup with Initialized EHCI

Debug software can attempt to use the debug port if the Current Connect Status bit in

the appropriate (See Determining the Debug Port) PORTSC register is set. If the

Current Connect Status bit is not set, then debug software may choose to terminate or

it may choose to wait until a device is connected.

If a device is connected, then debug software must set the OWNER_CNT bit and then

the ENABLED_CNT bit in the Debug Port Control/Status register.

Functional Description

222 Datasheet

Determining Debug Peripheral Presence

After enabling the debug port functionality, debug software can determine if a debug

peripheral is attached by attempting to send data to the debug peripheral. If all

attempts result in an error (Exception bits in the Debug Port Control/Status register

indicates a Transaction Error), then the attached device is not a debug peripheral. If the

debug port peripheral is not present, then debug software may choose to terminate or

it may choose to wait until a debug peripheral is connected.

5.18.10 EHCI Caching

EHCI Caching is a power management feature in the USB (EHCI) host controllers which

enables the controller to execute the schedules entirely in cache and eliminates the

need for the DMA engine to access memory when the schedule is idle. EHCI caching

allows the processor to maintain longer C-state residency times and provides

substantial system power savings.

5.18.11 Intel® USB Pre-Fetch Based Pause

The Intel USB Pre-Fetch Based Pause is a power management feature in USB (EHCI)

host controllers to ensure maximum C3/C4 processor power state time with C2 popup.

This feature applies to the period schedule, and works by allowing the DMA engine to

identify periods of idleness and preventing the DMA engine from accessing memory

when the periodic schedule is idle. Typically in the presence of periodic devices with

multiple millisecond poll periods, the periodic schedule will be idle for several frames

between polls.

The Intel USB Pre-Fetch Based Pause feature is disabled by setting bit 4 of EHCI

Configuration Register Section 16.2.1.

5.18.12 Function Level Reset Support (FLR)

The USB EHCI Controllers support the Function Level Reset (FLR) capability. The FLR

capability can be used in conjunction with Intel® Virtualization Technology. FLR allows

an Operating System in a Virtual Machine to have complete control over a device,

including its initialization, without interfering with the rest of the platform. The device

provides a software interface that enables the Operating System to reset the whole

device as if a PCI reset was asserted.

5.18.12.1 FLR Steps

5.18.12.1.1 FLR Initialization

1. A FLR is initiated by software writing a ‘1’ to the Initiate FLR bit.

2. All subsequent requests targeting the Function will not be claimed and will be

Master Abort Immediate on the bus. This includes any configuration, I/O or

Memory cycles, however, the Function shall continue to accept completions

targeting the Function.

Datasheet 223

Functional Description

5.18.12.1.2 FLR Operation

The Function will Reset all configuration, I/O and memory registers of the Function

except those indicated otherwise and reset all internal states of the Function to the

default or initial condition.

5.18.12.1.3 FLR Completion

The Initiate FLR bit is reset (cleared) when the FLR reset is completed. This bit can be

used to indicate to the software that the FLR reset is completed.

Note: From the time Initiate FLR bit is written to 1, software must wait at least 100 ms before

accessing the function.

5.18.13 USB Overcurrent Protection

The PCH has implemented programmable USB Overcurrent signals. The PCH provides a

total of 8 overcurrent pins to be shared across the 14 ports.

Four overcurrent signals have been allocated to the ports in each USB Device:

• OC[3:0]# for Device 29 (Ports 0-7)

• OC[7:4]# for Device 26 (Ports 8-13)

Each pin is mapped to one or more ports by setting bits in the USBOCM1 and USBOCM2

registers. See Section 10.1.51 and Section 10.1.52. It is system BIOS’ responsibility to

ensure that each port is mapped to only one over current pin. Operation with more

than one overcurrent pin mapped to a port is undefined. It is expected that multiple

ports are mapped to a single overcurrent pin, however they should be connected at the

port and not at the PCH pin. Shorting these pins together may lead to reduced test

capabilities. By default, two ports are routed to each of the OC[6:0]# pins. OC7# is not

used by default.

NOTES:

1. All USB ports routed out of the package must have Overcurrent protection. It is

system BIOS responsibility to ensure all used ports have OC protection

2. USB Ports that are unused on the system (not routed out from the package) should

not have OC pins assigned to them

Functional Description

224 Datasheet

5.19 Integrated USB 2.0 Rate Matching Hub

5.19.1 Overview

The PCH has integrated two USB 2.0 Rate Matching Hubs (RMH). One hub is connected

to each of the EHCI controllers as shown in Figure 5-10. The Hubs convert low and full-

speed traffic into high-speed traffic. When the RMHs are enabled, they will appear to

software like an external hub is connected to Port 0 of each EHCI controller. In addition,

port 1 of each of the RMHs is multiplexed with Port 1 of the EHCI controllers and is able

to bypass the RMH for use as the Debug Port.

The hub operates like any USB 2.0 Discrete Hub and will consume one tier of hubs

allowed by the USB 2.0 Specification. section 4.1.1. A maximum of four additional non-

root hubs can be supported on any of the PCH USB Ports. The RMH will report the

following Vendor ID = 8087h and Product ID = 0024h.

5.19.2 Architecture

A hub consists of three components: the Hub Repeater, the Hub Controller, and the

Transaction Translator.

1. The Hub Repeater is responsible for connectivity setup and tear-down. It also

supports exception handling, such as bus fault detection and recovery and connect/

disconnect detect.

2. The Hub Controller provides the mechanism for host-to-hub communication. Hub-

specific status and control commands permit the host to configure a hub and to

monitor and control its individual downstream facing ports.

3. The Transaction Translator (TT) responds to high-speed split transactions and

translates them to full-/low-speed transactions with full-/low-speed devices

attached on downstream facing ports. There is 1 TT per RMH in the PCH.

See chapter 11 of the USB 2.0 Specification for more details on the architecture of the

hubs.

Figure 5-10. EHCI with USB 2.0 with Rate Matching Hub

Datasheet 225

Functional Description

5.20 SMBus Controller (D31:F3)

The PCH provides an System Management Bus (SMBus) 2.0 host controller as well as

an SMBus Slave Interface. The host controller provides a mechanism for the processor

to initiate communications with SMBus peripherals (slaves). The PCH is also capable of

operating in a mode in which it can communicate with I2C compatible devices.

The PCH can perform SMBus messages with either packet error checking (PEC) enabled

or disabled. The actual PEC calculation and checking is performed in hardware by the

PCH.

The Slave Interface allows an external master to read from or write to the PCH. Write

cycles can be used to cause certain events or pass messages, and the read cycles can

be used to determine the state of various status bits. The PCH’s internal host controller

cannot access the PCH’s internal Slave Interface.

The PCH SMBus logic exists in Device 31:Function 3 configuration space, and consists

of a transmit data path, and host controller. The transmit data path provides the data

flow logic needed to implement the seven different SMBus command protocols and is

controlled by the host controller. The PCH’s SMBus controller logic is clocked by RTC

clock.

The SMBus Address Resolution Protocol (ARP) is supported by using the existing host

controller commands through software, except for the new Host Notify command

(which is actually a received message).

The programming model of the host controller is combined into two portions: a PCI

configuration portion, and a system I/O mapped portion. All static configuration, such

as the I/O base address, is done using the PCI configuration space. Real-time

programming of the Host interface is done in system I/O space.

The PCH SMBus host controller checks for parity errors as a target. If an error is

detected, the detected parity error bit in the PCI Status Register (Device 31:Function

3:Offset 06h:Bit 15) is set. If Bit 6 and Bit 8 of the PCI Command Register (Device

31:Function 3:Offset 04h) are set, an SERR# is generated and the signaled SERR# bit

in the PCI Status Register (bit 14) is set.

5.20.1 Host Controller

The SMBus host controller is used to send commands to other SMBus slave devices.

Software sets up the host controller with an address, command, and, for writes, data

and optional PEC; and then tells the controller to start. When the controller has finished

transmitting data on writes, or receiving data on reads, it generates an SMI# or

interrupt, if enabled.

The host controller supports 8 command protocols of the SMBus interface (see System

Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte,

Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, Block

Write–Block Read Process Call, and Host Notify.

The SMBus host controller requires that the various data and command fields be setup

for the type of command to be sent. When software sets the START bit, the SMBus Host

controller performs the requested transaction, and interrupts the processor (or

generates an SMI#) when the transaction is completed. Once a START command has

been issued, the values of the “active registers” (Host Control, Host Command,

Transmit Slave Address, Data 0, Data 1) should not be changed or read until the

interrupt status message (INTR) has been set (indicating the completion of the

command). Any register values needed for computation purposes should be saved prior

to issuing of a new command, as the SMBus host controller updates all registers while

completing the new command.

Functional Description

226 Datasheet

The PCH supports the System Management Bus (SMBus) Specification, Version 2.0.

Slave functionality, including the Host Notify protocol, is available on the SMBus pins.

The SMLink and SMBus signals can be tied together externally depending on TCO mode

used. Refer to Section 5.14.2 for more details.

Using the SMB host controller to send commands to the PCH SMB slave port is not

supported.

5.20.1.1 Command Protocols

In all of the following commands, the Host Status Register (offset 00h) is used to

determine the progress of the command. While the command is in operation, the

HOST_BUSY bit is set. If the command completes successfully, the INTR bit will be set

in the Host Status Register. If the device does not respond with an acknowledge, and

the transaction times out, the DEV_ERR bit is set. If software sets the KILL bit in the

Host Control Register while the command is running, the transaction will stop and the

FAILED bit will be set.

Quick Command

When programmed for a Quick Command, the Transmit Slave Address Register is sent.

The PEC byte is never appended to the Quick Protocol. Software should force the

PEC_EN bit to 0 when performing the Quick Command. Software must force the

I2C_EN bit to 0 when running this command. See section 5.5.1 of the System

Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.

Send Byte / Receive Byte

For the Send Byte command, the Transmit Slave Address and Device Command

Registers are sent. For the Receive Byte command, the Transmit Slave Address Register

is sent. The data received is stored in the DATA0 register. Software must force the

I2C_EN bit to 0 when running this command.

The Receive Byte is similar to a Send Byte, the only difference is the direction of data

transfer. See sections 5.5.2 and 5.5.3 of the System Management Bus (SMBus)

Specification, Version 2.0 for the format of the protocol.

Write Byte/Word

The first byte of a Write Byte/Word access is the command code. The next 1 or 2 bytes

are the data to be written. When programmed for a Write Byte/Word command, the

Transmit Slave Address, Device Command, and Data0 Registers are sent. In addition,

the Data1 Register is sent on a Write Word command. Software must force the I2C_EN

bit to 0 when running this command. See section 5.5.4 of the System Management Bus

(SMBus) Specification, Version 2.0 for the format of the protocol.

Read Byte/Word

Reading data is slightly more complicated than writing data. First the PCH must write a

command to the slave device. Then it must follow that command with a repeated start

condition to denote a read from that device's address. The slave then returns 1 or 2

bytes of data. Software must force the I2C_EN bit to 0 when running this command.

When programmed for the read byte/word command, the Transmit Slave Address and

Device Command Registers are sent. Data is received into the DATA0 on the read byte,

and the DAT0 and DATA1 registers on the read word. See section 5.5.5 of the System

Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.

Datasheet 227

Functional Description

Process Call

The process call is so named because a command sends data and waits for the slave to

return a value dependent on that data. The protocol is simply a Write Word followed by

a Read Word, but without a second command or stop condition.

When programmed for the Process Call command, the PCH transmits the Transmit

Slave Address, Host Command, DATA0 and DATA1 registers. Data received from the

device is stored in the DATA0 and DATA1 registers. The Process Call command with

I2C_EN set and the PEC_EN bit set produces undefined results. Software must force

either I2C_EN or PEC_EN to 0 when running this command. See section 5.5.6 of the

System Management Bus (SMBus) Specification, Version 2.0 for the format of the

protocol.

Note: For process call command, the value written into bit 0 of the Transmit Slave Address

Note: If the I2C_EN bit is set, the protocol sequence changes slightly: the Command Code

(Bits 18:11 in the bit sequence) are not sent - as a result, the slave will not

acknowledge (Bit 19 in the sequence).

Block Read/Write

The PCH contains a 32-byte buffer for read and write data which can be enabled by

setting bit 1 of the Auxiliary Control register at offset 0Dh in I/O space, as opposed to a

single byte of buffering. This 32-byte buffer is filled with write data before

transmission, and filled with read data on reception. In the PCH, the interrupt is

generated only after a transmission or reception of 32 bytes, or when the entire byte

count has been transmitted/received.

Note: When operating in I2C mode (I2C_EN bit is set), the PCH will never use the 32-byte

buffer for any block commands.

The byte count field is transmitted but ignored by the PCH as software will end the

transfer after all bytes it cares about have been sent or received.

For a Block Write, software must either force the I2C_EN bit or both the PEC_EN and

AAC bits to 0 when running this command.

The block write begins with a slave address and a write condition. After the command

code the PCH issues a byte count describing how many more bytes will follow in the

message. If a slave had 20 bytes to send, the first byte would be the number 20 (14h),

followed by 20 bytes of data. The byte count may not be 0. A Block Read or Write is

allowed to transfer a maximum of 32 data bytes.

When programmed for a block write command, the Transmit Slave Address, Device

Command, and Data0 (count) registers are sent. Data is then sent from the Block Data

Byte register; the total data sent being the value stored in the Data0 Register. On block

read commands, the first byte received is stored in the Data0 register, and the

remaining bytes are stored in the Block Data Byte register. See section 5.5.7 of the

System Management Bus (SMBus) Specification, Version 2.0 for the format of the

protocol.

Note: For Block Write, if the I2C_EN bit is set, the format of the command changes slightly.

The PCH will still send the number of bytes (on writes) or receive the number of bytes

(on reads) indicated in the DATA0 register. However, it will not send the contents of the

DATA0 register as part of the message. Also, the Block Write protocol sequence

changes slightly: the Byte Count (bits 27:20 in the bit sequence) are not sent – as a

result, the slave will not acknowledge (bit 28 in the sequence).

Functional Description

228 Datasheet

I2C Read

This command allows the PCH to perform block reads to certain I2C devices, such as

serial E2PROMs. The SMBus Block Read supports the 7-bit addressing mode only.

However, this does not allow access to devices using the I2C “Combined Format” that

has data bytes after the address. Typically these data bytes correspond to an offset

(address) within the serial memory chips.

Note: This command is supported independent of the setting of the I2C_EN bit. The I2C Read

command with the PEC_EN bit set produces undefined results. Software must force

both the PEC_EN and AAC bit to 0 when running this command.

For I2C Read command, the value written into bit 0 of the Transmit Slave Address

The format that is used for the command is shown in Table 5 - 4 3.

The PCH will continue reading data from the peripheral until the NAK is received.

Table 5-43. I2C Block Read

Bit Description

1Start

8:2 Slave Address – 7 bits

9Write

10 Acknowledge from slave

18:11 Send DATA1 register

19 Acknowledge from slave

20 Repeated Start

27:21 Slave Address – 7 bits

28 Read

29 Acknowledge from slave

37:30 Data byte 1 from slave – 8 bits

38 Acknowledge

46:39 Data byte 2 from slave – 8 bits

47 Acknowledge

– Data bytes from slave / Acknowledge

– Data byte N from slave – 8 bits

– NOT Acknowledge

–Stop

Datasheet 229

Functional Description

Block Write–Block Read Process Call

The block write-block read process call is a two-part message. The call begins with a

slave address and a write condition. After the command code the host issues a write

byte count (M) that describes how many more bytes will be written in the first part of

the message. If a master has 6 bytes to send, the byte count field will have the value 6

(0000 0110b), followed by the 6 bytes of data. The write byte count (M) cannot be 0.

The second part of the message is a block of read data beginning with a repeated start

condition followed by the slave address and a Read bit. The next byte is the read byte

count (N), which may differ from the write byte count (M). The read byte count (N)

cannot be 0.

The combined data payload must not exceed 32 bytes. The byte length restrictions of

this process call are summarized as follows:

•M  1 byte

•N  1 byte

•M + N  32 bytes

The read byte count does not include the PEC byte. The PEC is computed on the total

message beginning with the first slave address and using the normal PEC

computational rules. It is highly recommended that a PEC byte be used with the Block

Write-Block Read Process Call. Software must do a read to the command register

(offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register.

Note that there is no STOP condition before the repeated START condition, and that a

NACK signifies the end of the read transfer.

Note: E32B bit in the Auxiliary Control register must be set when using this protocol.

See section 5.5.8 of the System Management Bus (SMBus) Specification, Version 2.0

for the format of the protocol.

5.20.2 Bus Arbitration

Several masters may attempt to get on the bus at the same time by driving the

SMBDATA line low to signal a start condition. The PCH continuously monitors the

SMBDATA line. When the PCH is attempting to drive the bus to a 1 by letting go of the

SMBDATA line, and it samples SMBDATA low, then some other master is driving the bus

and the PCH will stop transferring data.

If the PCH sees that it has lost arbitration, the condition is called a collision. The PCH

will set the BUS_ERR bit in the Host Status Register, and if enabled, generate an

interrupt or SMI#. The processor is responsible for restarting the transaction.

When the PCH is a SMBus master, it drives the clock. When the PCH is sending address

or command as an SMBus master, or data bytes as a master on writes, it drives data

relative to the clock it is also driving. It will not start toggling the clock until the start or

stop condition meets proper setup and hold time. The PCH will also ensure minimum

time between SMBus transactions as a master.

Note: The PCH supports the same arbitration protocol for both the SMBus and the System

Management (SMLink) interfaces.

Functional Description

230 Datasheet

5.20.3 Bus Timing

5.20.3.1 Clock Stretching

Some devices may not be able to handle their clock toggling at the rate that the PCH as

an SMBus master would like. They have the capability of stretching the low time of the

clock. When the PCH attempts to release the clock (allowing the clock to go high), the

clock will remain low for an extended period of time.

The PCH monitors the SMBus clock line after it releases the bus to determine whether

to enable the counter for the high time of the clock. While the bus is still low, the high

time counter must not be enabled. Similarly, the low period of the clock can be

stretched by an SMBus master if it is not ready to send or receive data.

5.20.3.2 Bus Time Out (The PCH as SMBus Master)

If there is an error in the transaction, such that an SMBus device does not signal an

acknowledge, or holds the clock lower than the allowed time-out time, the transaction

will time out. The PCH will discard the cycle and set the DEV_ERR bit. The time out

minimum is 25 ms (800 RTC clocks). The time-out counter inside the PCH will start

after the last bit of data is transferred by the PCH and it is waiting for a response.

The 25-ms time-out counter will not count under the following conditions:

1. BYTE_DONE_STATUS bit (SMBus I/O Offset 00h, Bit 7) is set

2. The SECOND_TO_STS bit (TCO I/O Offset 06h, Bit 1) is not set (this indicates that

the system has not locked up).

5.20.4 Interrupts / SMI#

The PCH SMBus controller uses PIRQB# as its interrupt pin. However, the system can

alternatively be set up to generate SMI# instead of an interrupt, by setting the

SMBUS_SMI_EN bit (Device 31:Function 0:Offset 40h:Bit 1).

Table 5 - 45 and Tab l e 5-46 specify how the various enable bits in the SMBus function

control the generation of the interrupt, Host and Slave SMI, and Wake internal signals.

The rows in the tables are additive, which means that if more than one row is true for a

particular scenario then the Results for all of the activated rows will occur.

Table 5-44. Enable for SMBALERT#

Event

INTREN (Host

Control I/O

02h, Bit 0)

SMB_SMI_EN

(Host

Configuration

D31:F3:Offset 40h,

Bit 1)

SMBALERT_DIS

(Slave Command I/

O Register, Offset

11h, Bit 2)

Result

SMBALERT#

asserted low

(always reported in

Host Status

XX XWake generated

X1 0

Slave SMI# generated

(SMBUS_SMI_STS)

1 0 0 Interrupt generated

Datasheet 231

Functional Description

5.20.5 SMBALERT#

SMBALERT# is multiplexed with GPIO[11]. When enable and the signal is asserted, the

PCH can generate an interrupt, an SMI#, or a wake event from S1–S5.

5.20.6 SMBus CRC Generation and Checking

If the AAC bit is set in the Auxiliary Control register, the PCH automatically calculates

and drives CRC at the end of the transmitted packet for write cycles, and will check the

CRC for read cycles. It will not transmit the contents of the PEC register for CRC. The

PEC bit must not be set in the Host Control register if this bit is set, or unspecified

behavior will result.

If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the

Auxiliary Status register at Offset 0Ch will be set.

Table 5-45. Enables for SMBus Slave Write and SMBus Host Events

Event

INTREN (Host

Control I/O Register,

Offset 02h, Bit 0)

SMB_SMI_EN (Host

Configuration Register,

D31:F3:Offset 40h,

Bit 1)

Event

Slave Write to Wake/

SMI# Command XX

Wake generated when asleep.

Slave SMI# generated when

awake (SMBUS_SMI_STS).

Slave Write to

SMLINK_SLAVE_SMI

Command

Slave SMI# generated when in

the S0 state (SMBUS_SMI_STS)

Any combination of Host

Status Register [4:1]

asserted

0XNone

1 0 Interrupt generated

11Host SMI# generated

Table 5-46. Enables for the Host Notify Command

HOST_NOTIFY_INTRE

N (Slave Control I/O

Bit 0)

SMB_SMI_EN (Host

Config Register,

D31:F3:Off40h,

Bit 1)

HOST_NOTIFY_WKEN

(Slave Control I/O

Bit 1)

Result

0X0None

XX 1Wake generated

1 0 X Interrupt generated

11X

Slave SMI# generated

(SMBUS_SMI_STS)

Functional Description

232 Datasheet

5.20.7 SMBus Slave Interface

The PCH SMBus Slave interface is accessed using the SMBus. The SMBus slave logic will

not generate or handle receiving the PEC byte and will only act as a Legacy Alerting

Protocol device. The slave interface allows the PCH to decode cycles, and allows an

external microcontroller to perform specific actions. Key features and capabilities

include:

• Supports decode of three types of messages: Byte Write, Byte Read, and Host

Notify.

• Receive Slave Address register: This is the address that the PCH decodes. A default

value is provided so that the slave interface can be used without the processor

having to program this register.

• Receive Slave Data register in the SMBus I/O space that includes the data written

by the external microcontroller.

• Registers that the external microcontroller can read to get the state of the PCH.

• Status bits to indicate that the SMBus slave logic caused an interrupt or SMI# due

to the reception of a message that matched the slave address.

— Bit 0 of the Slave Status Register for the Host Notify command

— Bit 16 of the SMI Status Register (Section 13.8.3.8) for all others

Note: The external microcontroller should not attempt to access the PCH SMBus slave logic

until either:

— 800 milliseconds after both: RTCRST# is high and RSMRST# is high, OR

— The PLTRST# deasserts

If a master leaves the clock and data bits of the SMBus interface at 1 for 50 µs or more

in the middle of a cycle, the PCH slave logic's behavior is undefined. This is interpreted

as an unexpected idle and should be avoided when performing management activities

to the slave logic.

Note: When an external microcontroller accesses the SMBus Slave Interface over the SMBus

a translation in the address is needed to accommodate the least significant bit used for

read/write control. For example, if the PCH slave address (RCV_SLVA) is left at 44h

(default), the external micro controller would use an address of 88h/89h (write/read).

Datasheet 233

Functional Description

5.20.7.1 Format of Slave Write Cycle

The external master performs Byte Write commands to the PCH SMBus Slave I/F. The

“Command” field (bits 11:18) indicate which register is being accessed. The Data field

(bits 20:27) indicate the value that should be written to that register.

Ta b l e 5 - 4 7 has the values associated with the registers.

NOTE: The external microcontroller is responsible to make sure that it does not update the

contents of the data byte registers until they have been read by the system processor. The

PCH overwrites the old value with any new value received. A race condition is possible

where the new value is being written to the register just at the time it is being read. The

PCH will not attempt to cover this race condition (that is, unpredictable results in this

case).

Table 5-47. Slave Write Registers

0Command Register. See Ta b l e 5 - 4 8 for legal values written to this register.

1–3 Reserved

4 Data Message Byte 0

5 Data Message Byte 1

6–7 Reserved

8 Reserved

9–FFh Reserved

Table 5-48. Command Types (Sheet 1 of 2)

Command

Type Description

0 Reserved

WAKE/SMI#. This command wakes the system if it is not already awake. If

system is already awake, an SMI# is generated.

NOTE: The SMB_WAK_STS bit will be set by this command, even if the system

is already awake. The SMI handler should then clear this bit.

2Unconditional Powerdown. This command sets the PWRBTNOR_STS bit,

and has the same effect as the Powerbutton Override occurring.

HARD RESET WITHOUT CYCLING: This command causes a hard reset of the

system (does not include cycling of the power supply). This is equivalent to a

write to the CF9h register with Bits 2:1 set to 1, but Bit 3 set to 0.

HARD RESET SYSTEM. This command causes a hard reset of the system

(including cycling of the power supply). This is equivalent to a write to the

CF9h register with Bits 3:1 set to 1.

Disable the TCO Messages. This command will disable the PCH from sending

Heartbeat and Event messages (as described in Section 5.14). Once this

command has been executed, Heartbeat and Event message reporting can

only be re-enabled by assertion and deassertion of the RSMRST# signal.

6WD RELOAD: Reload watchdog timer.

7 Reserved

Functional Description

234 Datasheet

5.20.7.2 Format of Read Command

The external master performs Byte Read commands to the PCH SMBus Slave interface.

The “Command” field (bits 18:11) indicate which register is being accessed. The Data

field (bits 30:37) contain the value that should be read from that register.

SMLINK_SLV_SMI. When the PCH detects this command type while in the S0

state, it sets the SMLINK_SLV_SMI_STS bit (see Section 13.9.5). This

command should only be used if the system is in an S0 state. If the message is

received during S1–S5 states, the PCH acknowledges it, but the

SMLINK_SLV_SMI_STS bit does not get set.

NOTE: It is possible that the system transitions out of the S0 state at the

same time that the SMLINK_SLV_SMI command is received. In this

case, the SMLINK_SLV_SMI_STS bit may get set but not serviced

before the system goes to sleep. Once the system returns to S0, the

SMI associated with this bit would then be generated. Software must

be able to handle this scenario.

9–FFh Reserved.

Table 5-48. Command Types (Sheet 2 of 2)

Command

Type Description

Table 5-49. Slave Read Cycle Format

Bit Description Driven by Comment

1 Start External Microcontroller

2-8 Slave Address - 7 bits External Microcontroller Must match value in Receive Slave

Address register

9 Write External Microcontroller Always 0

10 ACK PCH

11-18 Command code – 8 bits External Microcontroller

Indicates which register is being

accessed. See Ta b l e 5 - 5 0 for a list

of implemented registers.

19 ACK PCH

20 Repeated Start External Microcontroller

21-27 Slave Address - 7 bits External Microcontroller Must match value in Receive Slave

Address register

28 Read External Microcontroller Always 1

29 ACK PCH

30-37 Data Byte PCH

Value depends on register being

accessed. See Ta b l e 5 - 5 0 for a list

of implemented registers.

38 NOT ACK External Microcontroller

39 Stop External Microcontroller

Datasheet 235

Functional Description

Table 5-50. Data Values for Slave Read Registers (Sheet 1 of 2)

07:0

Reserved for capabilities indication. Should always return 00h. Future

chips may return another value to indicate different capabilities.

12:0

System Power State

000 = S0 001 = S1 010 = Reserved 011 = S3

100 = S4 101 = S5 110 = Reserved 111 = Reserved

7:3 Reserved

23:0 Reserved

7:4 Reserved

35:0

Watchdog Timer current value Note that Watchdog Timer has 10 bits,

but this field is only 6 bits. If the current value is greater than 3Fh, the

PCH will always report 3Fh in this field.

7:6 Reserved

01 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the

system cover has probably been opened.

11 = BTI Temperature Event occurred. This bit will be set if the PCH’s

THRM# input signal is active. Else this bit will read “0.”

2 DOA Processor Status. This bit will be 1 to indicate that the processor is

dead

31 = SECOND_TO_STS bit set. This bit will be set after the second time-

out (SECOND_TO_STS bit) of the Watchdog Timer occurs.

6:4 Reserved. Will always be 0, but software should ignore.

Reflects the value of the GPIO[11]/SMBALERT# pin (and is dependent

upon the value of the GPI_INV[11] bit. If the GPI_INV[11] bit is 1, then

the value in this bit equals the level of the GPI[11]/SMBALERT# pin

(high = 1, low = 0).

If the GPI_INV[11] bit is 0, then the value of this bit will equal the inverse

of the level of the GPIO[11]/SMBALERT# pin (high = 0, low = 1).

0 FWH bad bit. This bit will be 1 to indicate that the FWH read returned

FFh, which indicates that it is probably blank.

1 Reserved

2SYS_PWROK Failure Status: This bit will be 1 if the SYSPWR_FLR bit in

the GEN_PMCON_2 register is set.

INIT3_3V# due to receiving Shutdown message: This event is

visible from the reception of the shutdown message until a platform reset

is done if the Shutdown Policy Select bit (SPS) is configured to drive

INIT3_3V#. When the SPS bit is configured to generate PLTRST# based

on shutdown, this register bit will always return 0.

Events on signal will not create a event message

4Reserved

POWER_OK_BAD: Indicates the failure core power well ramp during

boot/resume. This bit will be active if the SLP_S3# pin is deasserted and

PWROK pin is not asserted.

Thermal Trip: This bit will shadow the state of processor Thermal Trip

status bit (CTS) (16.2.1.2, GEN_PMCON_2, bit 3). Events on signal will

not create a event message

Reserved: Default value is “X”

NOTE: Software should not expect a consistent value when this bit is read

through SMBUS/SMLink

Functional Description

236 Datasheet

5.20.7.2.1 Behavioral Notes

According to SMBus protocol, Read and Write messages always begin with a Start bit –

Address– Write bit sequence. When the PCH detects that the address matches the

value in the Receive Slave Address register, it will assume that the protocol is always

followed and ignore the Write bit (Bit 9) and signal an Acknowledge during bit 10. In

other words, if a Start –Address–Read occurs (which is illegal for SMBus Read or Write

protocol), and the address matches the PCH’s Slave Address, the PCH will still grab the

cycle.

Also according to SMBus protocol, a Read cycle contains a Repeated Start–Address–

Read sequence beginning at Bit 20. Once again, if the Address matches the PCH’s

Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and

proceed with the Slave Read cycle.

Note: An external microcontroller must not attempt to access the PCH’s SMBus Slave logic

until at least 1 second after both RTCRST# and RSMRST# are deasserted (high).

5.20.7.3 Slave Read of RTC Time Bytes

The PCH SMBus slave interface allows external SMBus master to read the internal RTC’s

time byte registers.

The RTC time bytes are internally latched by the PCH’s hardware whenever RTC time is

not changing and SMBus is idle. This ensures that the time byte delivered to the slave

read is always valid and it does not change when the read is still in progress on the bus.

The RTC time will change whenever hardware update is in progress, or there is a

software write to the RTC time bytes.

The PCH SMBus slave interface only supports Byte Read operation. The external SMBus

master will read the RTC time bytes one after another. It is software’s responsibility to

check and manage the possible time rollover when subsequent time bytes are read.

67:0

Contents of the Message 1 register. Refer to Section 13.9.8 for the

description of this register.

77:0

Contents of the Message 2 register. Refer to Section 13.9.8 for the

description of this register.

87:0

Contents of the TCO_WDCNT register. Refer to Section 13.9.9 for the

description of this register.

9 7:0 Seconds of the RTC

A 7:0 Minutes of the RTC

B7:0Hours of the RTC

C 7:0 “Day of Week” of the RTC

D 7:0 “Day of Month” of the RTC

E 7:0 Month of the RTC

F7:0Year of the RTC

10h–FFh 7:0 Reserved

Table 5-50. Data Values for Slave Read Registers (Sheet 2 of 2)

Datasheet 237

Functional Description

For example, assuming the RTC time is 11 hours: 59 minutes: 59 seconds. When the

external SMBus master reads the hour as 11, then proceeds to read the minute, it is

possible that the rollover happens between the reads and the minute is read as 0. This

results in 11 hours: 0 minute instead of the correct time of 12 hours: 0 minutes. Unless

it is certain that rollover will not occur, software is required to detect the possible time

rollover by reading multiple times such that the read time bytes can be adjusted

accordingly if needed.

5.20.7.4 Format of Host Notify Command

The PCH tracks and responds to the standard Host Notify command as specified in the

System Management Bus (SMBus) Specification, Version 2.0. The host address for this

command is fixed to 0001000b. If the PCH already has data for a previously-received

host notify command which has not been serviced yet by the host software (as

indicated by the HOST_NOTIFY_STS bit), then it will NACK following the host address

byte of the protocol. This allows the host to communicate non-acceptance to the

master and retain the host notify address and data values for the previous cycle until

host software completely services the interrupt.

Note: Host software must always clear the HOST_NOTIFY_STS bit after completing any

necessary reads of the address and data registers.

Ta b l e 5 - 5 1 shows the Host Notify format.

Table 5-51. Host Notify Format

Bit Description Driven By Comment

1 Start External Master

8:2 SMB Host Address – 7 bits External Master Always 0001_000

9 Write External Master Always 0

10 ACK (or NACK) PCH PCH NACKs if HOST_NOTIFY_STS is 1

17:11 Device Address – 7 bits External Master

Indicates the address of the master;

loaded into the Notify Device Address

18 Unused – Always 0 External Master 7-bit-only address; this bit is inserted

to complete the byte

19 ACK PCH

27:20 Data Byte Low – 8 bits External Master Loaded into the Notify Data Low Byte

28 ACK PCH

36:29 Data Byte High – 8 bits External Master Loaded into the Notify Data High Byte

37 ACK PCH

38 Stop External Master

Functional Description

238 Datasheet

5.21 Thermal Management

5.21.1 Thermal Sensor

The PCH incorporates one on-die Digital thermal sensor (DTS) for thermal

management. The thermal sensor can provide PCH temperature information to an EC

or SIO device that can be used to determine how to control the fans.

This thermal sensor is located near the DMI interface. The on-die thermal sensor is

placed as close as possible to the hottest on-die location to reduce thermal gradients

and to reduce the error on the sensor trip thresholds. The thermal Sensor trip points

may be programmed to generate various interrupts including SCI, SMI, PCI and other

General Purpose events.

5.21.1.1 Internal Thermal Sensor Operation

The internal thermal sensor reports four trip points: Aux2, Aux, Hot and Catastrophic

trip points in the order of increasing temperature.

Aux, Aux2 Temperature Trip Points

These trip points may be set dynamically if desired and provides an interrupt to ACPI

(or other software) when it is crossed in either direction. These auxiliary temperature

trip points do not automatically cause any hardware throttling but may be used by

software to trigger interrupts. This trip point is set below the Hot temperature trip point

and responses are separately programmable from the hot temperature settings, in

order to provide incrementally more aggressive actions. Aux and Aux2 trip points are

fully Software programmable during system run-time. Aux2 trip point is set below the

Aux temperature trip point.

Hot Temperature Trip Point

This trip point may be set dynamically if desired and provides an interrupt to ACPI (or

other software) when it is crossed in either direction. Software could optionally set this

as an Interrupt when the temperature exceeds this level setting. Hot trip does not

provide any default hardware based thermal throttling, and is available only as a

customer configurable interrupt when Tj,max has been reached.

Catastrophic Trip Point

This trip point is set at the temperature at which the PCH must be shut down

immediately without any software support. The catastrophic trip point must correspond

to a temperature ensured to be functional in order for the interrupt generation and

Hardware response. Hardware response using THERMTRIP# would be an unconditional

transition to S5. The catastrophic transition to the S5 state does not enforce a

minimum time in the S5 state. It is assumed that the S5 residence and the reboot

sequence cools down the system. If the catastrophic condition remains when the

catastrophic power down enable bit is set by BIOS, then the system will re-enter S5.

Thermometer Mode

The thermometer is implemented using a counter that starts at 0 and increments

during each sample point until the comparator indicates the temperature is above the

current value. The value of the counter is loaded into a read-only register (Thermal

Sensor Thermometer Read) when the comparator first trips.

Datasheet 239

Functional Description

5.21.1.1.1 Recommended Programming for Available Trip Points

There may be a ±2 °C offset due to thermal gradient between the hot-spot and the

location of the thermal sensor. Trip points should be programmed to account for this

temperature offset between the hot-spot Tj,max and the thermal sensor.

Aux Trip Points should be programmed for software and firmware control using

interrupts.

Hot Trip Point should be set to throttle at 108 °C (Tj,max) due to DTS trim accuracy

adjustments. Hot trip points should also be programmed for a software response.

Catastrophic Trip Point should be set to halt operation to avoid maximum Tj of about

120 C.

Note: Crossing a trip point in either direction may generate several types of interrupts. Each

trip point has a register that can be programmed to select the type of interrupt to be

generated. Crossing a trip point is implemented as edge detection on each trip point to

generate the interrupts.

5.21.1.1.2 Thermal Sensor Accuracy (Taccuracy)

Taccuracy for the PCH is ±5 °C in the temperature range 90 °C to 120 °C. Taccuracy is

±10 °C for temperatures from 45 °C – 90 °C. The PCH may not operate above

+108 °C. This value is based on product characterization and is not ensured by

manufacturing test.

Software has the ability to program the Tcat, Thot, and Taux trip points, but these trip

points should be selected with consideration for the thermal sensor accuracy and the

quality of the platform thermal solution. Overly conservative (unnecessarily low)

temperature settings may unnecessarily degrade performance due to frequent

throttling, while overly aggressive (dangerously high) temperature settings may fail to

protect the part against permanent thermal damage.

5.21.2 PCH Thermal Throttling

Occasionally the PCH may operate in conditions that exceed its maximum operating

temperature. In order to protect itself and the system from thermal failure, the PCH is

capable of reducing its overall power consumption and as a result, lower its

temperature. This is achieved by:

• Forcing the SATA device and interface in to a lower power state

• Reducing the number of active lanes on the DMI interface

• Reducing the Intel Manageability Engine (Intel ME) clock frequency

Functional Description

240 Datasheet

The severity of the throttling response is defined by four global PCH throttling states

referred to as T-states. In each T-state, the throttling response will differ per interface,

but will operate concurrently when a global T-state is activated. A T-state corresponds

to a temperature range. The T-states are defined in Table 5 - 5 2.

Enabling of this feature requires appropriate Intel Manageability Engine firmware and

configuration of the following registers shown in Tabl e 5 -53.

5.21.3 Thermal Reporting Over System Management Link 1

Interface (SMLink1)

SMLink1 interface in the PCH is the SMBus link to an optional external controller. A

SMBus protocol is defined on the PCH to allow compatible devices such as Embedded

Controller (EC) or SIO to obtain system thermal data from sensors integrated into

components on the system using the SMLink1 interface. The sensors that can be

monitored using the SMLink1 include those in the processor, PCH and DIMMs with

sensors implemented. This solution allows an external device or controller to use the

system thermal data for system thermal management.

Note: To enable Thermal Reporting, the Thermal Data Reporting enable and PCH/DIMM

temperature read enables have to be set in the Thermal Reporting Control (TRC)

There are two uses for the PCH's thermal reporting capability:

1. To provide system thermal data to an external controller. The controller can

manage the fans and other cooling elements based on this data. In addition, the

PCH can be programmed by setting appropriate bits in the Alert Enable (AE)

device has gone outside of its temperature limits. The alert causes the assertion of

the PCH TEMP_ALERT# (SATA5GP/GPIO49/TEMP_ALERT#) signal. See

Section 5.21.3.6 for more details.

2. To provide an interface between the external controller and host software. This

software interface has no direct affect on the PCH's thermal collection. It is strictly

a software interface to pass information or data.

The PCH responds to thermal requests only when the system is in S0 or S1. Once the

PCH has been programmed, it will start responding to a request while the system is in

S0 or S1.

Table 5-52. PCH Thermal Throttle States (T-states)

State Description

T0 Normal operation, temperature is less than the T1 trip point temperature

T1 Temperature is greater than or equal to the T1 trip point temperature, but less

than the T2 trip point temperature. The default temperature is Tj,max at 108 °C

T2 Temperature is greater than or equal to the T2 trip point temperature, but less

than the T3 trip point temperature. The default temperature is 112 °C

T3 Temperature is greater than or equal to the T3 trip point temperature. The

default temperature is 116 °C

Table 5-53. PCH Thermal Throttling Configuration Registers

Location

TT — Thermal Throttling TBARB+6Ch Section 22.2.15

Datasheet 241

Functional Description

To implement this thermal reporting capability, the platform is required to have

appropriate Intel ME firmware, BIOS support, and compatible devices that support the

SMBus protocol.

5.21.3.1 Supported Addresses

The PCH supports 2 addresses: I2C Address for writes and Block Read Address for

reads. These addresses need to be distinct.

The two addresses may be fixed by the external controller, or programmable within the

controller. The addresses used by the PCH are completely programmable.

5.21.3.1.1 I2C Address

This address is used for writes to the PCH.

• The address is set by soft straps which are values stored in SPI flash and are

defined by the OEM. The address can be set to any value the platform requires.

• This address supports all the writes listed in Ta b l e 5 - 5 4 .

• SMBus reads by the external controller to this address are not allowed and result in

indeterminate behavior.

5.21.3.1.2 Block Read Address

This address is used for reads from the PCH.

• The address is set by soft straps or BIOS. It can be set to any value the platform

requires.

• This address only supports SMBus Block Read command and not Byte or Word

Read.

• The Block Read command is supported as defined in the SMBus 2.0 specification,

with the command being 40h, and the byte count being provided by the PCH

following the block read format in the SMBus specification.

• Writes are not allowed to this address, and result in indeterminate behavior.

• Packet Error Code (PEC) may be enabled or not, which is set up by BIOS.

Functional Description

242 Datasheet

5.21.3.2 I2C Write Commands to the Intel® ME

Table 5 - 54 lists the write commands supported by the Intel ME.

All bits in the write commands must be written to the PCH or the operation will be

aborted. For example, for 6-bytes write commands, all 48 bits must be written or the

operation will be aborted.

The command format follows the Block Write format of the SMBus specification.

5.21.3.3 Block Read Command

The external controller may read thermal information from the PCH using the SMBus

Block Read Command. Byte-read and Word-read SMBus commands are not supported.

Note that the reads use a different address than the writes.

The command format follows the Block Read format of the SMBus specification.

The PCH and external controller are set up by BIOS with the length of the read that is

supported by the platform. The device must always do reads of the lengths set up by

BIOS.

The PCH supports any one of the following lengths: 2, 4, 5, 9, 10, 14 or 20 bytes. The

data always comes in the order described in Tab l e 5-54, where 0 is the first byte

received in time on the SMBus.

Table 5-54. I2C Write Commands to the Intel® ME

Transaction Slave

Addr

Data Byte0

(Command)

Data

Byte 1

(Byte

Count)

Data

Byte 2

Data

Byte 3

Data

Byte 4

Data

Byte 5

Data

Byte 6

Data

Byte 7

Write

Processor

Tem p Limits

I2C 42h 4h

Lower

Limit

[15:8]

Lower

Limit

[7:0]

Upper

Limit

[15:8]

Upper

Limit

[7:0]

Write PCH

Tem p Limits I2C 44h 2h

Lower

Limit

[7:0]

Upper

Limit

[7:0]

Write DIMM

Tem p Limits I2C 45h 2h

Lower

Limit

[7:0]

Upper

Limit

[7:0]

Datasheet 243

Functional Description

A 2-byte read would provide both the PCH and processor temperature. A device that

wants DIMM information would read 9 bytes.

Table 5-55. Block Read Command – Byte Definition

Byte Definition

Byte 0

Processor Package temperature, in absolute degrees Celsius (C). This is not

relative to some max or limit, but is the maximum in absolute degrees.

If the processor temperature collection has errors, this field will be FFh.

Read value represents bits [7:0] of PTV (Processor Temperature Value)

Byte 1

The PCH temp in degrees C.

FFh indicates error condition.

Read value represents bits [7:0] of ITV (Internal Temperature Values)

NOTE: Requires TRC (Thermal Reporting Control) Register bit [5] to be

enabled. See Section 22.2.

Byte 3:2 Reserved

Byte 4 Reserved

Byte 5

Thermal Sensor (TS) on DIMM 0

If DIMM not populated, or if there is no TS on DIMM, value will be 0h

Read value represents bits[7:0] of DTV (DIMM Temperature Values) Register

described in Section 22.2.

NOTE: Requires TRC (Thermal Reporting Control) Register bit [0] to be

enabled. See Section 22.2.

Byte 6

Thermal Sensor (TS) on DIMM 1

If DIMM not populated, or if there is no TS on DIMM, value will be 0h

Read value represents bits[15:8] of DTV (DIMM Temperature Values)

NOTE: Requires TRC (Thermal Reporting Control) Register bit [1] to be

enabled. See Section 22.2.

Byte 7

Thermal Sensor (TS) on DIMM 2

If DIMM not populated, or if there is no TS on DIMM, value will be 0h.

Read value represents bits[23:16] of DTV (DIMM Temperature Values)

NOTE: Requires TRC (Thermal Reporting Control) Register bit [2] to be

enabled. See Section 22.2.

Byte 8

Thermal Sensor (TS) on DIMM 3

If DIMM not populated, or if there is no TS on DIMM, value will be 0h.

Read value represents bits[31:24] of DTV (DIMM Temperature Values)

NOTE: Requires TRC (Thermal Reporting Control) Register bit [3] to be

enabled.

Byte 9

Sequence number. Can be used to check if the PCH's FW or HW is hung. See

Section 5.21.3.9 for usage.

This byte is updated every time the collected data is updated

Read value represents bits[23:16] of ITV (Internal Temperature Values)

Byte 19:10 Reserved

Functional Description

244 Datasheet

5.21.3.4 Read Data Format

For each of the data fields an ERROR Code is listed below. This code indicates that the

PCH failed in its access to the device. This would be for the case where the read

returned no data, or some illegal value. In general that would mean the device is

broken. The EC can treat the device that failed the read as broken or with some fail-

safe mechanism.

5.21.3.4.1 PCH and DIMM Temperature

The temperature readings for the PCH, DIMM are 8-bit unsigned values from 0–255.

The minimum granularity supported by the internal thermal sensor is 1 °C. Thus, there

are no fractional values for the PCH or DIMM temperatures.

Note the sensors used within the components do not support values below 0 degrees,

so this field is treated as 8 bits (0–255) absolute and not 2's complement (-128 to

127).

Devices that are not present or that are disabled will be set to 0h. Devices that have a

failed reading (that is, the read from the device did not return any legal value) will be

set to FFh. A failed reading means that the attempt to read that device returned a

failure. The failure could have been from a bus failure or that the device itself had an

internal failure. For instance, a system may only have one DIMM and it would report

only that one value, and the values for the other DIMMs would all be 00h.

5.21.3.5 Thermal Data Update Rate

The temperature values are updated every 200 ms in the PCH, so reading more often

than that simply returns the same data multiple times. Also, the data may be up to

200 ms old if the external controller reads the data right before the next update

window.

5.21.3.6 Temperature Comparator and Alert

The PCH has the ability to alert the external controller when temperatures are out of

range. This is done using the PCH TEMP_ALERT# signal. The alert is a simple

comparator. If any device's temperature is outside the limit range for that device, then

the signal is asserted (electrical low). Note that this alert does not use the

SML1ALERT#.

The PCH supports 4 ranges:

1. PCH range - upper and lower limit (8 bits each, in degrees C) for the PCH

temperature.

2. DIMM range - upper and lower limit (8 bits each, in degrees C), applies to all

DIMMs (up to 4 supported) that are enabled. Disabled (unpopulated) DIMMs do not

participate in the thermal compares.

3. Processor Package range - upper and lower limit (8 bits each, in degrees C)

The comparator checks if the device is within the specified range, including the limits.

For example, a device that is at 100 degrees when the upper limit is 100 will not trigger

the alert. Likewise, a device that is at 70 degrees when the lower limit is 70 will not

trigger the alert.

The compares are done only on devices that have been enabled by BIOS for checking.

Since BIOS knows how many DIMMs are in the system, it enables the checking only for

those devices that are physically present.

The compares are done in firmware, so all the compares are executed in one software

loop and at the end, if there is any out of bound temperature, the PCH’s TEMP_ALERT#

signal is asserted.

Datasheet 245

Functional Description

When the external controller sees the TEMP_ALERT# signal low, it knows some device

is out of range. It can read the temperatures and then change the limits for the

devices. Note that it may take up to 250 ms before the actual writes cause the signal to

change state. For instance if the PCH is at 105 degrees and the limit is 100, the alert is

triggered. If the controller changes the limits to 110, the TEMP_ALERT# signal may

remain low until the next thermal sampling window (every 200 ms) occurs and only

then go high, assuming the PCH was still within its limits.

At boot, the controller can monitor the TEMP_ALERT# signal state. When BIOS has

finished all the initialization and enabled the temperature comparators, the

TEMP_ALERT# signal will be asserted since the default state of the limit registers is 0h;

hence, when the PCH first reads temperatures, they will be out of range. This is the

positive indication that the external controller may now read thermal information and

get valid data. If the TEMP_ALERT# signal is enabled and not asserted within 30

seconds after PLTRST#, the external controller should assume there is a fatal error and

handle accordingly. In general the TEMP_ALERT# signal will assert within a 1–4

seconds, depending on the actual BIOS implementation and flow.

Note: The TEMP_ALERT# assertion is only valid when PLTRST# is deasserted. The controller

should mask the state of this signal when PLTRST# is asserted. Since the controller

may be powered even when the PCH and the rest of the platform are not, the signal

may glitch as power is being asserted; thus, the controller should wait until PLTRST#

has deasserted before monitoring the signal.

5.21.3.6.1 Special Conditions

The external controller should have a graceful means of handling the following:

1. TEMP_ALERT# asserts, and the controller reads PCH, but all temperature values

are within limits.

In this case, the controller should assume that by the time the controller could read

the data, it had changed and moved back within the limits.

2. External controller writes new values to temperature limits, but TEMP_ALERT# is

still asserted after several hundred msecs. When read, the values are back within

limits.

In this case, the controller should treat this as case where the temperature

changed and caused TEMP_ALERT# assertion, and then changed again to be back

within limits.

3. There is the case where the external controller writes an update to the limit

thermal registers. The limit change will only take affect when the write completes

and the Intel® ME can process this change. If the Intel® ME is already in the

process of collecting data and doing the compares, then it will continue to use the

old limits during this round of compares, and then use the new limits in the next

compare window.

4. Each SMBus write to change the limits is an atomic operation, but is distinct in

itself. Therefore the external controller could write PCH limit, and then write DIMM

limit. In the middle of those 2 writes, the thermal collecting procedure could be

called by the Intel® ME, so that the comparisons for the limits are done with the

new PCH limits but the old DIMM limits.

Note: The limit writes are done when the SMBus write is complete; therefore, the limits are

updated atomically with respect to the thermal updates and compares. There is never a

case where the compares and the thermal update are interrupted in the middle by the

write of new limits. The thermal updates and compares are done as one non-

interruptible routine, and then the limit writes would change the limit value outside of

that routine.

Functional Description

246 Datasheet

5.21.3.7 BIOS Set Up

In order for the PCH to properly report temperature and enable alerts, the BIOS must

configure the PCH at boot or from suspend/resume state by writing the following

information to the PCH MMIO space. This information is NOT configurable using the

external controller.

• Enables for each of the possible thermal alerts (PCH and DIMM). Note that each

DIMM is enabled individually.

• Enables for reading DIMM and PCH temperatures. Note that each can be enabled

individually.

• SMBus address to use for each DIMM.

Setting up the temperature calculation equations.

5.21.3.8 SMBus Rules

The PCH may NACK an incoming SMBus transaction. In certain cases the PCH will NACK

the address, and in other cases it will NACK the command depending on internal

conditions (such as errors, busy conditions). Given that most of the cases are due to

internal conditions, the external controller must alias a NACK of the command and a

NACK of the address to the same behavior. The controller must not try to make any

determination of the reason for the NACK, based on the type of NACK (command vs.

address).

The PCH will NACK when it is enabled but busy. The external controller is required to

retry up to 3 times when they are NACK'ed to determine if the FW is busy with a data

update. When the data values are being updated by the Intel ME, it will force this NACK

to occur so that the data is atomically updated to the external controller. In reality if

there is a NACK because of the PCH being busy, in almost all cases the next read will

succeed since the update internally takes very little time.

The only long delay where there can be a NACK is if the internal Intel ME engine is

reset. This is due to some extreme error condition and is therefore rare. In this case

the NACK may occur for up to 30 seconds. After that, the external controller must

assume that the PCH will never return good data. Even in the best of cases, when this

internal reset occurs, it will always be a second or 2 to re-enable responding.

5.21.3.8.1 During Block Read

On the Block Read, the PCH will respect the NACK and Stop indications from the

external controller, but will consider this an error case. It will recover from this case

and correctly handle the next SMBus request.

The PCH will honor STOP during the block read command and cease providing data. On

the next Block Read, the data will start with byte 0 again. However, this is not a

recommended usage except for 'emergency cases'. In general the external controller

should read the entire length of data that was originally programmed.

5.21.3.8.2 Power On

On the Block Read, the PCH will respect the NACK and Stop indications from the

external controller, but will consider this an error case. It will recover from this case

and correctly handle the next SMBus request.

The PCH will honor STOP during the block read command and cease providing data. On

the next Block Read, the data will start with byte 0 again. However, this is not a

recommended usage except for 'emergency cases'. In general the external controller

should read the entire length of data that was originally programmed.

Datasheet 247

Functional Description

5.21.3.9 Case for Considerations

Below are some corner cases and some possible actions that the external controller

could take.

Note that a 1-byte sequence number is available to the data read by the external

controller. Each time the PCH updates the thermal information it will increment the

sequence number. The external controller can use this value as an indication that the

thermal FW is actually operating. Note that the sequence number will roll over to 00h

when it reaches FFh.

1. Power on:

The PCH will not respond to any SMBus activity (on SMLink1 interface) until it

has loaded the thermal Firmware (FW), which in general would take 1–4

seconds. During this period, the PCH will NACK any SMBus transaction from the

external controller.

The load should take 1-4 seconds, but the external controller should design for

30 seconds based on long delays for S4 resume which takes longer than normal

power up. This would be an extreme case, but for larger memory footprints and

non-optimized recovery times, 30 seconds is a safe number to use for the time-

out.

Recover/Failsafe: if the PCH has not responded within 30 seconds, the external

controller can assume that the system has had a major error and the external

controller should ramp the fans to some reasonably high value.

The only recover from this is an internal reset on the PCH, which is not visible

to the external controller. Therefore the external controller might choose to poll

every 10-60 seconds (some fairly long period) hereafter to see if the PCH's

thermal reporting has come alive.

2. The PCH Thermal FW hangs and requires an internal reset which is not visible to

the external controller.

The PCH will NACK any SMBus transaction from the external controller. The PCH

may not be able to respond for up to 30 seconds while the FW is being reset and

reconfigured.

The external controller could choose to poll every 1-10 seconds to see if the

thermal FW has been successfully reset and is now providing data.

General recovery for this case is about 1 second, but 30 seconds should be used

by the external controller at the time-out.

Recovery/Failsafe: same as in case #1.

3. Fatal PCH error, causes a global reset of all components.

When there is a fatal PCH error, a global reset may occur, and then case #1

applies.

The external controller can observe, if desired, PLTRST# assertion as an

indication of this event.

4. The PCH thermal FW fails or is hung, but no reset occurs

The sequence number will not be updated, so the external controller knows to

go to failsafe after some number of reads (8 or so) return the same sequence

number.

The external controller could choose to poll every 1-10 seconds to see if the

thermal FW has been successfully reset and working again.

In the absence of other errors, the updates for the sequence number should

never be longer than 400 ms, so the number of reads needed to indicate that

there is a hang should be at around 2 seconds. But when there is an error, the

sequence number may not get updated for seconds. In the case that the

Functional Description

248 Datasheet

external controller sees a NACK from the PCH, then it should restart its sequence

counter, or otherwise be aware that the NACK condition needs to be factored into

the sequence number usage.

The use of sequence numbers is not required, but is provided as a means to

ensure correct PCH FW operation.

5. When the PCH updates the Block Read data structure, the external controller gets a

NACK during this period.

To ensure atomicity of the SMBus data read with respect to the data itself, when

the data buffer is being updated, the PCH will NACK the Block Read transaction.

The update is only a few micro-seconds, so very short in terms of SMBus polling

time; therefore, the next read should be successful. The external controller

should attempt 3 reads to handle this condition before moving on.

If the Block read has started (that is, the address is ACK'ed) then the entire read

will complete successfully, and the PCH will update the data only after the SMBus

read has completed.

6. System is going from S0 to S3/4/5. Note that the thermal monitoring FW is fully

operational if the system is in S0/S1, so the following only applies to S3/4/5.

When the PCH detects the OS request to go to S3/4/5, it will take the SMLink1

controller offline as part of the system preparation. The external controller will

see a period where its transactions are getting NACK'ed, and then see SLP_S3#

assert.

This period is relatively short (a couple of seconds depending on how long all the

devices take to place themselves into the D3 state), and would be far less than

the 30 second limit mentioned above.

7. TEMP_ALERT# – Since there can be an internal reset, the TEMP_ALERT# may get

asserted after the reset. The external controller must accept this assertion and

handle it.

5.21.3.9.1 Example Algorithm for Handling Transaction

One algorithm for the transaction handling could be summarized as follows. This is just

an example to illustrate the above rules. There could be other algorithms that can

achieve the same results.

1. Perform SMBus transaction.

2. If ACK, then continue

3. If NACK

a. Try again for 2 more times, in case the PCH is busy updating data.

b. If 3 successive transactions receive NACK, then

- Ramp fans, assuming some general long reset or failure

- Try every 1-10 seconds to see if SMBus transactions are now working

- If they start then return to step 1

- If they continue to fail, then stay in this step and poll, but keep the fans

ramped up or implement some other failure recovery mechanism.

Datasheet 249

Functional Description

5.22 Intel® High Definition Audio Overview (D27:F0)

The PCH High Definition Audio (HDA) controller communicates with the external

codec(s) over the Intel High Definition Audio serial link. The controller consists of a set

of DMA engines that are used to move samples of digitally encoded data between

system memory and an external codec(s). The PCH implements four output DMA

engines and 4 input DMA engines. The output DMA engines move digital data from

system memory to a D-A converter in a codec. The PCH implements a single Serial

Data Output signal (HDA_SDO) that is connected to all external codecs. The input DMA

engines move digital data from the A-D converter in the codec to system memory. The

PCH implements four Serial Digital Input signals (HDA_SDI[3:0]) supporting up to four

codecs.

Audio software renders outbound and processes inbound data to/from buffers in

system memory. The location of individual buffers is described by a Buffer Descriptor

List (BDL) that is fetched and processed by the controller. The data in the buffers is

arranged in a predefined format. The output DMA engines fetch the digital data from

memory and reformat it based on the programmed sample rate, bit/sample and

number of channels. The data from the output DMA engines is then combined and

serially sent to the external codecs over the Intel High Definition Audio link. The input

DMA engines receive data from the codecs over the Intel High Definition Audio link and

format the data based on the programmable attributes for that stream. The data is

then written to memory in the predefined format for software to process. Each DMA

engine moves one stream of data. A single codec can accept or generate multiple

streams of data, one for each A-D or D-A converter in the codec. Multiple codecs can

accept the same output stream processed by a single DMA engine.

Codec commands and responses are also transported to and from the codecs using

DMA engines.

The PCH HD audio controller supports the Function Level Reset (FLR).

5.22.1 Intel® High Definition Audio Docking (Mobile Only)

5.22.1.1 Dock Sequence

Note that this sequence is followed when the system is running and a docking event

occurs.

1. Since the PCH supports docking, the Docking Supported (DCKSTS. DS) bit defaults

to a 1. POST BIOS and ACPI BIOS software uses this bit to determine if the HD

Audio controller supports docking. BIOS may write a 0 to this R/WO bit during

POST to effectively turn off the docking feature.

2. After reset in the undocked quiescent state, the Dock Attach (DCKCTL.DA) bit and

the Dock Mate (DCKSTS.DM) bit are both deasserted. The HDA_DOCK_EN# signal

is deasserted and HDA_DOCK_RST# is asserted. Bit Clock, SYNC and SDO signals

may or may no be running at the point in time that the docking event occurs.

3. The physical docking event is signaled to ACPI BIOS software using ACPI control

methods. This is normally done through a GPIO signal on the PCH and is outside

the scope of this section of the specification.

4. ACPI BIOS software first checks that the docking is supported using DCKSTS.DS=1

and that the DCKSTS.DM=0 and then initiates the docking sequence by writing a 1

to the DCKCTL.DA bit.

Functional Description

250 Datasheet

5. The HD Audio controller then asserts the HDA_DOCK_EN# signal so that the Bit

Clock signal begins toggling to the dock codec. HDA_DOCK_EN# shall be asserted

synchronously to Bit Clock and timed such that Bit Clock is low, SYNC is low, and

SDO is low. Pull-down resistors on these signals in the docking station discharge

the signals low so that when the state of the signal on both sides of the switch is

the same when the switch is turned on. This reduces the potential for charge

coupling glitches on these signals. Note that in the PCH the first 8 bits of the

Command field are “reserved” and always driven to 0's. This creates a predictable

point in time to always assert HDA_DOCK_EN#. Note that the HD Audio link reset

exit specification that requires that SYNC and SDO be driven low during Bit Clock

startup is not ensured. Note also that the SDO and Bit Clock signals may not be low

while HDA_DOCK_RST# is asserted which also violates the specification.

6. After the controller asserts HDA_DOCK_EN# it waits for a minimum of 2400 Bit

Clocks (100 µs) and then deasserts HDA_DOCK_RST#. This is done in such a way

to meet the HD Audio link reset exit specification. HDA_DOCK_RST# deassertion

should be synchronous to Bit Clock and timed such that there are least 4 full Bit

ClockS from the deassertion of HDA_DOCK_RST# to the first frame SYNC

assertion.

7. The Connect/Turnaround/Address Frame hardware initialization sequence will now

occur on the dock codecs' SDI signals. A dock codec is detected when SDI is high

on the last Bit Clock cycle of the Frame Sync of a Connect Frame. The appropriate

bit(s) in the State Change Status (STATESTS) register will be set. The Turnaround

and Address Frame initialization sequence then occurs on the dock codecs' SDI(s).

8. After this hardware initialization sequence is complete (approximately 32 frames),

the controller hardware sets the DCKSTS.DM bit to 1 indicating that the dock is now

mated. ACPI BIOS polls the DCKSTS.DM bit and when it detects it is set to 1,

conveys this to the OS through a plug-N-play IRP. This eventually invokes the HD

Audio Bus Driver, which then begins it's codec discovery, enumeration, and

configuration process.

9. Alternatively to step #8, the HD Audio Bus Driver may choose to enable an

interrupt by setting the WAKEEN bits for SDINs that didn't originally have codecs

attached to them. When a corresponding STATESTS bit gets set an interrupt will be

generated. In this case the HD Audio Bus Driver is called directly by this interrupt

instead of being notified by the plug-N-play IRP.

10. Intel HD Audio Bus Driver software “discovers” the dock codecs by comparing the

bits now set in the STATESTS register with the bits that were set prior to the

docking event.

5.22.1.2 Exiting D3/CRST# When Docked

1. In D3/CRST#, CRST# is asserted by the HD Audio Bus Driver. CRST# asserted

resets the dock state machines, but does not reset the DCKCTL.DA bit. Because the

dock state machines are reset, the dock is electrically isolated (HDA_DOCK_EN#

deasserted) and DOCK_RST# is asserted.

2. The Bus Driver clears the STATESTS bits, then deasserts CRST#, waits

approximately 7 ms, then checks the STATESTS bits to see which codecs are

present.

3. When CRST# is deasserted, the dock state machine detects that DCKCTL.DA is still

set and the controller hardware sequences through steps to electrically connect the

dock by asserting HDA_DOCK_EN# and then eventually deasserts DOCK_RST#.

This completes within the 7ms mentioned in step 2).

4. The Bus Driver enumerates the codecs present as indicated using the STATESTS

bits.

5. Note that this process did not require BIOS or ACPI BIOS to set the DCKCTL.DA bit.

Datasheet 251

Functional Description

5.22.1.3 Cold Boot/Resume from S3 When Docked

1. When booting and resuming from S3, PLTRST# switches from asserted to

deasserted. This clears the DCKCTL.DA bit and the dock state machines. Because

the dock state machines are reset, the dock is electrically isolated

(HDA_DOCK_EN# deasserted) and DOCK_RST# is asserted.

2. POST BIOS detects that the dock is attached and sets the DCKCTL.DA bit to 1. Note

that at this point CRST# is still asserted so the dock state machine will remain in its

reset state.

3. The Bus Driver clears the STATESTS bits, then deasserts CRST#, waits

approximately 7ms, then checks the STATESTS bits to see which codecs are

present.

4. When CRST# is deasserted, the dock state machine detects that DCKCTL.DA is still

set and the controller hardware sequences through steps to electrically connect the

dock by asserting HDA_DOCK_EN# and then eventually deasserts DOCK_RST#.

This completes within the 7ms mentioned in step 3).

5. The Bus Driver enumerates the codecs present as indicated using the STATESTS

bits.

5.22.1.4 Undock Sequence

There are two possible undocking scenarios. The first is the one that is initiated by the

user that invokes software and gracefully shuts down the dock codecs before they are

undocked. The second is referred to as the “surprise undock” where the user undocks

while the dock codec is running. Both of these situations appear the same to the

controller as it is not cognizant of the “surprise removal”. But both sequences will be

discussed here.

5.22.1.5 Normal Undock

1. In the docked quiescent state, the Dock Attach (DCKCTL.DA) bit and the Dock Mate

(DCKSTS.DM) bit are both asserted. The HDA_DOCK_EN# signal is asserted and

HDA_DOCK_RST# is deasserted.

2. The user initiates an undock event through the GUI interface or by pushing a

button. This mechanism is outside the scope of this section of the document. Either

way ACPI BIOS software will be invoked to manage the undock process.

3. ACPI BIOS will call the HD Audio Bus Driver software in order to halt the stream to

the dock codec(s) prior to electrical undocking. If the HD Audio Bus Driver is not

capable of halting the stream to the docked codec, ACPI BIOS will initiate the

hardware undocking sequence as described in the next step while the dock stream

is still running. From this standpoint, the result is similar to the “surprise undock”

scenario where an audio glitch may occur to the docked codec(s) during the undock

process.

4. The ACPI BIOS initiates the hardware undocking sequence by writing a 0 to the

DCKCTL.DA bit.

5. The HD Audio controller asserts HDA_DOCK_RST#. HDA_DOCK_RST# assertion

shall be synchronous to Bit Clock. There are no other timing requirements for

HDA_DOCK_RST# assertion. Note that the HD Audio link reset specification

requirement that the last Frame sync be skipped will not be met.

6. A minimum of 4 Bit Clocks after HDA_DOCK_RST# the controller will deassert

HDA_DOCK_EN# to isolate the dock codec signals from the PCH HD Audio link

signals. HDA_DOCK_EN# is deasserted synchronously to Bit Clock and timed such

that Bit Clock, SYNC, and SDO are low.

7. After this hardware undocking sequence is complete the controller hardware clears

the DCKSTS.DM bit to 0 indicating that the dock is now un-mated. ACPI BIOS

software polls DCKSTS.DM and when it sees DM set, conveys to the end user that

physical undocking can proceed. The controller is now ready for a subsequent

docking event.

Functional Description

252 Datasheet

5.22.1.6 Surprise Undock

1. In the surprise undock case the user undocks before software has had the

opportunity to gracefully halt the stream to the dock codec and initiate the

hardware undock sequence.

2. A signal on the docking connector is connected to the switch that isolates the dock

codec signals from the PCH HD Audio link signals (DOCK_DET# in the conceptual

diagram). When the undock event begins to occur the switch will be put into isolate

mode.

3. The undock event is communicated to the ACPI BIOS using ACPI control methods

that are outside the scope of this section of the document.

4. ACPI BIOS software writes a 0 to the DCKCTL.DA bit. ACPI BIOS then calls the HD

Audio Bus Driver using plug-N-play IRP. The Bus Driver then posthumously cleans

up the dock codec stream.

5. The HD Audio controller hardware is oblivious to the fact that a surprise undock

occurred. The flow from this point on is identical to the normal undocking sequence

described in section 0 starting at step 3). It finishes with the hardware clearing the

DCKSTS.DM bit set to 0 indicating that the dock is now un-mated. The controller is

now ready for a subsequent docking event.

5.22.1.7 Interaction between Dock/Undock and Power Management

States

When exiting from S3, PLTRST# will be asserted. The POST BIOS is responsible for

initiating the docking sequence if the dock is already attached when PLTRST# is

deasserted. POST BIOS writes a 1 to the DCKCTL.DA bit prior to the HD Audio driver

deasserting CRTS# and detecting and enumerating the codecs attached to the

HDA_DOCK_RST# signal. The HD Audio controller does not directly monitor a hardware

signal indicating that a dock is attached. Therefore a method outside the scope of this

document must be used to cause the POST BIOS to initiate the docking sequence.

When exiting from D3, CRST# will be asserted. When CRST# bit is “0” (asserted), the

DCKCTL.DA bit is not cleared. The dock state machine will be reset such that

HDA_DOCK_EN# will be deasserted, HDA_DOCK_RST# will be asserted and the

DCKSTS.DM bit will be cleared to reflect this state. When the CRST# bit is deasserted,

the dock state machine will detect that DCKCTL.DA is set to “1” and will begin

sequencing through the dock process. Note that this does not require any software

intervention.

5.22.1.8 Relationship between HDA_DOCK_RST# and HDA_RST#

HDA_RST# will be asserted when a PLTRST# occurs or when the CRST# bit is 0. As

long as HDA_RST# is asserted, the DOCK_RST# signal will also be asserted.

When PLTRST# is asserted, the DCKCTL.DA and DCKSTS.DM bits will be get cleared to

their default state (0's), and the dock state machine will be reset such that

HDA_DOCK_EN# will be deasserted, and HDA_DOCK_RST# will be asserted. After any

PLTRST#, POST BIOS software is responsible for detecting that a dock is attached and

then writing a “1” to the DCKCTL.DA bit prior to the HD Audio Bus Driver deasserting

CRST#.

When CRST# bit is “0” (asserted), the DCKCTL.DA bit is not cleared. The dock state

machine will be reset such that HDA_DOCK_EN# will be deasserted, HDA_DOCK_RST#

will be asserted and the DCKSTS.DM bit will be cleared to reflect this state. When the

CRST# bit is deasserted, the dock state machine will detect that DCKCTL.DA is set to

“1” and will begin sequencing through the dock process. Note that this does not require

any software intervention.

Datasheet 253

Functional Description

5.23 Intel® ME and Intel® ME Firmware 7.0

In 2005 Intel developed a set of manageability services called Intel® Active

Management Technology (Intel® AMT). To increase features and reduce cost in 2006

Intel integrated the operating environment for Intel AMT to run on all Intel chipsets:

• A microcontroller and support HW was integrated in the MCH

• Additional support HW resided in ICH

This embedded operating environment is called the Intel Manageability Engine (Intel

ME). In 2009 with platform repartitioning Intel ME was designed to reside in the PCH.

Key properties of Intel ME:

• Connectivity

— Integration into I/O subsystem of PCH

— Delivers advanced I/O functions

•Security

— More secure (Intel root of trust) & isolated execution

— Increased security of flash file system

• Modularity & Partitioning

— OSV, VMM & SW Independence

— Respond rapidly to competitive changes

•Power

— Always On Always Connected

— Advanced functions in low power S3-S4-S5 operation

— OS independent PM & thermal heuristics

Intel ME FW provides a variety of services that range from low-level hardware

initialization and provisioning to high-level end-user software based IT manageability

services. One of Intel ME FW’s most established and recognizable features is Intel

Active Management Technology.

Intel® Active Management Technology is a set of advanced manageability features

developed to meet the evolving demands placed on IT to manage a network

infrastructure. Intel® AMT reduces the Total Cost of Ownership (TCO) for IT

management through features such as asset tracking, remote manageability, and

robust policy-based security, resulting in fewer desk-side visits and reduced incident

support durations. Intel AMT extends the manageability capability for IT through Out Of

Band (OOB), allowing asset information, remote diagnostics, recovery, and contain

capabilities to be available on client systems even when they are in a low power, or

“off” state, or in situations when the operating system is hung.

For more details on various Intel ME FW features supported by Intel ME FW, such as

Intel Active Management Technology, please refer to the relevant FW feature

Product Requirements Document (PRD).

Functional Description

254 Datasheet

5.23.1 Intel® ME Requirements

Intel ME is a platform-level solution that utilizes multiple system components including:

• The Intel ME is the general purpose controller that resides in the PCH. It operates in

parallel to, and is resource-isolated from, the host processor.

• The flash device stores Intel ME Firmware code that is executed by the Intel ME for

its operations. In M0, the highest power state, this code is loaded from flash into

DRAM and cached in secure and isolated SRAM. Code that resides in DRAM is

stored in 16 MB of unified memory architecture (UMA) memory taken off the

highest order rank in channel 0. The PCH controls the flash device through the SPI

interface and internal logic.

• In order to interface with DRAM, the Intel ME utilizes the integrated memory

controller (IMC) present in the processor. DMI serves as the interface for

communication between the IMC and Intel ME. This interfacing occurs in only M0

power state. In the lower Intel ME power state, M3, code is executed exclusively

from secure and isolated Intel ME local RAM.

• The LAN controller embedded in the PCH as well as the Intel Gigabit Platform LAN

Connect device are required for Intel ME and Intel AMT network connectivity.

• BIOS to provide asset detection and POST diagnostics (BIOS and Intel AMT can

optionally share same flash memory device)

• An ISV software package, such as LANDesk*, Altiris*, or Microsoft* SMS, can be

used to take advantage of the platform manageability capabilities of Intel AMT.

Figure 5-11. PCH Intel® Management Engine High-Level Block Diagram

SLP_S3#

SLP_S4#

SLP S5#

IMC

DMI

SLP

S5#

SLP_A#

SLP_LAN#

PWROK

AWROK

DPWROK

Processor

DMI CLK/BCLK

GbE

Intel®

Clocks

Local

RAM

GbE

SUS

PCIe*

SMLink

MAC

PHY

PCH Platform Circuitry

SPI

Control

SPI Flash

Desc

GbE FW

Intel ME FW

BIOS

Datasheet 255

Functional Description

5.24 Serial Peripheral Interface (SPI)

The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a lower-cost

alternative for system flash versus the Firmware Hub on the LPC bus.

The 4-pin SPI interface consists of clock (CLK), master data out (Master Out Slave In

(MOSI)), master data in (Master In Slave Out (MISO)) and an active low chip select

(SPI_CS[1:0]#).

The PCH supports up to two SPI flash devices using two separate Chip Select pins. Each

SPI flash device can be up to 16 MB. The PCH SPI interface supports 20 MHz, 33 MHz,

and 50 MHz SPI devices. A SPI Flash device on with Chip Select 0 with a valid

descriptor MUST be attached directly to the PCH.

Communication on the SPI bus is done with a Master – Slave protocol. The Slave is

connected to the PCH and is implemented as a tri-state bus.

Note: If Boot BIOS Strap =’00’ then LPC is selected as the location for BIOS. BIOS may still

be placed on LPC, but all platforms with the PCH require a SPI flash connected directly

to the PCH's SPI bus with a valid descriptor connected to Chip Select 0 in order to boot.

Note: When SPI is selected by the Boot BIOS Destination Strap and a SPI device is detected

by the PCH, LPC based BIOS flash is disabled.

5.24.1 SPI Supported Feature Overview

SPI Flash on the PCH has two operational modes, descriptor and non-descriptor.

5.24.1.1 Non-Descriptor Mode

Non-Descriptor Mode is not supported as a valid flash descriptor is required for all PCH

Platforms.

5.24.1.2 Descriptor Mode

Descriptor Mode is required for all SKUs of the PCH. It enables many new features of

the chipset:

• Integrated Gigabit Ethernet and Host processor for Gigabit Ethernet Software

•Intel

Active Management Technology

•Intel

Management Engine Firmware

• PCI Express* root port configuration

• Supports up to two SPI components using two separate chip select pins

• Hardware enforced security restricting master accesses to different regions

• Chipset Soft Strap regions provides the ability to use Flash NVM as an alternative to

hardware pull-up/pull-down resistors for the PCH and processor

• Supports the SPI Fast Read instruction and frequencies of up to 50 MHz

• Support Single Input, Dual Output Fast read

• Uses standardized Flash Instruction Set

Functional Description

256 Datasheet

5.24.1.2.1 SPI Flash Regions

In Descriptor Mode the Flash is divided into five separate regions:

Only three masters can access the four regions: Host processor running BIOS code,

Integrated Gigabit Ethernet and Host processor running Gigabit Ethernet Software, and

Intel Management Engine. The only required region is Region 0, the Flash Descriptor.

Region 0 must be located in the first sector of Device 0 (Offset 0).

Flash Region Sizes

SPI flash space requirements differ by platform and configuration. The Flash Descriptor

requires one 4 KB or larger block. GbE requires two 4 KB or larger blocks. The amount

of flash space consumed is dependent on the erase granularity of the flash part and the

platform requirements for the Intel ME and BIOS regions. The Intel ME region contains

firmware to support Intel Active Management Technology and other Intel ME

capabilities.

5.24.2 Flash Descriptor

The maximum size of the Flash Descriptor is 4 KB. If the block/sector size of the SPI

flash device is greater than 4 KB, the flash descriptor will only use the first 4 KB of the

first block. The flash descriptor requires its own block at the bottom of memory (00h).

The information stored in the Flash Descriptor can only be written during the

manufacturing process as its read/write permissions must be set to Read only when the

computer leaves the manufacturing floor.

The Flash Descriptor is made up of eleven sections (see Figure 5-12).

Region Content

0 Flash Descriptor

1BIOS

2Intel Management

Engine

3 Gigabit Ethernet

4Platform Data

Table 5-56. Region Size versus Erase Granularity of Flash Components

Region Size with 4 KB

Blocks

Size with 8 KB

Blocks

Size with 64 KB

Blocks

Descriptor 4 KB 8 KB 64 KB

GbE 8 KB 16 KB 128 KB

BIOS Varies by Platform Varies by Platform Varies by Platform

Intel ME Varies by Platform Varies by Platform Varies by Platform

Datasheet 257

Functional Description

1. The Flash signature selects Descriptor Mode as well as verifies if the flash is

programmed and functioning. The data at the bottom of the flash (offset 10h) must

be 0FF0A55Ah in order to be in Descriptor mode.

2. The Descriptor map has pointers to the other five descriptor sections as well as the

size of each.

Figure 5-12. Flash Descriptor Sections

Descriptor

MAP

Component

Signature

Region

Master

PCH Soft

Straps

4KB

Management

Engine VSCC

Table

Descriptor

Upper MAP

OEM Section

Reserved

10 h

Functional Description

258 Datasheet

3. The component section has information about the SPI flash in the system including:

the number of components, density of each, illegal instructions (such as chip

erase), and frequencies for read, fast read and write/erase instructions.

4. The Region section points to the three other regions as well as the size of each

region.

5. The master region contains the security settings for the flash, granting read/write

permissions for each region and identifying each master by a requestor ID. See

Section 5.24.2.1 for more information.

6 & 7. The processor and PCH soft strap sections contain processor and PCH

configurable parameters.

8. The Reserved region between the top of the processor strap section and the bottom

of the OEM Section is reserved for future chipset usages.

9. The Descriptor Upper MAP determines the length and base address of the

Management Engine VSCC Table.

10. The Management Engine VSCC Table holds the JEDEC ID and the VSCC information

of the entire SPI Flash supported by the NVM image.

11. OEM Section is 256 Bytes reserved at the top of the Flash Descriptor for use by

OEM.

5.24.2.1 Descriptor Master Region

The master region defines read and write access setting for each region of the SPI

device. The master region recognizes three masters: BIOS, Gigabit Ethernet, and

Management Engine. Each master is only allowed to do direct reads of its primary

regions.

Table 5-57. Region Access Control Table

Master Read/Write Access

Region Processor and BIOS ME GbE Controller

Descriptor N/A N/A N/A

BIOS

Processor and BIOS

can always read from

and write to BIOS

Region

Read / Write Read / Write

Management

Engine Read / Write

Intel® ME can always

read from and write to

Intel ME Region

Read / Write

Gigabit Ethernet Read / Write Read / Write

GbE software can

always read from and

write to GbE region

Platform Data

Region N/A N/A N/A

Datasheet 259

Functional Description

5.24.3 Flash Access

There are two types of flash accesses:

Direct Access:

• Masters are allowed to do direct read only of their primary region

— Gigabit Ethernet region can only be directly accessed by the Gigabit Ethernet

controller. Gigabit Ethernet software must use Program Registers to access the

Gigabit Ethernet region.

• Master's Host or Management Engine virtual read address is converted into the SPI

Flash Linear Address (FLA) using the Flash Descriptor Region Base/Limit registers

Program Register Access:

• Program Register Accesses are not allowed to cross a 4 KB boundary and can not

issue a command that might extend across two components

• Software programs the FLA corresponding to the region desired

— Software must read the devices Primary Region Base/Limit address to create a

FLA.

5.24.3.1 Direct Access Security

• Requester ID of the device must match that of the primary Requester ID in the

Master Section

• Calculated Flash Linear Address must fall between primary region base/limit

• Direct Write not allowed

• Direct Read Cache contents are reset to 0's on a read from a different master

— Supports the same cache flush mechanism in ICH7 which includes Program

5.24.3.2 Register Access Security

• Only primary region masters can access the registers

Note: Processor running Gigabit Ethernet software can access Gigabit Ethernet registers

• Masters are only allowed to read or write those regions they have read/write

permission

• Using the Flash Region Access Permissions, one master can give another master

read/write permissions to their area

• Using the five Protected Range registers, each master can add separate read/write

protection above that granted in the Flash Descriptor for their own accesses

— Example: BIOS may want to protect different regions of BIOS from being

erased

— Ranges can extend across region boundaries

Functional Description

260 Datasheet

5.24.4 Serial Flash Device Compatibility Requirements

A variety of serial flash devices exist in the market. For a serial flash device to be

compatible with the PCH SPI bus, it must meet the minimum requirements detailed in

the following sections.

Note: All PCH platforms have require Intel® Management Engine Firmware.

5.24.4.1 PCH SPI-Based BIOS Requirements

A serial flash device must meet the following minimum requirements when used

explicitly for system BIOS storage.

• Erase size capability of at least one of the following: 64 Kbytes, 8 Kbytes, 4 Kbytes,

or 256 bytes.

• Device must support multiple writes to a page without requiring a preceding erase

cycle (Refer to Section 5.24.5)

• Serial flash device must ignore the upper address bits such that an address of

FFFFFFh aliases to the top of the flash memory.

• SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising

edge of the clock).

• If the device receives a command that is not supported or incomplete (less than 8

bits), the device must complete the cycle gracefully without any impact on the flash

content.

• An erase command (page, sector, block, chip, etc.) must set all bits inside the

designated area (page, sector, block, chip, etc.) to 1 (Fh).

• Status Register bit 0 must be set to 1 when a write, erase or write to status register

is in progress and cleared to 0 when a write or erase is NOT in progress.

• Devices requiring the Write Enable command must automatically clear the Write

Enable Latch at the end of Data Program instructions.

• Byte write must be supported. The flexibility to perform a write between 1 byte to

64 bytes is recommended.

• Hardware Sequencing requirements are optional in BIOS only platforms.

• SPI flash parts that do not meet Hardware sequencing command set requirements

may work in BIOS only platforms using software sequencing.

5.24.4.2 Integrated LAN Firmware SPI Flash Requirements

A serial flash device that will be used for system BIOS and Integrated LAN or

Integrated LAN only must meet all the SPI Based BIOS Requirements plus:

• Hardware sequencing

• 4-, 8-, or 64-KB erase capability must be supported.

5.24.4.2.1 SPI Flash Unlocking Requirements for Integrated LAN

BIOS must ensure there is no SPI flash based read/write/erase protection on the GbE

region. GbE firmware and drivers for the integrated LAN need to be able to read, write

and erase the GbE region at all times.

Datasheet 261

Functional Description

5.24.4.3 Intel® Management Engine Firmware SPI Flash Requirements

Intel Management Engine Firmware must meet the SPI flash based BIOS Requirements

plus:

• Hardware Sequencing.

• Flash part must be uniform 4-KB erasable block throughout the entire device or

have 64-KB blocks with the first block (lowest address) divided into 4-KB or 8-KB

blocks.

• Write protection scheme must meet SPI flash unlocking requirements for Intel ME.

5.24.4.3.1 SPI Flash Unlocking Requirements for Intel® Management Engine

Flash devices must be globally unlocked (read, write and erase access on the ME

region) from power on by writing 00h to the flash’s status register to disable write

protection.

If the status register must be unprotected, it must use the enable write status register

command 50h or write enable 06h.

Opcode 01h (write to status register) must then be used to write a single byte of 00h

into the status register. This must unlock the entire part. If the SPI flash’s status

If bits [5:2] return a non zero values, the Intel ME firmware will send a write of 00h to

the status register. This must keep the flash part unlocked.

If there is no need to execute a write enable on the status register, then opcodes 06h

and 50h must be ignored.

After global unlock, BIOS has the ability to lock down small sections of the flash as long

as they do not involve the Intel ME or GbE region.

5.24.4.4 Hardware Sequencing Requirements

Ta b l e 5 - 5 8 contains a list of commands and the associated opcodes that a SPI-based

serial flash device must support in order to be compatible with hardware sequencing.

Table 5-58. Hardware Sequencing Commands and Opcode Requirements

Commands Opcode Notes

Write to Status

Status Register command must be run prior to this command.

Program Data 02h Single byte or 64 byte write as determined by flash part

capabilities and software.

Read Data 03h

Write Disable 04h

Read Status 05h Outputs contents of SPI flash’s status register

Write Enable 06h

Fast Read 0Bh

Enable Write to

Status Register

50h or

60h

Enables a bit in the status register to allow an update to the

status register

Erase Program

mable 256B, 4 Kbyte, 8 Kbyte or 64 Kbyte

Full Chip Erase C7h

JEDEC ID 9Fh See Section 5.24.4.4.3.

Functional Description

262 Datasheet

5.24.4.4.1 Single Input, Dual Output Fast Read

The PCH now supports the functionality of a single input, dual output fast read. Opcode

and address phase are shifted in serially to the serial flash SI (Serial In) pin. Data is

read out after 8 clocks (dummy bits or wait states) from the both the SI and SO pin

effectively doubling the through put of each fast read output. In order to enable this

functionality, both Single Input Dual Output Fast Read Supported and Fast Read

supported must be enabled

5.24.4.4.2 Serial Flash Discoverable Parameters (SFDP)

As the number of features keeps growing in the serial flash, the need for correct,

accurate configuration increases. A new method of determining configuration

information is Serial Flash Discoverable Parameters (SFDP). Information such as VSCC

values and flash attributes can be read directly from the flash parts. The discoverable

parameter read opcode behaves like a fast read command. The opcode is 5Ah and the

address cycle is 24 bits long. After the opcode 5Ah and address are clocked in, there

will then be eight clocks (8 wait states) before valid data is clocked out. SFDP is a

capability of the flash part, please confirm with target flash vendor to see if it is

supported.

In order for BIOS to take advantage of the 5Ah opcode it needs to be programmed in

the Software sequencing registers.

5.24.4.4.3 JEDEC ID

Since each serial flash device may have unique capabilities and commands, the JEDEC

ID is the necessary mechanism for identifying the device so the uniqueness of the

device can be comprehended by the controller (master). The JEDEC ID uses the opcode

9Fh and a specified implementation and usage model. This JEDEC Standard

Manufacturer and Device ID read method is defined in Standard JESD21-C, PRN03-NV.

5.24.5 Multiple Page Write Usage Model

The system BIOS and Intel® Management Engine firmware usage models require that

the serial flash device support multiple writes to a page (minimum of 512 writes)

without requiring a preceding erase command. BIOS commonly uses capabilities such

as counters that are used for error logging and system boot progress logging. These

counters are typically implemented by using byte-writes to ‘increment’ the bits within a

page that have been designated as the counter. The Intel® ME firmware usage model

requires the capability for multiple data updates within any given page. These data

updates occur using byte-writes without executing a preceding erase to the given page.

Both the BIOS and Intel® ME firmware multiple page write usage models apply to

sequential and non-sequential data writes.

Note: This usage model requirement is based on any given bit only being written once from a

‘1’ to a ‘0’without requiring the preceding erase. An erase would be required to change

bits back to the 1 state.

Datasheet 263

Functional Description

5.24.5.1 Soft Flash Protection

There are two types of flash protection that are not defined in the flash descriptor

supported by PCH:

1. BIOS Range Write Protection

2. SMI#-Based Global Write Protection

Both mechanisms are logically OR’d together such that if any of the mechanisms

indicate that the access should be blocked, then it is blocked. Ta b l e 5 - 5 9 provides a

summary of the mechanisms.

A blocked command will appear to software to finish, except that the Blocked Access

status bit is set in this case.

5.24.5.2 BIOS Range Write Protection

The PCH provides a method for blocking writes to specific ranges in the SPI flash when

the Protected BIOS Ranges are enabled. This is achieved by checking the Opcode type

information (which can be locked down by the initial Boot BIOS) and the address of the

requested command against the base and limit fields of a Write Protected BIOS range.

Note: Once BIOS has locked down the Protected BIOS Range registers, this mechanism

remains in place until the next system reset.

5.24.5.3 SMI# Based Global Write Protection

The PCH provides a method for blocking writes to the SPI flash when the Write

Protected bit is cleared (that is, protected). This is achieved by checking the Opcode

type information (which can be locked down by the initial Boot BIOS) of the requested

command.

The Write Protect and Lock Enable bits interact in the same manner for SPI BIOS as

they do for the FWH BIOS.

5.24.6 Flash Device Configurations

The PCH-based platform must have a SPI flash connected directly to the PCH with a

valid descriptor and Intel Management Engine Firmware. BIOS may be stored in other

locations such as Firmware Hub and SPI flash hooked up directly to an embedded

controller for Mobile platforms. Note this will not avoid the direct SPI flash connected to

PCH requirement.

Table 5-59. Flash Protection Mechanism Summary

Mechanism Accesses

Blocked

Range

Specific?

Reset-Override

or SMI#-

Override?

Equivalent Function on

FWH

BIOS Range

Write

Protection

Writes Yes Reset Override FWH Sector Protection

Write Protect Writes No SMI# Override Same as Write Protect in

Intel® ICHs for FWH

Functional Description

264 Datasheet

5.24.7 SPI Flash Device Recommended Pinout

Table 5 - 60 contains the recommended serial flash device pin-out for an 8-pin device.

Use of the recommended pin-out on an 8-pin device reduces complexities involved with

designing the serial flash device onto a motherboard and allows for support of a

common footprint usage model (refer to Section 5.24.8.1).

Although an 8-pin device is preferred over a 16-pin device due to footprint

compatibility, the following table contains the recommended serial flash device pin-out

for a 16-pin SOIC.

5.24.8 Serial Flash Device Package

5.24.8.1 Common Footprint Usage Model

In order to minimize platform motherboard redesign and to enable platform Bill of

Material (BOM) selectability, many PC System OEMs design their motherboard with a

single common footprint. This common footprint allows population of a soldered down

device or a socket that accepts a leadless device. This enables the board manufacturer

to support, using selection of the appropriate BOM, either of these solutions on the

same system without requiring any board redesign.

The common footprint usage model is desirable during system debug and by flash

content developers since the leadless device can be easily removed and reprogrammed

without damage to device leads. When the board and flash content is mature for high-

volume production, both the socketed leadless solution and the soldered down leaded

solution are available through BOM selection.

Table 5-60. Recommended Pinout for 8-Pin Serial Flash Device

Pin # Signal

1Chips Select

2 Data Output

3 Write Protect

4Ground

5 Data Input

6Serial Clock

7Hold / Reset

8 Supply Voltage

Table 5-61. Recommended Pinout for 16-Pin Serial Flash Device

Pin # Signal Pin # Signal

1 Hold / Reset 9 Write Protect

2 Supply Voltage 10 Ground

3 No Connect 11 No Connect

4 No Connect 12 No Connect

5 No Connect 13 No Connect

6 No Connect 14 No Connect

7 Chip Select 15 Serial Data In

8 Serial Data Out 16 Serial Clock

Datasheet 265

Functional Description

5.24.8.2 Serial Flash Device Package Recommendations

It is highly recommended that the common footprint usage model be supported. An

example of how this can be accomplished is as follows:

• The recommended pinout for 8-pin serial flash devices is used (refer to

Section 5.24.7).

• The 8-pin device is supported in either an 8-contact VDFPN (6x5 mm MLP) package

or an 8-contact WSON (5x6 mm) package. These packages can fit into a socket

that is land pattern compatible with the wide body SO8 package.

• The 8-pin device is supported in the SO8 (150 mil) and in the wide-body SO8

(200 mil) packages.

The 16-pin device is supported in the SO16 (300 mil) package.

5.24.9 PWM Outputs (Server/Workstation Only)

This signal is driven as open-drain. An external pull-up resistor is integrated into the

fan to provide the rising edge of the PWM output signal. The PWM output is driven low

during reset, which represents 0% duty cycle to the fans. After reset deassertion, the

PWM output will continue to be driven low until one of the following occurs:

• The internal PWM control register is programmed to a non-zero value by

appropriate firmware.

• The watchdog timer expires (enabled and set at 4 seconds by default).

• The polarity of the signal is inverted by firmware.

Note that if a PWM output will be programmed to inverted polarity for a particular fan,

then the low voltage driven during reset represents 100% duty cycle to the fan.

5.24.10 TACH Inputs (Server/Workstation Only)

This signal is driven as an open-collector or open-drain output from the fan. An

external pull-up is expected to be implemented on the motherboard to provide the

rising edge of the TACH input. This signal has analog hysteresis and digital filtering due

to the potentially slow rise and fall times. This signal has a weak internal pull-up

resistor to keep the input buffer from floating if the TACH input is not connected to a

fan.

5.25 Feature Capability Mechanism

A set of registers is included in the PCH LPC Interface (Device 31, Function 0, offset

E0h–EBh) that allows the system software or BIOS to easily determine the features

supported by the PCH. These registers can be accessed through LPC PCI configuration

space, thus allowing for convenient single point access mechanism for chipset feature

detection.

This set of registers consists of:

• Capability ID (FDCAP)

• Capability Length (FDLEN)

• Capability Version and Vendor-Specific Capability ID (FDVER)

• Feature Vector (FVECT)

Functional Description

266 Datasheet

5.26 PCH Display Interfaces and Intel

® Flexible Display

Interconnect

Display is divided between processor and PCH. The processor houses memory

interface, display planes, and pipes while PCH has transcoder and display interface or

ports. Intel® FDI connects the processor and PCH display engine. The number of

planes, pipes, and transcoders decide the number of simultaneous and concurrent

display devices that can be driven on a platform.

The PCH integrates one Analog, LVDS (mobile only) and three Digital Ports B, C, and D.

Each Digital Port can transmit data according to one or more protocols. Digital Port B,

C, and D can be configured to drive natively HDMI, DisplayPort, or DVI. Digital Port B

also supports Serial Digital Video Out (SDVO) that converts one protocol to another.

Digital Port D can be configured to drive natively Embedded DisplayPort (eDP). Each

display port has control signals that may be used to control, configure and/or

determine the capabilities of an external device.

The PCH’s Analog Port uses an integrated 340.4 MHz RAMDAC that can directly drive a

standard progressive scan analog monitor up to a resolution of 2048x1536 pixels with

32-bit color at 75 Hz.

The PCH SDVO port (configured through Digital Port B) is capable of driving a 200 MP/s

(Megapixels/second) rate.

Each digital port is capable of driving resolutions up to 2560x1600 at 60 Hz through

DisplayPort and 1920x1200 at 60 Hz using HDMI or DVI (with reduced blanking).

5.26.1 Analog Display Interface Characteristics

The Analog Port provides a RGB signal output along with a HSYNC and VSYNC signal.

There is an associated Display Data Channel (DDC) signal pair that is implemented

using GPIO pins dedicated to the Analog Port. The intended target device is for a moni-

tor with a VGA connector. Display devices such as LCD panels with analog inputs may

work satisfactory but no functionality added to the signals to enhance that capability.

Figure 5-13. Analog Port Characteristics

Datasheet 267

Functional Description

5.26.1.1 Integrated RAMDAC

The display function contains a RAM-based Digital-to-Analog Converter (RAMDAC) that

transforms the digital data from the graphics and video subsystems to analog data for

the VGA monitor. The PCH’s integrated 340.4 MHz RAMDAC supports resolutions up to

2048x1536 at 75 Hz. Three 8-bit DACs provide the R, G, and B signals to the monitor.

5.26.1.1.1 Sync Signals

HSYNC and VSYNC signals are digital and conform to TTL signal levels at the connector.

Since these levels cannot be generated internal to the device, external level shifting

buffers are required. These signals can be polarity adjusted and individually disabled in

one of the two possible states. The sync signals should power up disabled in the high

state. No composite sync or special flat panel sync support are included.

5.26.1.1.2 VESA/VGA Mode

VESA/VGA mode provides compatibility for pre-existing software that set the display

mode using the VGA CRTC registers. Timings are generated based on the VGA register

values and the timing generator registers are not used.

5.26.1.2 DDC (Display Data Channel)

DDC is a standard defined by VESA. Its purpose is to allow communication between the

host system and display. Both configuration and control information can be exchanged

allowing plug- and-play systems to be realized. Support for DDC 1 and 2 is imple-

mented. The PCH uses the DDC_CLK and DDC_DATA signals to communicate with the

analog monitor. The PCH will generate these signals at 2.5 V. External pull-up resistors

and level shifting circuitry should be implemented on the board.

5.26.2 Digital Display Interfaces

The PCH can drive a number of digital interfaces natively. The Digital Ports B, C, and/or

D can be configured to drive HDMI, DVI, DisplayPort, and Embedded DisplayPort (port

D only). The PCH provides a dedicated port for Digital Port LVDS (mobile only).

5.26.2.1 LVDS (Mobile only)

LVDS for flat panel is compatible with the ANSI/TIA/EIA-644 specification. This is an

electrical standard only defining driver output characteristics and receiver input

characteristics.

Each channel supports transmit clock frequency ranges from 25 MHz to 112 MHz, which

provides a throughput of up to 784 Mbps on each data output and up to 112 MP/s on

the input. When using both channels, each carry a portion of the data; thus, doubling

the throughput to a maximum theoretical pixel rate of 224 MP/s.

There are two LVDS transmitter channels (Channel A and Channel B) in the LVDS

interface. Channel A and Channel B consist of 4-data pairs and a clock pair each.

The LVDS data pair is used to transfer pixel data as well as the LCD timing control

signals.

Figure 5-14 shows a pair of LVDS signals and swing voltage.

Functional Description

268 Datasheet

Logic values of 1s and 0s are represented by the differential voltage between the pair

of signals. As shown in the Figure 5-15 a serial pattern of 1100011 represents one

cycle of the clock.

5.26.2.1.1 LVDS Pair States

The LVDS pairs can be put into one of five states:

•Active

•Powered down Hi-Z

• Powered down 0 V

•Common mode

•Send zeros

When in the active state, several data formats are supported. When in powered down

state, the circuit enters a low power state and drives out 0 V or the buffer is the Hi-Z

state on both the output pins for the entire channel. The common mode Hi-Z state is

both pins of the pair set to the common mode voltage. When in the send zeros state,

the circuit is powered up but sends only zero for the pixel color data regardless what

the actual data is with the clock lines and timing signals sending the normal clock and

timing data.

The LVDS Port can be enabled/disabled using software. A disabled port enters a low

power state. Once the port is enabled, individual driver pairs may be disabled based on

the operating mode. Disabled drivers can be powered down for reduced power

consumption or optionally fixed to forced 0s output.

Individual pairs or sets of LVDS pairs can be selectively powered down when not being

used. The panel power sequencing can be set to override the selected power state of

the drivers during power sequencing.

Figure 5-14. LVDS Signals and Swing Voltage

Figure 5-15. LVDS Clock and Data Relationship

Datasheet 269

Functional Description

5.26.2.1.2 Single Channel versus Dual Channel Mode

In the single channel mode, only Channel-A is used. Channel-B cannot be used for

single channel mode. In the dual channel mode, both Channel-A and Channel-B pins

are used concurrently to drive one LVDS display.

In Single Channel mode, Channel A can take 18 bits of RGB pixel data, plus 3 bits of

timing control (HSYNC/VSYNC/DE) and output them on three differential data pair

outputs; or 24 bits of RGB (plus 4 bits of timing control) output on four differential data

pair outputs. A dual channel interface converts 36 or 48 bits of color information plus

the 3 or 4 bits of timing control respectively and outputs it on six or eight sets of

differential data outputs respectively.

Dual Channel mode uses twice the number of LVDS pairs and transfers the pixel data at

twice the rate of the single channel. In general, one channel will be used for even pixels

and the other for odd pixel data. The first pixel of the line is determined by the display

enable going active and that pixel will be sent out Channel-A. All horizontal timings for

active, sync, and blank will be limited to be on two pixel boundaries in the two channel

modes.

Note: Platforms using the PCH for integrated graphics support 24-bpp display panels of Type

1 only (compatible with VESA LVDS color mapping).

5.26.2.1.3 Panel Power Sequencing

This section provides details for the power sequence timing relationship of the panel

power, the backlight enable and the LVDS data timing delivery. To meet the panel

power timing specification requirements two signals, LFP_VDD_EN and LFP_BKLT_EN,

are provided to control the timing sequencing function of the panel and the backlight

power supplies.

A defined power sequence is recommended when enabling the panel or disabling the

panel. The set of timing parameters can vary from panel to panel vendor, provided that

they stay within a predefined range of values. The panel VDD power, the backlight on/

off state and the LVDS clock and data lines are all managed by an internal power

sequencer.

NOTE: Support for programming parameters TX and T1 through T5 using software is provided.

Figure 5-16. Panel Power Sequencing

Power On S equ ence from off state and

Power O ff S eque nce after full On

Panel VDD

Enable

Panel

BackLight

Enable

Clock/Data Lines

T1+T2 T5 T3

Valid

Panel

Off Off

Functional Description

270 Datasheet

5.26.2.1.4 LVDS DDC

The display pipe selected by the LVDS display port is programmed with the panel timing

parameters that are determined by installed panel specifications or read from an

onboard EDID ROM. The programmed timing values are then ‘locked’ into the registers

to prevent unwanted corruption of the values. From that point on, the display modes

are changed by selecting a different source size for that pipe, programming the VGA

registers, or selecting a source size and enabling the VGA.

The LVDS DDC helps to reads the panel timing parameters or panel EDID.

5.26.2.2 High Definition Multimedia Interface

The High-Definition Multimedia Interface (HDMI) is provided for transmitting uncom-

pressed digital audio and video signals from DVD players, set-top boxes and other

audiovisual sources to television sets, projectors and other video displays. It can carry

high quality multi-channel audio data and all standard and high-definition consumer

electronics video formats. HDMI display interface connecting the PCH and display

devices utilizes transition minimized differential signaling (TMDS) to carry audiovisual

information through the same HDMI cable.

HDMI includes three separate communications channels: TMDS, DDC, and the optional

CEC (consumer electronics control) (not supported by the PCH). As shown in

Figure 5-17 the HDMI cable carries four differential pairs that make up the TMDS data

and clock channels. These channels are used to carry video, audio, and auxiliary data.

In addition, HDMI carries a VESA DDC. The DDC is used by an HDMI Source to deter-

mine the capabilities and characteristics of the Sink.

Audio, video and auxiliary (control/status) data is transmitted across the three TMDS

data channels. The video pixel clock is transmitted on the TMDS clock channel and is

used by the receiver for data recovery on the three data channels. The digital display

data signals driven natively through the PCH are AC coupled and needs level shifting to

convert the AC coupled signals to the HDMI compliant digital signals.

PCH HDMI interface is designed as per High-Definition Multimedia Interface Specifica-

tion 1.4a. The PCH supports High-Definition Multimedia Interface Compliance Test

Specification 1.4a.

Figure 5-17. HDMI Overview

Datasheet 271

Functional Description

5.26.2.3 Digital Video Interface (DVI)

The PCH Digital Ports can be configured to drive DVI-D. DVI uses TMDS for transmitting

data from the transmitter to the receiver which is similar to the HDMI protocol but the

audio and CEC. Refer to the HDMI section for more information on the signals and data

transmission. To drive DVI-I through the back panel the VGA DDC signals is connected

along with the digital data and clock signals from one of the Digital Ports. When a sys-

tem has support for a DVI-I port, then either VGA or the DVI-D through a single DVI-I

connector can be driven but not both simultaneously.

The digital display data signals driven natively through the PCH are AC coupled and

needs level shifting to convert the AC coupled signals to the HDMI compliant digital sig-

nals.

5.26.2.4 DisplayPort*

DisplayPort is a digital communication interface that utilizes differential signaling to

achieve a high bandwidth bus interface designed to support connections between PCs

and monitors, projectors, and TV displays. DisplayPort is also suitable for display

connections between consumer electronics devices such as high definition optical disc

players, set top boxes, and TV displays.

A DisplayPort consists of a Main Link, Auxiliary channel, and a Hot Plug Detect signal.

The Main Link is a uni-directional, high-bandwidth, and low latency channel used for

transport of isochronous data streams such as uncompressed video and audio. The

Auxiliary Channel (AUX CH) is a half-duplex bidirectional channel used for link manage-

ment and device control. The Hot Plug Detect (HPD) signal serves as an interrupt

request for the sink device.

PCH is designed as per VESA DisplayPort Standard Version 1.1a. The PCH supports

VESA DisplayPort* PHY Compliance Test Specification 1.1 and VESA DisplayPort* Link

Layer Compliance Test Specification 1.1.

Figure 5-18. DisplayPort Overview

Functional Description

272 Datasheet

5.26.2.5 Embedded DisplayPort

Embedded DisplayPort (eDP*) is a embedded version of the DisplayPort standard

oriented towards applications such as notebook and All-In-One PCs. eDP is supported

only on Digital Port D. Like DisplayPort, Embedded DisplayPort also consists of a Main

Link, Auxiliary channel, and a optional Hot Plug Detect signal.

The eDP support on desktop PCH is possible because of the addition of the panel power

sequencing pins: L_VDD, L_BKLT_EN and L_BLKT_CTRL. The eDP on the PCH can be

configured for 2 or 4 lanes.

PCH supports Embedded DisplayPort* (eDP*) Standard Version 1.1.

5.26.2.6 DisplayPort Aux Channel

A bi-directional AC coupled AUX channel interface replaces the I2C for EDID read, link

management and device control. I2C-to-Aux bridges are required to connect legacy

display devices.

5.26.2.7 DisplayPort Hot-Plug Detect (HPD)

The PCH supports HPD for Hot-Plug sink events on the HDMI and DisplayPort interface.

5.26.2.8 Integrated Audio over HDMI and DisplayPort

DisplayPort and HDMI interfaces on PCH support audio. Ta b l e 5 - 5 9 shows the

supported audio technologies on the PCH.

PCH will continue to support Silent stream. Silent stream is a integrated audio feature

that enables short audio streams such as system events to be heard over the HDMI and

DisplayPort monitors. PCH supports silent streams over the HDMI and DisplayPort

interfaces at 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz and 192 kHz sampling

rates.

5.26.2.9 Serial Digital Video Out (SDVO)

Serial Digital Video Out (SDVO) sends display data in serialized format which then can

be converted into appropriate display protocol using a SDVO device. Serial Digital Video

Out (SDVO) supports SDVO-LVDS only on the PCH. Though the SDVO electrical

interface is based on the PCI Express interface, the protocol and timings are completely

unique. The PCH utilizes an external SDVO device to translate from SDVO protocol and

timings to the desired display format and timings.

SDVO is supported only on Digital Port B of the PCH.

Table 5-59. PCH Supported Audio Formats over HDMI and DisplayPort*

Audio Formats HDMI DisplayPort

AC-3 - Dolby* Digital Yes No

Dolby Digital Plus Yes No

DTS-HD* Yes No

LPCM, 192 kHz/24 bit, 8 Channel Yes Yes (two channel - up to 96 kHz 24 bit)

Dolby TrueHD, DTS-HD Master Audio*

(Losses Blu-ray Disc* Audio Format) Yes No

Datasheet 273

Functional Description

5.26.2.9.1 Control Bus

Communication to SDVO registers and if utilized, ADD2 PROMs and monitor DDCs, are

accomplished by using the SDVOCTRLDATA and SDVOCTRLCLK signals through the

SDVO device. These signals run up to 400 kHz and connect directly to the SDVO

device.

The SDVO device is then responsible for routing the DDC and PROM data streams to

the appropriate location. Consult SDVO device data sheets for level shifting require-

ments of these signals.

Figure 5-19. SDVO Conceptual Block Diagram

SDVO B

3rd Party

SDVO

External

Device

GREEN B

RED B

BLUE B

TV Clock in

Control D ata

Control Clock

Stall

Interrupt

PCH LVDS

Panel

Functional Description

274 Datasheet

5.26.3 Mapping of Digital Display Interface Signals

Table 5-60. PCH Digital Port Pin Mapping

Port

Description

DisplayPort*

Signals HDMI* Signals SDVO Signals PCH Display

Port Pin details

Port B

DPB_LANE3 TMDSB_CLK SDVOB_CLK DDPB_[3]P

DPB_LANE3# TMDSB_CLKB SDVOB_CLK# DDPB_[3]N

DPB_LANE2 TMDSB_DATA0 SDVOB_BLUE DDPB_[2]P

DPB_LANE2# TMDSB_DATA0B SDVOB_BLUE# DDPB_[2]N

DPB_LANE1 TMDSB_DATA1 SDVOB_GREEN DDPB_[1]P

DPB_LANE1# TMDSB_DATA1B SDVOB_GREEN# DDPB_[1]N

DPB_LANE0 TMDSB_DATA2 SDVOB_RED DDPB_[0]P

DPB_LANE0# TMDSB_DATA2B SDVOB_RED* DDPB_[0]N

DPB_HPD TMDSB_HPD DDPB_HPD

DPB_AUX DDPB_AUXP

DPB_AUXB DDPB_AUXN

Port C

DPC_LANE3 TMDSC_CLK DDPC_[3]P

DPC_LANE3# TMDSC_CLKB DDPC_[3]N

DPC_LANE2 TMDSC_DATA0 DDPC_[2]P

DPC_LANE2# TMDSC_DATA0B DDPC_[2]N

DPC_LANE1 TMDSC_DATA1 DDPC_[1]P

DPC_LANE1# TMDSC_DATA1B DDPC_[1]N

DPC_LANE0 TMDSC_DATA2 DDPC_[0]P

DPC_LANE0# TMDSC_DATA2B DDPC_[0]N

DPC_HPD TMDSC_HPD DDPC_HPD

DPC_AUX DDPC_AUXP

DPC_AUXC DDPC_AUXN

Port D

DPD_LANE3 TMDSD_CLK DDPD_[3]P

DPD_LANE3# TMDSD_CLKB DDPD_[3]N

DPD_LANE2 TMDSD_DATA0 DDPD_[2]P

DPD_LANE2# TMDSD_DATA0B DDPD_[2]N

DPD_LANE1 TMDSD_DATA1 DDPD_[1]P

DPD_LANE1# TMDSD_DATA1B DDPD_[1]N

DPD_LANE0 TMDSD_DATA2 DDPD_[0]P

DPD_LANE0# TMDSD_DATA2B DDPD_[0]N

DPD_HPD TMDSD_HPD DDPD_HPD

DPD_AUX DDPD_AUXP

DPD_AUXD DDPD_AUXN

Datasheet 275

Functional Description

5.26.4 Multiple Display Configurations

The following multiple display configuration modes are supported (with appropriate

driver software):

• Single Display is a mode with one display port activated to display the output to

one display device.

•Intel

® Dual Display Clone is a mode with two display ports activated to drive the

display content of same color depth setting but potentially different refresh rate

and resolution settings to all the active display devices connected.

• Extended Desktop is a mode with two display ports activated used to drive the

content with potentially different color depth, refresh rate, and resolution settings

on each of the active display devices connected.

Ta b l e 5 - 6 1 describes the valid interoperability between display technologies.

5.26.5 High-bandwidth Digital Content Protection (HDCP)

HDCP is the technology for protecting high definition content against unauthorized copy

or unreceptive between a source (computer, digital set top boxes, etc.) and the sink

(panels, monitor, and TVs). The PCH supports HDCP 1.4 for content protection over

wired displays (HDMI, DVI, and DisplayPort).

The HDCP 1.4 keys are integrated into the PCH and customers are not required to

physically configure or handle the keys.

Table 5-61. Display Co-Existence Table

Display Not

Attached

DAC Integrated

LVDS

Integrated

DisplayPort*

HDMI*/

DVI eDP*

VGA

Not

Attached XS S S S S

DAC VGA SXS

1, C, E A A S1, C, E

Integrated

LVDS SS

1, C, E XS

1, C, E S1, C, E X

Integrated

DisplayPort SAS

1, C, E A A S1, C, E

HDMI/DVI SAS

1, C, E A S1, C, E S1, C, E

SDVO LVDS SS

1, C, E S1, C, E S1, C, E S1, C, E A

eDP SS

1, C, E XS

1, C, E S1, C, E X

• A = Single Pipe Single Display, Intel® Dual Display Clone (Only 24-bpp), or Extended Desktop

Mode

• C = Clone Mode

• E = Extended Desktop Mode

• S = Single Pipe Single Display

•S

1 = Single Pipe Single Display With One Display Device Disabled

• X = Unsupported/Not Applicable

Functional Description

276 Datasheet

5.26.6 Intel® Flexible Display Interconnect

Intel® FDI connects the display engine in the processor with the display interfaces on

the PCH. The display data from the frame buffer is processed in the display engine of

the processor and sent to the PCH over the Intel FDI where it is transcoded as per the

display protocol and driven to the display monitor.

Intel FDI has two channels A and B. Each channel has 4 lanes and total combined is 8

lanes to transfer the data from the processor to the PCH. Depending on the data

bandwidth the interface is dynamically configured as x1, x2 or x4 lanes. Intel FDI

supports lane reversal and lane polarity reversal.

5.27 Intel® Virtualization Technology

Intel Virtualization Technology (Intel® VT) makes a single system appear as multiple

independent systems to software. This allows for multiple, independent operating

systems to be running simultaneously on a single system. Intel VT comprises

technology components to support virtualization of platforms based on Intel

architecture microprocessors and chipsets. The first revision of this technology (Intel

VT-x) added hardware support in the processor to improve the virtualization

performance and robustness. The second revision of this specification (Intel VT-d) adds

chipset hardware implementation to improve I/O performance and robustness.

The Intel VT-d specification and other VT documents can be referenced here: http://

www.intel.com/technology/platform-technology/virtualization/index.htm

5.27.1 Intel® VT-d Objectives

The key Intel VT-d objectives are domain based isolation and hardware based

virtualization. A domain can be abstractly defined as an isolated environment in a

platform to which a subset of host physical memory is allocated. Virtualization allows

for the creation of one or more partitions on a single system. This could be multiple

partitions in the same OS or there can be multiple operating system instances running

on the same system offering benefits such as system consolidation, legacy migration,

activity partitioning or security.

5.27.2 Intel® VT-d Features Supported

• The following devices and functions support FLR in the PCH:

— High Definition Audio (Device 27: Function 0)

— SATA Host Controller 1 (Device 31: Function 2)

— SATA Host Controller 2 (Device 31: Function 5)

— USB2 (EHCI) Host Controller 1 (Device 29: Function 0)

— USB2 (EHCI) Host Controller 2 (Device 26: Function 0)

— GbE Lan Host Controller (Device 25: Function 0)

• Interrupt virtualization support for IOxAPIC

• Virtualization support for HPETs

Datasheet 277

Functional Description

5.27.3 Support for Function Level Reset (FLR) in PCH

Intel VT-d allows system software (VMM/OS) to assign I/O devices to multiple domains.

The system software, then, requires ways to reset I/O devices or their functions within,

as it assigns/re-assigns I/O devices from one domain to another. The reset capability is

required to ensure the devices have undergone proper re-initialization and are not

keeping the stale state. A standard ability to reset I/O devices is also useful for the

VMM in case where a guest domain with assigned devices has become unresponsive or

has crashed.

PCI Express defines a form of device hot reset which can be initiated through the

Bridge Control register of the root/switch port to which the device is attached. How-

ever, the hot reset cannot be applied selectively to specific device functions. Also, no

similar standard functionality exists for resetting root-complex integrated devices.

Current reset limitations can be addressed through a function level reset (FLR) mecha-

nism that allows software to independently reset specific device functions.

5.27.4 Virtualization Support for PCH’s IOxAPIC

The Intel VT-d architecture extension requires Interrupt Messages to go through the

similar Address Remapping as any other memory requests. This is to allow domain

isolation for interrupts such that a device assigned in one domain is not allowed to

generate interrupts to another domain.

The Address Remapping for Intel VT-d is based on the Bus:Device:Function field

associated with the requests. Hence, it is required for the internal IOxAPIC to initiate

the Interrupt Messages using a unique Bus:Device:Function.

The PCH supports BIOS programmable unique Bus:Device:Function for the internal

IOxAPIC. The Bus:Device:Function field does not change the IOxAPIC functionality in

anyway, nor promoting IOxAPIC as a stand-alone PCI device. The field is only used by

the IOxAPIC in the following:

• As the Requestor ID when initiating Interrupt Messages to the processor

• As the Completer ID when responding to the reads targeting the IOxAPIC’s

Memory-Mapped I/O registers

5.27.5 Virtualization Support for High Precision Event Timer

(HPET)

The Intel VT-d architecture extension requires Interrupt Messages to go through the

similar Address Remapping as any other memory requests. This is to allow domain

isolation for interrupts such that a device assigned in one domain is not allowed to

generate interrupts to another domain.

The Address Remapping for Intel VT-d is based on the Bus:Device:Function field

associated with the requests. Hence, it is required for the HPET to initiate the direct

FSB Interrupt Messages using unique Bus:Device:Function.

The PCH supports BIOS programmable unique Bus:Device:Function for each of the

HPET timers. The Bus:Device:Function field does not change the HPET functionality in

anyway, nor promoting it as a stand-alone PCI device. The field is only used by the

HPET timer in the following:

• As the Requestor ID when initiating direct interrupt messages to the processor

• As the Completer ID when responding to the reads targeting its Memory-Mapped

registers

• The registers for the programmable Bus:Device:Function for HPET timer 7:0 reside

under the Device 31:Function 0 LPC Bridge’s configuration space.

§ §

Functional Description

278 Datasheet

Datasheet 279

Ballout Definition

6 Ballout Definition

This chapter contains the PCH Ballout information.

6.1 Desktop PCH Ballout

This section contains the Desktop PCH ballout. Figure 6-1, Figure 6-2, Figure 6-3, and

Figure 6-4 show the ballout from a top of the package quadrant view. Ta b l e 6-1 is the

BGA ball list, sorted alphabetically by signal name.

Note: References to PWM[3:0], TACH[7:0], SST, NMI#, SMI# are for Server/Workstation

SKUs only. Pin names PWM[3:0], TACH[7:0], SST, NMI#, SMI# are Reserved on

Desktop SKUs. See Chapter 2 for further details.

Figure 6-1. Desktop PCH Ballout (Top View - Upper Left)

BU BT BR BP BN BM BL BK BJ BH BG BF BE BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK

1VSS_NCTF VSS_NCTF Vss V5REF Vss CRT_DDC

_DATA VccADAC CRT_BLU

2VSS_NCTF AD14 AD21 C/BE2# GNT3# /

GPIO55 AD24 CLKOUTF

LEX3 /

GPIO67 VssADAC CRT_VSY

NC CRT_GRE

EN XCLK_RC

OMP

3Vss PERR# AD9 AD13 Vss CRT_DDC

_CLK DAC_IREF Vss

4VSS_NCTF PIRQH# /

GPIO5 C/BE0# AD23 AD15 AD22 CRT_HSY

NC Vss

5REQ1# /

GPIO50 PIRQD# Vss PIRQB# REQ0# CLKOUTF

LEX1 /

GPIO65

CLKOUTF

LEX2 /

GPIO66 Vss VccAClk

6VSS_NCTF SERR# Vss Vss Vss Vss AD16 AD18 Vss Vss Vss Vss Vss CRT_RED CRT_IRTN Vss

7AD2 C/BE1#

8AD12 REQ2# /

GPIO52 PAR AD29 TRDY# AD28 GNT1# /

GPIO51 Vss REFCLK14

IN DDPD_CT

RLDATA

9AD7 AD10 PIRQE# /

GPIO2 DEVSEL# AD27 Vss AD26 PIRQF# /

GPIO3

CLKOUTF

LEX0 /

GPIO64 Vss DDPD_CT

RLCLK

10 Vss PIRQA# AD11

11 AD19 AD5 IRDY# FRAME# Vss REQ3# /

GPIO54 CLKOUT_

PCI0 Vss Vss

12 GNT2# /

GPIO53 AD8 Vss AD31 AD6 AD4 Vss STOP# Vss Vss CLKOUT_

PCI2 Vss DDPC_CT

RLCLK

13 AD3 C/BE3# AD25

14 Vss AD20 PCIRST# CLKOUT_

PCI4 CLKOUT_

PCI1 DDPC_CT

RLDATA

15 PIRQG# /

GPIO4 TACH7 /

GPIO71 PIRQC# FWH0 /

LAD0 Vss AD17 AD0 CLKIN_PCI

LOOPBAC

KVss GNT0# PME# Vss Vss SDVO_CT

RLCLK

16 TACH4 /

GPIO68 TACH3 /

GPIO7 Vss

17 TACH0 /

GPIO17 TACH6 /

GPIO70 LDRQ0# FWH1 /

LAD1 FWH4 /

LFRAME# AD1 Vcc3_3 Vcc3_3 PLOCK# AD30 CLKOUT_

PCI3 Vss SDVO_CT

RLDATA

18 TACH5 /

GPIO69 Vss Vss Vss Vss

19 Vss TACH1 /

GPIO1 PWM3

20 PWM2 Vss FWH2 /

LAD2 FWH3 /

LAD3 Vss Vcc3_3 Vss LDRQ1# /

GPIO23 NC_1 Vcc3_3 Vcc3_3 Vss Vss Vss

21 PWM1 PWM0

22 HDA_BCL

KVss Vss HDA_SDIN

2HDA_SDIN

3Vss HDA_SDIN

1HDA_SDIN

0HDA_RST# TACH2 /

GPIO6 Vss Vss Vcc3_3 Vss VccASW Vss

23 HDA_SDO HDA_SYN

CVss

24 VccIO Vss VccASW VccASW VccASW

25 V5REF_Su

sUSBRBIAS

#USBRBIAS USBP10N USBP10P Vss Vss Vss HDA_DOC

K_EN# /

GPIO33

HDA_DOC

K_RST# /

GPIO13 VccIO

26 Vss USBP9N Vss VccIO Vss VccASW VccASW Vss

27 USBP9P USBP8N USBP13P USBP13N Vss USBP12N USBP12P Vss TP11 VccIO

28 Vss VccSusHD

AVss VccASW VccASW VccASW

280 Datasheet

Ballout Definition

Figure 6-2. Desktop PCH Ballout (Top View - Lower Left)

29 Vss USBP8P USBP5N

30 USBP5P VccSus3_3 VccASW VccASW Vss Vss

31 USBP4P Vss USBP11P USBP11N Vss USBP7N USBP7P Vss Vss VccSus3_3

32 USBP3P USBP4N Vss VccSus3_3 VccASW VccCore VccCore VccCore

33 USBP3N Vss USBP2N USBP6N USBP6P Vss Vss Vss USBP1N USBP1P VccSus3_3

34 Vss VccASW VccCore VccCore VccCore

35 VccSus3_3 Vss USBP2P

36 Vss Vss VccSus3_3 VccSus3_3VccSus3_3 Vss USBP0N USBP0P Vss TP17 TP18 VccASW VccASW VccASW Vss Vss

37 DPWROK SRTCRST#

38 INTRUDER

#RSMRST# PWROK Vss CLKIN_DO

T_96P CLKIN_DO

T_96N Vss VccIO Vss Vss VccSus3_3 VccASW Vcc3_3 Vcc3_3

39 Vss RTCX1 RTCX2

40 Vss VccDSW3_

3VccSus3_3 VccIO VccIO

41 RTCRST# INTVRMEN Vss OC5# /

GPIO9 OC2# /

GPIO41 Vss OC1# /

GPIO40 SLP_A# Vss DcpSusBy

pDcpSus VccIO Vss

42 VccRTC DSWVRME

NVss

43 PWRBTN# OC4# /

GPIO43 OC0# /

GPIO59 OC3# /

GPIO42 GPIO27 GPIO31 Vss SLP_SUS# SST JTAG_TCK

PCIECLKR

Q2# /

GPIO20/

SMI#

Vss Vss Vss

44 WAKE# Vss PCIECLKR

Q6# /

GPIO45

SATA5RX

PSATA3RX

PVss

45 OC6# /

GPIO10 SUSACK# OC7# /

GPIO14

SUSWARN

SUSPWRD

NACK/

GPIO30

SML1ALE

RT# /

PCHHOT#

/ GPIO74

TP10 SML1DAT

A / GPIO75SML1CLK /

GPIO58 DRAMPW

ROK Vss APWROK DcpSST BATLOW#

/ GPIO72 SATA5RX

NSATA3RX

NVss

47 SMBCLK Vss JTAG_TD

OVss SUSCLK /

GPIO62 Vss Vss Vss Vss

48 Vss PLTRST# RI#

49 SML0ALE

RT# /

GPIO60 SMBDATA SMBALER

T# /

GPIO11

SLP_LAN#

/ GPIO29 CL_RST1# TP12 Vss SATA5TXP SATA4TXP SATA4RX

NSATA2RX

50 SML0DAT

LAN_PHY_

PWR_CTR

L / GPIO12

SLP_S5# /

GPIO63 CL_DATA1 JTAG_TM

SCL_CLK1 SATA5TXN SATA4TXN SATA4RX

PSATA2RX

51 SML0CLK GPIO8

52 VSS_NCTF Vss SLP_S4# Vss Vss Vss SYS_RESE

T# JTAG_TDI Vss SATA1GP /

GPIO19 SERIRQ Vss Vss VccSPI Vss Vss

53 GPIO57 GPIO24 /

PROC_MIS

SING SLP_S3# SYS_PWR

OK SATA3GP /

GPIO37 SCLOCK /

GPIO22

SDATAOU

T1 /

GPIO48 SPI_MOSI SATA2TXP

54 VSS_NCTF DcpRTC SUS_STAT

# / GPIO61

PCIECLKR

Q5# /

GPIO44

SLOAD /

GPIO38 SATA0GP /

GPIO21 SPI_CLK Vss

55 PCIECLKR

Q7# /

GPIO46 GPIO15 GPIO28 SDATAOU

T0 /

GPIO39

SATA2GP /

GPIO36 BMBUSY#

/ GPIO0 SPI_MISO SATA3TXP

56 DcpRTC_N

CTF INIT3_3V# STP_PCI# /

GPIO34 RCIN# SPKR CLKRUN# /

GPIO32

SATA5GP /

GPIO49/

THERM_A

LERT#

SATA4GP /

GPIO16 SPI_CS1# SATA3TXN SATA2TXN

57 VSS_NCTF VSS_NCTF GPIO35/

NMI# SATALED# A20GATE Vss SPI_CS0# Vss

BU BT BR BP BN BM BL BK BJ BH BG BF BE BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK

Datasheet 281

Ballout Definition

Figure 6-3. Desktop PCH Ballout (Top View - Upper Right)

AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A

VccVRM CLKOUT_

PCIE7P VccADPLL

AVss DDPB_HP

DDDPD_HP

DVss VSS_NCT

FVSS_NCT

CLKOUT_

PCIE5P CLKOUT_

PCIE7N VccADPLL

BCLKOUT_

PCIE6P SDVO_INT

PVccVRM DDPC_HP

DDDPC_0P DDPC_1P DDPC_3N VSS_NCT

XTAL25_I

NCLKOUT_

PCIE5N CLKOUT_

PCIE6N SDVO_ST

ALLP SDVO_INT

NDDPB_3N DDPC_0N DDPC_2P Vss 3

Vss Vss Vss Vss DDPC_1N DDPC_3P Vss VSS_NCT

XTAL25_O

UT Vss CLKOUT_

PCIE1N CLKOUT_

PCIE1P SDVO_ST

ALLN DDPB_3P Vss DDPC_2N DDPD_0P DDPD_0N 5

Vss Vss CLKOUT_

PCIE0N CLKOUT_

PCIE0P Vss Vss Vss Vss DDPD_AU

XN DDPD_AU

XP Vss Vss Vss Vss DDPD_1P VSS_NCT

DDPD_1N DDPD_2P 7

CLKOUT_

PEG_A_N Vss CLKOUT_

PCIE3P CLKOUT_

PCIE4P SDVO_TV

CLKINP DDPB_AU

XP Vss DDPB_2N DDPB_2P Vss 8

CLKOUT_

PEG_A_P Vss CLKOUT_

PCIE3N CLKOUT_

PCIE4N SDVO_TV

CLKINN DDPB_AU

XN Vss Vss Vss DDPD_2N Vss 9

PERp8 PERn8 Vss 10

Vss CLKOUT_

PEG_B_P Vss Vss Vss Vss DDPB_1P DDPD_3P DDPD_3N 11

L_BKLTC

TL CLKOUT_

PEG_B_N CLKOUT_

PCIE2N TP20 DDPC_AU

XN DDPB_0N DDPB_1N Vss PERn7 PERp7 Vss Vss Vcc3_3 12

PETp7 PETp8 PETn8 13

Vss Vss CLKOUT_

PCIE2P TP19 DDPC_AU

XP DDPB_0P 14

VccDIFFC

LKN VccDIFFC

LKN Vss Vss Vss Vss PERn5 PERp5 PERp6 PERn6 Vss PETn7 Vss PETp6 15

Vss PETp5 PETn6 16

L_VDD_E

NVccDIFFC

LKN TP9 TP7 Vss Vss PERn4 PERp4 Vss PERp3 PERn3 PETp4 PETn5 17

L_BKLTE

NVss TP8 TP6 PETn4 18

Vss Vss VccAPLLD

MI2 19

VccClkDM

IVss VccSSC VccSSC Vss VccIO Vss Vss PERp2 PERn2 Vss PERp1 PERn1 Vss VccIO 20

PETn3 PETp3 21

Vss Vss Vss Vss Vss VccIO VccIO Vss Vss TP1 Vss TP24 TP28 Vss Vss PETn2 PETp2 22

PETp1 Vss Vss 23

VccASW VccASW VccCore VccCore Vss VccIO 24

VccIO Vss Vss Vss Vss TP27 TP23 Vss PETn1 TP36 TP32 25

VccASW VccASW Vss VccCore Vss VccIO Vss TP31 Vss 26

VccIO Vss CLKIN_GN

D1_N CLKIN_GN

D1_P Vss TP26 TP22 Vss TP34 TP35 27

VccASW VccASW VccCore VccCore Vss VccIO TP30 28

282 Datasheet

Ballout Definition

Figure 6-4. Desktop PCH Ballout (Top View - Lower Right)

TP33 TP29 Vss 29

Vss Vss VccCore VccCore Vss VccIO VccIO 30

VccIO VccSus3_

3CLKOUT_

DMI_P CLKOUT_

DMI_N Vss TP2 TP25 TP21 DMI_ZCO

MP DMI_IRCO

MP 31

VccCore VccCore VccCore VccCore DcpSus VccIO Vss Vss DMI2RBIA

S32

VccIO Vss CLKIN_D

MI_P CLKIN_D

MI_N Vss TP3 Vss Vss Vss DMI0RXN DMI0RXP 33

VccCore VccCore VccCore Vss VccIO VccIO 34

Vss Vss DMI1RXP 35

VccCore Vss VccCore Vss VccIO VccIO VccIO Vss Vss Vss Vss TP5 DMI0TXN DMI0TXP Vss DMI2RXP DMI1RXN 36

DMI3RXN DMI2RXN 37

VccIO VccIO Vss Vss Vss Vss Vss Vss DMI1TXP DMI1TXN TP4 Vss DMI2TXP DMI2TXN DMI3RXP 38

Vss Vss DcpSus 39

VccIO VccIO Vss Vss Vss 40

VccIO TP14 Vss Reserved Vss Vss DMI3TXP DMI3TXN Vss FDI_RXP2 FDI_RXN2 VccDMI VccDMI 41

Vss FDI_RXN0 Vss 42

Vss TP15 Vss Vss Reserved Vss FDI_RXP7 FDI_RXN7 Vss FDI_RXN6 FDI_RXP6 FDI_RXP1 Vss FDI_RXP0 43

Vss SATA0TX

PReserved Reserved Reserved Reserved 44

FDI_RXN1 Vss FDI_RXN4 45

Vss SATA0TX

NReserved Vss Reserved Vss Vss Reserved Vss FDI_INT Vss FDI_RXN3 FDI_RXP4 46

SATA1TX

PVss Vss Vss Vss DF_TVS FDI_RXP3 FDI_RXN5 47

Reserved Vss PECI Vss 48

SATA1TX

NTP13 Reserved Vss Reserved Vss Reserved Reserved FDI_LSYN

C0 FDI_RXP5 Vss 49

Vss TP16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Vss 50

FDI_LSYN

C1 FDI_FSYN

C0 51

Vss Vss SATA3RC

OMPO SATA3RBI

AS Vss Vss CLKIN_GN

D0_P Vss CLKOUT_I

TPXDP_N CLKOUT_I

TPXDP_P Vss Vss Reserved Reserved FDI_FSYN

C1 TS_VSS2 52

SATAICO

MPO Vss SATA1RX

NCLKIN_GN

D0_N Vss Reserved Vss Reserved PROCPW

RGD VccAPLLE

XP 53

SATA3CO

MPI Vss VccVRM Vss Vss Vss VccAFDIP

LL TS_VSS1 54

SATAICO

MPI CLKIN_SA

TA_N SATA0RX

PVss VccDFTER

MCLKOUT_

DP_P Reserved PMSYNCH V_PROC_I

O55

CLKIN_SA

TA_P Vss SATA0RX

NSATA1RX

PVccAPLLS

ATA VccVRM CLKOUT_D

P_N Reserved Reserved THRMTRI

P# V_PROC_I

O_NCTF 56

Vss Vcc3_3 Vss Vss VccDFTER

MVss Reserved TS_VSS3 TS_VSS4 57

AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A

Datasheet 283

Ballout Definition

Table 6-1. Desktop PCH Ballout By Signal Name

Desktop PCH

Ball Map Ball #

A20GATE BB57

AD0 BF15

AD1 BF17

AD2 BT7

AD3 BT13

AD4 BG12

AD5 BN11

AD6 BJ12

AD7 BU9

AD8 BR12

AD9 BJ3

AD10 BR9

AD11 BJ10

AD12 BM8

AD13 BF3

AD14 BN2

AD15 BE4

AD16 BE6

AD17 BG15

AD18 BC6

AD19 BT11

AD20 BA14

AD21 BL2

AD22 BC4

AD23 BL4

AD24 BC2

AD25 BM13

AD26 BA9

AD27 BF9

AD28 BA8

AD29 BF8

AD30 AV17

AD31 BK12

APWROK BC46

BATLOW# / GPIO72 AV46

BMBUSY# / GPIO0 AW55

C/BE0# BN4

C/BE1# BP7

C/BE2# BG2

C/BE3# BP13

CL_CLK1 BA50

CL_DATA1 BF50

CL_RST1# BF49

CLKIN_DMI_N P33

CLKIN_DMI_P R33

CLKIN_DOT_96N BD38

CLKIN_DOT_96P BF38

CLKIN_GND0_N W53

CLKIN_GND0_P V52

CLKIN_GND1_N R27

CLKIN_GND1_P P27

CLKIN_PCILOOPBACK BD15

CLKIN_SATA_N AF55

CLKIN_SATA_P AG56

CLKOUT_DMI_N P31

CLKOUT_DMI_P R31

CLKOUT_DP_N N56

CLKOUT_DP_P M55

CLKOUT_ITPXDP_N R52

CLKOUT_ITPXDP_P N52

CLKOUT_PCI0 AT11

CLKOUT_PCI1 AN14

CLKOUT_PCI2 AT12

CLKOUT_PCI3 AT17

CLKOUT_PCI4 AT14

CLKOUT_PCIE0N AE6

CLKOUT_PCIE0P AC6

CLKOUT_PCIE1N AA5

CLKOUT_PCIE1P W5

CLKOUT_PCIE2N AB12

CLKOUT_PCIE2P AB14

CLKOUT_PCIE3N AB9

CLKOUT_PCIE3P AB8

CLKOUT_PCIE4N Y9

CLKOUT_PCIE4P Y8

CLKOUT_PCIE5N AF3

CLKOUT_PCIE5P AG2

CLKOUT_PCIE6N AB3

CLKOUT_PCIE6P AA2

CLKOUT_PCIE7N AE2

CLKOUT_PCIE7P AF1

CLKOUT_PEG_A_N AG8

CLKOUT_PEG_A_P AG9

CLKOUT_PEG_B_N AE12

CLKOUT_PEG_B_P AE11

CLKOUTFLEX0 /

GPIO64 AT9

CLKOUTFLEX1 /

GPIO65 BA5

CLKOUTFLEX2 /

GPIO66 AW5

Desktop PCH

Ball Map Ball #

CLKOUTFLEX3 /

GPIO67 BA2

CLKRUN# / GPIO32 BC56

CRT_BLUE AM1

CRT_DDC_CLK AW3

CRT_DDC_DATA AW1

CRT_GREEN AN2

CRT_HSYNC AR4

CRT_IRTN AM6

CRT_RED AN6

CRT_VSYNC AR2

DAC_IREF AT3

DcpRTC BR54

DcpRTC_NCTF BT56

DcpSST BA46

DcpSus AA32

DcpSus AT41

DcpSus A39

DcpSusByp AV41

DDPB_0N R12

DDPB_0P R14

DDPB_1N M12

DDPB_1P M11

DDPB_2N K8

DDPB_2P H8

DDPB_3N M3

DDPB_3P L5

DDPB_AUXN R9

DDPB_AUXP R8

DDPB_HPD T1

DDPC_0N J3

DDPC_0P L2

DDPC_1N G4

DDPC_1P G2

DDPC_2N F5

DDPC_2P F3

DDPC_3N E2

DDPC_3P E4

DDPC_AUXN U12

DDPC_AUXP U14

DDPC_CTRLCLK AL12

DDPC_CTRLDATA AL14

DDPC_HPD N2

DDPD_0N B5

DDPD_0P D5

DDPD_1N D7

Desktop PCH

Ball Map Ball #

284 Datasheet

Ballout Definition

DDPD_1P C6

DDPD_2N C9

DDPD_2P B7

DDPD_3N B11

DDPD_3P E11

DDPD_AUXN R6

DDPD_AUXP N6

DDPD_CTRLCLK AL9

DDPD_CTRLDATA AL8

DDPD_HPD M1

DEVSEL# BH9

DMI_IRCOMP B31

DMI_ZCOMP E31

DMI0RXN D33

DMI0RXP B33

DMI0TXN J36

DMI0TXP H36

DMI1RXN A36

DMI1RXP B35

DMI1TXN P38

DMI1TXP R38

DMI2RBIAS A32

DMI2RXN B37

DMI2RXP C36

DMI2TXN H38

DMI2TXP J38

DMI3RXN E37

DMI3RXP F38

DMI3TXN M41

DMI3TXP P41

DPWROK BT37

DRAMPWROK BG46

DSWVRMEN BR42

FDI_FSYNC0 B51

FDI_FSYNC1 C52

FDI_INT H46

FDI_LSYNC0 E49

FDI_LSYNC1 D51

FDI_RXN0 C42

FDI_RXN1 F45

FDI_RXN2 H41

FDI_RXN3 C46

FDI_RXN4 B45

FDI_RXN5 B47

FDI_RXN6 J43

FDI_RXN7 M43

Desktop PCH

Ball Map Ball #

FDI_RXP0 B43

FDI_RXP1 F43

FDI_RXP2 J41

FDI_RXP3 D47

FDI_RXP4 A46

FDI_RXP5 C49

FDI_RXP6 H43

FDI_RXP7 P43

FRAME# BC11

FWH0 / LAD0 BK15

FWH1 / LAD1 BJ17

FWH2 / LAD2 BJ20

FWH3 / LAD3 BG20

FWH4 / LFRAME# BG17

GNT0# BA15

GNT1# / GPIO51 AV8

GNT2# / GPIO53 BU12

GNT3# / GPIO55 BE2

GPIO15 BM55

GPIO24 /

PROC_MISSING BP53

GPIO27 BJ43

GPIO28 BJ55

GPIO31 BG43

GPIO35 / NMI# BJ57

GPIO57 BT53

GPIO8 BP51

HDA_BCLK BU22

HDA_DOCK_EN# /

GPIO33 BC25

HDA_DOCK_RST# /

GPIO13 BA25

HDA_RST# BC22

HDA_SDIN0 BD22

HDA_SDIN1 BF22

HDA_SDIN2 BK22

HDA_SDIN3 BJ22

HDA_SDO BT23

HDA_SYNC BP23

INIT3_3V# BN56

INTRUDER# BM38

INTVRMEN BN41

IRDY# BF11

JTAG_TCK BA43

JTAG_TDI BC52

JTAG_TDO BF47

JTAG_TMS BC50

L_BKLTCTL AG12

Desktop PCH

Ball Map Ball #

L_BKLTEN AG18

L_VDD_EN AG17

LAN_PHY_PWR_CTRL /

GPIO12 BK50

LDRQ0# BK17

LDRQ1# / GPIO23 BA20

TS_VSS1 A54

TS_VSS2 A52

TS_VSS3 F57

TS_VSS4 D57

NC_1 AY20

Reserved M48

Reserved K50

Reserved K49

Reserved AB46

Reserved G56

DF_TVS R47

Reserved AB50

Reserved Y50

Reserved AB49

Reserved AB44

Reserved U49

Reserved R44

Reserved U50

Reserved U46

Reserved U44

Reserved H50

Reserved K46

Reserved L56

Reserved J55

Reserved F53

Reserved H52

Reserved E52

Reserved Y44

Reserved L53

Reserved Y41

Reserved R50

Reserved M50

Reserved M49

Reserved U43

Reserved J57

OC0# / GPIO59 BM43

OC1# / GPIO40 BD41

OC2# / GPIO41 BG41

OC3# / GPIO42 BK43

OC4# / GPIO43 BP43

OC5# / GPIO9 BJ41

Desktop PCH

Ball Map Ball #

Datasheet 285

Ballout Definition

OC6# / GPIO10 BT45

OC7# / GPIO14 BM45

PAR BH8

PCIECLKRQ2# /

GPIO20 / SMI# AV43

PCIECLKRQ5# /

GPIO44 BL54

PCIECLKRQ6# /

GPIO45 AV44

PCIECLKRQ7# /

GPIO46 BP55

PCIRST# AV14

PECI H48

PERn1 J20

PERn2 P20

PERn3 H17

PERn4 P17

PERn5 N15

PERn6 J15

PERn7 J12

PERn8 H10

PERp1 L20

PERp2 R20

PERp3 J17

PERp4 M17

PERp5 M15

PERp6 L15

PERp7 H12

PERp8 J10

PERR# BM3

PETn1 F25

PETn2 C22

PETn3 E21

PETn4 F18

PETn5 B17

PETn6 A16

PETn7 F15

PETn8 B13

PETp1 F23

PETp2 A22

PETp3 B21

PETp4 E17

PETp5 C16

PETp6 B15

PETp7 F13

PETp8 D13

PIRQA# BK10

PIRQB# BJ5

Desktop PCH

Ball Map Ball #

PIRQC# BM15

PIRQD# BP5

PIRQE# / GPIO2 BN9

PIRQF# / GPIO3 AV9

PIRQG# / GPIO4 BT15

PIRQH# / GPIO5 BR4

PLOCK# BA17

PLTRST# BK48

PME# AV15

PMSYNCH F55

PROCPWRGD D53

PWM0 BN21

PWM1 BT21

PWM2 BM20

PWM3 BN19

PWRBTN# BT43

PWROK BJ38

RCIN# BG56

REFCLK14IN AN8

REQ0# BG5

REQ1# / GPIO50 BT5

REQ2# / GPIO52 BK8

REQ3# / GPIO54 AV11

RI# BJ48

RSMRST# BK38

RTCRST# BT41

RTCX1 BR39

RTCX2 BN39

SATA0GP / GPIO21 BC54

SATA0RXN AC56

SATA0RXP AB55

SATA0TXN AE46

SATA0TXP AE44

SATA1GP / GPIO19 AY52

SATA1RXN AA53

SATA1RXP AA56

SATA1TXN AG49

SATA1TXP AG47

SATA2GP / GPIO36 BB55

SATA2RXN AL50

SATA2RXP AL49

SATA2TXN AL56

SATA2TXP AL53

SATA3COMPI AE54

SATA3GP / GPIO37 BG53

SATA3RBIAS AC52

Desktop PCH

Ball Map Ball #

SATA3RCOMPO AE52

SATA3RXN AN46

SATA3RXP AN44

SATA3TXN AN56

SATA3TXP AM55

SATA4GP / GPIO16 AU56

SATA4RXN AN49

SATA4RXP AN50

SATA4TXN AT50

SATA4TXP AT49

SATA5GP / GPIO49 /

THERM_ALERT# BA56

SATA5RXN AT46

SATA5RXP AT44

SATA5TXN AV50

SATA5TXP AV49

SATAICOMPI AJ55

SATAICOMPO AJ53

SATALED# BF57

SCLOCK / GPIO22 BA53

SDATAOUT0 / GPIO39 BF55

SDATAOUT1 / GPIO48 AW53

SDVO_CTRLCLK AL15

SDVO_CTRLDATA AL17

SDVO_INTN T3

SDVO_INTP U2

SDVO_STALLN U5

SDVO_STALLP W3

SDVO_TVCLKINN U9

SDVO_TVCLKINP U8

SERIRQ AV52

SERR# BR6

SLOAD / GPIO38 BE54

SLP_A# BC41

SLP_LAN# / GPIO29 BH49

SLP_S3# BM53

SLP_S4# BN52

SLP_S5# / GPIO63 BH50

SLP_SUS# BD43

SMBALERT# / GPIO11 BN49

SMBCLK BT47

SMBDATA BR49

SML0ALERT# /

GPIO60 BU49

SML0CLK BT51

SML0DATA BM50

Desktop PCH

Ball Map Ball #

286 Datasheet

Ballout Definition

SML1ALERT# /

PCHHOT# / GPIO74 BR46

SML1CLK / GPIO58 BJ46

SML1DATA / GPIO75 BK46

SPI_CLK AR54

SPI_CS0# AT57

SPI_CS1# AR56

SPI_MISO AT55

SPI_MOSI AU53

SPKR BE56

SRTCRST# BN37

SST BC43

STOP# BC12

STP_PCI# / GPIO34 BL56

SUS_STAT# / GPIO61 BN54

SUSACK# BP45

SUSCLK / GPIO62 BA47

SUSWARN#/

SUSPWRDNACK/

GPIO30

BU46

SYS_PWROK BJ53

SYS_RESET# BE52

TACH0 / GPIO17 BT17

TACH1 / GPIO1 BR19

TACH2 / GPIO6 BA22

TACH3 / GPIO7 BR16

TACH4 / GPIO68 BU16

TACH5 / GPIO69 BM18

TACH6 / GPIO70 BN17

TACH7 / GPIO71 BP15

THRMTRIP# E56

TP1 P22

TP2 L31

TP3 L33

TP4 M38

TP5 L36

TP6 Y18

TP7 Y17

TP8 AB18

TP9 AB17

TP10 BM46

TP11 BA27

TP12 BC49

TP13 AE49

TP14 AE41

TP15 AE43

TP16 AE50

TP17 BA36

Desktop PCH

Ball Map Ball #

TP18 AY36

TP19 Y14

TP20 Y12

TP21 H31

TP22 J27

TP23 J25

TP24 L22

TP25 J31

TP26 L27

TP27 L25

TP28 J22

TP29 C29

TP30 F28

TP31 C26

TP32 B25

TP33 E29

TP34 E27

TP35 B27

TP36 D25

TRDY# BC8

USBP0N BF36

USBP0P BD36

USBP1N BC33

USBP1P BA33

USBP2N BM33

USBP2P BM35

USBP3N BT33

USBP3P BU32

USBP4N BR32

USBP4P BT31

USBP5N BN29

USBP5P BM30

USBP6N BK33

USBP6P BJ33

USBP7N BF31

USBP7P BD31

USBP8N BN27

USBP8P BR29

USBP9N BR26

USBP9P BT27

USBP10N BK25

USBP10P BJ25

USBP11N BJ31

USBP11P BK31

USBP12N BF27

USBP12P BD27

Desktop PCH

Ball Map Ball #

USBP13N BJ27

USBP13P BK27

USBRBIAS BM25

USBRBIAS# BP25

V_PROC_IO D55

V_PROC_IO_NCTF B56

V5REF BF1

V5REF_Sus BT25

Vcc3_3 AF57

Vcc3_3 BC17

Vcc3_3 BD17

Vcc3_3 BD20

Vcc3_3 AL38

Vcc3_3 AN38

Vcc3_3 AU22

Vcc3_3 A12

Vcc3_3 AU20

Vcc3_3 AV20

VccAClk AL5

VccADAC AT1

VccADPLLA AB1

VccADPLLB AC2

VccAFDIPLL C54

VccAPLLDMI2 A19

VccAPLLEXP B53

VccAPLLSATA U56

VccASW AU32

VccASW AV36

VccASW AU34

VccASW AG24

VccASW AG26

VccASW AG28

VccASW AJ24

VccASW AJ26

VccASW AJ28

VccASW AL24

VccASW AL28

VccASW AN22

VccASW AN24

VccASW AN26

VccASW AN28

VccASW AR24

VccASW AR26

VccASW AR28

VccASW AR30

Desktop PCH

Ball Map Ball #

Datasheet 287

Ballout Definition

VccASW AR36

VccASW AR38

VccASW AU30

VccASW AU36

VccClkDMI AJ20

VccCore AC24

VccCore AC26

VccCore AC28

VccCore AC30

VccCore AC32

VccCore AE24

VccCore AE28

VccCore AE30

VccCore AE32

VccCore AE34

VccCore AE36

VccCore AG32

VccCore AG34

VccCore AJ32

VccCore AJ34

VccCore AJ36

VccCore AL32

VccCore AL34

VccCore AN32

VccCore AN34

VccCore AR32

VccCore AR34

VccDIFFCLKN AE15

VccDIFFCLKN AE17

VccDIFFCLKN AG15

VccDMI E41

VccDMI B41

VccDSW3_3 AV40

VccIO AV24

VccIO AV26

VccIO AY25

VccIO AY27

VccIO AG41

VccIO AL40

VccIO AN40

VccIO AN41

VccIO AJ38

VccIO Y36

VccIO V36

VccIO Y28

Desktop PCH

Ball Map Ball #

VccIO AE40

VccIO BA38

VccIO AG38

VccIO AG40

VccIO AA34

VccIO AA36

VccIO F20

VccIO F30

VccIO V25

VccIO V27

VccIO V31

VccIO V33

VccIO Y24

VccIO Y26

VccIO Y30

VccIO Y32

VccIO Y34

VccIO V22

VccIO Y20

VccIO Y22

VccDFTERM T55

VccDFTERM T57

VccRTC BU42

VccSPI AN52

VccSSC AC20

VccSSC AE20

VccSus3_3 U31

VccSus3_3 AV30

VccSus3_3 AV32

VccSus3_3 AY31

VccSus3_3 AY33

VccSus3_3 BJ36

VccSus3_3 BK36

VccSus3_3 BM36

VccSus3_3 AT40

VccSus3_3 AU38

VccSus3_3 BT35

VccSusHDA AV28

VccVRM AJ1

VccVRM R56

VccVRM R54

VccVRM R2

Vss AE56

Vss BR36

Vss C12

Vss AY22

Desktop PCH

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Vss A26

Vss A29

Vss A42

Vss A49

Vss A9

Vss AA20

Vss AA22

Vss AA24

Vss AA26

Vss AA28

Vss AA30

Vss AA38

Vss AB11

Vss AB15

Vss AB40

Vss AB41

Vss AB43

Vss AB47

Vss AB52

Vss AB57

Vss AB6

Vss AC22

Vss AC34

Vss AC36

Vss AC38

Vss AC4

Vss AC54

Vss AE14

Vss AE18

Vss AE22

Vss AE26

Vss AE38

Vss AE4

Vss AE47

Vss AE8

Vss AE9

Vss AF52

Vss AF6

Vss AG11

Vss AG14

Vss AG20

Vss AG22

Vss AG30

Vss AG36

Vss AG43

Vss AG44

Desktop PCH

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288 Datasheet

Ballout Definition

Vss AG46

Vss AG5

Vss AG50

Vss AG53

Vss AH52

Vss AH6

Vss AJ22

Vss AJ30

Vss AJ57

Vss AK52

Vss AK6

Vss AL11

Vss AL18

Vss AL20

Vss AL22

Vss AL26

Vss AL30

Vss AL36

Vss AL41

Vss AL46

Vss AL47

Vss AM3

Vss AM52

Vss AM57

Vss AN11

Vss AN12

Vss AN15

Vss AN17

Vss AN18

Vss AN20

Vss AN30

Vss AN36

Vss AN4

Vss AN43

Vss AN47

Vss AN54

Vss AN9

Vss AR20

Vss AR22

Vss AR52

Vss AR6

Vss AT15

Vss AT18

Vss AT43

Vss AT47

Vss AT52

Desktop PCH

Ball Map Ball #

Vss AT6

Vss AT8

Vss AU24

Vss AU26

Vss AU28

Vss AU5

Vss AV12

Vss AV18

Vss AV22

Vss AV34

Vss AV38

Vss AV47

Vss AV6

Vss AW57

Vss AY38

Vss AY6

Vss B23

Vss BA11

Vss BA12

Vss BA31

Vss BA41

Vss BA44

Vss BA49

Vss BB1

Vss BB3

Vss BB52

Vss BB6

Vss BC14

Vss BC15

Vss BC20

Vss BC27

Vss BC31

Vss BC36

Vss BC38

Vss BC47

Vss BC9

Vss BD25

Vss BD33

Vss BF12

Vss BF20

Vss BF25

Vss BF33

Vss BF41

Vss BF43

Vss BF46

Vss BF52

Desktop PCH

Ball Map Ball #

Vss BF6

Vss BG22

Vss BG25

Vss BG27

Vss BG31

Vss BG33

Vss BG36

Vss BG38

Vss BH52

Vss BH6

Vss BJ1

Vss BJ15

Vss BK20

Vss BK41

Vss BK52

Vss BK6

Vss BM10

Vss BM12

Vss BM16

Vss BM22

Vss BM23

Vss BM26

Vss BM28

Vss BM32

Vss BM40

Vss BM42

Vss BM48

Vss BM5

Vss BN31

Vss BN47

Vss BN6

Vss BP3

Vss BP33

Vss BP35

Vss BR22

Vss BR52

Vss BU19

Vss BU26

Vss BU29

Vss BU36

Vss BU39

Vss C19

Vss C32

Vss C39

Vss C4

Vss D15

Desktop PCH

Ball Map Ball #

Datasheet 289

Ballout Definition

Vss D23

Vss D3

Vss D35

Vss D43

Vss D45

Vss E19

Vss E39

Vss E54

Vss E6

Vss E9

Vss F10

Vss F12

Vss F16

Vss F22

Vss F26

Vss F32

Vss F33

Vss F35

Vss F36

Vss F40

Vss F42

Vss F46

Vss F48

Vss F50

Vss F8

Vss G54

Vss H15

Vss H20

Vss H22

Vss H25

Vss H27

Vss H33

Vss H6

Vss J1

Vss J33

Vss J46

Vss J48

Vss J5

Vss J53

Vss K52

Vss K6

Vss K9

Vss L12

Vss L17

Vss L38

Vss L41

Desktop PCH

Ball Map Ball #

Vss L43

Vss M20

Vss M22

Vss M25

Vss M27

Vss M31

Vss M33

Vss M36

Vss M46

Vss M52

Vss M57

Vss M6

Vss M8

Vss M9

Vss N4

Vss N54

Vss R11

Vss R15

Vss R17

Vss R22

Vss R4

Vss R41

Vss R43

Vss R46

Vss R49

Vss T52

Vss T6

Vss U11

Vss U15

Vss U17

Vss U20

Vss U22

Vss U25

Vss U27

Vss U33

Vss U36

Vss U38

Vss U41

Vss U47

Vss U53

Vss V20

Vss V38

Vss V6

Vss W1

Vss W55

Vss W57

Desktop PCH

Ball Map Ball #

Vss Y11

Vss Y15

Vss Y38

Vss Y40

Vss Y43

Vss Y46

Vss Y47

Vss Y49

Vss Y52

Vss Y6

Vss AL43

Vss AL44

Vss R36

Vss P36

Vss R25

Vss P25

VSS_NCTF A4

VSS_NCTF A6

VSS_NCTF B2

VSS_NCTF BM1

VSS_NCTF BM57

VSS_NCTF BP1

VSS_NCTF BP57

VSS_NCTF BT2

VSS_NCTF BU4

VSS_NCTF BU52

VSS_NCTF BU54

VSS_NCTF BU6

VSS_NCTF D1

VSS_NCTF F1

VssADAC AU2

WAKE# BC44

XCLK_RCOMP AL2

XTAL25_IN AJ3

XTAL25_OUT AJ5

Desktop PCH

Ball Map Ball #

290 Datasheet

Ballout Definition

6.2 Mobile PCH Ballout

This section contains the PCH ballout. Figure 6-5, Figure 6-6, Figure 6-7 and Figure 6-8

show the ballout from a top of the package quadrant view. Ta b l e 6 - 2 is the BGA ball list,

sorted alphabetically by signal name.

Figure 6-5. Mobile PCH Ballout (Top View - Upper Left)

49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

BJ Vss_NCTF Vss_NCTF Vss_NCTF DDPD_3N PERp7 PERn6 PERp3 PERp1 TP28 CLKIN_GND

1_N Vss TP2

BH Vss_NCTF Vss DDPD_HPD Vss PERp5 Vss Vss Vss Vcc3_3 Vss

BG Vss_NCTF TP24 Vss DDPD_3P Vss PERn7 PERp6 PERn5 PERn3 PERn1 Vss TP32 CLKIN_GND

1_P Vss Vss TP1

BF Vss_NCTF VccADPLLB DDPD_1N DDPD_2N Vss Vss PERn4 PERp2 TP31 Vss Vss Vss

BE Vss_NCTF DDPD_1P DDPD_2P Vss PERn8 PERp4 PERn2 TP27 TP30 TP25 Vss

BD Vss_NCTF VccADPLLA Vss

BC Vss Vss Vss PERp8 Vss Vss Vss TP26 TP29 Vss

BB DDPC_3P DDPC_3N Vss DDPD_0P DDPD_0N PETp7 Vss PETp5 PETp4 PETn2 Vss Vss TP34

BA DDPC_2P DDPC_2N

AY DDPC_0P DDPC_0N Vss DDPC_1P DDPC_1N Vss PETn7 PETp8 PETn5 PETn4 PETp2 TP36 Vss TP38

AW Vss Vss PETn8 Vss Vss Vss TP40 Vss Vss

AV DDPB_3P DDPB_3N DDPB_1P DDPB_1N Vss DDPB_0N DDPB_0P Vss PETp6 PETn3 PETn1 Vss TP39 TP33

AU DDPB_2N DDPB_2P PETn6 PETp3 PETp1 Vss TP35 TP37

AT DDPB_AUX

NDDPB_AUX

PVss DDPD_AUX

NDDPD_AUX

PVss DDPB_HPD Vss DDPC_HPD Vss Vss Vss Vss Vss

AR Vss

AP DDPC_AUX

PDDPC_AUX

NVss SDVO_TVCL

KINP SDVO_TVCL

KINN Vss SDVO_INTP SDVO_INTN Vss VccTX_LVD

SVccTX_LVD

SVss Vss Vss VccIO

AN LVDSA_DAT

A#0 LVDSA_DAT

A0 VccIO VccIO Vss Vss VccIO VccIO

AM LVDSA_DAT

A1 LVDSA_DAT

A#1 Vss Vss Vss SDVO_STAL

LN SDVO_STAL

LP Vss VccTX_LVD

SVccTX_LVD

SVss

AL Vss Vss Vss Vss VccIO Vss Vss

AK LVDSA_DAT

A2 LVDSA_DAT

A#2 Vss TP9 TP8 Vss LVDSA_CLKLVDSA_CLK

#Vss VssALVDS VccALVDS

AJ LVDSA_DAT

A#3 LVDSA_DAT

A3 Vss Vss VccCore VccCore VccCore VccCore

AH LVDSB_DAT

A1 LVDSB_DAT

A#1 Vss LVDSB_DAT

A#0 LVDSB_DAT

A0 Vss Vss Vss TP6 TP7 Vss

AG Vss VccDIFFCLK

NVccSSC Vss VccCore VccCore VccCore

AF LVDSB_DAT

A#2 LVDSB_DAT

A2 Vss LVDSB_DAT

A#3 LVDSB_DAT

A3 Vss LVDSB_CLK

#LVDSB_CLK Vss LVD_IBG LVD_VBG VccDIFFCLK

NVccDIFFCLK

NVss Vss Vss Vss

Datasheet 291

Ballout Definition

Figure 6-6. Mobile PCH Ballout (Top View - Lower Left)

AE LVD_VREFH LVD_VREFL

AD VccAClk Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss VccASW VccASW Vss Vss

AC Vss Vss Vss VccASW VccASW VccASW VccASW

AB CLKOUT_PC

IE1N CLKOUT_PC

IE1P TP19 TP20 Vss CLKOUT_PE

G_B_N CLKOUT_PE

G_B_P Vss CLKOUT_PE

G_A_P CLKOUT_PE

G_A_N VccClkDMI

AA CLKOUT_PC

IE2N CLKOUT_PC

IE2P Vss Vss VccASW VccASW VccASW VccASW

YVccVRM XCLK_RCO

MP Vss CLKOUT_PC

IE4P CLKOUT_PC

IE4N Vss CLKOUT_PC

IE0N CLKOUT_PC

IE0P Vss CLKOUT_PC

IE3N CLKOUT_PC

IE3P

WVss Vss VccASW VccASW VccASW Vss VccASW

VXTAL25_OU

TXTAL25_IN CLKOUT_PC

IE5P CLKOUT_PC

IE5N Vss CLKOUT_PC

IE6P CLKOUT_PC

IE6N Vss CLKOUT_PC

IE7N CLKOUT_PC

IE7P Vss Vcc3_3 Vcc3_3 Vss Vss Vss Vss

UVccADAC VssADAC

TCRT_RED Vss Vss L_CTRL_CL

KDAC_IREF CRT_IRTN L_DDC_CLK CRT_DDC_C

LK Vcc3_3 Vss Vss Vcc3_3 Vss Vss VccIO VccIO VccIO

RVss

PCRT_GREEN Vss DDPC_CTRL

CLK L_BKLTCTL Vss DDPC_CTRL

DATA Vss L_CTRL_DA

TA SDVO_CTRL

CLK NC_1 V5REF VccSusHDA Vss VccIO VccIO

NCRT_BLUE Vss HDA_BCLK HDA_DOCK

_RST# /

GPIO13

TP11 USBP7N VccIO

MCRT_VSYNC CRT_HSYNC Vss L_VDD_EN DDPD_CTRL

CLK Vss CRT_DDC_D

ATA SDVO_CTRL

DATA Vss DDPD_CTRL

DATA Vss Vss Vss USBP7P V5REF_Sus

LVss Vss HDA_SYNC USBP11N USBP8N Vss Vss

KCLKOUTFLE

X3 / GPIO67 L_DDC_DAT

AVss REFCLK14IN CLKOUTFLE

X0 / GP IO64 CLKOUT_PC

I3 PIRQA# Vss PIRQB# LDRQ1# /

GPIO23 HDA_RST# USBP11P USBP8P USBP3N Vss

JCLKOUT_PC

I2 L_BKLTEN

HCLKOUT_PC

I0 CLKOUTFLE

X2 / GP IO66 Vss CLKIN_PCIL

OOPBACK CLKOUT_PC

I1 CLKOUT_PC

I4 PIRQC# GPIO6 Vss Vss Vss USBP3P Vss

GVss PIRQE# /

GPIO2 PIRQF# /

GPIO3 PIRQD# Vss HDA_SDIN1 USBP12N USBP9N Vss Vss

FVss_NCTF CLKOUTFLE

X1 / GP IO65 GNT 3# /

GPIO55 Vss

EVss_NCTF GNT2# /

GPIO53 REQ3# /

GPIO54 GPIO7 LDRQ0# HDA_SDIN0 USBP12P USBP9P USBP4N Vss

DVss_NCTF GNT1# /

GPIO51 PIRQH# /

GPIO5 Vss GPIO17 Vss FWH4 /

LFRAME# Vss Vss Vss USBP4P Vss

CVss_NCTF REQ1# /

GPIO50 REQ2# /

GPIO52 PIRQG# /

GPIO4 GPIO70 GPIO68 FWH0 /

LAD0 FWH3 /

LAD3 HDA_DOCK

_EN# /

GPIO33

HDA_SDIN2 USBRBIAS# USBP13N USBP10N USBP6N USBP5N USBP2N

BVss_NCTF Vss GPIO69 Vss FWH2 /

LAD2 Vss USBRBIAS Vss USBP6P Vss

AVss_NCTF Vss_NCTF Vss_NCTF GPIO1 GPIO71 FWH1 /

LAD1 HDA_SDO HDA_SDIN3 USBP13P USBP10P USBP5P USBP2P

49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

292 Datasheet

Ballout Definition

Figure 6-7. Mobile PCH Ballout (Top View - Upper Right)

25242322212019181716151413121110987654321

DMI_ZCOM

PVccAPLLEX

PDMI3RXP DMI2RXP TP4 FDI_RXN0 FDI_RXN5 FDI_RXP6 V_PROC_IO Vss_NCTF Vss_NCTF Vss_NCTF BJ

TP3 VccAPLLD

MI2 DMI2RBIAS Vss Vss Vss FDI_RXN3 Vss FDI_RXP7 Vss Vss_NCTF BH

DMI_IRCOM

PVss Vss Vss DMI3RXN DMI2RXN Vss TP5 FDI_RXP0 FDI_RXP3 FDI_RXP5 FDI_RXN6 FDI_RXN7 Vss VccAFDIPL

LReserved Vss_NCTF BG

Vss Vss Vss CLKIN_DMI

_N Vss FDI_RXP2 Vss Vss Vss Reserved Reserved Vss_NCTF BF

DMI0RXP Vss DMI1RXN CLKIN_DMI

_P Vss FDI_RXN2 FDI_RXP4 Vss Reserved Vss_NCTF BE

Vss Reserved Vss Vss_NCTF BD

DMI0RXN Vss DMI1RXP Vss Vss Vss FDI_RXN4 FDI_FSYNC

1Reserved Vss BC

Vss Vss Vss DMI2TXN Vss FDI_RXP1 Vss FDI_LSYNC

1Reserved Reserved Vss Reserved Reserved BB

Reserved Reserved BA

DMI0TXP Vss DMI1TXP DMI2TXP TP23 FDI_RXN1 Vss PROCPWR

GD THRMTRIP# Vss Reserved Reserved Vss Reserved DF_TVS AY

DMI0TXN Vss DMI1TXN Vss FDI_INT Vss Vss AW

Vss CLKOUT_D

MI_N Vss DMI3TXN Vss FDI_LSYNC

0FDI_FSYNC

0Vss Reserved Vss Reserved Reserved Vss Reserved Reserved AV

Vss CLKOUT_D

MI_P VccDMI DMI3TXP PECI Reserved Reserved AU

VccIO Vss VccDMI Vss VccVRM Vss Reserved Vss Reserved Reserved Vss Reserved Reserved Reserved Reserved AT

Vss AR

VccIO VccIO VccIO Vss VccIO VccVRM PMSYNCH Vss Vss SATA1TXN SATA1TXP Vss SATA0TXN SATA0TXP Vss Vss Vss AP

VccSus3_3 DcpSus VccIO VccIO VccIO VccIO Vss Vss AN

Vss CLKOUT_D

P_P CLKOUT_D

P_N Vss SATA1RXN SATA1RXP Vss TP15 TP14 SATA0RXN SATA0RXP AM

DcpSus Vss Vss Vss Vss Vss Vss AL

CLKOUT_IT

PXDP_N CLKOUT_IT

PXDP_P Vss TS_VSS2 TS_VSS4 Vss CLKIN_SAT

A_N CLKIN_SAT

A_P Vss Vss VccAPLLSA

TA AK

Vss VccCore Vss Vss VccDFTER

MVccDFTER

MVss Vcc3_3 AJ

VccIO VccIO TP13 Vss VS_TSS3 TS_VSS1 Vss SATA2TXN SATA2TXP Vss SATA3RBIA

SAH

VccCore VccCore VccCore Vss VccDFTER

MVccDFTER

MVss AG

Vss VccCore VccCore Vss VccIO Vss VccIO VccIO Vss VccVRM Vss Vss Vss Vss Vss SATA3TXN SATA3TXP AF

Datasheet 293

Ballout Definition

Figure 6-8. Mobile PCH Ballout (Top View - Lower Right)

Vss Vss AE

Vss VccCore VccCore Vss VccIO Vss Vss Vss Vss Vss Vss Vss SATA2RXN SATA2RXP Vss SATA4TXN SATA4TXP AD

Vss VccCore Vss Vss VccIO VccIO Vss AC

Vss SATA3COM

PI SATA3RCO

MPO Vss SATA3RXP SATA3RXN Vss Vss Vss SATA5TXN SATA5TXP AB

VccASW VccCore VccASW VccASW Vss Vcc3_3 Vss Vss AA

SPI_CS0# TP16 Vss SATAICOM

PO SATAICOM

PI Vss SATA4RXN SATA4RXP Vss SATA5RXN SATA5RXP Y

VccASW VccASW VccASW Vss Vss Vcc3_3 Vss W

VccSus3_3 VccSus3_3 VccASW DcpSus Vss DcpSST SATA0GP /

GPIO21 SDATAOUT

1 / GPIO48 DcpSusByp Vss PCIECLKRQ

2# / GPIO20 SATA2GP /

GPIO36 Vss SERIRQ SPI_MOSI

SATA5GP /

GPIO49/

THERM_AL

ERT#

VccSPI V

SPI_MISO SATA4GP /

GPIO16 U

VccSus3_3 VccSus3_3 VccASW VccASW DcpSus VccDSW3_3 INIT3_3V# PCIECLKRQ

6# / GPIO45 Vss CL_DATA1 SPKR Vss BMBUSY# /

GPIO0 SCLOCK /

GPIO22 Vss SPI_CLK SPI_CS1# T

Vss R

VccSus3_3 VccSus3_3 VccSus3_3 Vss Vss SYS_PWRO

KVss CL_RST1# GPIO28 Vss RCIN# A20GATE SATALED# SATA1GP /

GPIO19 P

Vss VccSus3_3 VccSus3_3 Vss DcpRTC SUSCLK /

GPIO62 CLKRUN# /

GPIO32 SL OAD /

GPIO38 N

Vss Vss TP22 Vss SML1DATA

/ GPIO75 Vss Vss PEG_A_CL

KRQ# /

GPIO47 Vss CL_CLK1 SATA3GP /

GPIO37 Vss SDATAOUT

0 / GPIO39 PCIECLKRQ

1# / GPIO18 M

TP18 PWROK Vss Vss OC4# /

GPIO43 PCIECLKRQ

5# / GPIO44 PCIECLKRQ

4# / GPIO26 APWROK Vss L

TP17 INTRUDER# OC1# /

GPIO40 Vss

SUSWARN#

SUSPWRDN

ACK/

GPIO30

SLP_LAN# /

GPIO29 PCIECLKRQ

7# / GPIO46 PME# Vss JTAG_TDI GPIO35 SYS_RESET

#STP_PCI# /

GPIO34 K

JTAG_TCK PCIECLKRQ

0# / GPIO73 J

Vss Vss ACPRESEN

T / GPIO31 Vss Vss SMBCLK Vss Vss JTAG_TMS Vss SLP_S4# TP12 JTAG_TDO H

CLKIN_DOT

_96N SRTCRST# Vss Vss SLP_SUS# Vss SML0DATA SLP_A# SUS_STAT#

/ GPIO61 GPIO15 G

SLP_S3# Vss Vss_NCTF F

CLKIN_DOT

_96P DPWROK PWRBTN# Vss GPIO27 SML1CLK /

GPIO58 SMBALERT

# / GPIO11 BATLOW# /

GPIO72 GPIO24 PEG_B_CL

KRQ# /

GPIO56 Vss_NCTF E

Vss Vss RTCRST# Vss Vss OC6# /

GPIO10 Vss SLP_S5# /

GPIO63 Vss GPIO57 Vss Vss_NCTF D

USBP1N USBP0N Vss RSMRST# RTCX2 TP10 INTVRMEN OC3# /

GPIO42 OC7# /

GPIO14

SML1ALER

T# /

PCHHOT# /

GPIO74

SUSACK# GPIO8 SMBDATA SML0CLK PLTRST# LAN_PHY_P

WR_CTRL /

GPIO12 Vss_NCTF C

USBP1P Vss TP21 Vss OC2# /

GPIO41 Vss DRAMPWR

OK Vss WAKE# Vss Vss_NCTF B

USBP0P VccRTC RTCX1 DSWVRME

NOC5# /

GPIO9 OC0# /

GPIO59 SML0ALER

T# / GPIO60 RI# PCIECLKRQ

3# / GPIO25 Vss_NCTF Vss_NCTF Vss_NCTF A

25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

294 Datasheet

Ballout Definition

Table 6-2. Mobile PCH Ballout By Signal Name

Mobile PCH

Ball Name Ball #

A20GATE P4

ACPRESENT /

GPIO31 H20

APWROK L10

BATLOW# / GPIO72 E10

BMBUSY# / GPIO0 T7

CL_CLK1 M7

CL_DATA1 T11

CL_RST1# P10

CLKIN_DMI_N BF18

CLKIN_DMI_P BE18

CLKIN_DOT_96N G24

CLKIN_DOT_96P E24

CLKIN_GND1_N BJ30

CLKIN_GND1_P BG30

CLKIN_PCILOOPBAC

KH45

CLKIN_SATA_N AK7

CLKIN_SATA_P AK5

CLKOUT_DMI_N AV22

CLKOUT_DMI_P AU22

CLKOUT_DP_N AM12

CLKOUT_DP_P AM13

CLKOUT_ITPXDP_N AK14

CLKOUT_ITPXDP_P AK13

CLKOUT_PCI0 H49

CLKOUT_PCI1 H43

CLKOUT_PCI2 J48

CLKOUT_PCI3 K42

CLKOUT_PCI4 H40

CLKOUT_PCIE0N Y40

CLKOUT_PCIE0P Y39

CLKOUT_PCIE1N AB49

CLKOUT_PCIE1P AB47

CLKOUT_PCIE2N AA48

CLKOUT_PCIE2P AA47

CLKOUT_PCIE3N Y37

CLKOUT_PCIE3P Y36

CLKOUT_PCIE4N Y43

CLKOUT_PCIE4P Y45

CLKOUT_PCIE5N V45

CLKOUT_PCIE5P V46

CLKOUT_PCIE6N V40

CLKOUT_PCIE6P V42

CLKOUT_PCIE7N V38

CLKOUT_PCIE7P V37

CLKOUT_PEG_A_N AB37

CLKOUT_PEG_A_P AB38

CLKOUT_PEG_B_N AB42

CLKOUT_PEG_B_P AB40

CLKOUTFLEX0 /

GPIO64 K43

CLKOUTFLEX1 /

GPIO65 F47

CLKOUTFLEX2 /

GPIO66 H47

CLKOUTFLEX3 /

GPIO67 K49

CLKRUN# / GPIO32 N3

CRT_BLUE N48

CRT_DDC_CLK T39

CRT_DDC_DATA M40

CRT_GREEN P49

CRT_HSYNC M47

CRT_IRTN T42

CRT_RED T49

CRT_VSYNC M49

DAC_IREF T43

DcpRTC N16

DcpSST V16

DcpSus AL24

DcpSus T17

DcpSus V19

DcpSus AN23

DcpSusByp V12

DDPB_0N AV42

DDPB_0P AV40

DDPB_1N AV45

DDPB_1P AV46

DDPB_2N AU48

DDPB_2P AU47

DDPB_3N AV47

DDPB_3P AV49

DDPB_AUXN AT49

DDPB_AUXP AT47

DDPB_HPD AT40

DDPC_0N AY47

DDPC_0P AY49

DDPC_1N AY43

Mobile PCH

Ball Name Ball #

DDPC_1P AY45

DDPC_2N BA47

DDPC_2P BA48

DDPC_3N BB47

DDPC_3P BB49

DDPC_AUXN AP47

DDPC_AUXP AP49

DDPC_CTRLCLK P46

DDPC_CTRLDATA P42

DDPC_HPD AT38

DDPD_0N BB43

DDPD_0P BB45

DDPD_1N BF44

DDPD_1P BE44

DDPD_2N BF42

DDPD_2P BE42

DDPD_3N BJ42

DDPD_3P BG42

DDPD_AUXN AT45

DDPD_AUXP AT43

DDPD_CTRLCLK M43

DDPD_CTRLDATA M36

DDPD_HPD BH41

DMI_IRCOMP BG25

DMI_ZCOMP BJ24

DMI0RXN BC24

DMI0RXP BE24

DMI0TXN AW24

DMI0TXP AY24

DMI1RXN BE20

DMI1RXP BC20

DMI1TXN AW20

DMI1TXP AY20

DMI2RBIAS BH21

DMI2RXN BG18

DMI2RXP BJ18

DMI2TXN BB18

DMI2TXP AY18

DMI3RXN BG20

DMI3RXP BJ20

DMI3TXN AV18

DMI3TXP AU18

DPWROK E22

Mobile PCH

Ball Name Ball #

Datasheet 295

Ballout Definition

DRAMPWROK B13

DSWVRMEN A18

FDI_FSYNC0 AV12

FDI_FSYNC1 BC10

FDI_INT AW16

FDI_LSYNC0 AV14

FDI_LSYNC1 BB10

FDI_RXN0 BJ14

FDI_RXN1 AY14

FDI_RXN2 BE14

FDI_RXN3 BH13

FDI_RXN4 BC12

FDI_RXN5 BJ12

FDI_RXN6 BG10

FDI_RXN7 BG9

FDI_RXP0 BG14

FDI_RXP1 BB14

FDI_RXP2 BF14

FDI_RXP3 BG13

FDI_RXP4 BE12

FDI_RXP5 BG12

FDI_RXP6 BJ10

FDI_RXP7 BH9

FWH0 / LAD0 C38

FWH1 / LAD1 A38

FWH2 / LAD2 B37

FWH3 / LAD3 C37

FWH4 / LFRAME# D36

GNT1# / GPIO51 D47

GNT2# / GPIO53 E42

GNT3# / GPIO55 F46

GPIO1 A42

GPIO6 H36

GPIO7 E38

GPIO8 C10

GPIO15 G2

GPIO17 D40

GPIO24 E8

GPIO27 E16

GPIO28 P8

GPIO35 K4

GPIO57 D6

GPIO68 C40

GPIO69 B41

Mobile PCH

Ball Name Ball #

GPIO70 C41

GPIO71 A40

HDA_BCLK N34

HDA_DOCK_EN# /

GPIO33 C36

HDA_DOCK_RST# /

GPIO13 N32

HDA_RST# K34

HDA_SDIN0 E34

HDA_SDIN1 G34

HDA_SDIN2 C34

HDA_SDIN3 A34

HDA_SDO A36

HDA_SYNC L34

INIT3_3V# T14

INTRUDER# K22

INTVRMEN C17

JTAG_TCK J3

JTAG_TDI K5

JTAG_TDO H1

JTAG_TMS H7

L_BKLTCTL P45

L_BKLTEN J47

L_CTRL_CLK T45

L_CTRL_DATA P39

L_DDC_CLK T40

L_DDC_DATA K47

L_VDD_EN M45

LAN_PHY_PWR_CTR

L / GPIO12 C4

LDRQ0# E36

LDRQ1# / GPIO23 K36

LVD_IBG AF37

LVD_VBG AF36

LVD_VREFH AE48

LVD_VREFL AE47

LVDSA_CLK AK40

LVDSA_CLK# AK39

LVDSA_DATA#0 AN48

LVDSA_DATA#1 AM47

LVDSA_DATA#2 AK47

LVDSA_DATA#3 AJ48

LVDSA_DATA0 AN47

LVDSA_DATA1 AM49

LVDSA_DATA2 AK49

Mobile PCH

Ball Name Ball #

LVDSA_DATA3 AJ47

LVDSB_CLK AF39

LVDSB_CLK# AF40

LVDSB_DATA#0 AH45

LVDSB_DATA#1 AH47

LVDSB_DATA#2 AF49

LVDSB_DATA#3 AF45

LVDSB_DATA0 AH43

LVDSB_DATA1 AH49

LVDSB_DATA2 AF47

LVDSB_DATA3 AF43

TS_VSS1 AH8

TS_VSS2 AK11

TS_VSS3 AH10

TS_VSS4 AK10

NC_1 P37

Reserved AV5

Reserved AY7

Reserved AV7

Reserved AU3

Reserved BG4

DF_TVS AY1

Reserved AU2

Reserved AT4

Reserved BB5

Reserved BB3

Reserved BB7

Reserved BE8

Reserved BD4

Reserved BF6

Reserved AT3

Reserved AT1

Reserved AY3

Reserved AT5

Reserved AV3

Reserved AV1

Reserved BB1

Reserved BA3

Reserved AT10

Reserved BC8

Reserved AT8

Reserved AV10

Reserved AY5

Reserved BA2

Mobile PCH

Ball Name Ball #

296 Datasheet

Ballout Definition

Reserved AT12

Reserved BF3

OC0# / GPIO59 A14

OC1# / GPIO40 K20

OC2# / GPIO41 B17

OC3# / GPIO42 C16

OC4# / GPIO43 L16

OC5# / GPIO9 A16

OC6# / GPIO10 D14

OC7# / GPIO14 C14

PCIECLKRQ0# /

GPIO73 J2

PCIECLKRQ1# /

GPIO18 M1

PCIECLKRQ2# /

GPIO20 V10

PCIECLKRQ3# /

GPIO25 A8

PCIECLKRQ4# /

GPIO26 L12

PCIECLKRQ5# /

GPIO44 L14

PCIECLKRQ6# /

GPIO45 T13

PCIECLKRQ7# /

GPIO46 K12

PECI AU16

PEG_A_CLKRQ# /

GPIO47 M10

PEG_B_CLKRQ# /

GPIO56 E6

PERn1 BG34

PERn2 BE34

PERn3 BG36

PERn4 BF36

PERn5 BG37

PERn6 BJ38

PERn7 BG40

PERn8 BE38

PERp1 BJ34

PERp2 BF34

PERp3 BJ36

PERp4 BE36

PERp5 BH37

PERp6 BG38

PERp7 BJ40

PERp8 BC38

PETn1 AV32

Mobile PCH

Ball Name Ball #

PETn2 BB32

PETn3 AV34

PETn4 AY34

PETn5 AY36

PETn6 AU36

PETn7 AY40

PETn8 AW38

PETp1 AU32

PETp2 AY32

PETp3 AU34

PETp4 BB34

PETp5 BB36

PETp6 AV36

PETp7 BB40

PETp8 AY38

PIRQA# K40

PIRQB# K38

PIRQC# H38

PIRQD# G38

PIRQE# / GPIO2 G42

PIRQF# / GPIO3 G40

PIRQG# / GPIO4 C42

PIRQH# / GPIO5 D44

PLTRST# C6

PME# K10

PMSYNCH AP14

PROCPWRGD AY11

PWRBTN# E20

PWROK L22

RCIN# P5

REFCLK14IN K45

REQ1# / GPIO50 C46

REQ2# / GPIO52 C44

REQ3# / GPIO54 E40

RI# A10

RSMRST# C21

RTCRST# D20

RTCX1 A20

RTCX2 C20

SATA0GP / GPIO21 V14

SATA0RXN AM3

SATA0RXP AM1

SATA0TXN AP7

SATA0TXP AP5

Mobile PCH

Ball Name Ball #

SATA1GP / GPIO19 P1

SATA1RXN AM10

SATA1RXP AM8

SATA1TXN AP11

SATA1TXP AP10

SATA2GP / GPIO36 V8

SATA2RXN AD7

SATA2RXP AD5

SATA2TXN AH5

SATA2TXP AH4

SATA3COMPI AB13

SATA3GP / GPIO37 M5

SATA3RBIAS AH1

SATA3RCOMPO AB12

SATA3RXN AB8

SATA3RXP AB10

SATA3TXN AF3

SATA3TXP AF1

SATA4GP / GPIO16 U2

SATA4RXN Y7

SATA4RXP Y5

SATA4TXN AD3

SATA4TXP AD1

SATA5GP / GPIO49/

THERM_ALERT# V3

SATA5RXN Y3

SATA5RXP Y1

SATA5TXN AB3

SATA5TXP AB1

SATAICOMPI Y10

SATAICOMPO Y11

SATALED# P3

SCLOCK / GPIO22 T5

SDATAOUT0 /

GPIO39 M3

SDATAOUT1 /

GPIO48 V13

SDVO_CTRLCLK P38

SDVO_CTRLDATA M39

SDVO_INTN AP39

SDVO_INTP AP40

SDVO_STALLN AM42

SDVO_STALLP AM40

SDVO_TVCLKINN AP43

SDVO_TVCLKINP AP45

Mobile PCH

Ball Name Ball #

Datasheet 297

Ballout Definition

SERIRQ V5

SLOAD / GPIO38 N2

SLP_A# G10

SLP_LAN# / GPIO29 K14

SLP_S3# F4

SLP_S4# H4

SLP_S5# / GPIO63 D10

SLP_SUS# G16

SMBALERT# /

GPIO11 E12

SMBCLK H14

SMBDATA C9

SML0ALERT# /

GPIO60 A12

SML0CLK C8

SML0DATA G12

SML1ALERT# /

PCHHOT# / GPIO74 C13

SML1CLK / GPIO58 E14

SML1DATA / GPIO75 M16

SPI_CLK T3

SPI_CS0# Y14

SPI_CS1# T1

SPI_MISO U3

SPI_MOSI V4

SPKR T10

SRTCRST# G22

STP_PCI# / GPIO34 K1

SUS_STAT# /

GPIO61 G8

SUSACK# C12

SUSCLK / GPIO62 N14

SUSWARN#/

SUSPWRDNACK/

GPIO30

K16

SYS_PWROK P12

SYS_RESET# K3

THRMTRIP# AY10

TP1 BG26

TP2 BJ26

TP3 BH25

TP4 BJ16

TP5 BG16

TP6 AH38

TP7 AH37

TP8 AK43

Mobile PCH

Ball Name Ball #

TP9 AK45

TP10 C18

TP11 N30

TP12 H3

TP13 AH12

TP14 AM4

TP15 AM5

TP16 Y13

TP17 K24

TP18 L24

TP19 AB46

TP20 AB45

TP21 B21

TP22 M20

TP23 AY16

TP24 BG46

TP25 BE28

TP26 BC30

TP27 BE32

TP28 BJ32

TP29 BC28

TP30 BE30

TP31 BF32

TP32 BG32

TP33 AV26

TP34 BB26

TP35 AU28

TP36 AY30

TP37 AU26

TP38 AY26

TP39 AV28

TP40 AW30

USBP0N C24

USBP0P A24

USBP1N C25

USBP1P B25

USBP2N C26

USBP2P A26

USBP3N K28

USBP3P H28

USBP4N E28

USBP4P D28

USBP5N C28

USBP5P A28

Mobile PCH

Ball Name Ball #

USBP6N C29

USBP6P B29

USBP7N N28

USBP7P M28

USBP8N L30

USBP8P K30

USBP9N G30

USBP9P E30

USBP10N C30

USBP10P A30

USBP11N L32

USBP11P K32

USBP12N G32

USBP12P E32

USBP13N C32

USBP13P A32

USBRBIAS B33

USBRBIAS# C33

V_PROC_IO BJ8

V5REF P34

V5REF_Sus M26

Vcc3_3 AJ2

Vcc3_3 T34

Vcc3_3 AA16

Vcc3_3 W16

Vcc3_3 T38

Vcc3_3 BH29

Vcc3_3 V33

Vcc3_3 V34

VccAClk AD49

VccADAC U48

VccADPLLA BD47

VccADPLLB BF47

VccAFDIPLL BG6

VccALVDS AK36

VccAPLLDMI2 BH23

VccAPLLEXP BJ22

VccAPLLSATA AK1

VccASW T19

VccASW V21

VccASW T21

VccASW AA19

VccASW AA21

Mobile PCH

Ball Name Ball #

298 Datasheet

Ballout Definition

VccASW AA24

VccASW AA26

VccASW AA27

VccASW AA29

VccASW AA31

VccASW AC26

VccASW AC27

VccASW AC29

VccASW AC31

VccASW AD29

VccASW AD31

VccASW W21

VccASW W23

VccASW W24

VccASW W26

VccASW W29

VccASW W31

VccASW W33

VccClkDMI AB36

VccCore AA23

VccCore AC23

VccCore AD21

VccCore AD23

VccCore AF21

VccCore AF23

VccCore AG21

VccCore AG23

VccCore AG24

VccCore AG26

VccCore AG27

VccCore AG29

VccCore AJ23

VccCore AJ26

VccCore AJ27

VccCore AJ29

VccCore AJ31

VccDIFFCLKN AF33

VccDIFFCLKN AF34

VccDIFFCLKN AG34

VccDMI AU20

VccDMI AT20

VccDSW3_3 T16

VccIO N26

VccIO P26

Mobile PCH

Ball Name Ball #

VccIO P28

VccIO T27

VccIO T29

VccIO AF13

VccIO AC16

VccIO AC17

VccIO AD17

VccIO AF14

VccIO AP17

VccIO AN19

VccIO AL29

VccIO AF17

VccIO T26

VccIO AH13

VccIO AH14

VccIO AN16

VccIO AN17

VccIO AN21

VccIO AN26

VccIO AN27

VccIO AP21

VccIO AP23

VccIO AP24

VccIO AP26

VccIO AT24

VccIO AN33

VccIO AN34

VccDFTERM AG16

VccDFTERM AG17

VccDFTERM AJ16

VccDFTERM AJ17

VccRTC A22

VccSPI V1

VccSSC AG33

VccSus3_3 AN24

VccSus3_3 T23

VccSus3_3 T24

VccSus3_3 V23

VccSus3_3 V24

VccSus3_3 N20

VccSus3_3 N22

VccSus3_3 P20

VccSus3_3 P22

Mobile PCH

Ball Name Ball #

VccSus3_3 P24

VccSusHDA P32

VccTX_LVDS AM37

VccTX_LVDS AM38

VccTX_LVDS AP36

VccTX_LVDS AP37

VccVRM Y49

VccVRM AF11

VccVRM AP16

VccVRM AT16

Vss AJ3

Vss N24

Vss BG29

Vss H5

Vss AA17

Vss AA2

Vss AA3

Vss AA33

Vss AA34

Vss AB11

Vss AB14

Vss AB39

Vss AB4

Vss AB43

Vss AB5

Vss AB7

Vss AC19

Vss AC2

Vss AC21

Vss AC24

Vss AC33

Vss AC34

Vss AC48

Vss AD10

Vss AD11

Vss AD12

Vss AD13

Vss AD14

Vss AD16

Vss AD19

Vss AD24

Vss AD26

Vss AD27

Vss AD33

Mobile PCH

Ball Name Ball #

Datasheet 299

Ballout Definition

Vss AD34

Vss AD36

Vss AD37

Vss AD38

Vss AD39

Vss AD4

Vss AD40

Vss AD42

Vss AD43

Vss AD45

Vss AD46

Vss AD47

Vss AD8

Vss AE2

Vss AE3

Vss AF10

Vss AF12

Vss AF16

Vss AF19

Vss AF24

Vss AF26

Vss AF27

Vss AF29

Vss AF31

Vss AF38

Vss AF4

Vss AF42

Vss AF46

Vss AF5

Vss AF7

Vss AF8

Vss AG19

Vss AG2

Vss AG31

Vss AG48

Vss AH11

Vss AH3

Vss AH36

Vss AH39

Vss AH40

Vss AH42

Vss AH46

Vss AH7

Vss AJ19

Mobile PCH

Ball Name Ball #

Vss AJ21

Vss AJ24

Vss AJ33

Vss AJ34

Vss AK12

Vss AK3

Vss AK38

Vss AK4

Vss AK42

Vss AK46

Vss AK8

Vss AL16

Vss AL17

Vss AL19

Vss AL2

Vss AL21

Vss AL23

Vss AL26

Vss AL27

Vss AL31

Vss AL33

Vss AL34

Vss AL48

Vss AM11

Vss AM14

Vss AM36

Vss AM39

Vss AM43

Vss AM45

Vss AM46

Vss AM7

Vss AN2

Vss AN29

Vss AN3

Vss AN31

Vss AP12

Vss AP13

Vss AP19

Vss AP28

Vss AP30

Vss AP32

Vss AP38

Vss AP4

Vss AP42

Mobile PCH

Ball Name Ball #

Vss AP46

Vss AP8

Vss AR2

Vss AR48

Vss AT11

Vss AT13

Vss AT18

Vss AT22

Vss AT26

Vss AT28

Vss AT30

Vss AT32

Vss AT34

Vss AT39

Vss AT42

Vss AT46

Vss AT7

Vss AU24

Vss AU30

Vss AV11

Vss AV16

Vss AV20

Vss AV24

Vss AV30

Vss AV38

Vss AV4

Vss AV43

Vss AV8

Vss AW14

Vss AW18

Vss AW2

Vss AW22

Vss AW26

Vss AW28

Vss AW32

Vss AW34

Vss AW36

Vss AW40

Vss AW48

Vss AY12

Vss AY22

Vss AY28

Vss AY4

Vss AY42

Mobile PCH

Ball Name Ball #

300 Datasheet

Ballout Definition

Vss AY46

Vss AY8

Vss B11

Vss B15

Vss B19

Vss B23

Vss B27

Vss B31

Vss B35

Vss B39

Vss B43

Vss B7

Vss BB12

Vss BB16

Vss BB20

Vss BB22

Vss BB24

Vss BB28

Vss BB30

Vss BB38

Vss BB4

Vss BB46

Vss BC14

Vss BC18

Vss BC2

Vss BC22

Vss BC26

Vss BC32

Vss BC34

Vss BC36

Vss BC40

Vss BC42

Vss BC48

Vss BD3

Vss BD46

Vss BD5

Vss BE10

Vss BE22

Vss BE26

Vss BE40

Vss BF10

Vss BF12

Vss BF16

Vss BF20

Mobile PCH

Ball Name Ball #

Vss BF22

Vss BF24

Vss BF26

Vss BF28

Vss BF30

Vss BF38

Vss BF40

Vss BF8

Vss BG17

Vss BG21

Vss BG22

Vss BG24

Vss BG33

Vss BG41

Vss BG44

Vss BG8

Vss BH11

Vss BH15

Vss BH17

Vss BH19

Vss BH27

Vss BH31

Vss BH33

Vss BH35

Vss BH39

Vss BH43

Vss BH7

Vss C22

Vss D12

Vss D16

Vss D18

Vss D22

Vss D24

Vss D26

Vss D3

Vss D30

Vss D32

Vss D34

Vss D38

Vss D42

Vss D8

Vss E18

Vss E26

Vss F3

Mobile PCH

Ball Name Ball #

Vss F45

Vss G14

Vss G18

Vss G20

Vss G26

Vss G28

Vss G36

Vss G48

Vss H10

Vss H12

Vss H16

Vss H18

Vss H22

Vss H24

Vss H26

Vss H30

Vss H32

Vss H34

Vss H46

Vss K18

Vss K26

Vss K39

Vss K46

Vss K7

Vss L18

Vss L2

Vss L20

Vss L26

Vss L28

Vss L36

Vss L48

Vss M12

Vss M14

Vss M18

Vss M22

Vss M24

Vss M30

Vss M32

Vss M34

Vss M38

Vss M4

Vss M42

Vss M46

Vss M8

Mobile PCH

Ball Name Ball #

Datasheet 301

Ballout Definition

Vss N18

Vss N47

Vss P11

Vss P16

Vss P18

Vss P30

Vss P40

Vss P43

Vss P47

Vss P7

Vss R2

Vss R48

Vss T12

Vss T31

Vss T33

Vss T36

Vss T37

Vss T4

Vss T46

Vss T47

Vss T8

Vss V11

Vss V26

Vss V27

Vss V29

Vss V31

Vss V36

Vss V39

Vss V43

Vss V7

Vss W17

Vss W19

Vss W2

Vss W27

Vss W34

Vss W48

Vss Y12

Vss Y38

Vss Y4

Vss Y42

Vss Y46

Vss Y8

Vss V17

Vss AP3

Mobile PCH

Ball Name Ball #

Vss AP1

Vss BE16

Vss BC16

Vss BG28

Vss BJ28

Vss_NCTF A4

Vss_NCTF A44

Vss_NCTF A45

Vss_NCTF A46

Vss_NCTF A5

Vss_NCTF A6

Vss_NCTF B3

Vss_NCTF B47

Vss_NCTF BD1

Vss_NCTF BD49

Vss_NCTF BE1

Vss_NCTF BE49

Vss_NCTF BF1

Vss_NCTF BF49

Vss_NCTF BG2

Vss_NCTF BG48

Vss_NCTF BH3

Vss_NCTF BH47

Vss_NCTF BJ4

Vss_NCTF BJ44

Vss_NCTF BJ45

Vss_NCTF BJ46

Vss_NCTF BJ5

Vss_NCTF BJ6

Vss_NCTF C2

Vss_NCTF C48

Vss_NCTF D1

Vss_NCTF D49

Vss_NCTF E1

Vss_NCTF E49

Vss_NCTF F1

Vss_NCTF F49

VssADAC U47

VssALVDS AK37

WAKE# B9

XCLK_RCOMP Y47

XTAL25_IN V47

XTAL25_OUT V49

Mobile PCH

Ball Name Ball #

Ballout Definition

302 Datasheet

6.3 Mobile SFF PCH Ballout

Figure 6-9, Figure 6-10, Figure 6-11 and Figure 6-12 show the ballout from a top of the

package quadrant view.

Figure 6-9. Mobile SFF PCH Package (Top View – Upper Left)

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

BL Vss_

NCT

Vss_

NCT

Vss_

NCT

DDPD

_2P DDPD

_3N PERp8 PERp7 PERp5 PERp4 PERp2 PERp1 TP31 TP32 TP30

BK Vss DDPD

_HPD Vss PERp6 Vss PERp3 Vss Vss Vss Vcc3

_3 Vss

BJ Vss_

NCT

Vss_

NCT

FTP21

DDPD

_2N DDPD

_3P PERn8 PERn7 PERn5 PERn4 PERn2 PERn1 TP27 TP28 TP26

Vss_

NCT

FTP41 Vss Vss Vss Vss PERn6 Vss PERn3 Vss Vss Vss Vss Vss

BG DDPD

_0N DDPD

_0P

BF Vss Vss DDPC

_2N DDPC

_2P DDPD

_1N VccAD

PLLA PETp6 PETp4 PETn3 TP36 TP35 TP33

BE DDPC

_3P DDPC

_3N DDPC

_HPD Vss Vss Vss Vss Vss Vss Vss Vss Vss

BD DDPC

_1P DDPC

_1N DDPD

_1P VccAD

PLLB PETn6 PETn4 PETp3 TP40 TP39 TP37

BC DDPC

_0P DDPC

_0N Vss Vss Vss Vss Vss Vss Vss Vss Vss

BB Vss Vss DDPB

_2P DDPB

_2N TP42 PETp8 PETp7 PETp5 PETn2 PETn1 TP34 CLKIN

_GND1

BA DDPB

_3P DDPB

_3N Vss Vss Vss Vss Vss Vss Vss Vss Vss

AY DDPB

_0P DDPB

_0N DDPB

_1P DDPB

_1N DDPB

_HPD PETn8 PETn7 PETn5 PETp2 PETp1 TP38 CLKIN

_GND1

AW DDPB

_AUXN DDPB

_AUXP Vss Vss Vss Vss Vss VccI

VccA

PLLD

MI2 Vss Vss

AV Vss Vss

AU DDPC

_AUXN DDPC

_AUXP DDPD

_AUXN DDPD

_AUXP

SDVO_

TVCLK

INP

SDVO_

TVCLK

INN Vss VccI

ODcpSu

sDcpS

us VccIO VccIO

AT SDVO_

INTN SDVO_

INTP Vss Vss Vss Vss

SDVO_

STALL

SDVO_

STALL

LVDSA

_DATA

LVDSA

_DATA

0TP9 TP8 Vss Vss DcpSu

sVss VccIO VccIO

AP Vss Vss Vss Vss Vss VccClk

DMI Vss Vss Vss Vss Vss VccIO

AN LVDSA

_DATA

LVDSA

_DATA

LVDSA

_DATA

LVDSA

_DATA

#2 TP6 TP7

LVDSB

_DATA

LVDSB

_DATA

0Vss VccC

ore VccC

ore Vss Vss VccS

us3_

LVDSB

_DATA

LVDSB

_DATA

#1 Vss Vss Vss Vss

AK Vss Vss LVDSA

_CLK LVDSA

_CLK#

LVDSA

_DATA

LVDSA

_DATA

#3 Vss Vss VccC

ore VccC

ore Vss

LVDSB

_DATA

LVDSB

_DATA

2Vss Vss Vss Vss VccTX

_LVDS Vss Vss VccC

ore VccC

ore

LVDSB

_DATA

LVDSB

_DATA

LVDSB

_CLK# LVDSB

_CLK LVD_I

BG LVD_V

AG LVD_V

REFH LVD_V

REFL Vss Vss Vss VccTX

_LVDS VccTX

_LVDS Vss VccAL

VDS Vss Vss VccC

ore

AF Vss Vss CLKO

UT_PE

G_A_P

CLKO

UT_PE

G_A_N

CLKO

UT_PE

G_B_P

CLKO

UT_PE

G_B_N

VccTX

_LVDS Vss VccAL

VDS Vss Vss Vss

Datasheet 303

Ballout Definition

Figure 6-10. Mobile SFF PCH Package (Top View – Lower Left)

Ball

CLKO

UT_PC

IE1P

CLKO

UT_PC

IE1N Vss Vss Vss VccD

IFFC

LKN

VccD

IFFC

LKN Vss VssALV

DS Vcc AS

WVccAS

CLKO

UT_PC

IE0P

CLKO

UT_PC

IE0N TP20 TP19 CLKO

UT_PC

IE2P

CLKO

UT_PC

IE2N

AC VccAC

XCLK_

RCOM

PVss Vss Vss VccVR

VccD

IFFC

LKN

VccSS

CVssALV

DS Vcc AS

WVccAS

AB Vss Vss CLKO

UT_PC

IE6P

CLKO

UT_PC

IE6N

CLKO

UT_PC

IE5P

CLKO

UT_PC

IE5N Vss Vss Vss VccAS

WVccAS

CLKO

UT_PC

IE3P

CLKO

UT_PC

IE3N Vss Vss Vss Vss

CLKO

UT_PC

IE4P

CLKO

UT_PC

IE4N Vss Vss Vss VccAS

WVccAS

WXTAL2

5_OUT XTAL2

5_IN

CLKO

UT_PC

IE7P

CLKO

UT_PC

IE7N

SDVO_

CTRLC

LK TP23

VVSSA_

DAC Vss Vss Vss Vss Vcc3_

3Vcc 3_

3Vss Vss VccSu

sHDA Vss Vss

UVccAD

AC Vss CRT_R

DDPC

_CTRL

DATA

DDPD

_CTRL

DATA NC_1 Vcc3_

3VccSu

s3_3 Vc cSu

s3_3 Vss VCCP

USB VCCP

USB

DDPC

_CTRL

CLK

CRT_I

RTN Vss Vss Vss Vcc3_

RDAC_I

REF

CRT_D

DC_CL

CRT_G

REEN

SDVO_

CTRLD

ATA

L_CTR

L_CLK Vcc3_

3Vss VccSu

s3_3 Vc cSu

s3_3 Vss VccSu

s3_3 Vc cSu

s3_3

PVss Vss

NCRT_V

SYNC

CRT_D

DC_D

ATA Vss Vss Vss Vss V5REF Vss Vss Vss VccSu

s3_3

MCRT_H

SYNC

DDPD

_CTRL

CLK

CRT_B

LUE L_BKL

TEN L_VDD

_EN

L_CTR

L_DAT

V5REF

_Sus

HDA_

DOCK

_RST#

USBP1

3N TP11 USBP

8N USBP

LL_DDC

_CLK L_BKL

TCTL Vss Vss Vss Vss Vss Vss Vss Vss Vss

KVss Vss L_DDC

_DATA

REQ2#

GPIO5

TACH4

GPIO6

FWH4 /

LFRA

ME#

HDA_

SDO

HDA_

DOCK

_E N# /

USBP1

3P TP24

USBP

8P USBP

CLKO

UTFLE

X3 /

REFCL

K14IN Vss CLKO

UT_PC

I3 Vss Vss Vss Vss Vss Vss Vss

CLKO

UTFLE

X0 /

CLKO

UT_PC

GNT2#

GPIO5

LDRQ0

#HDA_

SYNC HDA_

BCLK USBP1

1N USBP1

2N USBP

3N USBP

CLKO

UT_PC

CLKO

UTFLE

X2 /

RE Q1#

GPIO5

CLKO

UT_PC

I4 Vss Vss Vss Vss Vss Vss Vss Vss

FVss Vss REQ3#

GPIO5

PIRQG

# /

GPIO4

GNT1#

GPIO5

PIRQH

# /

GPIO5

LDRQ1

# /

GPIO2

HDA_

RST# USBP1

1P USBP1

2P USBP

3P USBP

CLKIN

_PCIL

OOPB

CLKO

UT_PC

Vss_

NCT

PIRQA

CLKO

UTFLE

X1 / Vss GNT3#

GPIO5 Vss TACH6

GPIO7 Vss HDA_

SDIN0 Vss USBP

7N Vss USBP

5N Vss

CVss_

NCT

Vss_

NCT

PIRQB

#PIRQC

#PIRQD

TACH2

GPIO6

PIRQF

# /

GPIO3

FWH2 /

LAD2 FWH3 /

LAD3 HDA_

SDIN2 USBR

BIAS# USBP1

0N USBP

9N USBP

BVss TACH0

GPIO1 Vss TACH1

GPIO1 Vss HDA_

SDIN1 Vss USBP

7P Vss USBP

5P Vss

Vss_

NCT

Vss_

NCT

Vss_

NCT

PIRQE

# /

GPIO2

TACH3

GPIO7

TACH5

GPIO6

TACH7

GPIO7

FWH1 /

LAD1 FWH0 /

LAD0 HDA_

SDIN3 USBR

BIAS USBP1

0P USBP

9P USBP

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

Ballout Definition

304 Datasheet

Figure 6-11. Mobile SFF PCH Package (Top View – Upper Right)

25242322212019181716151413121110987654321

TP29 DMI1R

XN DMI0R

XN DMI2R

XP DMI3R

XN FDI_R

XP1 FDI_R

XN0 FDI_R

XP3 FDI_R

XP6 TP22 RSVD Vss_

NCT

Vss_

NCT

Vss_

NCT

FBL

TP2 Vss DMI2R

BIAS Vss TP4 Vss FDI_L

SYNC0 Vss FDI_F

SYNC1 RSVD BK

TP25 DMI1R

XP DMI0R

XP DMI2R

XN DMI3R

XP FDI_R

XN1 FDI_R

XP0 FDI_R

XN3 FDI_R

XN6 RSVD RSVD RSVD Vss_

NCT

Vss_

NCT

FBJ

TP1 Vss TP3 Vss TP5 Vss FDI_F

SYNC0 Vss FDI_L

SYNC1 Vss RSVD RSVD Vss_

NCT

FBH

RSVD RSVD BG

Vss DMI0T

XP DMI_Z

COMP

CLKIN

_DMI_

PVss FDI_R

XP2 FDI_R

XN7 RSVD RSVD Vss Vss BF

Vss Vss Vss Vss Vss Vss Vss Vss Vss RSVD RSVD RSVD BE

Vss DMI0T

DMI_I

RCOM

CLKIN

_DMI_

NVss FDI_R

XN2 FDI_R

XP7 RSVD RSVD BD

Vss Vss Vss Vss Vss Vss Vss THRM

TRIP# DF_TV

SRSVD RSVD BC

CLKO

UT_D

MI_N

DMI1T

XN DMI2T

XN DMI3T

XN FDI_R

XP4 FDI_R

XP5 FDI_IN

TPMSY

NCH RSVD Vss Vss BB

Vss Vss Vss Vss Vss Vss Vss Vss Vss RSVD RSVD BA

CLKO

UT_D

MI_P

DMI1T

XP DMI2T

XP DMI3T

XP FDI_R

XN4 FDI_R

XN5 Vss RSVD RSVD RSVD RSVD AY

Vss Vss VccVR

MVccVR

MVccDM

IVss Vss Vss Vss RSVD RSVD AW

Vss Vss AV

VccIO VccIO VCCA

DMI_V

VCCAF

DI_VR

MVss VccDM

IPECI PROC

PWRG

DRSVD RSVD SATA0

TXN SATA0

TXP AU

VccI

OVss Vss Vss TP14 TP15 AT

VccIO VccIO Vss Vss Vss VccI

CLKO

UT_IT

PXDP_

CLKO

UT_IT

PXDP_ Vss Vss SATA1

TXN SATA1

TXP AR

Vss Vss Vss VccAP

LLEXP Vss VccAF

DIPLL VccAF

DIPLL Vss Vss Vss Vss Vss AP

CLKO

UT_DP

CLKO

UT_DP

SATA1

RXP SATA1

RXN SATA0

RXP AN

Vss VccDM

IVccIO Vss V_PRO

C_IO Vss TP13 VCCA

PLL_S

ATA3 AM

VccDF

TERM Vss Vss Vss SATA2

TXN SATA2

TXP AL

Vss Vss VccIO Vss Vss VccDF

TERM TS_VS

S3 TS_VS

CLKIN

_SATA

CLKIN

_SATA

_P Vss Vss AK

VccC

ore VccC

ore Vss VccI

OVcc DF

TERM VccDF

TERM Vss Vss Vss SATA5

TXN SATA5

TXP AJ

TS_VS

S2 TS_VS

S4 SATA4

TXN SATA4

TXP SATA3

RBIAS Vss AH

VccC

ore VccC

ore Vss Vss VccI

OVccI

OVss Vss Vss SATA3

TXN SATA3

TXP AG

Vss VccC

ore VccC

ore Vss VccV

RM VccIO SATA3

COMPI

SATA3

RCOM

PO Vss Vcc3

_3 Vss Vss AF

Datasheet 305

Ballout Definition

§ §

Figure 6-12. Mobile SFF PCH Package (Top View – Lower Right)

Vss VccC

ore VccC

ore VccV

RM Vss Vss Vss Vss Vss Vss SATA4

RXN SATA4

RXP AE

SPI_C

LK TP16 SATA3

RXN SATA3

RXP SATA2

RXN SATA2

RXP AD

Vss VccC

ore VccC

ore Vcc3_

3Vss VccI

OVccI

OVss Vss Vss SATA5

RXN SATA5

RXP AC

Vss VccC

ore VccC

ore Vcc3_

3Vss VccI

OSATAI

COMPI

SATAI

COMP

SPI_C

S0# SPI_C

S1# Vss Vss AB

VccIO Vss Vss Vss SATA4

GP /

GPIO1

SATA5

GP /

GPIO4 AA

VccAS

WVccAS

WVccSP

IVss Vss SERIR

QSPI_M

ISO Y

GPIO3

5SATAL

ED# SPI_M

OSI

SATA2

GP /

GPIO3

SCLO

CK /

GPIO2

BMBU

SY # /

GPIO0 W

VccAS

WVccAS

WVss Vss DcpSu

sVss Vss Vss Vss Vss V

VccIO VccIO VccAS

WVccAS

WDcpSS

TDcpRT

CJTAG_

TDI

SDAT

OUT0

PCIEC

LKRQ1

# / RCIN# A20GA

SDAT

AOUT1

/ U

Vss Vss Vss Vss PCIEC

LKRQ2

# /

CLKR

UN# /

GPIO3 T

VccIO VccIO Vss VccAS

WVss DcpRT

CVccDS

W3_3 DcpSu

sByp

PEG_A

_CLKR

Q# /

INIT3_

3V#

STP_P

CI# /

GPIO3

SATA1

GP /

GPIO1 R

Vss Vss P

Vss Vss Vss Vc c IO Vc c RT

CVss Vss Vss Vss SLOA

D /

GPIO3 SPKR N

CLKIN

_DOT_

96N

PWRO

PCIEC

LKRQ4

# /

JTAG_

TCK JTAG_

TMS JTAG_

TDO SYS_P

WROK CL_RS

T1#

SATA3

GP /

GPIO3

PCIEC

LKRQ0

# /

SATA0

GP /

GPIO2 M

Vss Vss Vss Vss Vss Vss Vss Vss Vss CL_CL

K1 SYS_R

ESET# L

CLKIN

_DOT_

96P

INTRU

DER# PWRB

TN# GPIO5

GPIO2

4 /

MEM_

SML0

CLK SLP_S

PCIEC

LKRQ5

# /

GPIO1

5Vss Vss K

Vss Vss Vss Vss Vss Vss Vss Vss Vss PCIEC

LKRQ6

# /

CL_DA

TA1 J

USBP

SML0

ALERT

# /

ACPR

ESENT

/ GPIO8 OC7# /

GPIO1

SMBA

LERT#

BATLO

W# /

GPIO7

PCIEC

LKRQ7

# / PME# H

Vss Vss Vss Vss Vss VSS Vss Vss Vss SUS_

STAT#

APWR

OK GPIO2

USBP

0N DSWV

RMEN RTCR

ST# SMBC

LK SUSA

CK# RI# SMBD

ATA PLTRS

TB#

SLP_S

5# /

GPIO6 Vss Vss F

TP12 Vss_

NCT

TP18 Vss TP10 Vss

OC3# /

GPIO4

2Vss SML1C

LK /

GPIO5 Vss WAKE

#Vss SLP_S

SUSC

LK /

GPIO6

Vss_

NCT

USBP1

OC6# /

GPIO1

INTVR

MEN RTCX2 OC0# /

GPIO5

GPIO2

SUSW

ARN#/

SUSP

SML1D

AT A /

GPIO7

SML1A

LE RT #

SLP_A

LAN_P

HY_P

WR_C

PEG_B

_CLKR

Q# /

Vss_

NCT

TP17 Vss RSMR

ST# Vss

OC5# /

GPIO9 Vss DRAM

PWRO

KVss PCIEC

LKRQ3

# / Vss B

USBP1

PSRTC

RST# DPWR

OK RTCX1 OC1# /

GPIO4

SLP_S

US#

OC2# /

GPIO4

OC4# /

GPIO4

SML0

DATA

SLP_L

AN# /

GPIO2

Vss_

NCT

Vss_

NCT

25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Ballout Definition

306 Datasheet

Datasheet 307

Package Information

7 Package Information

7.1 Desktop PCH package

• FCBGA package

• Package size: 27 mm x 27 mm

• Ball Count: 942

• Ball pitch: 0.7 mm

The Desktop PCH package information is shown in Figure 7-1.

Note: All dimensions, unless otherwise specified, are in millimeters.

Package Information

308 Datasheet

Figure 7-1. Desktop PCH Package Drawing

Datasheet 309

Package Information

7.2 Mobile PCH Package

• FCBGA package

• Package size: 25 mm x 25 mm

• Ball Count: 989

• Ball pitch: 0.6 mm

The Mobile PCH package information is shown in Figure 7-2

Note: All dimensions, unless otherwise specified, are in millimeters.

Package Information

310 Datasheet

Figure 7-2. Mobile PCH Package Drawing

Datasheet 311

Package Information

7.3 Mobile SFF PCH Package

• FCBGA package

• Package size: 22 mm x 22 mm

• Ball Count: 1017

• Ball pitch: 0.59 mm

The Mobile SFF PCH package information is shown in Figure 7-3

Note: All dimensions, unless otherwise specified, are in millimeters.

Package Information

312 Datasheet

§ §

Figure 7-3. Mobile SFF PCH Package Drawing

Datasheet 313

Electrical Characteristics

8 Electrical Characteristics

This chapter contains the DC and AC characteristics for the PCH. AC timing diagrams

are included.

8.1 Thermal Specifications

8.1.1 Desktop Storage Specifications and Thermal Design Power

(TDP)

For desktop thermal information, refer to the Intel® 6 Series Chipset and UP Server /

Workstation Platform Controller Hub (PCH) – Thermal and Mechanical Specifications

Design Guide

8.1.2 Mobile Storage Specifications and Thermal Design Power

(TDP)

NOTES:

1. Refers to a component device that is not assembled in a board or socket and is not

electrically connected to a voltage reference or I/O signal.

2. Specified temperatures are not to exceed values based on data collected. Exceptions for

surface mount reflow are specified by the applicable JEDEC standard. Non-adherence may

affect PCH reliability.

3. TABSOLUTE STORAGE applies to the unassembled component only and does not apply to the

shipping media, moisture barrier bags, or desiccant.

4. Intel branded products are specified and certified to meet the following temperature and

humidity limits that are given as an example only (Non-Operating Temperature Limit:

-40 °C to 70 °C and Humidity: 50% to 90%, non-condensing with a maximum wet bulb of

28 °C.) Post board attach storage temperature limits are not specified for non-Intel

branded boards.

5. The JEDEC J-JSTD-020 moisture level rating and associated handling practices apply to all

moisture sensitive devices removed from the moisture barrier bag.

Table 8-1. Storage Conditions and Thermal Junction Operating Temperature Limits

Parameter Description Min Max Notes

TABSOLUTE STORAGE

The non-operating device storage

temperature. Damage (latent or

otherwise) may occur when exceeded for

any length of time.

-25 °C 125 °C 1,2,3

TSUSTAINED STORAGE

The ambient storage temperature (in

shipping media) for a sustained period of

time.

-5 °C 40 °C 4,5

RHSUSTAINED STORAGE

The maximum device storage relative

humidity for a sustained period of time. 60% @ 24 ° C 5,6

TIME SUSTAINED STORAGE

A prolonged or extended period of time;

typically associated with customer shelf

life.

Months

Months 6

Tj (Mobile Only) Mobile Thermal Junction Operating

Temp era tu re li mi ts 0 °C 108 °C 7

Electrical Characteristics

314 Datasheet

6. Nominal temperature and humidity conditions and durations are given and tested within

the constraints imposed by TSUSTAINED storage and customer shelf life in applicable Intel

boxes and bags.

7. The thermal solution needs to ensure that the temperature does not exceed the maximum

junction temperature (Tj,max) limit.

8.2 Absolute Maximum Ratings

Table 8 - 3 specifies absolute maximum and minimum ratings. At conditions outside

functional operation condition limits, but within absolute maximum and minimum

ratings, neither functionality nor long-term reliability can be expected. If a device is

returned to conditions within functional operation limits after having been subjected to

conditions outside these limits (but within the absolute maximum and minimum

ratings) the device may be functional, but with its lifetime degraded depending on

exposure to conditions exceeding the functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality

nor long-term reliability can be expected. Moreover, if a device is subjected to these

conditions for any length of time, it will either not function or its reliability will be

severely degraded when returned to conditions within the functional operating

condition limits.

Although the PCH contains protective circuitry to resist damage from Electrostatic

Discharge (ESD), precautions should always be taken to avoid high static voltages or

electric fields.

Table 8-2. Mobile Thermal Design Power

SKU Thermal Design Power (TDP) Notes

Standard 3.9 W

SFF 3.4 W

Low Power

(Intel® UM67

Chipset)

3.4 W

Table 8-3. PCH Absolute Maximum Ratings

Parameter Maximum Limits

Voltage on any 5 V Tolerant Pin with respect to Ground (V5REF = 5 V) -0.5 to V5REF + 0.5 V

Voltage on any 3.3 V Pin with respect to Ground -0.5 to Vcc3_3 + 0.4 V

Voltage on any 1.8 V Tolerant Pin with respect to Ground -0.5 to VccVRM + 0.5 V

Voltage on any 1.5 V Pin with respect to Ground -0.5 to VccVRM + 0.5 V

Voltage on any 1.05 V Tolerant Pin with respect to Ground -0.5 to VccCore + 0.5 V

1.05 V Supply Voltage with respect to VSS -0.5 to 1.3 V

1.8 V Supply Voltage with respect to VSS -0.5 to 1.98 V

3.3 V Supply Voltage with respect to VSS -0.5 to 3.7 V

5.0 V Supply Voltage with respect to VSS -0.5 to 5.5 V

V_PROC_IO Supply Voltage with respect to VSS -0.5 to 1.3 V

1.5 V Supply Voltage for the analog PLL with respect to VSS -0.5 to 1.65 V

1.8 V Supply Voltage for the analog PLL with respect to VSS -0.5 to 1.98 V

Datasheet 315

Electrical Characteristics

8.3 PCH Power Supply Range

8.4 General DC Characteristics

NOTES:

1. G3 state shown to provide an estimate of battery life.

Table 8-4. PCH Power Supply Range

Power Supply Minimum Nominal Maximum

1.0 V 0.95 V 1.00 V 1.05 V

1.05 V 1.00 V 1.05 V 1.10 V

1.5 V 1.43 V 1.50 V 1.58 V

1.8 V 1.71 V 1.80 V 1.89 V

3.3 V 3.14 V 3.30 V 3.47 V

5 V 4.75 V 5.00 V 5.25 V

Table 8-5. Measured ICC (Desktop Only)

Voltage Rail Voltage

(V)

S0 Iccmax

Current

Integrated

Graphics5

(A)

S0 Iccmax

Current

External

Graphics5

(A)

S0 Idle

Current

Integrated

Graphics4,5

(A)

S0 Idle

Current

External

Graphics5

(A)

Iccmax

Current5

(A)

Sx Idle

Current

(A)

V_PROC_IO 1.05 /

1.0 0.001 0.001 0.001 0.001 0 0 —

V5REF 5 0.001 0.001 0.001 0.001 0 0 —

V5REF_Sus 5 0.001 0.001 0.001 0.001 0.001 0.001 —

Vcc3_3 3.3 0.267 0.267 0.047 0.047 0 0 —

VccADAC33.3 0.068 0.001 0.001 0.001 0 0 —

VccADPLLA 1.05 0.08 0.02 0.065 0.005 0 0 —

VccADPLLB 1.05 0.08 0.02 0.01 0.01 0 0 —

VccCore 1.05 2.1 1.94 0.6 0.42 0 0 —

VccDMI 1.05 0.057 0.057 0.002 0.002 0 0 —

VccIO31.05 4.35 3.69 0.86 0.53 0 0 —

VccASW 1.05 1.31 1.31 0.353 0.353 0.703 0.350 —

VccSPI 3.3 0.02 0.02 0.001 0.001 0.015 0.001 —

VccDSW3_3 3.3 0.002 0.002 0.001 0.001 0.002 0.001 —

VccDFTERM 1.8 0.002 0.002 0.001 0.001 0 0 —

VccRTC 3.3 N/A N/A N/A N/A N/A N/A

6 µA

See notes

1, 2

VccSus3_3 3.3 0.097 0.097 0.009 0.009 0.142 0.033 —

VccSusHDA 3.3 0.01 0.01 0.001 0.001 0.001 0.001 —

VccVRM 1.8 0.175 0.135 0.129 0.089 0 0 —

VccClkDMI 1.05 0.08 0.08 0.08 0.08 0 0 —

VccSSC 1.05 0.105 0.105 0.03 0.03 0 0 —

VccDIFFCLKN 1.05 0.055 0.055 0.05 0.05 0 0 —

Electrical Characteristics

316 Datasheet

2. Icc (RTC) data is taken with VccRTC at 3.0 V while the system in a mechanical off (G3) state at room

temperature.

3. Numbers based on a worst-case of 3 displays - 2 DisplayPort and 1 CRT, even though only 2 display pipes

are enabled at any one time. If no CRT is used, VccADAC contribution can be ignored.

4. S0 Idle is based on 1 DisplayPort Panel used on Display Pipe A.

5. S0 Iccmax Measurements taken at 110 °C and S0 Idle/Sx Iccmax measurements taken at 50 °C.

Table 8-6. Measured ICC (Mobile Only) (Sheet 1 of 2)

Voltage Rail Voltage

(V)

S0 Iccmax

Current

Integrated

Graphics5

(A)

S0 Iccmax

Current

External

Graphics5

(A)

S0 Idle

Current

Integrated

Graphics4,5

(A)

S0 Idle

Current

External

Graphics5

(A)

Iccmax

Current5

(A)

Sx Idle

Current

(A)

V_PROC_IO 1.05 /

1.0 0.001 0.001 0.001 0.001 0 0 —

V5REF 5 0.001 0.001 0.001 0.001 0 0 —

V5REF_Sus 5 0.001 0.001 0.001 0.001 0.001 0.001 —

Vcc3_3 3.3 0.228 0.228 0.035 0.035 0 0 —

VccADAC3 3.3 0.001 0.001 0.001 0.001 0 0 —

VccADPLLA 1.05 0.075 0.01 0.07 0.005 0 0 —

VccADPLLB 1.05 0.075 0.01 0.01 0.005 0 0 —

VccCore

(Internal

Suspend VR

mode using

INTVRMEN)

1.05 1.3 1.14 0.36 0.28 0 0 —

VccCore

(External

Suspend VR

mode using

INTVRMEN)

1.05 1.2 1.04 0.31 0.23 0 0 —

VccDMI 1.05 /

1.0 0.042 0.042 0.001 0.001 0 0 —

VccIO3 1.05 3.709 3.187 0.458 0.319 0 0 —

VccASW 1.05 0.903 0.903 0.203 0.203 0.603 0.23 —

VccSPI 3.3 0.01 0.01 0.001 0.001 0.01 0.01

VccDSW3_3 3.3 0.001 0.001 0.001 0.001 0.003 0.001 —

VccDFTERM 1.8 0.002 0.002 0.001 0.001 0 0 —

VccRTC 3.3 N/A N/A N/A N/A N/A N/A

6 uA

See notes

1, 2

VccSus3_3

(Internal

Suspend VR

mode using

INTVRMEN)

3.3 0.065 0.065 0.009 0.009 0.119 0.031 —

Datasheet 317

Electrical Characteristics

NOTES:

1. G3 state shown to provide an estimate of battery life

2. Icc (RTC) data is taken with VccRTC at 3.0 V while the system in a mechanical off (G3) state at room

temperature.

3. Numbers based on 2 Display configuration - 1 external DisplayPort and 1 LVDS display. If VGA is used,

VccADAC S0 Iccmax in Integrated Graphics contribution is 63 mA.

4. S0 Idle is based on 1 LVDS display used on Display Pipe A.

5. S0 Iccmax Measurements taken at 110°C and S0 Idle/Sx Iccmax measurements taken at 50°C.

6. This applies to External Suspend VR powered mode for DcpSus. In Internal Suspend VR mode, DcpSus is a

No Connect and hence Iccmax is not applicable.

7. Sx Idle current measurement is based on Sx/M3 and assumes VccASW is powered

VccSus3_3

(External

Suspend VR

mode using

INTVRMEN)

3.3 0.065 0.065 0.005 0.005 0.059 0.014 —

VccSusHDA 3.3 0.01 0.01 0.001 0.001 0.001 0.001 —

VccVRM 1.5 0.167 0.127 0.124 0.075 0 0 —

VccClkDMI 1.05 0.075 0.075 0.065 0.065 0 0

VccSSC 1.05 0.095 0.095 0.095 0.095 0 0

VccDIFFCLKN 1.05 0.055 0.055 0.05 0.05 0 0

VccALVDS 3.3 0.001 0.001 0.001 0.001 0 0

VccTX_LVDS31.8 0.04 0.001 0.04 0.001 0 0

DcpSus

(External

Suspend VR

mode using

INTVRMEN)6

1.05 0.1 0.1 0.05 0.05 0.06 0.017

Table 8-6. Measured ICC (Mobile Only) (Sheet 2 of 2)

Voltage Rail Voltage

(V)

S0 Iccmax

Current

Integrated

Graphics5

(A)

S0 Iccmax

Current

External

Graphics5

(A)

S0 Idle

Current

Integrated

Graphics4,5

(A)

S0 Idle

Current

External

Graphics5

(A)

Iccmax

Current5

(A)

Sx Idle

Current

(A)

Electrical Characteristics

318 Datasheet

Table 8-7. DC Characteristic Input Signal Association (Sheet 1 of 2)

Symbol Associated Signals

VIH1/VIL1

(5V Tolerant)

PCI Signals (Desktop Only): AD[31:0], C/BE[3:0]#, DEVSEL#,

FRAME#, IRDY#, PAR, PERR#, PLOCK#, REQ[3:0]#, SERR#, STOP#,

TRDY#

Interrupt Signals: PIRQ[D:A]#, PIRQ[H:E]#

GPIO Signals: GPIO[54, 52, 50, 5:2]

VIH2/VIL2 Digital Display Port Hot Plug Detect: DDPB_HPD, DDPC_HPD,

DDPD_HPD

VIH3/VIL3

Power Management Signals: PWRBTN#, RI#, SYS_RESET#, WAKE#,

SUSACK#

Mobile Only: AC_PRESENT, CLKRUN#

GPIO Signals: GPIO[71:61, 57, 48, 39, 38, 34, 31:29, 24, 22, 17, 7, 6,

Desktop Only: GPIO32

Thermal/Fan Control Signals: TACH[7:0] (Server/Workstation Only)

VIH4/VIL4

Clock Signals: CLKIN_PCILOOPBACK, PCIECLKRQ[7:6]#,

PCIECLKRQ[2], PCIECLKRQ[5]

Mobile Only: PEG_A_CLKRQ#, PEG_B_CLKRQ#, PCIECLKRQ[1:0],

PCIECLKRQ[4:3]

Processor Signals: A20GATE

PCI Signals: PME#

Interrupt Signals: SERIRQ

Power Management Signals: BMBUSY#

Mobile Only: BATLOW#

SATA Signals: SATA[5:0]GP

SPI Signals: SPI_MISO

Strap Signals: SPKR, GNT[3:1]#, (Strap purposes only)

LPC/Firmware Hub Signals: LAD[3:0]/FWH[3:0], LDRQ0#, LDRQ1#,

GPIO Signals: GPIO[73, 72, 59, 56, 55, 53, 51, 49, 47:40, 37:35, 33,

28:25, 23, 21:18, 16:14, 10:8, 0]

Desktop Only: GPIO12

USB Signals: OC[7:0]#

VIH5/VIL5

SMBus Signals: SMBCLK, SMBDATA, SMBALERT#

System Management Signals: SML[1:0]CLK(1), SML[1:0]DATA(1)

GPIO Signals: GPIO[75, 74, 60, 58, 11]

VIH6/VIL6 JTAG Signals: JTAG_TDI, JTAG_TMS, JTAG_TCK

VIH7/VIL7 Processor Signals: THRMTRIP#

VIMIN8Gen1/

VIMAX8Gen1,

VIMIN8Gen2/

VIMAX8Gen2

PCI Express* Data RX Signals: PER[p,n][8:1] (2.5 GT/s and 5.0 GT/s)

VIH9/VIL9 Real Time Clock Signals: RTCX1

VIMIN10 -Gen1i/

VIMAX10-Gen1i SATA Signals: SATA[5:0]RX[P,N] (1.5 Gb/s internal SATA)

VIMIN10 -Gen1m/

VIMAX10-Gen1m SATA Signals: SATA[5:0]RX[P,N] (1.5 Gb/s external SATA)

VIMIN10 -Gen2i/

VIMAX10-Gen2i SATA Signals: SATA[5:0]RX[P,N] (3.0 Gb/s internal SATA)

VIMIN10 -Gen2m/

VIMAX10-Gen2m SATA Signals: SATA[5:0]RX[P,N] (3.0 Gb/s external SATA)

Datasheet 319

Electrical Characteristics

NOTES:

1. VDI = | USBPx[P] – USBPx[N]

2. Includes VDI range

3. Applies to Low-Speed/High-Speed USB

4. PCI Express mVdiff p-p = 2*|PETp[x] – PETn[x]|

5. SATA Vdiff, RX (VIMAX10/MIN10) is measured at the SATA connector on the receiver side

(generally, the motherboard connector), where SATA mVdiff p-p = 2*|SATA[x]RXP –

SATA[x]RXN|

6. VccRTC is the voltage applied to the VccRTC well of the PCH. When the system is in a G3

state, this is generally supplied by the coin cell battery, but for S5 and greater, this is

generally VccSus3_3.

7. CL_Vref = 0.12*(VccSus3_3)

8. This is an AC characteristic that represents transient values for these signals.

9. Applies to High-Speed USB 2.0.

VIH11/VIL11

Intel High Definition Audio Signals: HDA_SDIN[3:0] (3.3V Mode)

Strap Signals: HDA_SDO, HDA_SYNC (Strap purposes only)

GPIO Signals: GPIO13

NOTE: See VIL_HDA/VIH_HDA for High Definition Audio Low Voltage

Mode

VIH12 (Absolute

Maximum) / VIL12

(Absolute Minimum) /

Vclk_in_cross(abs)

Clock Signals: CLKIN_DMI_[P,N], CLKIN_DOT96[P,N],

CLKIN_SATA_[P,N]]

VIH13/VIL13 Miscellaneous Signals: RTCRST#

VIH14/VIL14

Power Management Signals: PWROK, RSMRST#, DPWROK

System Management Signals: INTRUDER#

Miscellaneous Signals: INTVRMEN, SRTCRST#

VIH15/VIL15

Digital Display Control Signals: CRT_DDC_CLK, CRT_DDC_DATA

SDVO_CTRLCLK, SDVO_CTRLDATA, DDPC_CTRLCLK, DDPC_CTRLDATA,

DDPD_CTRLCLK, DDPD_CTRLDATA

Mobile only: L_BKLTEN, L_BKLTCTL, L_DDC_CLK, L_DDC_DATA

VIH16/VIL16 Processor Interface: RCIN#

Power Management Signals: SYS_PWROK, APWROK

VIH_CL/VIL_CL Controller Link: CL_CLK1, CL_DATA1

VDI / VCM / VSE

(5V Tolerant) USB Signals: USBP[13:0][P,N] (Low-speed and Full-speed)

VHSSQ / VHSDSC /

VHSCM

(5V Tolerant)

USB Signals: USBP[13:0][P,N] (in High-speed Mode)

VIH_HDA / VIL_HDA

Intel® High Definition Audio Signals: HDA_SDIN[3:0]

Strap Signals: HDA_SDO, HDA_SYNC (Strap purposes only)

NOTE: Only applies when running in Low Voltage Mode (1.5 V)

VIH_SST/VIL_SST SST (Server/Workstation Only)

VIH_FDI/VIL_FDI Intel® Flexible Display Interface Signals: FDI_RX[P,N][7:0]

VAUX-Diff-P-P Digital Display Port Aux Signal (Receiving Side):

DDP[D:B]_AUX[P,N]

VIH_XTAL25/

VIL_XTAL25

25MHz Crystal Input

XTAL25_IN

VIMIN17-Gen3i/

VIMAX17-Gen3i SATA Signals: SATA[5:0]RX[P,N] (6.0 Gb/s internal SATA)

Table 8-7. DC Characteristic Input Signal Association (Sheet 2 of 2)

Symbol Associated Signals

Electrical Characteristics

320 Datasheet

Table 8-8. DC Input Characteristics (Sheet 1 of 3)

Symbol Parameter Min Max Unit Notes

VIL1 Input Low Voltage –0.5 0.3 × 3.3 V V 10

VIH1 Input High Voltage 0.5 × 3.3 V V5REF + 0.5 V 10

VIL2 Input Low Voltage — .8 V

VIH2 Input High Voltage 2 — V

VIL3 Input Low Voltage –0.5 0.8 V

VIH3 Input High Voltage 2.0 3.3 V + 0.5 V 10

VIL4 Input Low Voltage –0.5 0.3 × 3.3 V V 10

VIH4 Input High Voltage 0.5 × 3.3 V 3.3 V + 0.5 V 10

VIL5 Input Low Voltage 0 0.8 V

VIH5 Input High Voltage 2.1 3.3 V + 0.5 V 10

VIL6 Input Low Voltage -0.5 0.35 V 11

VIH6 Input High Voltage 0.75 1.05 V + 0.5 V 11

VIL7 Input Low Voltage 0 0.25 × V_PROC_IO V

VIH7 Input High Voltage 0.75 × V_PROC_IO V_PROC_IO V

VIMIN8Gen1 Minimum Input Voltage 175 — mVdiffp-p 4

VIMAX8Gen1 Maximum Input Voltage — 1200 mVdiffp-p 4

VIMIN8Gen2 Minimum Input Voltage 100 — mVdiffp-p 4

VIMAX8Gen2 Maximum Input Voltage — 1200 mVdiffp-p 4

VIL9 Input Low Voltage –0.5 0.10 V

VIH9 Input High Voltage 0.50 1.2 V

VIMIN10-

Gen1i

Minimum Input Voltage -

1.5 Gb/s internal SATA 325 — mVdiffp-p 5

VIMAX10-

Gen1i

Maximum Input Voltage -

1.5 Gb/s internal SATA — 600 mVdiffp-p 5

VIMIN10-

Gen1m

Minimum Input Voltage -

1.5 Gb/s eSATA 240 — mVdiffp-p 5

VIMAX10-

Gen1m

Maximum Input Voltage -

1.5 Gb/s eSATA — 600 mVdiffp-p 5

VIMIN10-

Gen2i

Minimum Input Voltage -

3.0 Gb/s internal SATA 275 — mVdiffp-p 5

VIMAX10-

Gen2i

Maximum Input Voltage -

3.0 Gb/s internal SATA — 750 mVdiffp-p 5

VIMIN10-

Gen2m

Minimum Input Voltage -

3.0 Gb/s eSATA 240 — mVdiffp-p 5

VIMAX10-

Gen2m

Maximum Input Voltage -

3.0 Gb/s eSATA — 750 mVdiffp-p 5

VIL11 Input Low Voltage 0 0.35 × 3.3 V V 10

VIH11 Input High Voltage 0.65 × 3.3 V 3.3 + 0.5V V 10

VIL12

(Absolute

Minimum)

Input Low Voltage -0.3 — V

Datasheet 321

Electrical Characteristics

VIH12

(Absolute

Maximum)

Input High Voltage — 1.150 V

VIL13 Input Low Voltage –0.5 0.78 V

VIH13 Input High Voltage 2.3 VccRTC + 0.5 V 6

VIL14 Input Low Voltage –0.5 0.78 V

VIH14 Input High Voltage 2.0 VccRTC + 0.5 V 6

VIL15 Input Low Voltage –0.5 0.3 × 3.3 V V 10

VIH15 Input High Voltage 0.7 × 3.3 V 3.3 V + 0.5 V 10

VIL16 Input Low Voltage –0.5 0.8 V 10

VIH16 Input High Voltage 2.1 3.3 V + 0.5 V 10

VIL_CL Input Low Voltage –0.3 CL_VREF - 0.075 V 7

VIH_CL Input High Voltage CL_VREF + 0.075 1.2 V 7

Vclk_in_cross

(abs) Absolute Crossing Point 0.250 0.550 V

VDI Differential Input Sensitivity 0.2 — V 1,3

VCM Differential Common Mode

Range 0.8 2.5 V 2,3

VSE Single-Ended Receiver

Threshold 0.8 2.0 V 3

VHSSQ HS Squelch Detection

Threshold 100 150 mV 9

VHSDSC HS Disconnect Detection

Threshold 525 625 mV 9

VHSCM HS Data Signaling Common

Mode Voltage Range –50 500 mV 9

VIL_HDA Input Low Voltage 0 0.4 × Vcc_HDA V

VIH_HDA Input High Voltage 0.6 × Vcc_HDA 1.5 V

VIL_SST

(Server/

Workstation

Only)

Input Low Voltage -0.3 0.4 V

VIH_SST

(Server/

Workstation

Only)

Input High Voltage 1.1 1.5 V

VIL_PECI Input Low Voltage -0.15 0.275 ×

V_PROC_IO V

VIH_PECI Input High Voltage 0.725 ×

V_PROC_IO V_PROC_IO + 0.15 V

VIL_FDI Minimum Input Voltage 175 — mVdiffp-p

VIH_FDI Maximum Input Voltage — 1000 mVdiffp-p

Table 8-8. DC Input Characteristics (Sheet 2 of 3)

Symbol Parameter Min Max Unit Notes

Electrical Characteristics

322 Datasheet

NOTES:

1. VDI = | USBPx[P] – USBPx[N]

2. Includes VDI range

3. Applies to Low-Speed/Full-Speed USB

4. PCI Express mVdiff p-p = 2*|PETp[x] – PETn[x]|

5. SATA Vdiff, RX (VIMAX10/MIN10) is measured at the SATA connector on the receiver side (generally, the

motherboard connector), where SATA mVdiff p-p = 2*|SATA[x]RXP – SATA[x]RXN|.

6. VccRTC is the voltage applied to the VccRTC well of the PCH. When the system is in a G3 state, this is

generally supplied by the coin cell battery, but for S5 and greater, this is generally VccSus3_3.

7. CL_Vref = 0.12*(VccSus3_3).

8. This is an AC Characteristic that represents transient values for these signals.

9. Applies to High-Speed USB 2.0.

10. 3.3 V refers to VccSus3_3 for signals in the suspend well, Vcc3_3 for signals in the core well and to

VccDSW3_3 for signals in the DSW well. See Ta b l e 3 - 2 , or Ta b l e 3 - 3 for signal and power well association.

11. 1.05 V refers to VccIO or VccCore for signals in the core well and to VccASW for signals in the ME well. See

Ta b l e 3 - 2 or Ta b l e 3 - 3 for signal and power well association.

12. Vpk-pk min for XTAL25 = 500 mV.

VAUX-Diff-P-P

Digital Display Port Auxiliary

Signal peak-to-peak voltage

at receiving device

0.32 1.36 Vdiffp-p

VIL_XTAL25 Minimum Input Voltage -0.25 0.15 V 12

VIH_XTAL25 Maximum Input Voltage 0.7 1.2 V 12

VIMIN17-

Gen3i

Minimum Input Voltage -

6.0 Gb/s internal SATA 240 — mVdiffp-p 5

VIMAX17-

Gen3i

Maximum Input Voltage -

6.0 Gb/s internal SATA — 1000 mVdiffp-p 5

Table 8-8. DC Input Characteristics (Sheet 3 of 3)

Symbol Parameter Min Max Unit Notes

Datasheet 323

Electrical Characteristics

Table 8-9. DC Characteristic Output Signal Association (Sheet 1 of 2)

Symbol Associated Signals

VOH1/VOL1 Processor Signal: PMSYNCH, PROCPWRGD

VOH2/VOL2

LPC/Firmware Hub Signals: LAD[3:0]/FWH[3:0], LFRAME#/FWH[4],

INIT3_3V#

Power Management Signal: LAN_PHY_PWR_CTRL

Intel® High Definition Audio Signals: HDA_DOCK_EN# (Mobile Only),

HDA_DOCK_RST# (Mobile Only)

PCI Signals: AD[31:0], C/BE[3:0], DEVSEL#, FRAME#, IRDY#, PAR,

PCIRST#, GNT[3:0]#, PME#(1)

Interrupt Signals: PIRQ[D:A], PIRQ[H:E]#(1)

GPIO Signals: GPIO[73, 72, 59, 56, 55:50, 49, 47:40, 37:35, 33, 28:25,

23, 21:18, 16:12, 10:8, 5:2, 0]

SPI Signals: SPI_CS0#, SPI_CS1#, SPI_MOSI, SPI_CLK

Miscellaneous Signals: SPKR

VOH3/VOL3

SMBus Signals: SMBCLK(1), SMBDATA(1)

System Management Signals: SML[1:0]CLK(1), SML[1:0]DATA(1),

SML0ALERT#, SML1ALERT#

GPIO Signals: GPIO[75, 74, 60, 58, 11]

VOH4/VOL4

Power Management Signals: SLP_S3#, SLP_S4#, SLP_S5#, SLP_A#,

SLP_LAN#, SUSCLK, SUS_STAT#, SUSPWRDNACK, SLP_SUS#, STP_PCI#

Mobile Only: CLKRUN#

SATA Signals: SATALED#, SCLOCK, SLOAD, SDATAOUT0, SDATAOUT1

GPIO Signals: GPIO[71:68, 63:61, 57, 48, 39, 38, 34, 31, 30, 29, 24,

22, 17, 7, 6, 1]

Desktop Only: GPIO32

Controller Link: CL_RST1#

Interrupt Signals: SERIRQ

VOH5/VOL5 USB Signals: USBP[13:0][P,N] in Low-speed and Full-speed Modes

VOL6/VOL6 (Fast

Mode)

Digital Display Control Signals: CRT_DDC_CLK, CRT_DDC_DATA

SDVO_CTRLCLK, SDVO_CTRLDATA, DDPC_CTRLCLK, DDPC_CTRLDATA,

DDPD_CTRLCLK, DDPD_CTRLDATA

Mobile only: L_CTRL_CLK, L_CTRL_DATA, L_VDD_EN, L_BKLTEN,

L_BKLTCTL, L_DDC_CLK, L_DDC_DATA,

NOTE: Fast Mode is not applicable to L_VDD_EN

VOH6 L_VDD_EN, L_BKLTEN, L_BKLTCTL

VOMIN7 -Gen1i,m/

VOMAX7-Gen1i,m SATA Signals: SATA[5:0]RX[P,N] (1.5 Gb/s Internal and External SATA)

VOMIN7 -Gen2i,m/

VOMAX7-Gen2i,m SATA Signals: SATA[5:0]RX[P,N] (3.0 Gb/s Internal and External SATA)

VOMIN8/VOMAX8

Digital Display Ports when configured as HDMI/DVI:

DDPB_[3:0][P,N], DDPC_[3:0][P,N], DDPD_[3:0][P,N]

SDVO Signals: SDVO_INT[P,N], SDVO_TVCLKIN[P,N],

SDVO_STALL[P,N]

VOH9/VOL9 Power Management Signal: PLTRST#

Electrical Characteristics

324 Datasheet

NOTE:

1. These signals are open-drain.

VHSOI

VHSOH

VHSOL

VCHIRPJ

VCHIRPK

USB Signals: USBP[13:0][P:N] in High-speed Mode

VOH_HDA/

VOL_HDA

Intel® High Definition Audio Signals: HDA_RST#, HDA_SDO,

HDA_SYNC

VOL_JTAG JTAG Signals: JTAG_TDO

VOH_PCICLK/

VOL_PCICLK

Single Ended Clock Interface Output Signals: CLKOUT_PCI[4:0],

CLKOUTFLEX[3:0]

GPIO Signals: [67:64]

VOL_SGPIO SGPIO Signals: SCLOCK, SLOAD, SDATAOUT0, SDATAOUT1

VOH_PWM/

VOL_PWM

Thermal and Fan Control Signals: PWM[3:0] (Server/Workstation

Only)

VOH_CRT/VOL_CRT Display Signals: CRT_HSYNC, CRT_VSYNC

VOH_CL1/VOL_CL1 Controller Link Signals: CL_CLK1, CL_DATA1

VOH_SST/VOL_SST

(Server/Workstation

Only)

SST signal: SST

VAUX-Diff-P-P Digital Display Port Aux Signal (Transmit Side): DDP[D:B]_AUX[P,N]

VOH_FDI//VOL_FDI Intel® FDI signals:FDI_FSYNC_[1:0],FDI_LSYNC_[1:0],FDI_INT

VOMIN10 -Gen3i/

VOMAX10-Gen3i SATA Signals: SATA[5:0]RX[P,N] (6.0 Gb/s Internal SATA)

VOMIN11-

PCIeGen12

VOMAX11-

PCIeGen12

PCI Express* Data TX Signals: PET[p,n][8:1] (Gen1 and Gen2)

Table 8-9. DC Characteristic Output Signal Association (Sheet 2 of 2)

Symbol Associated Signals

Datasheet 325

Electrical Characteristics

Table 8-10. DC Output Characteristics (Sheet 1 of 2)

Symbol Parameter Min Max Unit IOL / IOH Notes

VOL1 Output Low Voltage 0 0.255 V 3 mA

VOH1 Output High Voltage V_PROC_IO - 0.3 V_PROC_IO V -3 mA

VOL2 Output Low Voltage — 0.1 × 3.3 V V 1.5 mA 7

VOH2 Output High Voltage 0.9 × 3.3 V 3.3 V -0.5 mA 7

VOL3 Output Low Voltage 0 0.4 V 3 mA

VOH3 Output High Voltage 3.3 V - 0.5 — V 4 mA 1, 7

VOL4 Output Low Voltage — 0.4 V 6 mA

VOH4 Output High Voltage 3.3 V - 0.5 3.3 V V -2 mA 7

VOL5 Output Low Voltage — 0.4 V 5 mA

VOH5 Output High Voltage 3.3 V – 0.5 — V -2 mA 7

VOL6 Output Low Voltage 0 400 mV 3 mA 2

VOL6 (Fast

Mode) Output Low Voltage 0 600 mV 6 mA 2

VOH6 Output High Voltage 3.3 V – 0.5 3.3 V -2 mA 7, 2

VOMIN7-

Gen1i,m Minimum Output Voltage 400 — mVdif

fp-p 3

VOMAX7-

Gen1i,m Maximum Output Voltage — 600 mVdif

fp-p 3

VOMIN7-

Gen2i,m Minimum Output Voltage 400 — mVdif

fp-p 3

VOMAX7-

Gen2i,m Maximum Output Voltage — 700 mVdif

fp-p 3

VOMIN8 Output Low Voltage 400 — mVdif

fp-p

VOMAX8 Output High Voltage — 600 mVdif

fp-p

VOL9 Output Low Voltage — 0.1 × 3.3 V V 1.5 mA 7

VOH9 Output High Voltage 0.9 × 3.3 V 3.3 V -2.0 mA 7

VHSOI HS Idle Level –10.0 10.0 mV

VHSOH HS Data Signaling High 360 440 mV

VHSOL HS Data Signaling Low –10.0 10.0 mV

VCHIRPJ Chirp J Level 700 1100 mV

VCHIRPK Chirp K Level –900 –500 mV

VOL_HDA Output Low Voltage — 0.1 × VccSusHDA V 1.5 mA

VOH_HDA Output High Voltage 0.9 × VccSusHDA — V -0.5 mA

VOL_PWM

(Server/

Workstation

Only)

Output Low Voltage — 0.4 V 8 mA

VOH_PWM

(Server/

Workstation

Only)

Output High Voltage — — 1

VOL_SGPIO Output Low Voltage — 0.4 V

Electrical Characteristics

326 Datasheet

NOTES:

1. The SERR#, PIRQ[H:A], SMBDATA, SMBCLK, SML[1:0]CLK, SML[1:0]DATA, SML[1:0]ALERT# and

PWM[3:0] signals has an open-drain driver and SATALED# has an open-collector driver, and the VOH

specification does not apply. This signal must have external pull-up resistor.

2. PCI Express mVdiff p-p = 2*|PETp[x] – PETn[x]|

3. SATA Vdiff, tx (VOMIN7/VOMAX7) is measured at the SATA connector on the transmit side (generally, the

motherboard connector), where SATA mVdiff p-p = 2*|SATA[x]TXP – SATA[x]TXN|

VOL_CRT Output Low Voltage — 0.5 V 8 mA

VOH_CRT Output High Voltage 2.4 — V 8 mA

VOL_CL1 Output Low Voltage — 0.15 V 1 mA

VOH_CL1 Output High Voltage .61 .98 V

VOL_SST

(Server/

Workstation

Only)

Output Low Voltage 0 0.3 V 0.5 mA

VOH_SST

(Server/

Workstation

Only)

Output High Voltage 1.1 1.5 V -6 mA

VOL_PECI Output Low Voltage — 0.25 × V_PROC_IO V 0.5 mA

VOH_PECI Output High Voltage 0.75 ×

V_PROC_IO V_PROC_IO -6 mA

VOL_HDA Output Low Voltage — 0.1 × VccHDA V 1.5 mA

VOL_JTAG Output Low Voltage 0 0.1 × 1.05 V V 1.5 mA

V_CLKOUT_swi

ng Differential Output Swing 300 — mV

V_CLKOUT_cro

ss Clock Cross-Over point 300 550 mV

V_CLKOUTMIN Min output Voltage -0.3 — V

V_CLKOUTMAX Max output Voltage 1.15 V V

VOL_PCICLK Output Low Voltage — 0.4 V -1 mA

VOH_PCICLK Output High Voltage 2.4 — V 1 mA

VAUX-Diff-P-P

Digital Display Port

Auxiliary Signal peak-to-

peak voltage at

transmitting device

0.39 1.38 Vdiffp

-p

VOL_FDI Output Low Voltage -.1 0.2 × 3.3 V V 4.1 mA 7

VOH_FDI Output High Voltage 0.8 × 3.3 V 1.2 V 4.1 mA 7

VOMIN10-

Gen3i Minimum Output Voltage 200 — mVdif

fp-p 3

VOMAX10-

Gen3i Maximum Output Voltage — 900 mVdif

fp-p 3

VOMIN11-

PCIeGen12 Output Low Voltage 800 — mVdif

fp-p 2

VOMAX11-

PCIeGen12 Output High Voltage — 1200 mVdif

fp-p 2

Table 8-10. DC Output Characteristics (Sheet 2 of 2)

Symbol Parameter Min Max Unit IOL / IOH Notes

Datasheet 327

Electrical Characteristics

4. Maximum Iol for PROCPWRGD is 12mA for short durations (<500 mS per 1.5 s) and 9 mA for long

durations.

5. For INIT3_3V only, for low current devices, the following applies: VOL5 Max is 0.15 V at an IOL5 of 2 mA.

6. 3.3 V refers to VccSus3_3 for signals in the suspend well, to Vcc3_3 for signals in the core well, to

VccDSW3_3 for those signals in the Deep S4/S5 well. See Ta b l e 3 - 2 or Ta b l e 3 - 3 for signal and power well

association.

7. 3.3 V refers to VccSus3_3 for signals in the suspend well, to Vcc3_3 for signals in the core well,

VccDSW3_3 for signals in the Deep S4/S5 well. See Tab le 3 -2, or Tab le 3- 3 for signal and power well

association.

Table 8-11. Other DC Characteristics (Sheet 1 of 2)

Symbol Parameter Min Nom Max Unit Notes

V_PROC_IO Processor I/F .95 1.0 1.05 V 1

V_PROC_IO Processor I/F .998 1.05 1.10 V 1

V5REF PCH Core Well Reference Voltage 4.75 5 5.25 V 1

Vcc3_3 I/O Buffer Voltage 3.14 3.3 3.47 V 1

VccVRM Internal PLL and VRMs (1.5V for Mobile) 1.455 1.5 1.545 V 1, 3

VccVRM 1.8 V Internal PLL and VRMs (1.8 V for

Desktop) 1.746 1.8 1.854 V 1, 3

V5REF_Sus Suspend Well Reference Voltage 4.75 5 5.25 V 1

VccSus3_3 Suspend Well I/O Buffer Voltage 3.14 3.3 3.47 V 1

VccCore Internal Logic Voltage .998 1.05 1.10 V 1

VccIO Core Well I/O buffers .998 1.05 1.10 V 1

VccDMI DMI Buffer Voltage .95 1.0 1.05 V 1

VccDMI DMI Buffer Voltage .998 1.05 1.10 V 1

VccClkDMI DMI Clock Buffer Voltage .998 1.05 1.10 1

VccSPI 3.3 V Supply for SPI Controller Logic 3.14 3.3 3.47 V 1

VccASW 1.05 V Supply for Intel® Management

Engine and Integrated LAN .998 1.05 1.10 V 1

VccRTC (G3-S0) Battery Voltage 2 — 3.47 V 1

VccSusHDA High Definition Audio Controller Suspend

Voltage 3.14 3.3 3.47 V 1

VccSusHDA (low

voltage)

High Definition Audio Controller Low

Voltage Mode Suspend Voltage 1.43 1.5 1.58 V 1

VccADPLLA Display PLL A power .998 1.05 1.10 1

VccADPLLB Display PLL B power .998 1.05 1.10 1

VccADAC Display DAC Analog Power. This power is

supplied by the core well. 3.14 3.3 3.47 1

VccALVDS Analog power supply for LVDS (Mobile

Only) 3.14 3.3 3.47 1

VccTX_LVDS I/O power supply for LVDS. (Mobile Only) 1.71 1.8 1.89

VccSSC Spread Modulators Power Supply .998 1.05 1.10 V 1

VccDIFFCLKN Differential Clock Buffers Power Supply .998 1.05 1.10 V 1

VccDFTERM 1.8V power supply for DF_TVS 1.71 1.8 1.89 V 1

VccACLK Analog Power Supply for internal PLL .998 1.05 1.10 V 1

Electrical Characteristics

328 Datasheet

NOTES:

1. The I/O buffer supply voltage is measured at the PCH package pins. The tolerances shown in Table 8 -1 1

are inclusive of all noise from DC up to 20 MHz. In testing, the voltage rails should be measured with a

bandwidth limited oscilloscope that has a rolloff of 3 dB/decade above 20 MHz.

2. Includes Single Ended clocks REFCLK14IN, CLKOUTFLEX[3:0] and PCICLKIN.

3. Includes only DC tolerance. AC tolerance will be 2% in addition to this range.

8.5 Display DC Characteristics

VccAPLLEXP Analog Power Supply for DMI PLL .998 1.05 1.10 V 1

VccFDIPLL Analog Power Supply for FDI PLL .998 1.05 1.10 V 1

VccDSW3_3 3.3 V supply for Deep S4/S5 wells 3.14 3.3 3.47 1

ILI1 PCI_3V Hi-Z State Data Line Leakage –10 — 10 µA (0 V < VIN

< Vcc3_3)

ILI2 PCI_5V Hi-Z State Data Line Leakage –70 — 70 µA

Max VIN =

2.7 V Min

VIN = 0.5 V

ILI3 Input Leakage Current – All Other –10 — 10 µA 2

CIN Input Capacitance – All Other — — TBD pF FC = 1 MHz

COUT Output Capacitance — — TBD pF FC = 1 MHz

CI/O I/O Capacitance — — 10 pF FC = 1 MHz

Typical Value

CLXTAL25_IN 3 pF

CLRTCX1 6 pF

Table 8-12. Signal Groups

Signal Group Associated Signals Note

LVDS LVDSA_DATA[3:0], LVDSA_DATA#[3:0], LVDSA_CLK, LVDSA_CLK#,

LVDSB_DATA[3:0], LVDSB_DATA#[3:0], LVDSB_CLK, LVDSB_CLK#

CRT DAC CRT_RED, CRT_GREEN, CRT_BLUE, CRT_IRTN, CRT_TVO_IREF

Digital

DisplayPort

Auxilliary

DDP[D:B]_AUX[P,N]

Table 8-13. CRT DAC Signal Group DC Characteristics: Functional Operating Range

(VccADAC = 3.3 V ±5%) (Sheet 1 of 2)

Parameter Min Nom Max Unit Notes

DAC Resolution —8—Bits 1

Max Luminance (full-scale) 0.665 0.7 0.77 V 1, 2, 4 white video

level voltage

Min Luminance —0—V

1, 3, 4 black video

level voltage

LSB Current —73.2—uA 4, 5

Integral Linearity (INL) -1 — 1 LSB 1, 6

Table 8-11. Other DC Characteristics (Sheet 2 of 2)

Symbol Parameter Min Nom Max Unit Notes

Datasheet 329

Electrical Characteristics

NOTES:

1. Measured at each R, G, B termination according to the VESA Test Procedure – Evaluation of

Analog Display Graphics Subsystems Proposal (Version 1, Draft 4, December 1, 2000).

2. Max steady-state amplitude

3. Min steady-state amplitude

4. Defined for a double 75- termination.

5. Set by external reference resistor value.

6. INL and DNL measured and calculated according to VESA video signal standards.

7. Max full-scale voltage difference among R,G,B outputs (percentage of steady-state full-

scale voltage).

Differential Linearity (DNL) -1 — 1 LSB 1, 6

Video channel-channel voltage ampli-

tude mismatch —— 6% 7

Monotonicity Yes

Table 8-13. CRT DAC Signal Group DC Characteristics: Functional Operating Range

(VccADAC = 3.3 V ±5%) (Sheet 2 of 2)

Parameter Min Nom Max Unit Notes

Table 8-14. LVDS Interface: Functional Operating Range (VccALVDS = 1.8 V ±5%)

Symbol Parameter Min Nom Max Unit

VOD Differential Output Voltage 250 350 450 mV

VOD Change in VOD between Complementary

Output States ——50mV

VOS Offset Voltage 1.125 1.25 1.375 V

VOS Change in VOS between Complementary

Output States ——50mV

IOs Output Short Circuit Current —-3.5-10mA

IOZ Output TRI-STATE Current — ±1 ±10 µA

Vcm(ac) AC Common Mode noise 150 mV

Table 8-15. Display Port Auxiliary Signal Group DC Characteristics

Symbol Parameter Min Nom Max Unit

Vaux-diff-p-p Aux peak-to-peak voltage at a transmit-

ting devices 0.39 — 1.38 V

Aux peak-to-peak voltage at a receiving

devices 0.32 — 1.36 V

Vaux-term-R AUX CH termination DC resistance —100 — 

V-aux-dc-cm AUX DC common mode voltage 0— 2V

V-aux_turn-CM Aux turn around common mode voltage —0.4 V

Electrical Characteristics

330 Datasheet

8.6 AC Characteristics

NOTES:

1. Specified at the measurement point into a timing and voltage compliance test load and

measured over any 250 consecutive TX UIs. (Also refer to the Transmitter compliance eye

diagram)

2. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of

TTXJITTER-MAX = 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The

TTXEYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median

and the maximum deviation from the median is less than half of the total TX jitter budget

collected over any 250 consecutive TX UIs. It should be noted that the median is not the

same as the mean. The jitter median describes the point in time where the number of jitter

points on either side is approximately equal as opposed to the averaged time value.

3. Specified at the measurement point and measured over any 250 consecutive UIs. The test

load documented in the PCI Express* specification 2.0 should be used as the RX device

when taking measurements (also refer to the Receiver compliance eye diagram). If the

clocks to the RX and TX are not derived from the same reference clock, the TX UI

recovered from 3500 consecutive UI must be used as a reference for the eye diagram.

4. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter

budget for the Transmitter and interconnect collected any 250 consecutive UIs. The TRX-

EYE-MEDIAN-to--MAX-JITTER specification ensures a jitter distribution in which the median and

the maximum deviation from the median is less than half of the total 0.6 UI jitter budget

collected over any 250 consecutive TX UIs. It should be noted that the median is not the

same as the mean. The jitter median describes the point in time where the number of jitter

points on either side is approximately equal as opposed to the averaged time value. If the

clocks to the RX and TX are not derived from the same reference clock, the TX UI

recovered from 3500 consecutive UI must be used as the reference for the eye diagram.

5. Nominal Unit Interval is 400 ps for 2.5 GT/s and 200 ps for 5 GT/s.

Table 8-16. PCI Express* Interface Timings

Symbol Parameter Min Max Unit Figures Notes

Transmitter and Receiver Timings

UI Unit Interval – PCI Express*

Gen 1 (2.5 GT/s) 399.88 400.12 ps 5

UI Unit Interval – PCI Express*

Gen 2 (5.0 GT/s) 199.9 200.1 ps 5

TTX-EYE

Minimum Transmission Eye

Width 0.7 — UI 8-28 1,2

TTX-RISE/Fall

(Gen1)

D+/D- TX Out put Rise/Fall

time —0.125 UI 1,2

TTX-RISE/Fall

(Gen2)

D+/D- TX Out put Rise/Fall

time —0.15 UI 1,2

TRX-EYE Minimum Receiver Eye Width 0.40 — UI 8-29 3,4

Datasheet 331

Electrical Characteristics

NOTES:

1. Specified at the measurement point into a timing and voltage compliance test load and

measured over any 250 consecutive TX UIs. (Also refer to the Transmitter compliance eye

diagram)

2. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of

TTXJITTER-MAX = 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The

TTXEYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median

and the maximum deviation from the median is less than half of the total TX jitter budget

collected over any 250 consecutive TX UIs. It should be noted that the median is not the

same as the mean. The jitter median describes the point in time where the number of jitter

points on either side is approximately equal as opposed to the averaged time value.

NOTES:

1. Specified at the measurement point into a timing and voltage compliance test load and

measured over any 250 consecutive TX UIs. (Also refer to the Transmitter compliance eye

diagram)

2. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of

TTXJITTER-MAX = 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The

TTXEYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median

and the maximum deviation from the median is less than half of the total TX jitter budget

collected over any 250 consecutive TX UIs. It should be noted that the median is not the

same as the mean. The jitter median describes the point in time where the number of jitter

points on either side is approximately equal as opposed to the averaged time value.

Table 8-17. HDMI Interface Timings (DDP[D:B][3:0])Timings

Symbol Parameter Min Max Unit Figures Notes

Transmitter and Receiver Timings

UI Unit Interval 600 4000 ps

TTX-EYE

Minimum Transmission Eye

Width 0.8 — UI 1,2

TTX-RISE/Fall

D+/D- TX Out put Rise/Fall

time —0.125UI 1,2

TMDS

Clock Jitter —0.25UI

T-skew-

intra-pair

Intra pair skew at source

connector —0.15T

BIT

T-skew-

inter-pair

Inter pair skew at source

connector —0.2

Tch ar

acter

Duty Cycle Clock Duty Cycle 10 60% %

Table 8-18. SDVO Interface Timings

Symbol Parameter Min Max Unit Figures Notes

Transmitter and Receiver Timings

UI Unit Interval 369.89 1000 ps 5

TTX-EYE

Minimum Transmission

Eye Width 0.7 — UI 8-28 1,2

TTX-RISE/Fall

D+/D- TX Out put Rise/

Fall time — 0.125 UI 1,2

TRX-EYE

Minimum Receiver Eye

Width 0.40 — UI 8-29 3,4

Electrical Characteristics

332 Datasheet