DS099-1 (v1.4) January 17, 2005 www.xilinx.com 1
Preliminary Product Specification
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Introduction
The Spartan™-3 family of Field-Programmable Gate Arrays
is specifically designed to meet the needs of high volume,
cost-sensitive consumer electronic applications. The
eight-member family offers densities ranging from 50,000 to
five million system gates, as shown in Ta ble 1 .
The Spartan-3 family builds on the success of the earlier
Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of
I/Os, and the overall level of performance as well as by
improving clock management functions. Numerous
enhancements derive from state-of-the-art Virtex™-II tech-
nology. These Spartan-3 enhancements, combined with
advanced process technology, deliver more functionality
and bandwidth per dollar than was previously possible, set-
ting new standards in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3 FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home network-
ing, display/projection and digital television equipment.
The Spartan-3 family is a superior alternative to mask pro-
grammed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
Features
• Very low cost, high-performance logic solution for
high-volume, consumer-oriented applications
- Densities as high as 74,880 logic cells
- Three power rails: for core (1.2V), I/Os (1.2V to
3.3V), and auxiliary purposes (2.5V)
• SelectIO™ signaling
- Up to 784 I/O pins
- 622 Mb/s data transfer rate per I/O
- 18 single-ended signal standards
- 6 differential I/O standards including LVDS, RSDS
- Termination by Digitally Controlled Impedance
- Signal swing ranging from 1.14V to 3.45V
- Double Data Rate (DDR) support
• Logic resources
- Abundant logic cells with shift register capability
- Wide multiplexers
- Fast look-ahead carry logic
- Dedicated 18 x 18 multipliers
- JTAG logic compatible with IEEE 1149.1/1532
• SelectRAM™ hierarchical memory
- Up to 1,872 Kbits of total block RAM
- Up to 520 Kbits of total distributed RAM
• Digital Clock Manager (up to four DCMs)
- Clock skew elimination
- Frequency synthesis
- High resolution phase shifting
• Eight global clock lines and abundant routing
• Fully supported by Xilinx ISE development system
- Synthesis, mapping, placement and routing
• MicroBlaze™ processor, PCI, and other cores
• Pb-free packaging options
• Low-power Spartan-3L Family and Automotive
Spartan-3 XA Family options
06 Spartan-3 FPGA Family:
Introduction and Ordering
Information
DS099-1 (v1.4) January 17, 2005 00Preliminary Product Specification
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Table 1: Summary of Spartan-3 FPGA Attributes
Device
System
Gates
Equivalent
Logic Cells
CLB Array
(One CLB = Four Slices) Distributed
RAM (bits1)
Block RAM
(bits1)
Dedicated
Multipliers DCMs
Maximum
User I/O
Maximum
Differential
I/O PairsRows Columns Total CLBs
XC3S50250K 1,728 16 12 192 12K 72K 4 2 124 56
XC3S2002200K 4,320 24 20 480 30K 216K 12 4 173 76
XC3S4002400K 8,064 32 28 896 56K 288K 16 4 264 116
XC3S10002, 31M 17,280 48 40 1,920 120K 432K 24 4 391 175
XC3S150031.5M 29,952 64 52 3,328 208K 576K 32 4 487 221
XC3S2000 2M 46,080 80 64 5,120 320K 720K 40 4 565 270
XC3S400034M 62,208 96 72 6,912 432K 1,728K 96 4 712 312
XC3S5000 5M 74,880 104 80 8,320 520K 1,872K 104 4 784 344
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
2. These devices are available in Xilinx Automotive versions as described in DS314: Spartan-3 Automotive XA FPGA Family.
3. XC3S1000, XC3S1500, and XC3S4000 are also available in lower static power versions as described in DS313: Spartan-3L Low Power FPGA Family.