LMP7312
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SNOSB32B –MARCH 2010–REVISED MARCH 2013
LMP7312 Precision SPI-Programmable AFE with Differential/Single-Ended Input/Output
Check for Samples: LMP7312
1FEATURES DESCRIPTION
The LMP7312 is a digitally programmable variable
2• Typical Values, TA= 25°C, V+=5V, V-=0V. gain amplifier/attenuator. Its wide input voltage range
• Gain Bandwidth 1 MHz and superior precision make it a prime choice for
• Input Voltage Range (G= 0.096 V/V) -15V to applications requiring high accuracy such as data
+15V acquisition systems for IO modules in programmable
logic control (PLC). The LMP7312 provides a
• Core Op-Amp Input Offset Voltage 100 µV differential output to maximize dynamic range and
(Max) signal to noise ratio, thereby reducing the overall
• Supply Current 2 mA (Max) system error. It can also be configured to handle
• Gain (Attenuation Mode) 0.096 V/V, 0.192 single ended input data converters by means of the
VOCM pin (see Application Section for details). The
V/V0.384 V/V, 0.768 V/V inputs of LMP7312 can be configured in attenuation
• Gain (Amplification Mode) 1 V/V, 2 V/V mode to handle large input signals of up to +/- 15V,
• Gain Error 0.035% (Max) as well as in amplification mode to handle current
• Core Op-Amp PSRR 90 dB (Min) loops of 0-20mA and 4-20mA.The LMP7312 is
equipped with a null switch to evaluate the offset of
• CMRR 80 dB (min) the internal amplifier. A ensured 0.035% maximum
• Adjustable Output Common Mode 1V to 4V gain error (for all gains) and a maximum gain drift of
• Temperature Range −40 to 125°C 5ppm over the extended industrial temperature range
(-40° to 125°C) make the LMP7312 very attractive for
• Package 14-Pin SOIC high precision systems even under harsh conditions.
A low input offset voltage of 100µV and low voltage
APPLICATIONS noise of 3µVpp give the LMP7312 a superior
• Signal Conditioning AFE performance. The LMP7312 is fully specified from -
40° to 125°C and is available in SOIC-14 package.
– ±10V; ±5V; 0-5V; 0-10V; 0-20mA; 4-20mA
• Data Acquisition Systems
• Motor Control
• Instrument and Process Control
• Remote Sensing
• Programmable Automation Control
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SCK
CS
SDI
SDO
-
+
VIO
-VIN
+IN
+VIN
VOCM
SPI
Controller
RFP+VOUT
-VOUT/VR
100 k:
100 k:
V+
V
-
V
-
V+
ADC
VREF V+ ADC
VCM
R2P
R2N
-IN
R1N
R1P
-+
IS 4-20 mA
Driver RS
Sensor
-
+
RFN
LMP7312
SNOSB32B –MARCH 2010–REVISED MARCH 2013
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Typical Application
LMP™ is a trademark of Texas Instruments Corporation.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)
ESD Rating (3)
Human Body Model 2000V
Machine Body Model 150V
Charge device Model 1000V
Analog Supply Voltage (VS= V+- V-) 6V
DigitaI Supply Voltage (VDIO=VIO-V-) 6V
Attenuation pins -VIN, +VIN referred to V-±17.5V
Amplification pins -IN, +IN referred to V-±10V
Voltage at all other pins referred to V-6V
Storage Temperature Range -65°C to 150°C
For soldering specification: http://www.ti.com/lit/SNOA549
Junction Temperature 150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but for which specific performance is not ensured. For ensured specifications and the test
conditions, see Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22–A115–A (ESD MM std. of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22–C101–C (ESD FICDM std. of JEDEC).
Operating Ratings (1)
Analog Supply Voltage (VS= V+– V-), V-=0V 4.5V to 5.5V
Digital Supply Voltage (VDIO = VIO– V-), V-=0V 2.7V to 5.5V
Attenuation pins -VIN, +VIN referred to V--15V to 15V
Amplification pins -IN, +IN referred to V--2.35V to 7.35V
Temperature Range (2) −40°C to 125°C
Package Thermal Resistance (2)
SOIC-14 145°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but for which specific performance is not ensured. For ensured specifications and the test
conditions, see Electrical Characteristics.
(2) The maximum power dissipation is a function of TJ(max), θJA. The maximum allowable power dissipation at any ambient temperature
is: PD(max) = (TJ(max) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
5V Electrical Characteristics (1)
Unless otherwise specified, all limits ensured for TA= 25°C, V+= 5V, VIO = 5V, V−= 0V, G = 0.192 V/V, VCM_ATT=(+VIN+(-
VIN))/2, VCM_AMP=(+IN+(-IN))/2. Differential output configuration. SE = Single Ended Output, DE = Differential Output.Boldface
limits apply at the temperature extremes.
Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units
VOS Core op-amp Input Nulling Switch Mode, DE, VOCM = 1V; –100 100
Offset Voltage Nulling switch Mode, SE, -VOUT/VR= 1V –250 250 µV
Nulling Switch Mode, DE, VOCM = 4V; –100 100
Nulling Switch Mode, SE, -VOUT/VR= 4V –250 250
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ> TA.
(2) All limits are specified by testing, design, or statistical analysis.
(3) Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and
will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production
material.
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5V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits ensured for TA= 25°C, V+= 5V, VIO = 5V, V−= 0V, G = 0.192 V/V, VCM_ATT=(+VIN+(-
VIN))/2, VCM_AMP=(+IN+(-IN))/2. Differential output configuration. SE = Single Ended Output, DE = Differential Output.Boldface
limits apply at the temperature extremes.
Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units
TCVOS Core op-amp Input Nulling Switch Mode, DE, VOCM = 1V; -3 ±1.5 3
Offset Voltage (4) Nulling Switch Mode, SE, -VOUT/VR= 1V µV/°C
Nulling Switch Mode, DE, VOCM = 4V; -3 ±1.5 3
Nulling Switch Mode, SE, -VOUT/VR= 4V
All gains, RL= 10 kΩ, CL= 50pF, SE / DE –0.035 0.035
Gain Error %
–0.045 0.045
Av Gain Drift SE / DE -5 ±1 5 ppm/°C
enCore op-amp Voltage RTI, Nulling Switch Mode, f = 10 kHz 7.25 nV/√Hz
Noise Density
Core op-amp Peak to RTI, Nulling Switch Mode, f= 0.1Hz to 10Hz 3 µVPP
Peak Voltage Noise
IVA Analog Supply Current +VIN =−VIN = VOCM 2mA
IVIO Digital Supply Current Without any load connected to SDO pin 120 μA
RIN_CM CM Input Resistance G= 0.192 V/V 62.08 kΩ
G= 1 V/V 40
RIN_DIFF Differential Input G= 0.192 V/V 248.3 kΩ
Resistance G= 1 V/V 160
G= 0.096V/V, -15V < VCM_ATT < 15V, SE / DE
G= 0.192V/V, -11.4V < VCM_ATT < 15V, SE / DE
G= 0.384V/V, -6V < VCM_ATT < 11V, SE / DE
DC Common Mode 80
CMRR dB
Rejection Ratio 77
G= 0.768V/V, -3V < VCM_ATT < 8V, SE / DE
G= 1V/V, -2.3V < VCM_AMP < 7.3V, SE / DE
G= 2V/V, -1.15V < VCM_AMP < 6.15V, SE / DE.
PSRR Core op-amp DC Nulling Switch Mode, 4.5V <V+<5.5V 90 dB
Power Supply Rejection
Ratio
VOCM_OS VOCM Output Offset (5) VOCM = 2.5 V -20 20 mV
VOUT Positive Output Voltage RL= 10 kΩ, CL= 50 pF, V+−0.2
Swing +VIN= 15V, -VIN= -15V V
Negative Output RL= 10 kΩ, CL= 50 pF, V−+0.2
Voltage Swing +VIN= -15V, -VIN= 15V
+VIN= -VIN = 2.5V, +VOUT, -VOUT/VRconnected 10
Short circuit current individually to either V+or V-
IOUT mA
Current limitation Internal current limiter 55
Attenuation Mode, G = 0.096 V/V, RL=10 kΩ, 1.2
CL= 50 pF MHz
Attenuation Mode, G = 0.192 V/V, RL= 10 kΩ, 1.0
CL= 50 pF
Attenuation Mode, G = 0.384 V/V, RL= 10 kΩ, 560
CL= 50 pF
GBW Bandwidth kHz
Attenuation Mode, G = 0.768 V/V, RL= 10 kΩ, 310
CL= 50 pF
Amplification Mode, G = 1 V/V, RL= 10 kΩ, 530
CL= 50 pF kHz
Amplification Mode, G = 2 V/V, RL= 10 kΩ, 280
CL= 50 pF
(4) Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.
(5) VOCM_OS is the difference between the Output Common mode voltage (+VOUT+(-VOUT/VR))/2 and the Voltage on the VOCM pin.
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5V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits ensured for TA= 25°C, V+= 5V, VIO = 5V, V−= 0V, G = 0.192 V/V, VCM_ATT=(+VIN+(-
VIN))/2, VCM_AMP=(+IN+(-IN))/2. Differential output configuration. SE = Single Ended Output, DE = Differential Output.Boldface
limits apply at the temperature extremes.
Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units
SR Slew Rate RL= 10 kΩ, CL= 50 pF 1.4 V/μsec
(6)
THD+N Total Harmonic Vout = 4.096 Vpp, f = 1KHz, 0.0026 %
Distorsion + Noise RL= 10 kΩ
(6) The number specified is the average of rising and falling slew rates and is measured at 90% to 10%.
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IOL
100 PA
IOH
100 PA
VIO/2
TO SDO PIN CL
20 pF
LMP7312
SNOSB32B –MARCH 2010–REVISED MARCH 2013
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Electrical Characteristics (Serial Interface) (1)
Unless otherwise specified. All limits ensured for TA= 25°C, V+= 5V, V−= 0V, 2.7V < VIO < 5.5V
Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units
VIL Input Logic Low Threshold 0.8 V
VIH Input Logic High Threshold (SDO pin) 2 V
VOL Output logic Low Threshold (SDO pin) ISDO= 100µA 0.2 V
ISDO= 2mA 0.4
VOH Output logic High Threshold ISDO= 100µA VIO-0.2 V
ISDO= 2mA VIO-0.6
t1High Period, SCK (4) 100 ns
t2Low Period, SCK (4) 100 ns
t3Set Up Time, CS to SCK (4) 50 ns
t4Set Up Time, SDI to SCK (4) 30 ns
t5Hold Time, SCK to SDI (4) 10 ns
t6Prop. Delay, SCK to SDO (4) 60 ns
t7Hold Time, SCK Transition to CS Rising (4) 50 ns
Edge
t8CS Inactive (4) 100 ns
t9Hold Time, SCK Transition to CS Falling (4) 10 ns
Edge
tR/tFSignal Rise and Fall Times (4) 1.5 5 ns
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ> TA.
(2) All limits are specified by testing, design, or statistical analysis.
(3) Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and
will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production
material.
(4) Load for these tests is shown in Test Circuit Diagram.
TEST CIRCUIT DIAGRAM
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14
13
12
1
2
3
4
5
6
7
11
10
9
8
LMP7312
SDI
+IN
-IN
+VIN
-VIN
CS
SDO VIO
V+
+VOUT
-VOUT/VR
VOCM
V-
SCK
t7
t8
t3t2t1
t4t5
t6
DNDN±4
DN±1
SCK
SDO
SDI
CS
OLD DN
t9
OLD DN±3OLD DN±4
LMP7312
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SNOSB32B –MARCH 2010–REVISED MARCH 2013
Timing Diagram
Connection Diagram
Figure 1. 14-Pin SOIC-Top View
PIN DESCRIPTIONS
Pin Name Description
1 SDI SPI data IN
2 +IN Non-inverting input of Amplification pair
3 -IN Inverting input of Amplification pair
4 +VIN Non-inverting input of Attenuation pair
5 -VIN Inverting input of Attenuation pair
6 CS SPI chip select
7 SDO SPI data OUT
8 VIO SPI supply voltage
9 V+Positive supply voltage
10 +VOUT Non-inverting output
11 -VOUT/VRInverting output in differential output mode, reference input in single-ended operation mode
12 VOCM Output common mode voltage in DE
13 V−Negative supply voltage, reference for both Analog and Digital supplies
14 SCK SPI Clock
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FREQUENCY (Hz)
NOISE (nV/íHz)
100
10
1
10 100 1k 10k 100k 1M
1s/DIV
500 nV/DIV
TCVOS (éV/°C)
RELATIVE FREQUENCY (%)
15
12
9
6
3
0
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
Nulling Switch Mode
VOCM = 1V
LMP7312
SNOSB32B –MARCH 2010–REVISED MARCH 2013
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Typical Performance Characteristics
Unless otherwise specified, TA= 25°C, V+= 5V, VIO = 5V, V−= 0V, VCM_ATT=(+VIN+(-VIN))/2, VCM_AMP=(+IN+(-IN))/2. RL=
10kΩ, CL=50pF, Differential output configuration.
Offset Voltage distribution (PMOS) Offset Voltage distribution (NMOS)
Figure 2. Figure 3.
TCVOS distribution (PMOS) TCVOS distribution (NMOS)
Figure 4. Figure 5.
Noise
vs.
Frequency (Core op-amp) 0.1Hz to 10Hz Noise (Core op-amp)
Figure 6. Figure 7.
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FREQUENCY (Hz)
PSRR (dB)
110
100
90
80
70
60
50
10 100 1k 10k 100k 1M
VOCM (V)
VOUT (PV)
15
10
5
0
-5
-10
-15
-20
-25
1.0 1.0 2.0 2.5 3.0 3.5 4.0
NULLING SWITCH MODE
FREQUENCY (Hz)
CMRR (dB)
100
90
80
70
60
50
10 100 1k 10k 100k 1M
Gain 0.096V/V
Gain 0.384V/V
Gain 0.192V/V
Gain 0.768V/V
VOCM = 4V
FREQUENCY (Hz)
CMRR (dB)
100
90
80
70
60
50
10 100 1k 10k 100k 1M
Gain 2V/V
Gain 1V/V
VOCM = 4V
100
90
80
70
60
50
FREQUENCY (Hz)
GAIN (dB)
0
-5
-10
-15
-20
-25
100 1k 10k 100k 1M 10M
Gain 0.096V/V
Gain 0.192V/V
Gain 0.384V/V
Gain 0.768V/V
FREQUENCY (Hz)
GAIN (dB)
9
6
3
0
-3
-6
100 1k 10k 100k 1M
Gain 2V/V
Gain 1V/V
9
6
3
0
-3
-6
LMP7312
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SNOSB32B –MARCH 2010–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Unless otherwise specified, TA= 25°C, V+= 5V, VIO = 5V, V−= 0V, VCM_ATT=(+VIN+(-VIN))/2, VCM_AMP=(+IN+(-IN))/2. RL=
10kΩ, CL=50pF, Differential output configuration.
Gain Gain
vs. vs.
Frequency (Attenuation Mode) Frequency (Amplification Mode)
Figure 8. Figure 9.
CMRR CMRR
vs. vs.
Frequency (Attenuation Mode) Frequency (Amplification Mode)
Figure 10. Figure 11.
Vos
vs.
PSRR (Core op-amp) Input Common Mode Voltage
Figure 12. Figure 13.
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Gain 2V/V
Input
500 ns/DIV
50 mV/DIV
100 mV/DIV
Gain 1V/V
VCM_AMP = 2.5V
Input
Gain 0.096V/V
Gain 0.192V/V
Gain 0.384V/V
Gain 0.768V/V
500 ns/DIV
20 mV/DIV
100 mV/DIV
VCM_ATT = 2.5V
5 Ps/DIV
2V/DIV
10V/DIV
Input
Gain 0.096V/V
Gain 0.384V/V
Gain 0.768V/V VCM_ATT = 2.5V
Gain 0.192V/V
5 Ps/DIV
2V/DIV
5V/DIV
Input
Gain 1V/V
Gain 2V/V
VCM_AMP = 2.5V
Input
Gain 0.096V/V
Gain 0.768V/V
5 Ps/DIV
20 mV/DIV
200 mV/DIV
VCM_ATT = 2.5V
Gain 0.192V/V
Gain 0.384V/V
Gain 1V/V
Input Gain 2V/V
100 mV/DIV
200 mV/DIV
5 Ps/DIV
VCM_AMP = 2.5V
LMP7312
SNOSB32B –MARCH 2010–REVISED MARCH 2013
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA= 25°C, V+= 5V, VIO = 5V, V−= 0V, VCM_ATT=(+VIN+(-VIN))/2, VCM_AMP=(+IN+(-IN))/2. RL=
10kΩ, CL=50pF, Differential output configuration.
Small signal step (Attenuation Mode) Small signal step (Amplification Mode)
Figure 14. Figure 15.
Large signal step (Attenuation Mode) Large signal step (Amplification Mode)
Figure 16. Figure 17.
Settling time – Rise (Attenuation Mode) Settling time – Rise (Amplification Mode)
Figure 18. Figure 19.
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FREQUENCY (Hz)
THD + N (%)
1
0.1
0.01
0.001
10 100 1k 10k 100k
Gain 0.768V/V
Gain 0.384V/V
Gain 0.096V/V
Differential Input
VCM_ATT = 2.5V
+VOUT -(-VOUT) = 4.096 Vpp
Gain 0.192V/V
FREQUENCY (Hz)
THD + N (%)
1
0.1
0.01
0.001
10 100 1k 10k 100k
Gain 2V/V
Gain 1V/V
Differential Input
VCM_AMP = 2.5V
+VOUT -(-VOUT) = 4.096 Vpp
2V/DIV
1V/DIV
CS
Gain 0.096V/V
Gain 0.768V/V
10 Ps/DIV
CS Gain 1V/V
Gain 2V/V
10 Ps/DIV
2V/DIV
1V/DIV
Input
Gain 0.096V/V
Gain 0.192V/V
Gain 0.768V/V
500 ns/DIV
20 mV/DIV
100 mV/DIV
VCM_ATT = 2.5V
Gain 0.384V/V
Gain 2V/V
Input
500 ns/DIV
55 mV/DIV
100 mV/DIV
Gain 1V/V
VCM_AMP = 2.5V
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA= 25°C, V+= 5V, VIO = 5V, V−= 0V, VCM_ATT=(+VIN+(-VIN))/2, VCM_AMP=(+IN+(-IN))/2. RL=
10kΩ, CL=50pF, Differential output configuration.
Settling time – Fall (Attenuation Mode) Settling time – Fall (Amplification Mode)
Figure 20. Figure 21.
Gain change (Attenuation Mode) Gain change (Amplification Mode)
Figure 22. Figure 23.
THD + N (Attenuation Mode) THD + N (Amplification Mode)
Figure 24. Figure 25.
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OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
5.0
4.0
3.0
2.0
1.0
0
-30 -20 -10 0 10 20 30
-40°C
-40°C
25°C
25°C
125°C 125°C
SOURCE
VIN+ = +15V
VIN- = -15V
SINK
VIN+ = -15V
VIN- = +15V
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
5.0
4.0
3.0
2.0
1.0
0
-30 -20 -10 0 10 20 30
-40°C
-40°C
25°C
25°C
125°C 125°C
SOURCE
VIN+ = -15V
VIN- = +15V
SINK
VIN+ = +15V
VIN- = -15V
TEMPERATURE (°C)
IOUT (mA)
50.0
30.0
10.0
-10.0
-30.0
-50.0
-40 -7 26 59 92 125
Source
Sink
TEMPERATURE (°C)
IOUT (mA)
50.0
30.0
10.0
-10.0
-30.0
-50.0
-40 -7 26 59 92 125
Source
Sink
VA (V)
IVA (mA)
1.35
1.31
1.27
1.23
1.19
1.15
4.5 4.7 4.9 5.1 5.3 5.5
125°C
25°C
-40°C
VIO (V)
IVIO (éA)
75
67
59
51
43
35
2.7 3.3 3.8 4.4 4.9 5.5
-40°C
125°C
25°C
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA= 25°C, V+= 5V, VIO = 5V, V−= 0V, VCM_ATT=(+VIN+(-VIN))/2, VCM_AMP=(+IN+(-IN))/2. RL=
10kΩ, CL=50pF, Differential output configuration.
IVA IVIO
vs. vs.
VAVIO Voltage
Figure 26. Figure 27.
Short Circuit Current +VOUT Short Circuit Current -VOUT
vs. vs.
Temperature Temperature
Figure 28. Figure 29.
Output voltage swing +VOUT Output voltage swing -VOUT
vs. vs.
Output current Output current
Figure 30. Figure 31.
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VSDO (V)
ISDO (mA)
20.0
16.0
12.0
8.0
4.0
0
1.0 2.0 3.0 4.0 5.0 6.0
VIO = 2.7V
VIO = 5.5V
20.0
16.0
12.0
8.0
4.0
0
VSDO (V)
ISDO (mA)
20.0
16.0
12.0
8.0
4.0
0
0 0.3 0.6 0.9 1.2 1.5
VIO = 2.7V
VIO = 5.5V
20.0
16.0
12.0
8.0
4.0
0
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA= 25°C, V+= 5V, VIO = 5V, V−= 0V, VCM_ATT=(+VIN+(-VIN))/2, VCM_AMP=(+IN+(-IN))/2. RL=
10kΩ, CL=50pF, Differential output configuration.
SDO sink current SDO source current
vs. vs.
SDO Voltage SDO Voltage
Figure 32. Figure 33.
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SCK
CS
SDI
SDO
-
+
VIO
-VIN
+IN
+VIN
VOCM
SPI
Controller
RFP+VOUT
-VOUT/VR
100 k:
100 k:
V+
V
-
V
-
V+
ADC
VREF V+ ADC
R2P
R2N
-IN
R1N
R1P
-
+
VCM
RFN
LMP7312
SNOSB32B –MARCH 2010–REVISED MARCH 2013
www.ti.com
APPLICATION SECTION
GENERAL DESCRIPTION
The LMP7312 is a single supply programmable gain difference amplifier with two input pairs: Attenuation pair (-
VIN, +VIN) and Amplification pair (-IN, +IN). The output can be configured in both single-ended and differential
modes with the output common mode voltage set by the user. The input selection, the gains and the mode of
operation of the LMP7312 are controlled through a 4- wire SPI interface (SCK, CS, SDI, SDO). These features
combined make the LMP7312 a very easy interface between the analog high voltage industrial buses and the
low voltage digital converters.
OUTPUT MODE CONFIGURATION
The LMP7312 is able to work in both single ended and differential output mode. The selection of the mode is
made through the VOCM (output common mode voltage) pin.
Differential Output
This mode of operation is enabled when the output common mode voltage pin (VOCM) is connected to a voltage
higher than 1V, for instance the common mode voltage supplied by an ADC, (Figure 34) or a voltage reference. If
the VOCM pin is floating an internal voltage divider biases it at the half supply voltage. In this configuration the
output signals are set on the VOCM voltage level.
Single-Ended Output
This mode of operation is enabled when the VOCM pin is tied to a voltage less than 0.5 V, for example to ground.
In this mode of operation the LMP7312 behaves as a difference amplifier, where the +VOUT pin is the single-
ended output while the –VOUT /VRis the reference voltage.
1. In the case of bipolar input signal the non inverting output will be connected to an external reference through
a buffer (Figure 35).
2. In the case of unipolar input signal the non inverting output will be connected to ground (Figure 36).
In both cases the inverting output pin is configured as an input pin.
Figure 34. Differential ADC Interfacing with VCM provided by the ADC
14 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: LMP7312
SCK
CS
SDI
SDO
-
+
VIO
-VIN
+VIN
VOCM
SPI
Controller
RFP
RF
+VOUT
-VOUT/VR
100 k:
100 k:
R1N
V+
V
-
V
-
V+
ADC
V+ ADC
R1P
R2P
R2N
-IN
+IN
VAC > 0
Where VAC = -VIN ± (+VIN)
VAC
VDC +
-N
SCK
CS
SDI
SDO
-
+
VIO
-VIN
+VIN
VOCM
SPI
Controller
RFP+VOUT
-VOUT/VR
100 k:
100 k:
R1N
R1P
V+
V
-
V
-
V+
ADC
VREF
-
+
R2N
-IN
+IN
R2P
VAC >0 , VAC <0
Where VAC = -VIN ± (+VIN)
VAC
VDC +
-
V+ ADC
RFN
LMP7312
www.ti.com
SNOSB32B –MARCH 2010–REVISED MARCH 2013
Figure 35. Bipolar Input Signal to Single-Ended ADC Interface
Figure 36. Unipolar Input Signal to Single-Ended ADC Interface
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LMP7312
LMP7312
SNOSB32B –MARCH 2010–REVISED MARCH 2013
www.ti.com
INPUT VOLTAGE RANGE
The LMP7312 has an internal OpAmp with rail-to-rail input voltage range capability. The requirement to stay
within the V-and V+rail at the OpAmp input translates in an Input Voltage Range specification as explained in this
application section.
Differential Output
Considering a single positive supply (V-= GND, V+= VS) the Input Common mode voltage, VCM_ATT = (+VIN + (-
VIN))/2 for the Attenuation inputs and VCM_AMP = (+IIN + (-IIN))/2 for the Amplification inputs, has to stay between
the MIN and MAX values determined by these formulas:
CMMAX = VS+ 1/KV*(VS- VOCM)
CMMIN = -1/KV*VOCM
KVis a function of the Gain according to the table below:
Gain 0.096 V/V 0.192 V/V 0.384 V/V 0.768 V/V 1 V/V 2 V/V
KV0.12 0.218 0.414 0.806 1.065 2.096
Regardless to the values derived by the formula, the voltage on each input pin must never exceed the specified
Absolute Maximum Ratings.
Below are some typical values:
Table 1. Differential Input, Differential Output, VS= 5V, VOCM = 2.5V
VCM_ATT VCM_AMP
Gain Min Max Min Max
0.096 V/V -15 V(1) +15 V(1)
0.192 V/V -11.5 V +15 V
0.384 V/V -6 V +11 V
0.768 V/V -3.1 V +8.1 V
1 V/V -2.3 V +7.3 V
2 V/V -1.2 V +6.2 V
(1) Limited by the operating ratings on input pins
In the case of a single ended input referred to ground (-VIN = GND, -IN = GND) the table below summarizes the
voltage range allowed on the +VINand +IIN inputs.
Table 2. Single Ended Input, Differential Output, VS= 5V, VOCM = 2.5V, -VIN = GND, -IIN = GND
+VIN +IN
Gain Min Max Min Max
0.096 V/V -15 V(1) +15 V(1)
0.192 V/V -15 V(1) +15 V(1)
0.384 V/V -12 V(2) +12 V(2)
0.768 V/V -6 V(2) +6 V(2)
1 V/V -4.6 V(2) +4.6 V(2)
2 V/V -2.3 V(2) +2.3 V(2)
(1) Limited by the operating ratings on input pins.
(2) Limited by the output voltage swing (0.2V to VS-0.2V on both + VOUT and -VOUT)
16 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: LMP7312
LMP7312
www.ti.com
SNOSB32B –MARCH 2010–REVISED MARCH 2013
Single Ended Output
In this mode the LMP7312 behaves as a Difference Amplifier, with -VOUT/VRbeing the reference output voltage
when a zero volt differential input signal is applied. The voltages at the OpAmp inputs are determined by +VIN
and -VOUT/VRvoltages. The voltage range of +VIN and +IIN inputs is as follows:
VMAX = VS+ 1/ KV* (VS– (-VOUT/VR))
VMIN = -1/KV* (-VOUT/VR)
Regardless of the values derived by the formula, the voltage on each input pin must never exceed the specified
Absolute Maximum Ratings.
Below are some typical values:
Table 3. Differential Input, Single Ended Output, VS= 5V, VOCM = GND, and -VOUT/VR= 2.5V
+VIN +IIN
Gain Min Max Min Max
0.096 V/V -15 V(1) +15 V(1)
0.192 V/V -11.5 V(1) +15 V
0.384 V/V -6 V +11 V
0.768 V/V -3.1 V +8.1 V
1 V/V -2.3 V +7.3 V
2 V/V -1.2 V +6.2 V
(1) Limited by the operating ratings on input pins
In the case of a single ended input referred to ground (-VIN = GND, -IN = GND) this table summarize the voltage
ranges allowed on the +VIN and +IIN inputs.
Table 4. Single Ended Input, Single Ended Output, VS= 5V, VOCM = GND, -VOUT/VR= 2.5V, -VIN = GND, -IIN =
GND
+VIN +IIN
Gain Min Max Min Max
0.096 V/V -15 V(1) +15 V(1)
0.192 V/V -11.5 V +12 V(2)
0.384 V/V -6 V(2) +6 V(2)
0.768 V/V -3 V** +3 V(2)
1 V/V -2.3 V(2) +2.3 V(2)
2 V/V -1.1 V(2) +1.1 V(2)
(1) Limited by the operating ratings on input pins.
(2) Limited by the output voltage swing (0.2V to VS-0.2V on +VOUT )
SERIAL INTERFACE CONTROL OPERATION
The serial interface control of the LMP7312 can be supplied with a voltage between 2.7V and 5.5V through the
VIO pin for compatibility with different logic families present in the market.
The LMP7312 Attenuation, Amplification, Null switch and HiZ modes are controlled by a register. Data to be
written into the control register is first loaded into the LMP7312 via the serial interface. The serial interface
employs a 5-bit shift register. Data is loaded through the serial data input, SDI. Data passing through the shift
register is obtained through the serial data output, SDO. The serial clock, SCK controls the serial loading
process. All five data bits are required to correctly program the device. The falling edge of CS enables the shift
register to receive data. The SCK signal must be high during the falling edge of CS. Each data bit is clocked into
the shift register on the rising edge of SCK. Data is transferred from the shift register to the holding register on
the rising edge of CS. Operation is shown in the Timing Diagram.
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LMP7312
LMP7312
SNOSB32B –MARCH 2010–REVISED MARCH 2013
www.ti.com
SPI Registers
MSB LSB
Gain_1 Gain_0 EN_CL Null_SW Hi_Z
Gain_0, Gain_1 bit:Gain Values
Different gains are available in Attenuation Mode or Amplification Mode according to the following Gain Table.
Gain_1 Gain_0 EN_CL Gain Value (V/V)
0 0 0 0.096
0 1 0 0.192
1 0 0 0.384
1 1 0 0.768
1 0 1 1
1 1 1 2
EN_CL bit:Enable Amplification Mode
This register selects which input pair is processed.
EN_CL Mode Description
0 Attenuation Mode ±VIN inputs are processed through the 104.16k input resistors
1 Amplification Mode ±IN inputs are processed through the 40k input resistors
NULL_SW bit: Input Offset Nulling Switch Mode
This register selects a mode in which the amplifier is not processing any input but it is configured in unity gain to
allow system level amplifier offset calibration. The Nulling Switch mode is available in both single ended and fully
differential output mode. The LMP7312 in Nulling Switch and fully differential mode has he following
configuration.
NULL_SW Mode Description
0 Normal Operation Mode ±VIN and ±IN inputs are processed depending on EN_CL register
setting.
1 Nulling Switch Mode Enables to evaluate the offset of the internal amplifier for system
level calibration
18 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: LMP7312
-
+
-VIN
+VIN
VOCM
RFP
+VOUT
-VOUT/VR
100 k:
100 k:
V+
V
-
V
-
R1P
R2P
R2N
R1N
-IN
+IN
VIO V+
RFN
LMP7312
www.ti.com
SNOSB32B –MARCH 2010–REVISED MARCH 2013
Figure 37. LMP7312 in Nulling Switch Mode
In this condition at the Output pins is possible to measure the input voltage offset of the op-amp:
Output Mode +VOUT −VOUT/VR
Differential VCM_out+VOS/2 VCM_out -VOS/2
Single-Ended VR+VOS VR
Hi_Z bit:High Impedance
In this mode both outputs +VOUT and -VOUT/VRof the LMP7312 are in tri-state Figure 38.
HI_Z Mode Description
0 Normal Operation Mode The LMP7312 is configured according to value of the other 4 bits of the
register.
1 High Impedance Mode The LMP7312 output is in high impedance
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LMP7312
-
+
-VIN
+VIN
VOCM
RFP
+VOUT
-VOUT/VR
100 k:
100 k:
V+
V
-
V
-
R1P
R2P
R2N
R1N
-IN
+IN
VIO V+
RFN
LMP7312
SNOSB32B –MARCH 2010–REVISED MARCH 2013
www.ti.com
Figure 38. LMP7312 in High Impedance Mode
In each case the SPI registers require 5 bits. The table below is a summary of all allowed configurations.
MSB LSB
Gain_1 Gain_0 EN_CL Null_SW Hi_Z Gain Value (V/V) Mode of Operation
0 0 0 0 0 0.096 Attenuation Mode
0 1 0 0 0 0.192 Attenuation Mode
1 0 0 0 0 0.384 Attenuation Mode
1 1 0 0 0 0.768 Attenuation Mode
1 0 1 0 0 1 Amplification Mode
1 1 1 0 0 2 Amplification Mode
x x x x 1 – High Impedance Output
x x x 1 0 1 Null Switch Mode
Daisy Chain
The LMP7312 supports daisy chaining of the serial data stream between multiple chips. To use this feature serial
data is clocked into the first chip SDI pin, and the next chip SDI pin is connected to the SDO pin of the first chip.
Both chips may share a chip select signal, or the second chip can be enabled separately. When the chip select
pin goes low on both chips and 5 bits have been clocked into the first chip the next 5 clock cycle begins moving
new configuration data into the second chip. With a full 10 clock cycles both chips have valid data and the chip
select pin of both chips should be brought high to prevent the data from overshooting.
20 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: LMP7312
éController
SCK
MOSI
MISO
ADC1x1S626
SCK
SDO
CS
LMP7312
SCK
SDI
CS
CS
éController
SCK
MOSI
MISO
CS
LMP7312
SCK
SDI
CS
SDO
LMP7312
SCK
SDI
CS
SDO
LMP7312
www.ti.com
SNOSB32B –MARCH 2010–REVISED MARCH 2013
Figure 39. Daisy Chain
Shared 4-wire SPI with ADC
The LMP7312 is a good choice when interfacing to differential analog to digital converters ADC141S626 and
ADC161S626 of PowerWise® Family. Its SPI interface has been designed to enable sharing CSB with the ADC.
LMP7312 register access happens only when CSB is asserted low while SCK is high. However, the ADC starts
conversion under any of the following conditions:
1. CSB goes low while SCK is high
2. CSB goes low while SCK is low
3. CSB and SCK both going low
Therefore, if a system uses timing condition #2 above, LMP7312 and ADC1x1S626 can share CSB and SCK as
shown in Figure 40. The only side-effect would be that writing to LMP7312 triggers an ADC conversion, but then
the result can be ignored. At other times, the LMP7312 is not affected by the CSB assertions used to initiate
normal ADC conversions.
Figure 40. 4-wire SPI with ADC interface
LMP7312 IN 4-20mA CURRENT LOOP APPLICATION
The 4-20mA current loop shown in Figure 41 is a common method of transmitting sensor information in many
industrial process-monitoring applications. Transmitting sensor information via a current loop is particularly useful
when the information has to be sent to a remote location over long distances (1000 feet, or more). The loop’s
operation is straightforward: a sensor’s output voltage is first converted to a proportional current, with 4mA
normally representing the sensor’s zero-level output, and 20mA representing the sensor’s full-scale output. Then,
a receiver at the remote end converts the 4-20mA current back into a voltage which in turn can be further
processed by a computer or display module. A typical 4-20mA current-loop circuit is made up of four individual
elements: a sensor/transducer; a voltage-to-current converter (commonly referred to as a transmitter and/or
signal conditioner); a loop power supply; and a receiver/monitor. In loop powered applications, all four elements
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LMP7312
ADC141S626
REF
AMPLIFICATION MODE
G = 2 V/V
1.1k:
1.1k:
VAVIO
680 pF
+5V
LM4132-4.1
+4.7 PF
0.1 PF
-
+
VIO
-VIN
+VIN
VOCM
+VOUT
-VOUT/VR
100 k:
100 k:
V+
V
-
V
-
V+
-IN
+IN
+5V
-+
100:
T
R
A
N
S
M
I
T
T
E
R
SENSOR I_LOOP
Fs = 70 kS/s
0.1 PF
10 PF0.1 PF
+
4.7 PF
+
10 PF
+
+5V
0.1 PF
LMP7312
SNOSB32B –MARCH 2010–REVISED MARCH 2013
www.ti.com
are connected in a closed, series circuit, loop configuration (Figure 41). Sensors provide an output voltage whose
value represents the physical parameter being measured. The transmitter amplifies and conditions the sensor’s
output, and then converts this voltage to a proportional 4-20mA dc-current that circulates within the closed
series-loop. The loop power-supply generally provides all operating power to the transmitter and receiver, and
any other loop components that require a well-regulated dc voltage. In loop-powered applications, the power
supply’s internal elements also furnish a path for closing the series loop. The receiver/monitor, normally a
subsection of a panel meter or data acquisition system, converts the 4-20mA current back into a voltage which
can be further processed and/or displayed. The high DC performance of the LMP7312 makes this difference
amplifier an ideal choice for use in current loop AFE receiver. The LMP7312 has a low input offset voltage and
low input offset voltage drift when configured in amplification mode. In the circuit shown in Figure 41 the
LMP7312 is in amplification mode with a gain of 2V/V and differential output in order to well match the input
stage of the ADC141S626 (SAR ADC with differential input). The shunt resistor is 100ohm in order to have a
max voltage drop of 2V when 20mA flows in the loop. The first order filter between the LMP7312 and the
ADC141S626 reduces the noise bandwidth and allows handling input signal up to 2kHz. That frequency has
been calculated taking in account the roll off of the filter and ensuring a gain error less than 1LSB of the
ADC141S626. In order to utilize the maximum number of bits of the ADC141S626 in this configuration, a 4.1V
reference voltage is used. With this system, the current of the 4-20mA loop is accurately gained to the full scale
of the ADC and then digitized for further processing.
Figure 41. LMP7312 in 4-20mA Current Loop application
LAYOUT CONSIDERATIONS
Power supply bypassing
In order to preserve the gain accuracy of the LMP7312, power supply stability requires particular attention. The
LMP7312 ensures minimum PSRR of 90dB (or 31.62 µV/V). However, the dynamic range, the gain accuracy and
the inherent low-noise of the amplifier can be compromised by introducing and amplifying power supply noise. To
decouple the LMP7312 from supply line AC noise, a 0.1 µF ceramic capacitor should be located on the supply
line, close to the LMP7312. Adding a 10 µF tantalum capacitor in parallel with the 0.1 µF ceramic capacitor will
reduce the noise introduced to the LMP7312 even further by providing an AC path to ground for most frequency
ranges.
22 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: LMP7312
-
+
ÂV2
+
-
ÂV1
+
-
ÂVCM
+
-
A
B
C
LMP7312
www.ti.com
SNOSB32B –MARCH 2010–REVISED MARCH 2013
APPENDIX
Offset Voltage and Offset Voltage Drift calculation
Listed in the table below are the calculated values for Offset Voltage and Offset Voltage Drift based on the max
specifications of these parameters for the core op-amp (for all gain configurations).
Parameter Unit Value
Gain V/V 0.096 0.192 0.384 0.768 1 2
Total Offset Input Referred (MAX) µV ±1141 ±620 ±360 ±230 ±200 ±150
Total Offset Output Referred (MAX) µV ±109 ±119 ±138 ±176 ±200 ±300
TCVOS Input Referred @ 25°C (MAX) µV/°C ±32.3 ±18.6 ±10.8 ±6.9 ±6 ±4.5
TCVOS Output Referred @ 25°C (MAX) µV/°C ±3.3 ±3.6 ±4.1 ±5.3 ±6 ±9
Noise calculation
Listed in the table below are the calculated values for Voltage Noise based on the spectral density of the core
op-amp at 10kHz (for all gain configurations).
Parameter Unit Value
Gain V/V 0.096 0.192 0.384 0.768 1 2
Total Noise Referred to Input nV/√Hz 211 150 112 89 53 46
Total Noise Referred to Output nV/√Hz 20 29 43 68 53 92
Input resistance calculation
The common mode input resistance is the resistance seen from node “A” when ΔV1 = ΔV2 = 0 and a common
mode voltage ΔVCM is applied to both inputs of the LMP7312. The differential input resistance is the resistance
seen from the nodes “B” and “C” when ΔVCM=0 and a differential voltage ΔV1 = ΔV2 = V/2 is applied to the
inputs of the LMP7312.
Figure 42. Circuit for Input Resistance calculation
Mode of Operation Unit Gains
Attenuation Mode 0.096 0.192 0.384 0.768
Common Mode Resistance kΩ57.08 62.08 72.08 92.08
Differential Resistance kΩ228.30 248.30 288.30 368.30
Amplification Mode 1 2
Common Mode Resistance kΩ40.0 60.0
Differential Resistance kΩ160.0 240.0
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LMP7312
LMP7312
SNOSB32B –MARCH 2010–REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 23
24 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: LMP7312
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
LMP7312MA/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMP7312
MA
LMP7312MAX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMP7312
MA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMP7312MAX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMP7312MAX/NOPB SOIC D 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 2
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