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April 1st, 2010
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Rev.2.00, Feb.18.2005, page 1 of 11
HD74LS193
Synchronous Up / Down Decade Counter (dual clock lines)
REJ03D0455–0200
Rev.2.00
Feb.18.2005
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the output change
coincidently with each other when so instructed by the steering logic. This mode of operation eliminates the output
counting spikes, which are normally associated with asynchronous (ripple clock) counters. Th e outputs of the four
master-slave flip-flops are triggered by a low-to-high-level transition of either coun t (clock) input. The direction of
counting is determined by which count input is pulsed while the other count input is high. This counter is fully
programmable; that is, each output may be preset to either level by entering the desired data at th e data inputs while the
load inputs is low. The output will change to agree with the data inputs independently of the count pulses. This feature
allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A
clear input has been provided which forces all outputs to the low level when a high level is applied. The clear function
is independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive
requirements. This reduces the number of clock driver s, etc., required for long words. This counter was designed to be
cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up-
and down-coun ting functions.
The borrow output produces a pulse equal in width to the cou nt-down input when the counter underflows. Similarly,
the carry output produces a pulse equ a l in width to the count up input when an overflow condition exists.
The counters can be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs
respectively of .the succeeding counter.
Features
• Ordering Information
Part Name Package Type Package Code
(Previous Code) Package
Abbreviation Taping Abbreviation
(Quantity)
HD74LS193P DILP-16 pin PRDP0016AE-B
(DP-16FV) P —
HD74LS193FPEL SOP-16 pin (JEITA) PRSP0016DH-B
(FP-16DAV) FP EL (2,000 pcs/reel)
HD74LS193RPEL SOP-16 pin (JEDEC) PRSP0016DG-A
(FP-16DNV) RP EL (2,500 pcs/reel)
Note: Please consult the sales office for the above packa ge availability.
HD74LS193
Rev.2.00, Feb.18.2005, page 2 of 11
Pin Arrangement
(Top view)
V
CC
GND
15
161
2
3
4
5
6
7
14
89
10
11
12
13
B
Q
B
Q
D
D
Q
C
Count
Down
Q
A
A
C
Load
Borrow
Clear
Data B
Input
Q
B
Q
A
Count
Down
Count
Up
Q
C
Q
D
Data D
Data C
Load
Carry
Borrow
Clear
Data A
Count
Up Carry
Inputs
Inputs
Outputs
Inputs
Outputs
Outputs
HD74LS193
Rev.2.00, Feb.18.2005, page 3 of 11
Block Diagram
Data
Input A
Down Count
Up Count
Data
Input B
Data
Input C
Data
Input D
Clear
Load
Q
B
Q
B
T
Output Q
B
Q
C
Q
C
T
Output Q
C
Q
D
Q
D
T
Output Q
D
Q
A
Q
A
T
Output Q
A
Carry
Output
Borrow
Output
Absolute Maximum Ratings
Item Symbol Ratings Unit
Supply voltage VCC 7 V
Input voltage VIN 7 V
Power dissipation PT 400 mW
Storage temperature Tstg –65 to +150 °C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
HD74LS193
Rev.2.00, Feb.18.2005, page 4 of 11
Recommended Operating Conditions
Item Symbol Min Typ Max Unit
Supply voltage VCC 4.75 5.00 5.25 V
IOH — — –400 µA
Output current IOL — — 8 mA
Operating temperature Topr –20 25 75 °C
Clock frequency ƒclock 0 — 25 MHz
Pulse width tw 20 — — ns
Setup time (Clear) tsu (CLR) 40 — — ns
Setup time tsu 20 — — ns
Hold time th 3 — — ns
Electrical Characteristics
(Ta = –20 to +75 °C)
Item Symbol min. typ.* max. Unit Condition
VIH 2.0 — — V
Input voltage VIL — — 0.8 V
VOH 2.7 — — V
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
IOH = –400 µA
— — 0.4 IOL = 4 mA
Output voltage VOL — — 0.5 V IOL = 8 mA VCC = 4.75 V, VIH = 2 V,
VIL = 0.8 V
IIH — — 20 µA VCC = 5.25 V, VI = 2.7 V
IIL — — –0.4 mA VCC = 5.25 V, VI = 0.4 V
Input current II — — 0.1 mA VCC = 5.25 V, VI = 7 V
Short-circuit output
current IOS –20 — –100 mA VCC = 5.25 V
Supply current** ICC — 19 34 mA VCC = 5.25 V
Input clamp voltage VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA
Notes: * VCC = 5 V, Ta = 25°C
** ICC is measured with all outputs open, clear and load inputs grounded, and all other inputs at 4.5 V.
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item Symbol Inputs Outputs min. typ. max. Unit Condition
Maximum clock frequency ƒmax 25 32 — MHz
tPLH — 17 26
tPHL Count-up Carry — 18 24 ns
tPLH — 16 24
tPHL Count-down Borrow — 15 24 ns
tPLH — 27 38
tPHL Either Count Q — 30 47 ns
tPLH — 24 40
tPHL Load Q
— 25 40 ns
Propagation delay time
tPHL Clear Q — 23 35 ns
CL = 15 pF,
RL = 2 kΩ
HD74LS193
Rev.2.00, Feb.18.2005, page 5 of 11
Count Sequences
13
014 15 0
Count Up
Count Up
Count Down
Count Down
Data
Inputs
12 10151413
Load
Carry
Clear Preset
Clear
Borrow
B
A
C
D
Q
C
Q
D
Q
A
Q
B
Outputs
Illustrated below is the following sequence:
1. Clear outputs to zero.
2. Load (preset) to binary thirteen.
3. Count up to fourteen, fifteen, carry, zero, one and two.
4. Count down to one, zero, borrow, fifteen, fourteen, and thirteen.
HD74LS193
Rev.2.00, Feb.18.2005, page 6 of 11
Testing Method
Test Circuit
4.5V
Borrow
Load circuit 1
Output
VCC
RL
CL
Input
P.G.
Zout = 50Ω
See Testing Table
A
B
Clear
Down
C
D
Load
QA
QB
QC
QD
Carry Same as Load Circuit 1.
Output
Same as Load Circuit 1.
Output
Same as Load Circuit 1.
Output
Same as Load Circuit 1.
Output
Same as Load Circuit 1.
Output
Up
Notes: 1. CL includes probe and jig capacitance.
2. All diodes are 1S2074(H).
Testing Table
Inputs
Item From input to output CLR Load Up Down A B C D
Up Count GND 4.5V IN 4.5V GND GND GND GND
ƒmax Down Count GND 4.5V 4.5V IN GND GND GND GND
Up Count GND 4.5V IN 4.5V GND GND GND GND
Down Count GND 4.5V 4.5V IN GND GND GND GND
Load→Q GND IN GND GND IN IN IN IN
tPLH
tPHL Clear→Q IN IN* GND GND 4.5V 4.5V 4.5V 4.5V
Note: *. For initialized
Outputs
Item From input to output QA Q
B Q
C Q
D Carry Borrow
Up Count OUT OUT OUT OUT OUT —
ƒmax Down Count OUT OUT OUT OUT — OUT
Up Count OUT OUT OUT OUT OUT —
Down Count OUT OUT OUT OUT — OUT
Load→Q OUT OUT OUT OUT — —
tPLH
tPHL Clear→Q OUT OUT OUT OUT — —
HD74LS193
Rev.2.00, Feb.18.2005, page 7 of 11
Waveforms 1
ƒmax, tPLH, tPHL, (Count Up)
(Measure at t
n
+ 16)
(Measure at
t
n
+ 16)
(Measure at
t
n
+ 1)
(Measure at
t
n
+ 8)
(Measure at
t
n
+ 4)
(Measure before
1 clock of t
n
+ 16)
(Measure at
t
n
+ 2)
Carry
Outputs
Count
Up 1.3V 1.3V 1.3V
1.3V 1.3V
1.3V
1.3V
1.3V
1.3V
1.3V
1.3V
1.3V
1.3V
Q
A
Q
B
Q
C
Q
D
t
TLH
t
PLH
t
PHL
t
PLH
(Measure at t
n
+ 2)
t
PLH
(Measure at t
n
+ 4)
t
PLH
(Measure at t
n
+ 8)
t
PLH
t
PHL
t
PHL
t
PHL
t
PHL
t
w (L)
t
w (H)
t
THL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
0V
3V
10% 10%
90% 90%
Notes: 1. Input pulse; tTLH, tTHL ≤ 7 ns, Duty Cycle ≤ 50%, PRR = 500 kHz (Data input). PRR = 1 MHz
(except data input)
2. for ƒmax tTLH = tTHL ≤ 2.5 ns.
3. tn is reference bit time when all outputs are low.
HD74LS193
Rev.2.00, Feb.18.2005, page 8 of 11
Waveforms 2
ƒmax, tPLH, tPHL, (Count Down)
Borrow
Outputs
Count
Down
1.3V
1.3V
1.3V
1.3V
1.3V
1.3V 1.3V
1.3V
1.3V
1.3V
1.3V1.3V
1.3V 1.3V 1.3V 1.3V
t
THL
t
w (H)
t
w (L)
t
TLH
Q
A
Q
B
Q
C
Q
D
t
PHL
t
PHL
t
PHL
t
PHL
t
PHL
(Measure before 1 clock of t
n
+ 0) (Measure
at t
n
+ 0)
(Measure
at t
n
+ 0)
(Measure
at t
n
+ 0)
(Measure
at t
n
+ 0)
(Measure
at t
n
+ 0)
(Measure at t
n
+ 1)
(Measure at t
n
+ 2)
(Measure at t
n
+ 4)
(Measure at t
n
+ 8)
t
PLH
t
PLH
t
PLH
t
PLH
t
PLH
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
0V
3V
10% 10%
90%90%
Notes: 1. Input pulse; tTLH ≤ 7 ns, tTHL ≤ 7 ns, PRR = 1 MHz, duty cycle 50%
2. for ƒmax tTLH , tTHL ≤ 2.5 ns.
3. tn is reference bit time when all outputs are high.
HD74LS193
Rev.2.00, Feb.18.2005, page 9 of 11
Waveforms 3
tPLH, tPHL, (Load, Clear→Q)
Clear
Data Inputs
(A to D)
Load
Q
1.3V
1.3V
1.3V
1.3V 1.3V 1.3V
1.3V 1.3V1.3V
1.3V
t
THL
t
TLH
t
TLH
t
TLH
t
THL
t
THL
t
PHL
t
PHL
t
su
t
h
t
su
t
w (CLR)
≥ 20ns
t
PLH
V
OH
V
OL
0V
3V
0V
3V
0V
3V
10%
10%
10%
10%
10%
90%
90%
90% 90%
90%
90%
1.3V
10%
Note: Input pulse: tTLH ≤ 7 ns, tTHL ≤ 7 ns
HD74LS193
Rev.2.00, Feb.18.2005, page 10 of 11
Package Dimensions
7.62
DP-16FV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
19.2
6.3
5.06
MASS[Typ.]
1.05g
A
Z
b
D
E
A
b
c
θ
e
L
1
1
p
3
e
0.51
0.56
1.30
0.19 0.25 0.31
2.29 2.54 2.79
0
°
15
°
PRDP0016AE-BP-DIP16-6.3x19.2-2.54
20.32
7.4
0.40 0.48
1.12
2.54
1
p
1
3
1 8
16 9
e
b
A
LA
Z
e c
E
D
b
0.89
θ
( Ni/Pd/Au plating )
0.80
0.15
1.27
7.50 8.00
0.400.34
p
A
1
10.5
FP-16DAV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
2.20
0.900.700.50
5.50
0.200.100.00
0.46
0.250.200.15
7.80
8
°
0
°
0.12
1.15
10.06
0.24g
MASS[Typ.]
1
E
1
1
2
L
Z
H
y
x
θ
c
b
A
E
D
b
c
e
L
A
P-SOP16-5.5x10.06-1.27 PRSP0016DH-B
*1
*2
E
81
16 9
xM
p
*3
y
F
Index mark
b
D
E
H
Z
A
Terminal cross section
( Ni/Pd/Au plating )
p
c
b
1
1
Detail F
L
L
A
θ
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
e
HD74LS193
Rev.2.00, Feb.18.2005, page 11 of 11
0.635
0.15
1.27
5.80 6.20
0.400.34
p
A
1
10.30
FP-16DNV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
1.75
1.270.600.40
3.95
0.250.140.10
0.46
0.250.200.15
6.10
8
°
0
°
0.25
1.08
9.90
0.15g
MASS[Typ.]
1
E
1
1
2
L
Z
H
y
x
θ
c
b
A
E
D
b
c
e
e
L
A
P-SOP16-3.95x9.9-1.27 PRSP0016DG-A
Index mark
E
1
y
xM
p
*3
*2
*1
F
8
916
E
H
D
A
Zb
Terminal cross section
( Ni/Pd/Au plating )
p
b
c
Detail F
1
1
L
L
A
θ
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
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may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits,
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