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PRELIMINARY DATA
December 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
Flash In-System Programmable (ISP) Peripherals
For 16-bit MCUs
FEATURES SUMMARY
PSD provides anintegrated solution to16-bitMCU
based applications that includes configurable
memories, PLD logic and I/O:
Dual Bank Flash Memories
8 Mbit of Primary Flash Memory (16 uniform
sectors, 32K x 16)
512 Kbit Secondary Flash Memory with 4
sectors
Concurrent operation: read from onememory
while erasing and writing the other
256 Kbit SRAM (Battery Backed)
PLD with Macrocells
Over3000 Gates of PLD: CPLD and DPLD
CPLD with 16 Output Macrocells (OMCs) and
24 Input Macrocells (IMCs)
DPLD user defined internal chip select de-
coding
Seven l/O Ports with 52 I/O pins
52 individually configurable I/O port pins that
can be used for the following functions:
MCU I/Os
PLD I/Os
Latched MCU address output
Special function l/Os
l/O ports may be configured as open-drain
outputs
In-System Programming (ISP) with JTAG
Built-in JTAG compliant serial port allows full-
chip In-System Programmability
Efficient manufacturing allow easy product
testing and programming
Use low cost FlashLINK cable with PC
Page Register
Internal page registerthat can be used to ex-
pand the microcontroller address space by a
factor of 256
Programmable power management
High Endurance:
100,000 Erase/Write Cycles of Flash Memory
1,000 EraseWrite Cycles of PLD
15 Year Data Retention
Single Supply Voltage
3V (+20%/–10%)
Memory Speed
100 ns Flash memory and SRAM access
time
Figure 1. Packages
TQFP80 (U)
PSD4256G6V
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TABLE OF CONTENTS
Summary Description . . . . . . . . . . . . . . . ...............................................7
In-System Programming (ISP) via JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............7
In-Application Programming(IAP). . . . . . . . . . . . . . . ..................................8
PSDsoft. . .....................................................................9
PSD Architectural Overview . . . . . . . . . . . . . ...........................................10
Memory. . . ...................................................................10
PLDs . . . . ....................................................................10
I/O Ports . . . . .................................................................10
MCU Bus Interface. . . ..........................................................10
ISP via JTAG Port . . . . . . . . . . . . . . . . . . ...........................................10
In-System Programming (ISP) . . . . . . . . . . . . . . .....................................10
In-Application Programming(IAP). . . . . . . . . . . . . . . .................................10
Page Register. . . . . . . . . . . . . . . . . . . ..............................................11
Power Management Unit (PMU) . . . . ..............................................11
Development System. . . . . . . . . . . . ..................................................12
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................................13
PSD Register Description and Address Offsets . .......................................16
Register Bit Definition . . . . . . .......................................................17
Detailed Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...................................22
Memory Blocks . ..............................................................22
Primary Flash Memory and Secondary Flash memory Description.....................23
Memory Block Select Signals. . ..................................................23
Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . ...........................................23
Memory Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............................23
Instructions . . . . . . . . . . . . . . . . . . . . ..............................................25
Power-up Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........26
READ . . . . . . . . . ..............................................................26
Read Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Read Primary Flash Identifier. . ..................................................26
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PSD4256G6V
Read Memory Sector Protection Status . . . . . . . ....................................26
Reading the Erase/Program Status Bits ...........................................26
Data Polling (DQ7) DQ15 for Motorola ...........................................27
Toggle Flag (DQ6) DQ14 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........27
Error Flag (DQ5) DQ13 for Motorola. . ...........................................27
Erase Time-out Flag (DQ3) DQ11 for Motorola ....................................27
Programming Flash Memory . . . . . . . . . . . . . . . . . . . ....................................28
Data Polling . . . . . . . . . . . . . . . . . . . . ..............................................28
Data Toggle . . ................................................................28
Unlock Bypass. . . . . . . . . . . . . . . . . . ..............................................29
Erasing Flash Memory. . . ..........................................................30
Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................30
Flash Sector Erase . . . . . . . . . . ..................................................30
Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................30
Resume Sector Erase ..........................................................30
Specific Features. . . . . . . . . . . . . . . ..................................................31
Flash Memory Sector Protect. . ..................................................31
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................31
Reset (RESET) Signal . . . . . . . . . . . . . . . . . . . . . .....................................31
SRAM . . . . . . ....................................................................32
MEMORY SELECT SIGNALS. . . . . . . . . . . . . . . . . . . . ....................................33
Example .....................................................................33
Memory Select Configuration for MCUs with Separate Program and Data Spaces . .......33
Configuration Modes for MCUs with Separate Program and Data Spaces . . . . . . . . . . . . . . . 33
Separate Space Modes. . . . . . . ..................................................33
Combined Space Modes. . . . . . . . . . . . . . . . . . . . ....................................34
80C51XA Memory Map Example . . . . . . . . . . . . . . ...................................34
Page Register. . . . . . ..............................................................35
Memory ID Registers . . . . . . . . . . . . ..................................................35
PLDs ...........................................................................36
PSD4256G6V
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The Turbo Bit in PSD. . . . . . . . . . . . . ..............................................36
Decode PLD (DPLD). . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................38
Complex PLD (CPLD) . . . . . . . . . . . ..................................................39
Output Macrocell (OMC) . . . . . . ..................................................40
Product Term Allocator. . . . . . . . . . . . . . ...........................................41
Loading and Reading the Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
The OMC Mask Register . . . . . . ..................................................42
The Output Enable of the OMC . . . . . . . . . . . . . . . . . .................................42
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................43
External Chip Select . . . . . . . . . ..................................................43
MCU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........45
PSD Interface to a Multiplexed Bus . . . . . . . . . . . . . . .................................45
PSD Interface to a Non-Multiplexed 8-Bit Bus . .....................................45
Data Byte Enable Reference. . . ..................................................47
MCU Bus Interface Examples. . ..................................................47
80C196 and 80C186. . . . . .......................................................48
MC683xx and MC68HC16 . . . . . . . . . . . . . . . . . . . ....................................49
80C51XA. ....................................................................50
H8/300. . . ....................................................................51
MMC2001 ....................................................................52
C16x Family . . . . . . . . . . . . . . . . ..................................................53
I/O Ports . . . . . ...................................................................55
General Port Architecture. . . . . . . . . . . . . . . . . . .....................................55
Port Operating Modes. . . . . . . . . . . . . . . ...........................................56
MCU I/O Mode . . . . . . . . . .......................................................56
PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................56
Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Address In Mode . . . . . . . . . . . . . . . . ..............................................58
Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................................58
Peripheral I/O Mode. . . . . .......................................................58
JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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PSD4256G6V
MCU Reset Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....58
Port Configuration Registers (PCR) . . . . . . . .......................................58
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................58
Direction Register . . . . . . . . . . . ..................................................59
Drive Select Register. . . . . . . . . . . . . . . . ...........................................59
Port Data Registers. . . . . . ......................................................60
Data In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Data Out Register . . . . . . . . . . . . . . . ..............................................60
Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Mask Macrocell Register. . . . . . . . . . . . . . . . . . . . ....................................60
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................60
Enable Out . . . . . . . . . . . . . . . . . . . . . ..............................................61
Ports A, B and C Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . ..............61
Port D Functionality and Structure. . . ...........................................62
Port E Functionality and Structure . . . ...........................................62
Port F Functionality and Structure . . . . . . . . . . ....................................63
Port G Functionality and Structure. . . . . . . .......................................63
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........64
Automatic Power-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . ...........65
Power-down Mode.............................................................65
Other Power Saving Options . . . . . . ..............................................66
PLD Power Management. . . . . . . . . . . . . ...........................................66
SRAM Stand-by Mode (Battery Backup) . . . . . . . ....................................66
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....66
Input Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............................66
Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . .................................67
Reset Timing and Device Status at Reset . . . . . . .......................................68
Power On Reset. . . . . . . . . . . . . ..................................................68
Warm Reset . . . . . . . . . . . . . . . . . . . . ..............................................68
I/O Pin, Register and PLD Status at Reset . . .......................................68
Reset of Flash Memory Erase and Program Cycles. .................................68
PSD4256G6V
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Programming In-Circuit using the JTAG Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Standard JTAG Signals. . . . . . . . . . . ..............................................69
JTAG Extensions. . . . . . . . . . . . . . . . ..............................................70
Security and Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........70
Initial Delivery State. . . . . . . . . . . . . ..................................................70
Maximum Rating . ................................................................74
DC and AC Parameters . . . . . . . . . . ..................................................75
Operating Conditions. . . . . .. . . . . . . . . . . . . . . . . . . . . .................................75
DC Characteristics. . . . . . . . . . . . . . . . . . . ...........................................77
CPLD Combinatorial Timing . . . . . . . . . . . . . . . . . . . ...................................78
CPLD Macrocell Synchronous Clock Mode Timing. ....................................78
CPLD Macrocell Asynchronous Clock Mode Timing. . . . . . . . . . . . . . ......................79
Input Macrocell Timing . . . .......................................................81
Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................82
Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................84
Port F Peripheral Data Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............86
Port F Peripheral Data Mode Write Timing . . . ........................................87
Power-down Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............................87
Reset (Reset) Timing. . . . . .......................................................88
VSTBYON Timing . . . . . . . . . . . . . . . ...............................................88
Program, Write and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
ISC Timing. . . . . . . . . . . . . .......................................................89
Package Mechanical . . . . . . . . . . . . . . . . ..............................................90
TQFP80 - 80 lead Plastic QuadFlatpack . . . . . . . .....................................90
Pin Assignments TQFP80 . . . . ..................................................91
Ordering Information Scheme . . . . . . . . . . . . . . . . . ....................................92
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PSD4256G6V
SUMMARY DESCRIPTION
The PSD family of memory systems for microcon-
trollers (MCUs)brings In-System-Programmability
(ISP) to Flash memory and programmable logic.
The result is a simple and flexible solution for em-
bedded designs. PSD devices combine many of
the peripheral functions found in MCU based ap-
plications.
PSD devices integrate anoptimized Macrocell log-
ic architecture. The Macrocell was created to ad-
dress the unique requirements of embedded
system designs. It allows direct connection be-
tween thesystem address/data bus, and the inter-
nal PSD registers, to simplify communication
between the MCU and other supporting devices.
Table 1. Pin Names
The PSD family offerstwo methods toprogram the
PSD Flash memory while the PSD is soldered to
the circuit board: In-System Programming (ISP)
via JTAG, and In-Application Programming (IAP).
In-System Programming (ISP) via JTAG
An IEEE 1149.1 compliant JTAG In-System Pro-
gramming (ISP) interface is included on the PSD
enabling the entire device (Flash memories, PLD,
configuration) to be rapidly programmed while sol-
dered to the circuit board. This requires no MCU
participation, which means the PSD can be pro-
grammed anytime, even when completely blank.
The innovative JTAG interface to Flashmemories
is an industry first, solving key problems faced by
designers and manufacturing houses, such as:
Figure 2. Logic Diagram
First time programming. How do I get firmware
into the Flash memory the very first time? JTAG is
the answer. Program the blank PSD with no MCU
involvement.
Inventory build-up of pre-programmed devic-
es. How do I maintain an accurate count of pre-
programmed Flash memory and PLD devices
based on customer demand? How manyand what
version? JTAG is the answer. Build your hardware
with blank PSDs soldered directly to the board and
then custom program just before they areshipped
to the customer. No more labels on chips, and no
more wasted inventory.
Expensive sockets. How do I eliminate the need
for expensive andunreliable sockets? JTAG is the
answer. Solder the PSD directly to the circuit
board. Program first time and subsequent times
with JTAG. No need to handle devices and bend
the fragile leads.
PA0-PA7 Port-A
PB0-PB7 Port-B
PC0-PC7 Port-C
PD0-PD3 Port-D
PE0-PE7 Port-E
PF0-PF7 Port-F
PG0-PG7 Port-G
AD0-AD15 Address/Data
CNTL0-CNTL2 Control
RESET Reset
VCC Supply Voltage
VSS Ground
AI04916
16
AD0-AD15
PF0-PF7
VCC
PSD4xxxGx
VSS
8
PG0-PG7
8
PB0-PB7
8
PA0-PA7
8
3
CNTL0-
CNTL2
RESET
PD0-PD3
4
PC0-PC7
8
PE0-PE7
8
PSD4256G6V
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Figure 3. TQFP Connections
In-Application Programming (IAP)
Two independentFlash memory arrays are includ-
ed so that the MCU can execute code from one
while erasing and programming the other. Robust
product firmware updates in the filed are possible
over any communication channel (CAN, Ethernet,
UART, J1850, etc) using this unique architecture.
Designers are relieved of these problems:
Simultaneous read and write to Flash memo-
ry. How can the MCU program the same memory
from which it executing code? It cannot. The PSD
allows the MCU to operate the two Flash memory
blocks concurrently, reading code from one while
erasing and programming the other during IAP.
Complex memory mapping. How can I map
these two memories efficiently? A programmable
Decode PLD (DPLD) is embedded in the PSD.
The concurrent PSD memories can be mapped
anywhere in MCU address space, segment by
segment with extermely high address resolution.
As an option, the secondary Flash memory can be
swapped out of the system memory map when
IAP is complete. A built-inpage register breaks the
MCU address limit.
Separate Program and Data space. How can I
write to Flash memory while it resides in Program
space during field firmware updates? My
80C51XA will not allow it. The PSD provides
means to reclassify Flash memory as Data space
during IAP, then back to Program space when
complete.
60 CNTL1
59 CNTL0
58
PA7
57
PA6
56
PA5
55
PA4
54
PA3
53
PA2
52
PA1
51
PA0
50
GND
49
GND
48
PC7
47
PC6
46
PC5
45
PC4
44
PC3
43
PC2
42
PC1
41 PC0
PD2
PD3
AD0
AD1
AD2
AD3
AD4
GND
VCC
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PD1
PD0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
GND
VCC
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
VCC
GND
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
RESET
CNTL2
AI04943
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PSD4256G6V
PSDsoft
PSDsoft, a software development tool from ST,
guides you through the design process step-by-
step making it possible to complete an embedded
MCU design capable of ISP/IAP in just hours. Se-
lect your MCU and PSDsoft takesyou through the
remainder of the design with point and click entry,
covering PSD selection, pin definitions, program-
mable logic inputs and outpus, MCU memory map
definition, ANSI-C code generation for your MCU,
and merging your MCU firmware with the PSD de-
sign. When complete, two different device pro-
grammers are supported directly from PSDsoft:
FlashLINK (JTAG) and PSDpro.
Figure 4. PSD Block Diagram
Note: Additional address lines can be brought in to the device via Port A, B, C, D or F.
PROG.
MCU BUS
INTRF.
ADIO
PORT
CNTL0,
CNTL1,
CNTL2
AD0 AD15
CLKIN
CLKIN
CLKIN
PLD
INPUT
BUS
PROG.
PORT
PORT
A
PROG.
PORT
PORT
B
POWER
MANGMT
UNIT
8 MBIT PRIMARY
FLASH MEMORY
16 SECTORS
VSTDBY
PA0 PA7
PB0 PB7
PROG.
PORT
PORT
C
PROG.
PORT
PORT
D
PC0 PC7
PD0 PD3
ADDRESS/DATA/CONTROL BUS
PORT A & B
8 EXT CS TO PORT C or F
24 INPUT MACROCELLS
PORT A ,B & C
82
82
512 KBIT SECONDARY
FLASH MEMORY
(BOOT OR DATA)
4 SECTORS
256 KBIT BATTERY
BACKUP SRAM
RUNTIME CONTROL
AND I/O REGISTERS
SRAM SELECT
PERIP I/O MODE SELECTS
MACROCELL FEEDBACK OR PORT INPUT
CSIOP
FLASH ISP CPLD
(CPLD) 16 OUTPUT MACROCELLS
FLASH DECODE
PLD (DPLD)
PLD, CONFIGURATION
& FLASH MEMORY
LOADER
JTAG
SERIAL
CHANNEL
(PE6)
PAGE
REGISTER EMBEDDED
ALGORITHM
SECTOR
SELECTS
SECTOR
SELECTS
GLOBAL
CONFIG. &
SECURITY
AI04917
8
PROG.
PORT
PORT
E
PE0 PE7
PORT F
PROG.
PORT
PORT
F
PF0 PF7
PROG.
PORT
PORT
G
PG0 PG7
PSD4256G6V
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PSD ARCHITECTURAL OVERVIEW
PSD devices contain several major functional
blocks. Figure4 showsthe architecture ofthe PSD
device family. The functions ofeach block are de-
scribed briefly in the following sections. Many of
the blocks perform multiple functions and are user
configurable.
Memory
Each of the memory blocks is briefly discussed in
the following paragraphs. A more detailed discus-
sion can be found in the section entitled “Memory
Blocks“ on page 22.
The 8 Mbit primary Flash memory is the main
memory of the PSD. It is divided into 16 equally-
sized sectors that are individually selectable.
The 512 Kbit secondary Flash memory is divided
into 4 sectors. Each sector is individually select-
able.
The 256 Kbit SRAM is intended for use as a
scratch-pad memory or as an extension to the
MCU SRAM. If an external battery isconnected to
the PSD’s Voltage Stand-by (VSTBY, PE6) signal,
data is retained in the event of power failure.
Each memory block can be located in a different
address space as defined by the user. The access
times for all memory types includes the address
latching and DPLD decoding time.
PLDs
The device contains two PLD blocks, the Decode
PLD (DPLD) and the Complex PLD (CPLD), as
shown in Table 2, each optimized for a different
function. The functional partitioning of the PLDs
reduces power consumption, optimizes cost/per-
formance, and eases design entry.
The DPLD is used to decode addresses and to
generate Sector Select signals for the PSD inter-
nal memory and registers. The DPLD has combi-
natorial outputs, while the CPLD can implement
more general user-defined logic functions. The
CPLD has 16 Output Macrocells (OMC) and 8
combinatorial outputs. The PSD also has 24 Input
Macrocells (IMC) that can be configured as inputs
to the PLDs. The PLDs receive their inputs from
the PLD Input Bus and are differentiated by their
output destinations, number of product terms, and
Macrocells.
The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
by the Turbo bit in PMMR0 and other bits in
PMMR2. These registers are set by the MCU at
run-time. There is aslight penalty to PLDpropaga-
tion time when not in the Turbo mode.
I/O Ports
The PSD has 52 I/O pins divided among seven
ports (Port A, B, C, D, E, F and G). Each I/O pin
can be individually configured for different func-
tions. Ports can be configured as standard MCU I/
O ports, PLD I/O, or latched address outputs for
MCUs using multiplexed address/data buses
The JTAG pins can be enabled on Port E for In-
System Programming (ISP).
Table 2. PLD I/O
MCU Bus Interface
The PSD easily interfaces easily with most 16-bit
MCUs, either with multiplexed or non-multiplexed
address/data buses. The device is configured to
respond to the MCU’s control pins, which are also
used as inputs to the PLDs.
ISP via JTAG Port
In-System Programming (ISP) can be performed
through the JTAG signals on Port E. Thisserial in-
terface allows complete programming of the entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT, TERR, TDI,TDO) can be multiplexed with
other functions on Port E. Table 3 indicates the
JTAG pin assignments.
In-System Programming (ISP)
Using the JTAG signals on Port E, the entire PSD
device (memory, logic, configuration) can be pro-
grammed or erased without the use of the MCU.
Table 3. JTAG SIgnals on Port E
In-Application Programming (IAP)
The primary Flash memory can also be pro-
grammed, or re-programmed, in-system by the
MCU executing the programmingalgorithms out of
the secondary Flash memory, or SRAM. The sec-
ondary Flash memory can be programmed the
same way by executing out of the primary Flash
memory. Table 4 indicates which programming
methods can program different functional blocks
of the PSD.
Name Inputs Outputs Product
Terms
Decode PLD (DPLD) 82 17 43
Complex PLD (CPLD) 82 24 150
Port E Pins JTAG Signal
PE0 TMS
PE1 TCK
PE2 TDI
PE3 TDO
PE4 TSTAT
PE5 TERR
11/94
PSD4256G6V
Page Register
The 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
address can be used as part ofthe address space
to access external memory and peripherals, or in-
ternal memory and I/O. The Page Register can
also be used to change the address mapping of
the Flash memory blocks into different memory
spaces for IAP.
Power Management Unit (PMU)
The Power Management Unit (PMU) gives the
user controlof the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The PSD also has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The Turbo bit in PMMR0 can be
reset to 0 and the CPLD latches its outputs and
goes to Stand-by mode until the next transition on
its inputs.
Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD to
reduce power consumption. See the section enti-
tled “Power Management”on page 64for more de-
tails.
Table 4. Methods of Programming Different Functional Blocks of the PSD
Functional Block JTAG-ISP Device Programmer IAP
Primary Flash Memory Yes Yes Yes
Secondary Flash memory Yes Yes Yes
PLD Array (DPLD and CPLD) Yes Yes No
PSD Configuration Yes Yes No
PSD4256G6V
12/94
DEVELOPMENT SYSTEM
The PSD family is supported by PSDsoft, a Win-
dows-based software development tool (Win-
dows-95, Windows-98, Windows-NT). A PSD
design is quicly and easily produced in a point and
click environment. The designer does not need to
enter Hardware Description Language (HDL)
equations, unless desired, to define PSD pin func-
tions and memory map information. The general
design flow is shown in Figure 5. PSDsoft is avail-
able from our web site (the address is given on the
back page of this data sheet) or other distribution
channels.
PSDsoft directly supports two low cost device pro-
grammers form ST: PSDpro and FlashLINK
(JTAG). Both of these programmers may be pur-
chased through your local distributor/representa-
tive, or directly from our web site using a credit
card. The PSD is also supported by thid party de-
vice programmers. See ourweb site for the current
list.
Figure 5. PSDsoft Development Tool
Merge MCU
Firmware
with PSD Configuration
PSD Programmer
*.OBJ FILE
PSDPro,
or
FlashLINK (JTAG)
A composite object file is created
containing MCU firmware
and
PSD configuration
C Code Generation
GENERATE C CODE
SPECIFIC TO PSD
FUNCTIONS
USER’S CHOICE
OF
MICROCONTROLLER
COMPILER/LINKER
*.OBJ
FILE
AVAILABLE
FOR 3rd PARTY
PROGRAMMERS
(CONVENTIONAL
or
JTAG-ISC)
MCU FIRMWARE
HEX OR S-RECORD
FORMAT
AI04919
Define General
Purpose
Logic in CPLD
Point and click definition of
combin-
atorial and registered logic in CPLD.
Access HDL is available if needed
Define PSD Pin
and
Node Functions
Point and click definition
of
PSD pin functions, internal
nodes,
and MCU system memory map
Choose MCU and PSD
Automatically configures MCU
bus interface and
other
PSD attributes
13/94
PSD4256G6V
PIN DESCRIPTION
Table 5 describes the signal names and signal
functions of the PSD. Those that have multiple
names or functions are defined using PSDsoft.
Table 5. Pin Description (for the TQFP package)
Pin Name Pin Type Description
ADIO0-
ADIO7 3-7
10-12 I/O
This is the lower Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
1. If your MCU has a multiplexedaddress/data bus where the data is multiplexed with
the lower address bits, connect AD0-AD7 to this port.
2. If your MCU does not have a multiplexed address/data bus, connect A0-A7 to this
port.
3. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this
port.
ALE or AS latches the address. The PSD drives data out only if the read signal is active
and one of the PSD functional blocks has been selected. The addresses on this port
are passed to the PLDs.
ADIO8-
ADIO15 13-20 I/O
This is the upper Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
1. If your MCU has a multiplexedaddress/data bus where the data is multiplexed with
the upper address bits, connect A8-A15 to this port.
2. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this
port.
3. Ifyou are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 tothis
port.
ALE or AS latches the address. The PSD drives data out only if the read signal is active
and one of the PSD functional blocks has been selected. The addresses on this port
are passed to the PLDs.
CNTL0 59 I
The following control signals can be connected to this pin, based on your MCU:
1. WR active Low, Write Strobe input.
2. R_W active High, read/active Low write input.
3. WRL active Low, Write to Low-byte.
This pin is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equations.
CNTL1 60 I
The following control signals can be connected to this pin, based on your MCU:
1. RD active Low, Read Strobe input.
2. E E clock input.
3. DS active Low, Data Strobe input.
4. LDS active Low, Strobe for low data byte.
This pin is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equations.
CNTL2 40 I
Read or other Control input pin, with multiple configurations. Depending on the MCU
interface selected, this pin can be:
1. PSEN Program Select Enable, active Low in code fetch bus cycle (80C51XA
mode).
2. BHE High-byte enable, 16-bit data bus.
3. UDS active Low, Strobe for high data byte, 16-bit data bus mode.
4. SIZ0 Byte enable input.
5. LSTRB Low Strobe input.
This pin is also connected to the PLDs.
Reset 39 I Active Low input. Resets I/O Ports, PLD Macrocells and some of the Configuration
Registers and JTAG registers. Must be Low at Power-up. Reset also aborts any Flash
memory Program or Erase cycle that is currently in progress.
PSD4256G6V
14/94
PA0-PA7 51-58
I/O
CMOS
or
Open
Drain
These pins make up Port A. These port pins are configurable and can have the
following functions:
1. MCU I/O standard output or input port.
2. CPLD Macrocell (McellA0-McellA7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
PB0-PB7 61-68
I/O
CMOS
or
Open
Drain
These pins make up Port B.These port pins are configurable and can have the
following functions:
1. MCU I/O standard output or input port.
2. CPLD Macrocell (McellB0-McellB7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
PC0-PC7 41-48 I/O
CMOS
These pins make up Port C. These port pins are configurable and can have the
following functions:
1. MCU I/O standard output or input port.
2. External Chip Select (ECS0-ECS7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
PD0 79
I/O
CMOS
or
Open
Drain
PD0 pin of Port D. This port pin can be configured to have the following functions:
1. ALE/AS input latches address on ADIO0-ADIO15.
2. AS input latches address on ADIO0-ADIO15 on the rising edge.
3. MCU I/O standard output or input port.
4. Transparent PLD input (can also be PLD input foraddress A16 and above).
PD1 80
I/O
CMOS
or
Open
Drain
PD1 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O standard output or input port.
2. Transparent PLD input (can also be PLD input foraddress A16 and above).
3. CLKIN clock input to the CPLD Macrocells, the APD Unit’sPower-down counter,
and the CPLD AND Array.
PD2 1
I/O
CMOS
or
Open
Drain
PD2 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O standard output or input port.
2. Transparent PLD input (can also be PLD input foraddress A16 and above).
3. PSD Chip Select Input (CSI). When Low,the MCU can access the PSD memory and
I/O. When High, the PSD memory blocks are disabled to conserve power. The falling
edge of this signal can be used to get the device out of Power-down mode.
PD3 2
I/O
CMOS
or
Open
Drain
PD3 pin of Port D.This port pin can be configured to have the following functions:
1. MCU I/O standard output or input port.
2. Transparent PLD input (can also be PLD input foraddress A16 and above).
3. WRH for 16-bit data bus, write to high byte, active low.
PE0 71
I/O
CMOS
or
Open
Drain
PE0 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O standard output or input port.
2. Latched address output.
3. TMS Input for the JTAGSerial Interface.
PE1 72
I/O
CMOS
or
Open
Drain
PE1 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O standard output or input port.
2. Latched address output.
3. TCK Input for the JTAG Serial Interface.
PE2 73
I/O
CMOS
or
Open
Drain
PE2 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O standard output or input port.
2. Latched address output.
3. TDI input for the JTAG Serial Interface.
Pin Name Pin Type Description
15/94
PSD4256G6V
PE3 74
I/O
CMOS
or
Open
Drain
PE3 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O standard output or input port.
2. Latched address output.
3. TDO output for the JTAG Serial Interface.
PE4 75
I/O
CMOS
or
Open
Drain
PE4 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O standard output or input port.
2. Latched address output.
3. TSTAToutput for the JTAG Serial Interface.
4. Ready/Busy output for parallel In-System Programming (ISP).
PE5 76
I/O
CMOS
or
Open
Drain
PE5 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O standard output or input port.
2. Latched address output.
3. TERR active Low output for the JTAGSerial Interface.
PE6 77
I/O
CMOS
or
Open
Drain
PE6 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O standard output or input port.
2. Latched address output.
3. VSTBY SRAM stand-by voltage input for SRAM battery backup.
PE7 78
I/O
CMOS
or
Open
Drain
PE7 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O standard output or input port.
2. Latched address output.
3. Battery-on Indicator (VBATON). Goes High when power is being drawn from the
external battery.
PF0-PF7 31-38
I/O
CMOS
or
Open
Drain
These pinsmake up Port F.These port pins are configurable and can havethe following
functions:
1. MCU I/O standard output or input port.
2. External Chip Select (ECS0-ECS7) outputs, or inputs to CPLD.
3. Latched address outputs.
4. Address A1-A3 inputs in 80C51XA mode (PF0 is grounded)
5. Data bus port (D0-D7) in a non-multiplexed bus configuration.
6. Peripheral I/O mode.
7. MCU reset mode.
PG0-PG7 21-28
I/O
CMOS
or
Open
Drain
These pins make up Port G. These port pins are configurable and can have the
following functions:
1. MCU I/O standard output or input port.
2. Latched address outputs.
3. Data bus port (D8-D15) in a non-multiplexed bus configuration.
4. MCU reset mode.
VCC 9, 29,
69 Supply Voltage
GND 8, 30,
49,
50, 70 Ground pins
Pin Name Pin Type Description
PSD4256G6V
16/94
PSD REGISTER DESCRIPTION AND ADDRESS OFFSETS
Table 6 shows the offset addresses to the PSD
registers relative to the CSIOP base address. The
CSIOP spaceis the 256bytes of address that is al-
located by the user to the internal PSD registers.
Table 6 provides brief descriptions of the registers
in CSIOP space. The following sections give a
more detailed description.
Table 6. Register Address Offset
Note: 1. Other registers that are not part of the I/O ports.
Register Name Port
APort
BPort
CPort
DPort
EPort
FPort
GOther1Description
Data In 00 01 10 11 30 40 41 Reads Port pin as input, MCU I/O input mode
Control 32 42 43 Selects mode between MCU I/O or Address
Out
DataOut 04051415344445 Stores data for output to Port pins, MCU I/O
output mode
Direction 06 07 16 17 36 46 47 Configures Port pin as input or output
Drive Select 08 09 19 38 49 Configures Port pins as either CMOS or
Open Drain
Input Macrocell 0A 0B 1A Reads Input Macrocells
Enable Out 0C 0D 1C 4C Reads the status of the output enable to the
I/O Port driver
Output
Macrocells A 20 Read reads output of Macrocells A
Write loads Macrocell Flip-flops
Output
Macrocells B 21 Read reads output of Macrocells B
Write loads Macrocell Flip-flops
Mask
Macrocells A 22 Blocks writing to the Output Macrocells A
Mask
Macrocells B 23 Blocks writing to the Output Macrocells B
Flash Memory
Protection 1 C0 Read only Primary Flash Sector Protection
Flash Memory
Protection 2 C1 Read only Primary Flash Sector Protection
Flash Boot
Protection C2 Read only PSD Security and Secondary
Flash memory Sector Protection
JTAG Enable C7 Enables JTAG Port
PMMR0 B0 Power Management Register 0
PMMR2 B4 Power Management Register 2
Page E0 Page Register
VM E2 Places PSD memory areas in Program and/
or Data space on an individual basis.
Memory_ID0 F0 Read only SRAM and Primary memory
size
Memory_ID1 F1 Read only Secondary memory type and
size
17/94
PSD4256G6V
REGISTER BIT DEFINITION
All the registers of the PSD are included here, for
reference. Detailed descriptions of these registers
can be found in the following sections.
Table 7. Data-In Registers Ports A, B, C, D, E, F, G
Note: Bit Definitions(Read-only registers):
Read Port pin status when Port is in MCU I/O inputmode.
Table 8. Data-Out Registers Ports A, B, C, D, E, F, G
Note: Bit Definitions:
Latched data for output to Port pin when pin is configured in MCU I/Ooutput mode.
Table 9. Direction Registers Ports A, B, C, D, E, F, G
Note: Bit Definitions:
Port pin <i> 0 = Port pin <i> isconfigured in Input mode (default).
Port pin <i> 1 = Port pin <i> isconfigured in Output mode.
Table 10. Control Registers Ports E, F, G
Note: Bit Definitions:
Port pin <i> 0 = Port pin <i> isconfigured in MCU I/O mode (default).
Port pin <i> 1 = Port pin <i> isconfigured in Latched Address Out mode.
Table 11. Drive Registers Ports A, B, D, E, G
Note: Bit Definitions:
Port pin <i> 0 = Port pin <i> isconfigured for CMOS Output driver (default).
Port pin <i> 1 = Port pin <i> isconfigured for Open Drain output driver.
Table 12. Enable-Out Registers Ports A, B, C, F
Note: Bit Definitions(Read-only registers):
Port pin <i> 0 = Port pin <i> isin tri-state driver (default).
Port pin <i> 1 = Port pin <i> isenabled.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
PSD4256G6V
18/94
Table 13. Input Macrocells Ports A, B, C
Note: Bit Definitions(Read-only registers):
Read Input Macrocell (IMC7-IMC0) status on Ports A, B and C.
Table 14. Output Macrocells A Register
Note: Bit Definitions:
Write Register: Load MCellA7-MCellA0 with 0 or 1.
Read Register: Read MCellA7-MCellA0output status.
Table 15. Output Macrocells B Register
Note: Bit Definitions:
Write Register: Load MCellB7-MCellB0 with 0 or 1.
Read Register: Read MCellB7-MCellB0output status.
Table 16. Mask Macrocells A Register
Note: Bit Definitions:
McellA<i>_Prot 0 = Allow MCellA<i> flip-flop to be loaded by MCU (default).
McellA<i>_Prot 1 = Prevent MCellA<i> flip-flop from being loaded by MCU.
Table 17. Mask Macrocells B Register
Note: Bit Definitions:
McellB<i>_Prot 0 = Allow MCellB<i> flip-flop to be loaded by MCU (default).
McellB<i>_Prot 1 = Prevent MCellB<i> flip-flop from being loaded by MCU.
Table 18. Flash Memory Protection Register 1
Note: Bit Definitions(Read-only register):
Sec<i>_Prot 1 = Primary Flash memory Sector <i> is write protected.
Sec<i>_Prot 0 = Primary Flash memory Sector <i> is not write protected.
Table 19. Flash Memory Protection Register 2
Note: Bit Definitions(Read-only register):
Sec<i>_Prot 1 = Primary Flash memory Sector <i> is write protected.
Sec<i>_Prot 0 = Primary Flash memory Sector <i> is not write protected.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IMcell 7 IMcell 6 IMcell 5 IMcell 4 IMcell 3 IMcell 2 IMcell 1 IMcell 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mcella 7 Mcella 6 Mcella 5 Mcella 4 Mcella 3 Mcella 2 Mcella 1 Mcella 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mcellb 7 Mcellb 6 Mcellb 5 Mcellb 4 Mcellb 3 Mcellb 2 Mcellb 1 Mcellb 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mcella 7 Mcella 6 Mcella 5 Mcella 4 Mcella 3 Mcella 2 Mcella 1 Mcella 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mcellb 7 Mcellb 6 Mcellb 5 Mcellb 4 Mcellb 3 Mcellb 2 Mcellb 1 Mcellb 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Sec15_Prot Sec14_Prot Sec13_Prot Sec12_Prot Sec11_Prot Sec10_Prot Sec9_Prot Sec8_Prot
19/94
PSD4256G6V
Table 20. Flash Boot Protection Register
Note: Bit Definitions:
Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write protected.
Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write protected.
Security_Bit 0 = Security Bit in device has not been set.
Security_Bit 1 = Security Bit in device has been set.
Table 21. JTAG Enable Register
Note: Bit Definitions:
JTAGEnable 1 = JTAG Port is enabled.
JTAGEnable 0 = JTAG Port is disabled.
Table 22. Page Register
Note: Bit Definitions:
Configure Page input to PLD. Default is PGR7-PGR0=0.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Security_Bit not used not used not used Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
not used not used not used not used not used not used not used JTAGEnable
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PGR 7 PGR 6 PGR 5 PGR 4 PGR 3 PGR 2 PGR 1 PGR 0
PSD4256G6V
20/94
Table 23. PMMR0 Register
Note: The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset) pulses do not clear the registers.
Note: Bit Definitions:
APD Enable 0 = Automatic Power-down (APD) is disabled.
1 = Automatic Power-down (APD) is enabled.
PLD Turbo 0 = PLD Turbo ison.
1 = PLD Turbo isoff, saving power.
PLD Array CLK 0 = CLKIN to the PLDAND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off.
1 = CLKIN to the PLDAND array is disconnected, saving power.
PLD MCells CLK 0 = CLKIN to the PLDMacrocells is connected.
1 = CLKIN to the PLD Macrocells is disconnected, saving power.
Table 24. PMMR2 Register
Note: For Bit 4, Bit 3, Bit 2: See Table 34 for the signals that are blocked on pins CNTL0-CNTL2.
Note: Bit Definitions:
PLD Array Addr 0 = Address A7-A0 are connected to the PLD array.
1 = Address A7-A0 are blocked from the PLD array, saving power.
(Note: inXA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4)
PLD Array CNTL20 = CNTL2 input to the PLD AND array is connected.
1 = CNTL2 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL10 = CNTL1 input to the PLD AND array is connected.
1 = CNTL1 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL00 = CNTL0 input to the PLD AND array is connected.
1 = CNTL0 input to the PLD AND array is disconnected, saving power.
PLD Array ALE 0 = ALE input to the PLD AND array is connected.
1 = ALE input to the PLD AND array is disconnected, saving power.
PLD Array WRH 0 = WRH/DBE input to the PLD AND array is connected.
1 = WRH/DBE input to the PLD AND array is disconnected, saving power.
Table 25. VM Register
Note: On reset, Bit1-Bit4are loaded to configurations that are selected by the user in PSDsoft. Bit0 and Bit7 are always cleared on reset.
Bit0-Bit4are active only when the device is configured in Philips 80C51XA mode.
Note: Bit Definitions:
SR_code 0 = PSEN cannot access SRAM in 80C51XA modes.
1 = PSEN can access SRAM in 80C51XA modes.
Boot_code 0 = PSEN cannot access Secondary NVM in 80C51XA modes.
1 = PSEN can access Secondary NVM in 80C51XA modes.
FL_code 0 = PSEN cannot access Primary Flash memory in 80C51XA modes.
1 = PSEN can access Primary Flash memory in 80C51XA modes.
Boot_data 0 = RD cannot access Secondary NVM in 80C51XA modes.
1 = RD can access Secondary NVM in 80C51XA modes.
FL_data 0 = RD cannot access Primary Flash memory in 80C51XA modes.
1 = RD can access Primary Flash memory in 80C51XA modes.
Peripheral mode 0 = Peripheral mode of Port F is disabled.
1 = Peripheral mode of Port F is enabled.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
not used
(set to 0) not used
(set to 0) PLD
MCells CLK PLD
Array CLK PLD
Turbo not used
(set to 0) APD
Enable not used
(set to 0)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
not used
(set to 0) PLD
Array WRH PLD
Array ALE PLD Array
CNTL2 PLD Array
CNTL1 PLD Array
CNTL0 not used
(set to 0) PLD
Array Addr
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Peripheral
mode not used
(set to 0) not used
(set to 0) FL_data Boot_data FL_code Boot_code SR_code
21/94
PSD4256G6V
Table 26. Memory_ID0 Register
Note: Bit Definitions:
F_size[3:0] 0h = There is no Primary Flash memory
1h = Primary Flash memory size is 256 Kbit
2h = Primary Flash memory size is 512 Kbit
3h = Primary Flash memory size is 1Mbit
4h = Primary Flash memory size is 2Mbit
5h = Primary Flash memory size is 4Mbit
6h = Primary Flash memory size is 8 Mbit
S_size[3:0] 0h = There is no SRAM
1h = SRAM size is 16 Kbit
2h = SRAM size is 32 Kbit
3h = SRAM size is 64 Kbit
4h = SRAM size is 128 Kbit
5h = SRAM size is 256 Kbit
Table 27. Memory_ID1 Register
Note: Bit Definitions:
B_size[3:0] 0h = There is no Secondary NVM
1h = Secondary NVM size is 128 Kbit
2h = Secondary NVM size is 256 Kbit
3h = Secondary NVM size is 512 Kbit
B_type[1:0] 0h = Secondary NVM is Flash memory
1h = Secondary NVM is EEPROM
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
S_size 3 S_size 2 S_size 1 S_size 0 F_size 3 F_size 2 F_size 1 F_size 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
not used
(set to 0) not used
(set to 0) B_type 1 B_type 0 B_size 3 B_size 2 B_size 1 B_size 0
PSD4256G6V
22/94
DETAILED OPERATION
As shown in Figure 4, the PSD consists of six ma-
jor types of functional blocks:
Memory Blocks
PLD Blocks
MCU Bus Interface
I/O Ports
Power Management Unit (PMU)
JTAG-ISP Interface
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
Memory Blocks
The PSD has the following memory blocks:
Primary Flash memory
Secondary Flash memory
SRAM
The Memory Select signals for these blocks origi-
nate from the Decode PLD (DPLD) and are user-
defined in PSDsoft.
Table 28 sumamarizes the sizes and organisa-
tions of the memory blocks.
Table 28. Memory Block Size and Organization
Primary Flash Memory Secondary Flash Memory SRAM
Sector
Number Sector Size
(x16) Sector Select
Signal Sector Size
(x16) Sector Select
Signal SRAM Size
(x16) SRAM Select
Signal
0 32K FS0 8K CSBOOT0 16K RS0
1 32K FS1 4K CSBOOT1
2 32K FS2 4K CSBOOT2
3 32K FS3 16K CSBOOT3
4 32K FS4
5 32K FS5
6 32K FS6
7 32K FS7
8 32K FS8
9 32K FS9
10 32K FS10
11 32K FS11
12 32K FS12
13 32K FS13
14 32K FS14
15 32K FS15
Totals 1024KByte 16 Sectors 64KByte 4 Sectors 32KByte
23/94
PSD4256G6V
Primary Flash Memory and Secondary Flash
memory Description
The primary Flash memory is divided evenly into
16 sectors. The secondary Flash memory is divid-
ed into 4 sectors of different size. Each sector of
either memory block can be separately protected
from Program and Erase cycles.
Flash memory may be erased on a sector-by-sec-
tor basis, and programmed word-by-word. Flash
sector erasure may be suspended while data is
read from other sectors of the block and then re-
sumed after reading.
During a Program or Erase cycle inFlash memory,
the status can be output on the Ready/Busy pin
(PE4). This pin is set up using PSDsoft.
Memory Block Select Signals
The DPLD generates the Select signals for all the
internal memory blocks (see the section entitled
“PLDs”, on page 36).Each ofthe sectors of the pri-
mary Flash memory has a Select signal (FS0-
FS15) which can contain up to three product
terms. Each of the sectors of the secondary Flash
memory has a Select signal (CSBOOT0-
CSBOOT3) which can contain up to three product
terms. Having three product terms for each Select
signal allows agiven sector to be mapped in differ-
ent areas of system memory. When using a MCU
with separate Program and Data space
(80C51XA), these flexible Select signals allow dy-
namic re-mapping of sectors from one memory
space to the other before and after IAP. The
SRAM block has a single Select signal (RS0).
Ready/Busy (PE4)
This signal can be used to output the Ready/Busy
status of the PSD. The output is a 0 (Busy) when
a Flash memory block is being written to,
or
when
a Flash memory block is being erased. The output
is a 1 (Ready) when no Write or Erase cycle is in
progress.
Memory Operation
The primary Flash memory and secondary Flash
memory are addressed through the MCU Bus In-
terface. The MCU can access these memories in
one of two ways:
The MCU can execute a typical bus Write or
Read
operation
just as it would if accessing a
RAM or ROMdevice using standard bus cycles.
The MCU canexecute a specificinstruction that
consists of several Write and Read operations.
This involves writing specific data patterns to
special addresses within the Flash memory to
invoke an embedded algorithm. These
instructions are summarized in Table 29.
Typically, the MCU can read Flash memory using
Read operations, just as it would read a ROM de-
vice. However, Flash memory can only be erased
and programmed using specific instructions. For
example, the MCU cannot write a single byte di-
rectly to Flash memory as one wouldwrite a byte
to RAM. To program a word into Flash memory,
the MCUmust execute aProgram instruction,then
test the status of the Programming event. This sta-
tus test is achieved by a Readoperation or polling
Ready/Busy (PE4).
Flash memory can also be read by using special
instructions to retrieve particular Flash device in-
formation (sector protect status and ID).
PSD4256G6V
24/94
Table 29. Instructions
Note: 1. All bus cycles are write bus cycles, except the ones with the “Read” label
2. All values are in hexadecimal:
X = Don’t Care. Addresses of the form XXXXh,in this table, must be even addresses
RA = Address of the memory location to be read
RD = Data read from location RA during the Read cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0).
PA is an even address for PSD in word programming mode.
PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS15 or CSBOOT0-CSBOOT3) of the sector tobe
erased, or verified, must be Active (High).
3. Sector Select (FS0 to FS15 or CSBOOT0 to CSBOOT3)signals are active High, and are defined in PSDsoft.
4. Only address bits A11-A0 are used in instruction decoding.
5. No Unlock or instruction cycles arerequired when the device is in the Read mode
6. The Reset instruction isrequired toreturn to theRead mode afterreading the Flash ID,orafter reading theSector Protection Status,
or if the Error Flag (DQ5/DQ13) bit goes High.
7. Additional sectors to be erased must be written at the endof the Sector Erase instruction within 80 µs.
8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
(A1,A0)=(1,0)
9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass
mode.
11. The system may perform Read and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status
when in theSuspend Sector Erasemode. The Suspend Sector Erase instruction is valid only during aSector Erase cycle.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is
intended. TheMCU must fetch, for example, thecode from the secondary Flashmemory when reading the Sector Protection Status
of the primary Flash memory.
14. All writebus cycles in an instruction arebyte writetoan even address (XA4Ah or X554h). AFlash memoryProgram buscycle writes
a word to an even address.
Instruction14 FS0-FS15 or
CSBOOT0-
CSBOOT3 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7
Read51“Read”
RD @ RA
Read Main Flash ID61AAh@
XAAAh 55h@
X554h 90h@
XAAAh Read ID
@ XX02h
Read Sector
Protection6,8,13 1AAh@
XAAAh 55h@
X554h 90h@
XAAAh
Read 00h
or 01h @
XX04h
Program a Flash
Word13 1AAh@
XAAAh 55h@
X554h A0h@
XAAAh PD@ PA
Flash Sector Erase7,13 1AAh@
XAAAh 55h@
X554h 80h@
XAAAh AAh@
XAAAh 55h@
X554h 30h@
SA 30h7@
next SA
Flash Bulk Erase13 1AAh@
XAAAh 55h@
X554h 80h@
XAAAh AAh@
XAAAh 55h@
X554h 10h@
XAAAh
Suspend Sector
Erase11 1B0h@
XXXXh
Resume Sector
Erase12 130h@
XXXXh
Reset61F0h@
XXXXh
Unlock Bypass 1 AAh@
XAAAh 55h@
X554h 20h@
XAAAh
Unlock Bypass
Program91A0h@
XXXXh PD@ PA
Unlock Bypass
Reset10 190h@
XXXXh 00h@
XXXXh
25/94
PSD4256G6V
INSTRUCTIONS
An instruction consists of a sequence of specific
operations. Each received byte is sequentially de-
coded by the PSD and not executed as a standard
Write operation. The instruction is executed when
the correct number of bytes are properly received
and the time between two consecutive bytes is
shorter than the time-out period. Some instruc-
tions are structured to include Read operations af-
ter the initial Write operations.
The instruction must be followed exactly. Any in-
valid combination of instruction bytes or time-out
between two consecutive bytes while addressing
Flash memory resets the device logic into Read
mode (Flash memory is read like a ROM device).
The PSD supports the instructions summarized in
Table 29:
Erase memory by chip or sector
Suspend or resume sector erase
Program a Word
Reset toRead mode
Read primary Flash Identifier value
Read Sector Protection Status
Bypass
These instructionsare detailed inTable 29.For ef-
ficient decoding of the instructions, the first two
bytes of an instruction are the coded cycles and
are followed by an instruction byte or confirmation
byte. The coded cycles consist of writing the data
AAh to address XAAAh during the first cycle and
data 55h to address X554h during the second cy-
cle (unless theBypass instruction feature is used,
as described later). Address signals A15-A12 are
Don’t Care during the instruction Write cycles.
However, the appropriate Sector Select signal
(FS0-FS15, or CSBOOT0-CSBOOT3) must be
selected.
The primary and secondary Flash memories have
the same instruction set (except for Read Primary
Flash Identifier). The Sector Select signals deter-
mine which Flash memory is to receive and exe-
cute the instruction. The primary Flash memory is
selected if any one of its Sector Select signals
(FS0-FS15) is High, and the secondary Flash
memory is selected if any one of its Sector Select
signals (CSBOOT0-CSBOOT3) is High.
PSD4256G6V
26/94
Power-up Condition
The PSD internal logic is reset upon Power-up to
the Read mode. Sector Select (FS0-FS15 and
CSBOOT0-CSBOOT3) must be held Low, and
Write Strobe (WR/WRL, CNTL0) High, during
Power-up for maximum security of the data con-
tents and to remove the possibility of data being
written on the first edge of Write Strobe (WR/WRL,
CNTL0). Any Write cycle initiation is locked when
VCC is below VLKO.
READ
Under typical conditions, the MCU may read the
primary Flash memory, or secondary Flash mem-
ory, using Read operationsjust as it would a ROM
or RAM device. Alternately, the MCU may use
Read operations to obtain status information
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these memory blocks. The
following sections describe these Read functions.
Read Memory Contents
Primary Flash memory and secondary Flash
memory areplaced in the Readmode afterPower-
up, chip reset, or a Reset Flash instruction (see
Table 29). The MCU can read the memory con-
tents of the primary Flash memory,or the second-
ary Flash memory by using Read operations any
time the Read operation is not part of an instruc-
tion.
Read Primary Flash Identifier
The primary Flash memory identifier is read with
an instructioncomposed of 4operations: 3specific
Write operations and a Read operation (see Table
29). The identifier for theprimary Flash memory is
E9h. The secondary Flash memory does not sup-
port this instruction.
Read Memory Sector Protection Status
The Flash memory Sector Protection Status is
read with an instruction composed of four opera-
tions: three specific Write operations and a Read
operation (see Table 29). The Read operation pro-
duces 01h ifthe Flash memory sector isprotected,
or 00h if the sector is not protected.
The sector protection status for all NVM blocks
(primary Flash memory, or secondary Flash mem-
ory) can be read by the MCU accessing the Flash
Protection and Flash Boot Protection registers in
PSD I/O space. See the section entitled “Flash
Memory Sector Protect”, on page 31, for register
definitions.
Reading the Erase/Program Status Bits
The PSD provides several status bits to be used
by theMCU to confirm the completion of an Erase
or Program cycle of Flash memory. These status
bits minimize the time that the MCU spends per-
forming these tasks and are defined in Table 30.
The status byte resides in an even location, and
can be read as many times as needed. Also note
that DQ15-DQ8 is an even byte for Motorola
MCUs with a 16-bit data bus.
For Flash memory, the MCU can perform a Read
operation to obtain these status bits while an
Erase or Program instruction is being executed by
the embedded algorithm. See the section entitled
“Programming Flash Memory”, onpage 28, for de-
tails.
Table 30. Status Bits
Table 31. Status Bits for Motorola
Note: 1. X = Not guaranteed value, can be read either 1 or 0.
2. DQ15-DQ0 represent the Data Bus bits, D15-D0.
3. FS0-FS15/CSBOOT0-CSBOOT3 are active High.
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Data Polling Toggle Flag Error Flag X Erase Time-
out XXX
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8
Data Polling Toggle Flag Error Flag X Erase Time-
out XXX
27/94
PSD4256G6V
Data Polling (DQ7) DQ15 for Motorola
When erasing or programming in Flash memory,
the Data Polling (DQ7/DQ15) bit outputs the com-
plement ofthe bit being entered for programming/
writing on the DQ7/DQ15 bit. Once the Program
instruction or the Write operation is completed, the
true logic value is read on the Data Polling (DQ7/
DQ15) bit (in a Read operation).
Data Polling is effective after the fourth Write
pulse (for a Program instruction) or after the
sixth Write pulse (for an Erase instruction). It
must be performed at the address being
programmed or at an address within the Flash
memory sector being erased.
During an Erase cycle, the Data Polling (DQ7/
DQ15) bit outputs a 0. After completion of the
cycle, the Data Polling (DQ7/DQ15) bit outputs
the last bit programmed(it is a 1 after erasing).
If the location to be programmed is in a
protected Flash memory sector, the instruction
is ignored.
If all the Flash memory sectors to be erased are
protected, the Data Polling (DQ7/DQ15) bit is
reset to 0 for about 100 µs, and then returns to
the value from the previously addressed
location. No erasure is performed.
Toggle Flag (DQ6) DQ14 for Motorola
The PSD offers another way for determining when
the Flash memory Program cycle is completed.
During the internal Write operation and when ei-
ther FS0-FS15 or CSBOOT0-CSBOOT3 is true,
the Toggle Flag (DQ6/DQ14) bit toggles from 0 to
1 and 1 to 0 on subsequent attempts to read any
word of the memory.
When the internal cycle is complete, the toggling
stops and the data read on the Data Bus D0-D7 is
the value from the addressed memory location.
The device is now accessible for a new Read or
Write operation. The cycle is finished when two
successive Reads yield the same output data.
The Toggle Flag (DQ6/DQ14) bit is effective
after the fourth Write pulse (for a Program
instruction) or after the sixth Write pulse (for an
Erase instruction).
If the location to be programmed belongs to a
protected Flash memory sector, the instruction
is ignored.
If all the Flash memory sectors selected for
erasure are protected, the Toggle Flag (DQ6/
DQ14) bit togglesto 0 forabout 100 µsand then
returns to the value from the previously
addressed location.
Error Flag (DQ5) DQ13 for Motorola
During a normal Program or Erase cycle, the Error
Flag (DQ5/DQ13)bit is reset to 0. This bit is setto
1 when there is a failure during a Flash memory
Program, Sector Erase, or Bulk Erase cycle.
In thecase of Flash memoryprogramming, the Er-
ror Flag (DQ5/DQ13) bit indicates the attempt to
program a Flash memory bit, or bits, from the pro-
grammed state, 0, to the erased state, 1, which is
not a valid operation. The Error Flag (DQ5/DQ13)
bit mayalso indicate aTime-out condition whileat-
tempting to program a word.
In caseof an error ina Flash memory Sector Erase
or Word Program cycle, the Flash memory sector
in which the error occurred or to which the pro-
grammed location belongs must no longer be
used. Other Flash memory sectors may still be
used. The Error Flag (DQ5/DQ13) bit is reset after
a Reset instruction. A Reset instruction is required
after detecting an error on the Error Flag (DQ5/
DQ13) bit.
Erase Time-out Flag (DQ3) DQ11for Motorola
The Erase Time-out Flag (DQ3/DQ11) bit reflects
the time-out period allowed between two consecu-
tive Sector Eraseinstructions. The Erase Time-out
Flag (DQ3/DQ11) bit is reset to 0 after a Sector
Erasecycle fora period of 100 µs + 20%unless an
additional Sector Erase instruction is decoded.Af-
terthis period, or whenthe additional Sector Erase
instruction is decoded, the Erase Time-out Flag
(DQ3/DQ11) bit is set to 1.
PSD4256G6V
28/94
PROGRAMMING FLASH MEMORY
Flash memory must be erased prior to being pro-
grammed. The MCU may erase Flash memory all
at onceor by-sector. Although erasingFlash mem-
ory occurs on a sector or device basis, program-
ming Flash memory occurs on a word basis.
The primary and secondary Flash memories re-
quire the MCU to send an instruction to program a
word or to erase sectors (see Table 29).
Once theMCU issues a Flash memoryProgram or
Erase instruction, it must check the status bits for
completion. Theembedded algorithms that are in-
voked inside the PSD support several means to
provide status to the MCU. Status may be checked
using any of three methods: Data Polling, Data
Toggle, or Ready/Busy (PE4) signal.
Data Polling
Polling on the Data Polling (DQ7/DQ15) bit is a
method of checking whether a Program or Erase
cycle is in progress or has completed. Figure 6
shows the Data Polling algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the word to be pro-
grammed in Flash memory to check the status.
The Data Polling (DQ7/DQ15) bit becomes the
complement of thecorresponding bit of the original
data word to be programmed. The MCU continues
to poll this location, comparing data and monitor-
ing the Error Flag (DQ5/DQ13) bit. When the Data
Polling (DQ7/DQ15) bit matches the correspond-
ing bit of the original data, and the Error Flag
(DQ5/DQ13) bit remains 0, the embedded algo-
rithm is complete. If the Error Flag(DQ5/DQ13) bit
is 1, the MCU should test the Data Polling (DQ7/
DQ15) bit again since the Data Polling (DQ7/
DQ15) bit may have changed simultaneously with
the Error Flag (DQ5/DQ13) bit (see Figure 6).
The Error Flag (DQ5/DQ13)bit is set if either an in-
ternal time-out occurred while theembedded algo-
rithm attempted to program the location or if the
MCU attemptedto programa 1 toabitthatwasnot
erased (not erased is logic 0).
It issuggested (as withall Flash memories)to read
the location again after the embedded program-
ming algorithm has completed, to compare the
word thatwas written tothe Flash memory with the
word that was intended to be written.
When using the Data Polling method during an
Erase cycle, Figure 6 still applies. However, the
Data Polling (DQ7/DQ15) bit is 0 until the Erase
cycle is complete. A 1 on the Error Flag (DQ5/
DQ13) bit indicates a time-out condition on the
Erase cycle, a 0 indicates no error. The MCU can
read any even location within the sector being
erased toget the Data Polling (DQ7/DQ15)bit and
the Error Flag (DQ5/DQ13) bit.
PSDsoft generates ANSI C code functions that im-
plement these Data Polling algorithms.
Figure 6. Data Polling Flowchart
Data Toggle
Checking the Toggle Flag (DQ6/DQ14) bit is an-
other method ofdetermining whetheraProgramor
Erase cycle is in progress or has completed. Fig-
ure 7 shows the Data Toggle algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads thelocation to beprogrammed in
Flash memory to check the status. The Toggle
Flag (DQ6/DQ14) bit toggles each time the MCU
reads this locationuntil the embedded algorithm is
complete. The MCU continues to read this loca-
tion, checking the Toggle Flag (DQ6/DQ14) bit
READ DQ5 and
DQ7
(DQ13 and
DQ15)
at Valid Even Address
START
READ
DQ7
(DQ15)
Program
or
Erase
Cycle failed
Program
or
Erase
Cycle is
complete
AI04920
Yes
No
Yes
No
DQ5
(DQ13)
=1
DQ7
(DQ15)
=
Data7
(Data15)
Yes
No
Issue RESET
instruction
DQ7
(DQ15)
=
Data7
(Data15)
29/94
PSD4256G6V
and monitoring the Error Flag (DQ5/DQ13) bit.
When the Toggle Flag (DQ6/DQ14) bit stops tog-
gling (two consecutive reads yield the same val-
ue), and the Error Flag (DQ5/DQ13) bit remains 0,
the embedded algorithm is complete. If the Error
Flag (DQ5/DQ13) bit is 1, the MCU should test the
Toggle Flag (DQ6/DQ14) bit again, since the Tog-
gle Flag (DQ6/DQ14)bit may have changed simul-
taneously with the Error Flag (DQ5/DQ13) bit (see
Figure 7).
Figure 7. Data Toggle Flowchart
TheError Flag (DQ5/DQ13) bit is set ifeither an in-
ternal time-outoccurred while the embedded algo-
rithm attempted to program, or if the MCU
attempted to program a 1 to a bit that was not
erased (not erased is logic 0).
It is suggested (aswith all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
word that was written to Flash memory with the
word that was intended to be written.
When using the Data Toggle method after an
Erase cycle, Figure 7 still applies. the Toggle Flag
(DQ6/DQ14) bit toggles until the Erase cycle is
complete.A 1 onthe Error Flag (DQ5/DQ13)bit in-
dicates a time-out condition on the Erase cycle, a
0 indicates no error. The MCU can read any even
location within the sector being erased to get the
Toggle Flag (DQ6/DQ14) bit and the Error Flag
(DQ5/DQ13) bit.
PSDsoft generates ANSI C code functions which
implement these Data Toggling algorithms.
Unlock Bypass
The Unlock Bypass instruction allows the system
to program words to the Flash memories faster
than using the standard Program instruction. The
Unlock Bypass mode is entered by first initiating
two Unlock cycles. Thisis followed by a third Write
cycle containing the Unlock Bypass command,
20h (as shown in Table 29). The Flash memory
then enters the Unlock Bypass mode.
A two-cycle Unlock Bypass Program instruction is
all that is required to program in this mode. The
first cycle in this instruction contains the Unlock
Bypass Program command, A0h. The second cy-
cle contains the program address and data. Addi-
tional data is programmed in the same manner.
This mode dispense with the initial two Unlock cy-
cles required in the standard Program instruction,
resulting in faster total programming time.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset in-
structions are valid.
To exit the Unlock Bypass mode, the system must
issue the two-cycle Unlock Bypass Reset instruc-
tion. The first cycle must contain the data 90h; the
second cycle the data 00h. Addresses are Don’t
Care for both cycles. The Flash memory then re-
turns to Read mode.
START
READ
DQ6
(DQ14)
AI04921
No
No
Yes
Yes
No
Yes
Program
or
Erase
Cycle failed
Program
or
Erase
Cycle is
complete
Issue RESET
instruction
READ DQ5 and
DQ6
(DQ13 and
DQ14)
at Valid Even Address
DQ5
(DQ13)
=1
DQ6
(DQ14)
=
Toggle
DQ6
(DQ14)
=
Toggle
PSD4256G6V
30/94
ERASING FLASH MEMORY
Flash Bulk Erase
The Flash Bulk Erase instruction uses six Write
operations followed by a Read operation of the
status register, as described in Table 29. If any
byte of the Bulk Erase instruction is wrong, the
Bulk Erase instruction aborts and the device is re-
set to the Read Memory mode.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag (DQ5/DQ13)
bit, the Toggle Flag (DQ6/DQ14) bit, and the Data
Polling (DQ7/DQ15) bit, as detailed in the section
entitled “Programming Flash Memory”, on page
28. The Error Flag (DQ5/DQ13) bit returnsa1if
there has been an Erase Failure (maximum num-
ber of Erase cycles have been executed).
It is not necessary to program the memory with
00h because the PSD automatically does this be-
fore erasing to 0FFh.
During execution of the Bulk Erase instruction, the
Flash memory does not accept any instructions.
Flash Sector Erase
The Sector Erase instruction uses six Write oper-
ations, as described in Table 29. Additional Flash
Sector Erase confirm commands and Flash mem-
ory sector addresses can be written subsequently
to erase other Flash memory sectors in parallel,
without further coded cycles, if the additional com-
mands are transmitted in a shorter time than the
time-out period ofabout 100 µs.Theinput ofanew
Sector Erase command restarts the time-out peri-
od.
The status of the internal timer can be monitored
through thelevel of the EraseTime-out Flag (DQ3/
DQ11) bit. If the Erase Time-out Flag (DQ3/DQ11)
bit is 0, the Sector Erase instruction has been re-
ceived and the time-out period is counting. If the
Erase Time-out Flag (DQ3/DQ11) bit is 1, the
time-out period has expired and the PSD is busy
erasing the Flash memory sector(s). Before and
during Erase time-out, any instruction other than
Suspend Sector Erase and ResumeSector Erase,
abort thecyclethatis currently in progress, andre-
set thedevice to Read mode. It is not necessary to
program the Flash memory sector with 00h as the
PSD does this automatically before erasing.
During a Sector Erase, the memory status maybe
checked by reading the Error Flag (DQ5/DQ13)
bit, the Toggle Flag (DQ6/DQ14) bit, and the Data
Polling (DQ7/DQ15) bit, as detailed in the section
entitled “Programming Flash Memory”, on page
28.
During execution of the Erase cycle, the Flash
memory accepts only Reset and Suspend Sector
Erase instructions. Erasure of one Flash memory
sector may be suspended, in order to read data
from another Flash memory sector, and then re-
sumed.
Suspend Sector Erase
Whena SectorErasecycleis inprogress, theSus-
pend Sector Erase instruction can be used to sus-
pend the cycle by writing 0B0h to any even
address when an appropriate Sector Select (FS0-
FS15 or CSBOOT0-CSBOOT3) is High. (See Ta-
ble 29). This allows reading of data from another
Flash memory sector after the Erase cycle has
been suspended. Suspend Sector Erase is ac-
cepted only during the Flash Sector Erase instruc-
tion execution and defaults to Read mode. A
Suspend Sector Erase instruction executed during
an Erase time-out period, in addition to suspend-
ing theErase cycle, terminatesthe time out period.
The Toggle Flag (DQ6/DQ14) bit stops toggling
when the PSD internal logic is suspended. The
status of this bit must be monitored at an address
within the Flash memory sector being erased. The
Toggle Flag (DQ6/DQ14) bit stops toggling be-
tween 0.1 µs and 15 µs after the Suspend Sector
Erase instruction has been executed. The PSD is
then automatically set to Read mode.
If an Suspend Sector Erase instruction was exe-
cuted, the following rules apply:
Attempting to read from a Flash memory sector
that was being erased outputs invalid data.
Reading from a Flash memory sector that was
not
being erased is valid.
The Flash memory
cannot
be programmed, and
only responds toResume Sector Erase and Re-
set instructions (Read is an operation and is al-
lowed).
If a Reset instruction is received, data in the
Flash memory sector that was being erased is
invalid.
Resume Sector Erase
If a Suspend Sector Erase instruction was previ-
ously executed, the Erase cycle may be resumed
with this instruction. The Resume Sector Erase in-
struction consists of writing 030h to any even ad-
dress while an appropriate Sector Select (FS0-
FS15 or CSBOOT0-CSBOOT3) is High. (See Ta-
ble 29.)
31/94
PSD4256G6V
SPECIFIC FEATURES
Flash Memory Sector Protect
Each sector of Primary or Secondary Flash mem-
ory can be separately protected against Program
and Erase cycles. Sector Protection provides ad-
ditional data security because it disables all Pro-
gram orErase cycles. This modecan be activated
(or deactivated) through the JTAG-ISP Port or a
Device Programmer.
Sector protection can be selected for each sector
using the PSDsoft program. This automatically
protects selected sectors when the device is pro-
grammed through the JTAG Port or a Device Pro-
grammer. Flash memory sectors can be
unprotected to allow updating of their contents us-
ing the JTAG Port or a Device Programmer. The
MCU canread (but cannot change) the sector pro-
tection bits.
Any attempt toprogram orerase a protected Flash
memory sector is ignored by thedevice. The Verify
operation results in a read of the protected data.
This allows a guarantee of the retention of the Pro-
tection status.
The sector protection status can be read by the
MCU through the Flash memory protection and
Secondary Flash memory protection registers (in
the CSIOP block) or use the Read Sector Protec-
tion instruction. See Table 18 toTable 20.
Reset
The Reset instruction consists of one Write cycle
(see Table 29). It can also be optionally preceded
by the standard two write decoding cycles (writing
AAh to AAAh, and 55h to 554h).
The Reset instruction must be executed after:
Reading theFlash Protection Status or Flash ID
An Error condition has occurred (and the device
has set the Error Flag (DQ5/DQ13) bit to 1) dur-
ing a Flash memory Program or Erase cycle.
The Reset instruction immediately puts the Flash
memory back into normal Read mode. However, if
there is an error condition (with the Error Flag
(DQ5/DQ13) bit setto 1)the Flash memory will re-
turn to the Read mode in 25 µs after the Reset in-
struction is issued.
The Reset instruction is ignored when it is issued
during a Program or Bulk Erase cycle of the Flash
memory. The Reset instruction aborts any on-go-
ing Sector Erase cycle, and returns the Flash
memory to the normal Read mode in 25 µs.
Reset (RESET) Pin
A pulse on the Reset (RESET) pin aborts any cy-
cle that is in progress, and resets the Flash mem-
ory to the Read mode. When the reset occurs
during a Program or Erase cycle, the Flash mem-
ory takes up to 25 µs to return to the Read mode.
It is recommended that the Reset (RESET) pulse
(except for Power On Reset, as described on page
68) be at least 25 µs so that the Flash memory is
always ready forthe MCU tofetch thebootstrap in-
structions after the Reset cycle is complete.
PSD4256G6V
32/94
SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain upto three product terms, allowingflexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to the Voltage Stand-by (VSTBY, PE6) line. If you
have an external battery connected to the PSD,
the contents of the SRAMare retained in the event
of a power loss. The contents of the SRAM are re-
tained so long as the battery voltage remains at
2 V or greater. If the supply voltage falls below the
battery voltage, an internal power switch-over to
the battery occurs.
PE7 can be configured as an output that indicates
when power is being drawn from the external bat-
tery. This Battery-on Indicator (VBATON, PE7)
signal is High when the supply voltage falls below
the battery voltage and the battery on Voltage
Stand-by (VSTBY, PE6) is supplying power to the
internal SRAM.
SRAM Select (RS0), Voltage Stand-by (VSTBY,
PE6) and Battery-on Indicator (VBATON, PE7)
are all configured using PSDsoft.
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PSD4256G6V
MEMORY SELECT SIGNALS
The Primary Flash Memory Sector Select (FS0-
FS15), Secondary Flash Memory Sector Select
(CSBOOT0-CSBOOT3) and SRAM Select (RS0)
signals are all outputs of the DPLD. They are de-
fined using PSDsoft. The following rules apply to
the equations for these signals:
1. Primary Flash memory and secondary Flash
memory Sector Select signals must
not
be larg-
er than the physical sector size.
2. Any primary Flash memory sector must
not
be
mapped in the same memory space as another
Flash memory sector.
3. A secondary Flash memory sector must
not
be
mapped in the same memory space as another
secondary Flash memory sector.
4. SRAM, I/O, and Peripheral I/O spaces must
not
overlap.
5. A secondary Flash memory sector
may
overlap
a primaryFlash memory sector. In case of over-
lap, priority is given to the secondary Flash
memory sector.
6. SRAM, I/O, and Peripheral I/O spaces
may
overlap any other memory sector. Priority is giv-
en to the SRAM, I/O, or Peripheral I/O.
Figure 8. Priority Level of Memory and I/O
Components
Example
FS0 is valid when the address is in the range of
8000h to BFFFh,CSBOOT0 isvalid from 8000hto
9FFFh, and RS0 is valid from 8000h to 87FFh.
Any address in the range of RS0 always accesses
the SRAM.Any address in the range of CSBOOT0
greater than 87FFh (and less than 9FFFh) auto-
matically addresses secondary Flash memory
segment 0. Any address greater than 9FFFh ac-
cesses the primaryFlash memory segment0. You
can see that halfof the primaryFlash memory seg-
ment 0and one-fourth ofsecondary Flash memory
segment 0 cannot be accessed in this example.
Also note that anequationthat definedFS1 toany-
where in the range of 8000h to BFFFh would
not
be valid.
Figure 8 shows the priority levels for all memory
components. Anycomponent on ahigher level can
overlap and has priority over any component on a
lower level. Components on the same level must
not
overlap. Level 1 has the highest priority and
level 3 has the lowest.
Memory Select Configuration for MCUs with
Separate Program and Data Spaces
The 80C51XA and compatible family of MCUs,
can beconfigured to have separate address spac-
es for Program memory (selected using Program
Select Enable (PSEN, CNTL2)) andData memory
(selected usingReadStrobe (RD, CNTL1)). Anyof
the memories within the PSD can reside in either
space or both spaces. This is controlled through
manipulation of the VM register that resides in the
CSIOP space.
The VM register is set using PSDsoft to have an
initial value. It can subsequently be changed by
the MCU so that memory mapping can be
changed on-the-fly.
For example, youmay wish tohaveSRAM and pri-
mary Flash memory in the Data space atBoot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the secondary
Flash memory and primary Flash memory. This is
easily done with the VM registerby using PSDsoft
to configure it for Boot-up and having the MCU
change it when desired.
Table 25 describes the VM Register.
Configuration Modes for MCUs with Separate
Program and Data Spaces
Separate Space Modes
Program space isseparated from Dataspace. For
example, Program Select Enable (PSEN, CNTL2)
is used to access the program code from the pri-
mary Flash memory, while Read Strobe (RD,
CNTL1) is used to access data fromthe secondary
Flash memory, SRAM and I/O Port blocks. This
configuration requires the VM register to be set to
0Ch (see Figure 9).
Level 1
SRAM, I/O,
or
Peripheral I/O
Level 2
Secondary
Non-VolatileMemory
Highest Priority
Lowest Priority
Level 3
Primary Flash Memory
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Figure 9. 8031 Memory Modules Separate Space
Combined Space Modes
The Program and Data spaces are combined into
one memory space that allows the primary Flash
memory, secondary Flash memory, and SRAM to
be accessed by either Program Select Enable
(PSEN, CNTL2)or Read Strobe (RD, CNTL1). For
example, to configure the primary Flash memory
in Combined space, bits 2 and 4of the VM register
are set to 1 (see Figure 10).
80C51XA Memory Map Example
See the Application Notes for examples.
Figure 10. 8031 Memory Modules Combined Space
Primary
Flash
Memory
DPLD
Secondary
Flash
Memory
SRAM
RS0
CSBOOT0-3
FS0-FS15 CS CSCS
OE OE
RD
PSEN
OE
AI04922
Primary
Flash
Memory
DPLD
Secondary
Flash
Memory
SRAM
RS0
CSBOOT0-3
FS0-FS15
RD
CS CSCS
RD
OE OE
VM REG BIT 2
PSEN
VM REG BIT 0
VM REG BIT 1
VM REG BIT 3
VM REG BIT 4
OE
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PSD4256G6V
PAGE REGISTER
The 8-bit Page Register increases the addressing
capability of the MCU by a factorof upto 256. The
contents of the register can also be read by the
MCU. The outputs of the Page Register (PGR0-
PGR7) areinputsto theDPLD decoder and canbe
included in the Sector Select (FS0-FS15,
CSBOOT0-CSBOOT3), and SRAM Select (RS0)
equations.
If memory paging is not needed, or if not all eight
page register bits are needed for memory paging,
these bits may be used in the CPLD for general
logic. See Application Note
AN1154
.
Table 22 and Figure 11 show the Page Register.
The eight flip-flops in the register are connected to
the internal data bus (D0-D7). The MCU can write
to or read from the Page Register. The Page Reg-
ister can be accessed at address location CSIOP
+ E0h.
Figure 11. Page Register
MEMORY ID REGISTERS
The 8-bit read-only Memory Status Registers are
included in the CSIOP space. The user can deter-
mine the memory configuration of the PSD device
by reading the Memory ID0 and Memory ID1 reg-
isters. The content of the registers is defined as
shown in Table 26 and Table 27.
RESET
D0-D7
R/W
D0 Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D1
D2
D3
D4
D5
D6
D7
PAGE
REGISTER
PGR0
PGR1
PGR2
PGR3 DPLD
AND
CPLD
INTERNAL
SELECTS
AND LOGIC
PLD
PGR4
PGR5
PGR6
PGR7
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PLDS
The PLDs bring programmable logic functionality
to the PSD. After specifying the logic for the PLDs
using PSDsoft, the logic is programmed into the
device and available upon Power-up.
Table 32. DPLD and CPLD Inputs
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
The PSD contains two PLDs: the Decode PLD
(DPLD), and the ComplexPLD (CPLD). The PLDs
are briefly discussed in the next few paragraphs,
and in more detail in the following sections. Figure
12 shows the configuration of the PLDs.
The DPLD performs address decoding for internal
components, such as memory, registers, and I/O
ports Select signals.
The CPLD can be used for logic functions, suchas
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array. The CPLD can also be
used to generate External Chip Select (ECS0-
ECS2) signals.
The AND Array is used to form product terms.
These product terms are specified using PSDsoft.
An Input Bus consisting of 82 signals is connected
to the PLDs. The signals are shown in Table 32.
The Turbo Bit in PSD
The PLDs in the PSD4256G6V can minimize pow-
er consumption by switching to standby when in-
puts remain unchanged for an extended time of
about 70 ns. Resetting the Turbo bit to 0 (Bit 3 of
the PMMR0 register) automatically places the
PLDs into standby if no inputs are changing. Turn-
ing the Turbo mode off increases propagation de-
lays while reducing power consumption. See the
section entitled “Power Management”, on page
64, on how to set the Turbo bit.
Additionally, five bits are available in the PMMR2
registerto block MCU controlsignals from entering
the PLDs. This reduces power consumption and
can be used only when these MCU control signals
are not used in PLD logic equations.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.
Input Source Input Name Number
of
Signals
MCU Address Bus1A15-A0 16
MCU Control Signals CNTL0-CNTL2 3
Reset RST 1
Power-down PDN 1
Port A Input
Macrocells PA7-PA0 8
Port B Input
Macrocells PB7-PB0 8
Port C Input
Macrocells PC7-PC0 8
Port D Inputs PD3-PD0 4
Port F Inputs PF7-PF0 8
Page Register PGR7-PGR0 8
Macrocell A Feedback MCELLA.FB7-FB0 8
Macrocell B Feedback MCELLB.FB7-FB0 8
Flash memory
Program Status Bit Ready/Busy 1
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PSD4256G6V
Figure 12. PLD Diagram
PLD INPUT BUS
8
INPUT MACROCELL and INPUT PORTS
DIRECT MACROCELL INPUT TO MCU DATA BUS
CSIOP SELECT
SRAM SELECT
SECONDARY NON-VOLATILE MEMORY SELECTS
DECODE PLD
PAGE
REGISTER
PERIPHERAL SELECTS
JTAG SELECT
CPLD
PT
ALLOC.
MCELLA
MCELLB
DIRECT MACROCELL ACCESS FROM MCU DATA BUS
24 INPUT MACROCELL
(PORT A,B,C)
16 OUTPUT
MACROCELL
I/O PORTS
PRIMARY FLASH MEMORY SELECTS
12 PORT D and PORT F INPUTS
TO PORT A
TO PORT B
DATA
BUS
16
8
8
4
3
1
2
1
EXTERNAL CHIP SELECTS
TO PORT C or PORT F
8
82
16
82
24
OUTPUT MACROCELL FEEDBACK
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DECODE PLD (DPLD)
The DPLD, shown in Figure 13,is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals:
16 Sector Select (FS0-FS15) signals for the
primary Flash memory (three product terms
each)
4 SectorSelect (CSBOOT0-CSBOOT3)signals
for the secondary Flash memory (three product
terms each)
1 internal SRAM Select (RS0) signal (three
product terms)
1 internal CSIOP Select (PSD Configuration
Register) signal
1 JTAG Select signal (enables JTAG-ISP on
Port E)
2 internal Peripheral Select signals
(Peripheral I/O mode).
Figure 13. DPLD Logic Array
Note: 1. The address inputs are A19-A4 when in80C51XA mode
2. Additional address lines can be brought ino the PSD via Port A, B, C, D, or F.
(INPUTS)
(32)
(8)
(16)
(1)
PDN (APDOUTPUT)
I/O PORTS (PORT A,B,C,F)
(8)
PGR0 -PGR7
(8)
MCELLA.FB [7:0] (FEEDBACKS)
MCELLB.FB [7:0] (FEEDBACKS)
A[15:0]*
(4)
(3)
PD[3:0](ALE,CLKIN,CSI)
CNTRL[2:0](
READ/WRITE CONTROL SIGNALS)
(1)
(1)
RESET
RD_BSY
RS0
CSIOP
PSEL0
PSEL1
16 PRIMARY
FLASH
MEMORY SECTOR SELECTS
SRAM SELECT
I/O
DECODER
SELECT
PERIPHERAL I/O
MODE
SELECT
CSBOOT 0
CSBOOT 1
CSBOOT 2
CSBOOT 3
FS0
FS15
3
3
3
3
3
3
3
3
3
3
3
3
3
JTAGSEL
AI04925B
°
°
°
°
°
°
1
1
1
1
4 SECONDARY
FLASH
MEMORY SECTOR SELECTS
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PSD4256G6V
COMPLEX PLD (CPLD)
The CPLD can be used to implement system logic
functions, suchas loadable counters and shiftreg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate eight External Chip Se-
lect (ECS0-ECS7), routed to Port C or Port F.
Although External Chip Select (ECS0-ECS7) can
be produced by any Output Macrocell (OMC),
these eight External Chip Select(ECS0-ECS7) on
Port C or Port F do not consume any Output Mac-
rocells (OMC).
As showninFigure 12,the CPLD hasthe following
blocks:
24 Input Macrocells (IMC)
16 Output Macrocells (OMC)
Product Term Allocator
AND Array capable of generating up to 196
product terms
Four I/O Ports.
Each of the blocks are described in the sections
that follow.
TheInput Macrocells(IMC) andOutputMacrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the MCU. This
enables the MCU software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
Thisfeature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
Figure 14. Macrocell and I/O Port
I/O PORTS
CPLD MACROCELLS
INPUT MACROCELLS
LATCHED
ADDRESS OUT
MUX
MUX
MUX
MUX MUX
D
D
Q
Q
Q
G
D
QD
WR
WR
PDR
DATA
PRODUCT
TERM
ALLOCATOR
DIR
REG.
SELECT
INPUT
PRODUCT
TERMS
FROM
OTHER
MACROCELLS
POLARITY
SELECT
UP TO 10
PRODUCT TERMS
CLOCK
SELECT
PR DI LD
D/T
CK
CL
Q
D/T/JK
FF
SELECT
PT CLEAR
PT
CLOCK
GLOBAL
CLOCK
PT OUTPUT ENABLE (OE)
MACROCELL FEEDBACK
I/O PORT INPUT
ALE/AS
PT INPUT LATCH GATE/CLOCK
MCU LOAD
PT PRESET MCU DATA IN
COMB.
/REG
SELECT
PLD INPUT BUSPLD INPUT BUS
MCU ADDRESS /DATA BUS
MACROCELL
OUT
TO
MCU
DATA
LOAD
CONTROL
AND ARRAY
CPLD OUTPUT
I/O PIN
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PSD4256G6V
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Output Macrocell (OMC)
Eight of the Output Macrocells (OMC) are con-
nected to Ports A pins and are named as McellA0-
McellA7. The other eight Macrocells are connect-
ed to Ports B pins and are named as McellB0-
McellB7.
The Output Macrocell (OMC) architecture is
shown in Figure 15. As shown in the figure, there
are native product terms available from the AND
Array, and borrowed product terms available (if
unused) from otherOutput Macrocells (OMC). The
polarity of the product term is controlled by the
XOR gate. The Output Macrocell (OMC) can im-
plement either sequential logic, using the flip-flop
element, or combinatorial logic. The multiplexer
selects between the sequential or combinatorial
logic outputs. The multiplexer output can drive a
port pin and has a feedback path tothe AND Array
inputs.
The flip-flop in the Output Macrocell (OMC) block
can be configured as a D, T, JK, or SR type in the
PSDsoft program. The flip-flop’s clock, preset, and
clear inputs may be driven from a product term of
the AND Array. Alternatively, the external CLKIN
(PD1) signal can be used for the clock input to the
flip-flop. The flip-flop is clocked on the rising edge
of CLKIN (PD1). The preset and clear are active
High inputs. Each clear input can use up to two
product terms.
Table 33. Output Macrocell Port and Data Bit Assignments
Output
Macrocell Port
Assignment Native Product
Terms
Maximum
Borrowed
Product Terms
Data Bit for
Loading or
Reading
Motorola 16-Bit
MCU for Loading or
Reading
McellA0 Port A0 3 6 D0 D8
McellA1 Port A1 3 6 D1 D9
McellA2 Port A2 3 6 D2 D10
McellA3 Port A3 3 6 D3 D11
McellA4 Port A4 3 6 D4 D12
McellA5 Port A5 3 6 D5 D13
McellA6 Port A6 3 6 D6 D14
McellA7 Port A7 3 6 D7 D15
McellB0 Port B0 4 5 D8 D0
McellB1 Port B1 4 5 D9 D1
McellB2 Port B2 4 5 D10 D2
McellB3 Port B3 4 5 D11 D3
McellB4 Port B4 4 6 D12 D4
McellB5 Port B5 4 6 D13 D5
McellB6 Port B6 4 6 D14 D6
McellB7 Port B7 4 6 D15 D7
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PSD4256G6V
Product Term Allocator
The CPLD has aProduct Term Allocator. PSDsoft,
uses the Product Term Allocator to borrow and
place product terms from one Macrocell to anoth-
er. The following list summarizes how product
terms are allocated:
McellA0-McellA7 all have three native product
terms and may borrow up to six more
McellB0-McellB3 all have four native product
terms and may borrow up to five more
McellB4-McellB7 all have four native product
terms and may borrow up to six more.
Each Macrocell may only borrow product terms
from certain other Macrocells. Product terms al-
ready inuse by one Macrocell are not available for
another Macrocell.
If an equation requires more product terms than
are available to it, then “external” product terms
are required, which consume other Output Macro-
cells (OMC). If external product terms are used,
extra delay is added for the equation that required
the extra productterms. This is called product term
expansion. PSDsoft performs this expansion as
needed.
Loading and Reading the Output Macrocells
(OMC)
The Output Macrocells (OMC) block occupies a
memory location in the MCU address space, as
defined by the CSIOP (see the section entitled “I/
O Ports”, on page 55). The flip-flops ineach of the
16 Output Macrocells (OMC) can be loaded from
the data bus by a MCU. Loading the Output Mac-
rocells (OMC) with datafrom the MCU takes prior-
ity over internal functions. As such, the preset,
clear, and clock inputs to the flip-flop can be over-
ridden by the MCU. The ability to load the flip-flops
and read them back is useful in such applications
as loadable counters and shift registers, mailbox-
es, and handshaking protocols.
Data is loaded tothe Output Macrocells (OMC) on
the trailing edge of Write Strobe (WR/WRL,
CNTL0).
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Figure 15. CPLD Output Macrocell
The OMC Mask Register
There is one Mask Register for each of the two
groups of eight Output Macrocells (OMC). The
Mask Registers can be used to block the loading
of data to individual Output Macrocells (OMC).
The default value for the Mask Registers is 00h,
which allows loading of the Output Macrocells
(OMC). When a given bit in a Mask Register is set
to a 1, the MCU is blocked from writing to the as-
sociated Output Macrocells (OMC). For example,
suppose McellA0-McellA3 are being used for a
state machine. You would not want a MCU write to
McellA to overwrite the state machine registers.
Therefore, you would want to load the Mask Reg-
ister for McellA (Mask Macrocell A) with the value
0Fh.
The Output Enable of the OMC
The Output Macrocells (OMC) can be connected
to an I/O port pin as a PLD output. The output en-
able of each port pin driver is controlled by a single
product term from the AND Array, ORed with the
Direction Register output. The pin is enabled upon
Power-up if no output enable equation is defined
and if the pin is declared as a PLDoutput in PSD-
soft.
If the Output Macrocell (OMC) output is declared
as an internal node and not as a port pin output in
the PSDabel file, then the port pin can be used for
other I/O functions. The internal node feedback
can be routed as an input to the AND Array.
PT
ALLOCATOR
MASK
REG.
PT CLK
PT
PT
PT
CLKIN
FEEDBACK (.FB)
PORT INPUT
AND ARRAY
PLD INPUT BUS
MUX
MUX
POLARITY
SELECT
LD
IN
CLR
Q
PRDIN
COMB/REG
SELECT
PORT
DRIVER
INPUT
MACROCELL
I/O PIN
INTERNAL DATA BUS
DIRECTION
REGISTER
CLEAR (.RE) PROGRAMMABLE
FF (D/T/JK/SR)
WR
ENABLE (.OE)
PRESET(.PR)
RD
MACROCELL CS
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PSD4256G6V
Figure 16. Input Macrocell
Input Macrocells (IMC)
The CPLD has 24 Input Macrocells (IMC), one for
each pin on Ports A, B, and C. The architecture of
the Input Macrocells (IMC) is shown in Figure 16.
The Input Macrocells (IMC) are individually config-
urable, and can be used as a latch, register, or to
pass incoming Port signals prior to driving them
onto the PLD input bus. The outputs of the Input
Macrocells (IMC)can be read by the MCU through
the internal data bus.
The enable for the latch and clock for the register
are driven by a multiplexer whose inputs are a
product term from the CPLD AND Array or the
MCU Address Strobe (ALE/AS). Each product
term output is used to latch or clock four Input
Macrocells (IMC). Port inputs 3-0 can be con-
trolled by one product term and 7-4 by another.
Configurations for the Input Macrocells (IMC) are
specified by PSDsoft (see Application Note
AN1171
). Outputs of the Input Macrocells (IMC)
can be read by the MCU via the IMC buffer. See
the section entitled “I/O Ports”, on page 55.
Input Macrocells (IMC) can use Address Strobe
(ALE/AS, PD0) to latch address bits higher than
A15. Any latched addresses are routed to the
PLDs as inputs.
Input Macrocells (IMC) are particularly useful with
handshaking communication applications where
two processors pass data back and forth through
a commonmailbox. Figure 18shows atypical con-
figuration where theMaster MCU writesto the Port
A Data OutRegister. This, in turn, can be read by
the Slave MCU via the activation of the “Slave-
Read” output enable product term.
The Slave can also write to the Port A Input Mac-
rocells (IMC) and the Master can then read the In-
put Macrocells (IMC) directly.
Note that the “Slave-Read” and “Slave-Wr” signals
are product terms that are derived from the Slave
MCU inputs Read Strobe (RD, CNTL1), Write
Strobe (WR/WRL, CNTL0), and Slave_CS.
External Chip Select
The CPLD also provides eight External Chip Se-
lect (ECS0-ECS7) outputs that can be used to se-
lect external devices. Each External Chip Select
(ECS0-ECS7) consists of one product term that
can be configured active High or Low.
The output enable of the pin iscontrolled by either
the output enable product term or the Direction
Register. (See Figure 17.)
OUTPUT
MACROCELLS
A
AND
MACROCELLS B
PT
PT
FEEDBACK
AND ARRAY
PLD INPUT BUS
PORT
DRIVER
I/O PIN
INTERNAL DATA BUS
DIRECTION
REGISTER
MUX
MUX
ALE/AS
PT
Q
Q
D
D
G
LATCH INPUT MACROCELL
ENABLE (.OE)
DFF
INPUT MACROCELL_RD
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Figure 17. External Chip Select Signal
Figure 18. Handshaking Communication Using Input Macrocells
PLD INPUT BUS
POLARITY
BIT
PORT PIN
ECS PT ECS
To Port C or F
ENABLE (.OE) PT DIRECTION
REGISTER
CPLD AND ARRAY
Port C or Port F
AI04927
MASTER
MCU
MCU-RD
MCU-RD
MCU-WR
SLAVEWR
SLAVECS
MCU-WR
D[7:0]
D[7:0]
CPLD DQ
QD
PORT A
DATA OUT
REGISTER
PORT A
INPUT
MACROCELL
PORT A
SLAVEREAD
SLAVE
MCU
RD
WR
AI02877C
PSD
45/94
PSD4256G6V
MCU BUS INTERFACE
The “no-glue logic” MCU Bus Interface block can
be directly connected to most popular MCUs and
their control signals. Key 16-bit MCUs, with their
bus types and control signals, are shown in Table
34. The MCU interface type is specified using the
PSDsoft.
PSD Interface to a Multiplexed Bus
Figure 19 shows an example of a system using a
MCU with a 16-bit multiplexed bus and a
PSD4256G6V. The ADIO port on the PSD is con-
nected directly to the MCU address/data bus. Ad-
dress Strobe (ALE/AS, PD0) latches the address
signals internally. Latched addresses can be
brought out to Port E, F or G. The PSD drives the
ADIO data bus only when one of its internal re-
sources is accessed and Read Strobe (RD,
CNTL1) is active. Should the system address bus
exceed sixteen bits, Ports A, B, C, or F may be
used as additional address inputs.
PSD Interface to a Non-Multiplexed 8-Bit Bus
Figure 20 shows an example of a system using a
MCU with a 16-bit non-multiplexed bus and a
PSD4256G6V. The address bus is connected to
the ADIO Port, and the data bus is connected to
Ports F and G. Ports F and G are in tri-state mode
when the PSD is not accessed by the MCU.
Should the system address bus exceed sixteen
bits, Ports A, B, or C may be used for additional
address inputs.
Table 34. MCUs and their Control Signals
Note: 1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PD3-PD0, PF3-PF0) canbe configured for other I/O func-
tions.
2. ALE/AS input is optional for MCUs with a non-multiplexed bus
3. This configuration is for MC68HC812A4_EC at 5 MHz, 3 V only.
MCU CNTL0 CNTL1 CNTL2 PD3 PD02ADIO0 PF3-PF0
68302, 68306, MMC2001 R/W LDS UDS (Note 1)AS (Note 1)
68330, 68331, 68332, 68340 R/W DS SIZ0 (Note 1)AS A0 (Note 1)
68LC302, MMC2001 WEL OE WEH AS (Note 1)
68HC16 R/W DS SIZ0 (Note 1)AS A0 (Note 1)
68HC912 R/W E LSTRB DBE E A0 (Note 1)
68HC812 3R/W E LSTRB (Note 1) (Note 1)A0 (Note 1)
80196 WR RD BHE (Note 1)ALE A0 (Note 1)
80196SP WRL RD (Note 1)WRH ALE A0 (Note 1)
80186 WR RD BHE (Note 1)ALE A0 (Note 1)
80C161, 80C164-80C167 WR RD BHE (Note 1)ALE A0 (Note 1)
80C51XA WRL RD PSEN WRH ALE A4/D0 A3-A1
H8/300 WRL RD (Note 1)WRH AS A0
M37702M2 R/W E BHE (Note 1)ALE A0 (Note 1)
PSD4256G6V
46/94
Figure 19. An Example of a Typical 16-bit Multiplexed Bus Interface
Figure 20. An Example of a Typical 16-bit Non-Multiplexed Bus Interface
MCU
WR
RD
BHE
ALE
RESET
AD[7:0]
AD[15:8]
A[15:8]
A[7:0]
ADIO
PORT
PORT
F
PORT
G
PORT
A, B
or C
WR (CNTRL0)
RD (CNTRL1)
BHE (CNTRL2)
RST
ALE (PD0)
PORT D
(OPTIONAL)
(OPTIONAL)
PSD
AI04928
A[23:16]
(OPTIONAL)
MCU
WR
RD
BHE
ALE
RESET
D[15:0]
A[15:0]
D[15:8]
D[7:0]
ADIO
PORT
PORT
F
PORT
G
PORT
A, B
or C
WR (CNTRL0)
RD (CNTRL1)
BHE (CNTRL2)
RST
ALE (PD0)
PORT D
PSD
AI04929
A[23:16]
(OPTIONAL)
47/94
PSD4256G6V
Data Byte Enable Reference
MCUs have different data byte orientations. Table
35 to Table 38 show how the PSD4256G6V inter-
prets byte/word operations in different bus write
configurations. Even-byte refers to locations with
address A0 equal to 0, and odd byte as locations
with A0 equal to1.
Table 35. 16-Bit Data Bus with BHE
MCU Bus Interface Examples
Figure 21 to Figure 26show examplesof the basic
connections between the PSD4256G6Vand some
popular MCUs. The PSD4256G6V Control input
pins are labeled as to the MCU function for which
they are configured. The MCU bus interface is
specified using PSDsoft. The Voltage Stand-by
(VSTBY, PE6) line should be held at Ground if not
in use.
Table 36. 16-Bit Data Bus with WRH and WRL
Table 37. 16-Bit Data Bus with SIZ0, A0
(Motorola MCU)
Table 38. 16-Bit Data Bus with LDS, UDS
(Motorola MCU)
BHE A0 D15-D8 D7-D0
0 0 Odd Byte Even Byte
0 1 Odd Byte
1 0 Even Byte
WRH WRL D15-D8 D7-D0
0 0 Odd Byte Even Byte
0 1 Odd Byte
1 0 Even Byte
SIZ0 A0 D15-D8 D7-D0
0 0 Even Byte Odd Byte
1 0 Even Byte
1 1 Odd Byte
WRH WRL D15-D8 D7-D0
0 0 Even Byte Odd Byte
1 0 Even Byte
0 1 Odd Byte
PSD4256G6V
48/94
Figure 21. Interfacing the PSD with an 80C196
80C196 and 80C186
In Figure 21, the Intel 80C196 MCU, which has a
16-bit multiplexed address/data bus, is shown
connected to a PSD4256G6V. The Read Strobe
(RD, CNTL1), and Write Strobe (WR/WRL,
CNTL0) signals are connected to the CNTL pins.
When BHE is not used, the PSD canbe configured
to receive WRL and Write Enable High-byte
(WRH/DBE, PD3) from the MCU. Higher address
inputs (A16-A19) can be routedto Ports A, B, orC
as input ot the PLD.
The AMD 80186 familyhas the same bus connec-
tion to the PSD as the 80C196.
X1
X2
P1.0/EPA0/T2CLK
P1.1/EPA1
P1.2/EPA2/T2DIR
P1.3/EPA3
P1.4/EPA4
P1.5/EPA5
P1.6/EPA6
P1.7/EPA7
P3.0/AD0
P3.1/AD1
P3.2/AD2
P3.3/AD3
P3.4/AD4
P3.5/AD5
P3.6/AD6
P3.7/AD7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PA0
PA2
PA1
PA3
PA4
PA5
PA6
PA7
P4.0/AD8
P4.1/AD9
P4.2/AD10
P4.3/AD11
P4.4/AD12
P4.5/AD13
P4.6/AD14
P4.7/AD15
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0 (WR)
CNTL1 (RD)
CNTL2 (BHE)
PD0 (ALE)
PD1 (CLKIN)
PD2 (CSI)
RESET
RD/P5.3
WR/WRL/P5.2
BHE/WRH/P5.5
ALE/ADV/P5.0
INST/P5.1
SLPINT/P5.4
RESET
31
32
33
34
35
36
37
38
3
19
18
57
56
55
54
53
52
51
50
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
59
39
60
40
79
80
1
21
22
23
24
25
26
27
28
PSD80C196NT
A19-A16 A[19:16]
7
9
8
4
RD
WR
BHE
ALE
3
1
RESET
51
52
53
54
55
56
57
58
AI04930
AD15-AD0 AD[15:0]
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC2
PC1
PC3
PC4
PC5
PC6
PC7
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
PD3 (WRH)
2
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
71
72
73
74
75
76
77
78
8 30495070
GNDGNDGNDGNDGND
92969
VCC VCC VCC
VCC
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
3
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
EP.0/A16
EP.1/A17
EP.2/A18
EP.3/A19
14
13
12
11
31
BUSWIDTH/P5.7 10
EA 33
RESET
READY/P5.6 2
P2.0/TX/PVR
P2.1/RXD/PALE
P2.2/EXINT/PROG
P2.3/INTB
P2.4/INTINTOUT
P2.5/HLD
P2.6/HLDA/CPVER
P2.7/CLKOUT/PAC
36
37
38
39
40
41
42
43
P6.0/EPA8
P6.1/EPA9
P6.2/T1CLK
P6.3/T1DIR
P6.4/SC0
P6.5/SD0
P6.6/SC1
P6.7/SD1
58
59
60
61
62
63
64
65
NMI
VREF
VPP
ANGND
ACH4/P0.4/PMD.0
ACH5/P0.5/PMD.1
ACH6/P0.6/PMD.2
ACH7/P0.7/PMD.3
32
49
6
48
44
45
46
47
A16
A17
A18
A19
A16
A17
A18
A19
49/94
PSD4256G6V
Figure 22. Interfacing the PSD with an MC68331
MC683xx and MC68HC16
Figure 22 shows a MC68331 with a 16-bit non-
multiplexed data bus and 24-bit address bus. The
data bus from the MC68331 is connected to Port F
(D0-D7) and Port G(D8-D15). The SIZ0 and A0 in-
puts determine thehigh/low byte selection. The R/
W, DS and SIZ0 signals are connected to the
CNTL0-CNTL2 pins.
The MC68HC16, and other members of the
MC683xx family, has the same bus connection to
the PSD as the MC68331 shown in Figure 22.
VCC_BAR
D[15:0]
A16
A5
D1
D13
DS\
AS
A8
D12
A1
A18
A19
A23
D4
D12
D8
A22
D7
D3
A[23:0]
D3
D11
A16
A17
D14
D13
A3
D2
D5
A19
A0
A12
D2
A4
R/W\
D6
D5
RESET\
A7
A2
A13
A14
A15
D7
D9
D10
D15
D4
A17
A6
SIZ0
D10
D15
A18
A21
A11
D0
D1
D6
D11
D14
D9
D0
A20
D8
A9
A10
MC68331
A1
20
A2
21
A3
22
A4
23
A5
24
A6
25
A7
26
A8
27
A9
30
A10
31
A11
32
A12
33
A13
35
A14
36
A15
37
A16
38
A17
41
A18
42
A19_CS6/
121
A20_CS7/
122
A21_CS8/
123
A22_CS9/
124
A23_CS10/
125
R_W
79
AS
82
D0
111
D1
110
D2
109
D4
105
D5
104
D6
103
D7
102
D8
100
D9
99
D10
98
D11
97
D13
93
D14
92
D15
91
A0
90
D3
108
D12
94
DS
85
SIZ0
81
SIZ1
80
CSBOOT/
112
BR_CS0/
113
BG_CS1/
114
BGACK_CS2/
115
FC0_CS3/
118
FC1_CS4/
119
FC2_CS5/
120
RESET
68
DSACK0
89
DSACK1
88
CLKOUT
66
IRQ1
77
IRQ2
76
IRQ3
75
IRQ4
74
IRQ5
73
IRQ6
72
IRQ7
71
PSD
ADIO0
3
ADIO1
4
ADIO2
5
ADIO3
6
ADIO4
7
ADIO5
10
ADIO6
11
ADIO7
12
ADIO9
14
ADIO10
15
ADIO11
16
ADIO12
17
ADIO13
18
ADIO14
19
ADIO15
20
PF0
31
PF1
32
PF2
33
PF3
34
PF4
35
PF5
36
PF6
37
PF7
38
PG1
22
PG2
23
PG3
24
PG4
25
PG5
26
PG6
27
PG7
28
PA5
56
PA6
57
PA7
58
CNTL0(R/W)
59
CNTL1(DS)
60
CNTL2
(SIZ0)
40
PD0
(AS)
79
RESET
39
ADIO8
13
PG0
21
PA3
54
PA4
55
PA2
53
PA0
51
PA1
52
PB0
61
PB1
62
PB2
63
PB3
64
PB4
65
PB5
66
PB6
67
PB7
68
PC0
41
PC1
42
PC2
43
PC3
44
PC4
45
PC5
46
PC6
47
PC7
48
PE0
(TMS)
71
PE1
(TCK/ST)
72
PE2
(TDI)
73
PE3 (TDO)
74
PE4
(TSTAT/RDY)
75
PE5 (TERR)
76
PE7 (VBATON)
78
Vcc
29
Vcc
69
Vcc
9
GND
50
GND
49
GND
30
GND
8
GND
70
PD2
(CSI)
1
PD1
(CLKIN)
80
PD3
2
PE6
(VSTBY)
77
RESET\
A[23:0]
D[15:0]
AI04951b
PSD4256G6V
50/94
Figure 23. Interfacing the PSD with an 80C51XA-G3
80C51XA
The Philips 80C51XA MCU has a 16-bit multi-
plexed bus with burst cycles. Address bits (A3-A1)
are not multiplexed, while (A19-A4) are multi-
plexed with data bits(D15-D0).
The PSD4256G6V supports the 80C51XA burst
mode. The WRH signal is connected to PD3, and
WHL is connected to CNTL0. The RD and PSEN
signals are connected to the CNTL1 and CNTL2
pins. Figure 23 shows the schematic diagram.
The 80C51XA improves bus throughput and per-
formance by issuing burst cycles to fetch codes
from memory. In burst cycles,address A19-A4 are
latched internally by the PSD, while the 80C51XA
drives theA3-A1 signals to fetch sequentially up to
16 bytes of code. The PSD access time is then
measured from address A3-A1 valid to data in val-
id. The PSD bus timing requirement in a burst cy-
cle is identical to the normal bus cycle, except the
address setup and hold time with respect to Ad-
dress Strobe (ALE/AS, PD0) is not required.
VCC_BAR
VCC_BAR
D[15:0]
WRL\
RD\
PSEN\
ALE
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12D8
A13D9
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
RESET\
RESET\
A3
A2
A1
WRH\
A[3:1]
A1
A2
A3
U3
CRYSTAL
PSD
ADIO0
3
ADIO1
4
ADIO2
5
ADIO3
6
ADIO4
7
ADIO5
10
ADIO6
11
ADIO7
12
ADIO9
14
ADIO10
15
ADIO11
16
ADIO12
17
ADIO13
18
ADIO14
19
ADIO15
20
PF0
31
PF1
32
PF2
33
PF3
34
PF4
35
PF5
36
PF6
37
PF7
38
PG1
22
PG2
23
PG3
24
PG4
25
PG5
26
PG6
27
PG7
28
PA5
56
PA6
57
PA7
58
CNTL0(WR)
59
CNTL1(RD)
60
CNTL2(PSEN)
40
PD0
(ALE)
79
RESET
39
ADIO8
13
PG0
21
PA3
54
PA4
55
PA2
53
PA0
51
PA1
52
PB0
61
PB1
62
PB2
63
PB3
64
PB4
65
PB5
66
PB6
67
PB7
68
PC0
41
PC1
42
PC2
43
PC3
44
PC4
45
PC5
46
PC6
47
PC7
48
PE0
(TMS)
71
PE1
(TCK/ST)
72
PE2
(TDI)
73
PE3
(TDO)
74
PE4 (TSTAT/RDY)
75
PE5
(TERR)
76
PE7
(VBATON)
78
Vcc
29
Vcc
69
Vcc
9
GND
50
GND
49
GND
30
GND
8
GND
70
PD2
(CSI)
1
PD1
(CLKIN)
80
PD3
(WRH)
2
PE6
(VSTBY)
77
XA-G3
A0/WRH
2
A1
3
A2
4
A3
5
A4D0
43
A5D1
42
A6D2
41
A7D3
40
A8D4
39
A9D5
38
A10D6
37
A11D7
36
A12D8
24
A13D9
25
A14D10
26
A15D11
27
A16D12
28
A17D13
29
A18D14
30
A19D15
31
PSEN
32
RD
19
WRL
18
ALE
33
RST
10
INT0
14
INT1
15
EA/WAIT
35
BUSW
17
XTAL1
21
XTAL2
20
RXD0
11
TXD0
13
RXD1
6
TXD1
7
T2EX
9
T2
8
T0
16
D[15:0]
A[3:1]
AI04952b
51/94
PSD4256G6V
Figure 24. Interfacing the PSD with an H83/2350
H8/300
Figure 24 shows an Hitachi H8/2350 with a 16-bit
non-multiplexed data bus, and a 24-bit address
bus. The H8 data bus is connected to Port F (D0-
D7) and Port G (D8-D15).
The WRH signal is connected to PD3, and WHL is
connected to CNTL0. The RD signal is connected
to CNTL1. The connection to the Address Strobe
(AS) signal is optional, and is required if the ad-
dresses are to be latched.
VCC_BAR
AS
RESET\
RD\
RESET\
WRL\
A21
A3
A[23:0]
A11
A1
A9
A14
A15
A20
A5
A8
A13
A10
A7
A18
A19
A17
A2
A16
A4
A6
A12
A0
D4
D9
D10
D15
D8
D7
D[15:0]
D2
D5
D0
D11
D13
D3
D14
D1
D6
D12
WRH\
A22
A23
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A16
A17
A18
A19
U3
CRYSTAL
H8S/2655
PC0/A0
2
PC1/A1
3
PC2/A2
4
PC3/A3
5
PC4/A4
7
PC5/A5
8
PC6/A6
9
PC7/A7
10
PB0/A8
11
PB1/A9
12
PB2/A10
13
PB3/A11
14
PB4/A12
16
PB5/A13
17
PB6/A14
18
PB7/A15
19
PA0/A16
20
PA1/A17
21
PA2/A18
22
PA3/A19
23
PA4/A20/IRQ4
25
PA5/A21/IRQ5
26
PA6/A22/IRQ6
27
PA7/A23/IRQ7
28
CS7/IRQ3
29
CS6/IRQ2
30
IRQ1
31
IRQ0
32
RXD0
55
TXD0
53
SCK0
57
RXD1
56
TXD1
54
SCK1
58
RXD2
90
TXD2
89
SCK2
91
PF0/BREQ
88
PF1/BACK
87
PF2/LCAS/WAIT/B
86
NMI
74
PO0/TIOCA3
71
PO1/TIOCB3
70
PO2/TIOCC3/TMRI
69
PO3/TIOCD3/TMCI
68
PO4/TIOCA4/TMRI
67
PO5/TIOCB4/TMRC
66
PO6/TIOCA5/TMRO
65
PO7/TIOCB5/TMRO
64
DREQ/CS4
60
TEND0/CS5
61
DREQ1
62
TEND1
63
PE0/D0
34
PE0/D1
35
PE0/D2
36
PE0/D3
37
PE0/D4
39
PE0/D5
40
PE0/D6
41
PE0/D7
42
PD0/D8
43
PD1/D9
44
PD2/D10
45
PD3/D11
46
PD4/D12
48
PD5/D13
49
PD6/D14
50
PD7/D15
51
RD
83
LWR
85
HWR
84
AS
82
PF0/PHI0
80
RESET
73
WDTOVF
72
MOD0
113
MOD1
114
MOD2
115
STBY
75
EXTAL
78
XTAL
77
PG0/CAS/OE
116
PG1/CS3
117
PG2/CS2
118
PG3/CS1
119
PG4/CS0
120
PO8/TIOCA0/DACK
112
PO9/TIOCB0/DACK
111
PO10/TIOCC0/TCL
110
PO11/TIOCD0/TCL
109
PO12/TIOCA1
108
PO13/TIOCB1/TCL
107
PO14/TIOCA2
106
PO15/TIOCB2/TCL
105
AN0
95
AN1
96
AN2
97
AN3
98
AN4
99
AN5
100
AN6/DA0
101
AN7/DA1
102
ADTRG
92
PSD
ADIO0
3
ADIO1
4
ADIO2
5
ADIO3
6
ADIO4
7
ADIO5
10
ADIO6
11
ADIO7
12
ADIO9
14
ADIO10
15
ADIO11
16
ADIO12
17
ADIO13
18
ADIO14
19
ADIO15
20
PF0
31
PF1
32
PF2
33
PF3
34
PF4
35
PF5
36
PF6
37
PF7
38
PG1
22
PG2
23
PG3
24
PG4
25
PG5
26
PG6
27
PG7
28
PA5
56
PA6
57
PA7
58
CNTL0(WRL)
59
CNTL1(RD)
60
CNTL2
40
PD0
(AS)
79
RESET
39
ADIO8
13
PG0
21
PA3
54
PA4
55
PA2
53
PA0
51
PA1
52
PB0
61
PB1
62
PB2
63
PB3
64
PB4
65
PB5
66
PB6
67
PB7
68
PC0
41
PC1
42
PC2
43
PC3
44
PC4
45
PC5
46
PC6
47
PC7
48
PE0
(TMS)
71
PE1
(TCK/ST)
72
PE2
(TDI)
73
PE3
(TDO)
74
PE4 (TSTAT/RDY)
75
PE5 (TERR)
76
PE7
(VBATON)
78
Vcc
29
Vcc
69
Vcc
9
GND
50
GND
49
GND
30
GND
8
GND
70
PD2 (CSI)
1
PD1 (CLKIN)
80
PD3 (WRH)
2
PE6
(VSTBY)
77
A[23:0]
D[15:0]
AI04953b
PSD4256G6V
52/94
Figure 25. Interfacing the PSD with an MMC2001
MMC2001
The Motorola MCORE MMC2001 MCU has a
MOD input pin that selects interal or external boot
ROM. The PSD can be configured as the external
flash boot ROM or as extension to the internal
ROM.
The MMC2001 has a 16-bit external data bus and
20 address lines with external chip select signals.
The Chip Select Control Registers allow the user
to customize the bus interface and timing to fit the
individual system requirement. A typical interface
configuaration to the PSD is shown in Figure 25.
The MMC2001’s R/W signal is conneced to the
CNTL0 pin,while EB0 and EB1(enable byte-0 and
enable byte-1) are connected to the CNTL1 (UDS)
and CNTL2 (LDS) pins. The WEN bit in the Chip
Select Control Register should be set to 1 to termi-
nate the EB0-EB1 earlier to provide the wrtie data
hold time for the PSD. The WSC and WWS bits in
VCC_BAR
VCC_BAR
A16
ALE
AD14
AD10
AD6
A17
A19
RD\
AD13
AD9
AD5
AD1
RESET\
A19
BHE\
AD7
A[19:16]
A17
AD[15:0]
AD12
AD4
AD2
A18
WR\
AD15
AD8
A18
AD11
A16
RESET\
AD3
AD0
U3
CRYSTAL
PSD
ADIO0
3
ADIO1
4
ADIO2
5
ADIO3
6
ADIO4
7
ADIO5
10
ADIO6
11
ADIO7
12
ADIO9
14
ADIO10
15
ADIO11
16
ADIO12
17
ADIO13
18
ADIO14
19
ADIO15
20
PF0
31
PF1
32
PF2
33
PF3
34
PF4
35
PF5
36
PF6
37
PF7
38
PG1
22
PG2
23
PG3
24
PG4
25
PG5
26
PG6
27
PG7
28
PA5
56
PA6
57
PA7
58
CNTL0(WR)
59
CNTL1(RD)
60
CNTL2(BHE)
40
PD0 (ALE)
79
RESET
39
ADIO8
13
PG0
21
PA3
54
PA4
55
PA2
53
PA0
51
PA1
52
PB0
61
PB1
62
PB2
63
PB3
64
PB4
65
PB5
66
PB6
67
PB7
68
PC0
41
PC1
42
PC2
43
PC3
44
PC4
45
PC5
46
PC6
47
PC7
48
PE0 (TMS)
71
PE1 (TCK/ST)
72
PE2
(TDI)
73
PE3
(TDO)
74
PE4 (TSTAT/RDY)
75
PE5
(TERR)
76
PE7 (VBATON)
78
Vcc
29
Vcc
69
Vcc
9
GND
50
GND
49
GND
30
GND
8
GND
70
PD2
(CSI)
1
PD1
(CLKIN)
80
PD3
(WRH)
2
PE6 (VSTBY)
77
Infineon
C167CR
AD0
100
AD1
101
Vcc
109
AD2
102
AD3
103
AD4
104
AD5
105
AD6
106
AD7
107
AD8
108
AD9
111
AD10
112
AD11
113
AD12
114
AD13
115
AD14
116
AD15
117
EA
99
ALE
98
READY
97
WR/WRL
96
RD
95
Vcc
93
XTAL1
138
XTAL2
137
RSTIN
140
RSTOUT
141
NMI
142
P4.0/A16
85
A17
86
A18
87
A19
88
A20
89
A21
90
A22
91
P4.7/A23
92
P3.0/T0IN
65
P3.1/T6OUT
66
P3.2/CAPIN
67
P3.3/T3OUT
68
P3.4/T3EUD
69
P3.5/T4IN
70
P3.6/T3IN
73
P3.7/T2IN
74
P3.8/MRST
75
P3.9/MTSR
76
P3.10/TXD0
77
P3.11/RXD0
78
P3.12/BHE/WRH
79
P3.13/SCLK
80
P3.15/CLKOUT
81
P1L0
118
P1L1
119
P1L2
120
P1L3
121
P1L4
122
P1L5
123
P1L6
124
P1L7
125
P1H0
128
P1H1
129
P1H2
130
P1H3
131
P1H4
132
P1H5
133
P1H6
134
P1H7
135
P2.0/CC0IO
47
P2.1/CC1IO
48
P2.2/CC2IO
49
P2.3/CC3IO
50
P2.4/CC4IO
51
P2.5/CC5IO
52
P2.6/CC6IO
53
P2.7/CC7IO
54
P2.8/CC8IO/EX0IN
57
P2.9/CC9IO/EX1IN
58
P2.10/CC10IO/EX2IN
59
P2.11/CC11IO/EX3IN
60
P2.12/CC12IO/EX4IN
61
P2.13/CC13IO/EX5IN
62
P2.14/CC14IO/EX6IN
63
P2.15/CC15IO/EX7IN
64
P5.0/AN0
27
P5.1/AN1
28
P5.2/AN2
29
P5.3/AN3
30
P5.4/AN4
31
P5.5/AN5
32
P5.6/AN6
33
P5.7/AN7
34
P5.8/AN8
35
P5.9/AN9
36
P5.10/AN10/T6UED
39
P5.11/AN11/T5UED
40
P5.12/AN12/T6IN
41
P5.13/AN13/T5IN
42
P5.14/AN14/T4UED
43
P5.15/AN15/T2UED
44
P6.0/!CS0
1
P6.1/!CS1
2
P6.2/!CS2
3
P6.3/!CS3
4
P6.4/!CS4
5
P6.5/!HOLD
6
P6.6/!HLDA
7
P6.7/!BREQ
8
P7.0/POUT0
19
P7.1/POUT1
20
P7.2/POUT2
21
P7.3/POUT3
22
P7.4/CC28IO
23
P7.5/CC29IO
24
P7.6/CC30IO
25
P7.7/CC31IO
26
P8.0/CC16IO
9
P8.1/CC17IO
10
P8.2/CC18IO
11
P8.3/CC19IO
12
P8.4/CC20IO
13
P8.5/CC21IO
14
P8.6/CC22IO
15
P8.7/CC23IO
16
Vss
143
Vss
139
Vss
127
Vss
110
Vss
94
Vss
83
Vss
71
Vss
55
Vss
45
Vss
18
Agnd
38
Vcc
144
Vcc
136
Vcc
126
Vcc
82
Vcc
72
Vcc
17
Vcc
56
Vcc
46
Vref
37
ADIO[15:0]
A[19:16]
AI04954b
53/94
PSD4256G6V
the Control Register are set to wait states that
meet the PSD access time requirement.
Another option isto configure the EB0 and EB1 as
WRL and WRH signals. In this case, the PSD con-
trol setting will be: OE, WRL, WRH where OE is
the read signal for the MMC2001.
C16x Family
The PSD supports Infineon’s C16X family of
MCUs (C161-C167) in both the multiplexed and
non-multiplexed bus configuration. In Figure 26,
the C167CR is shown connected to the PSD in a
multiplexed bus configuration. The control signals
from the MCU are WR, RD, BHE and ALE,and are
routed to the corresponding PSD pins.
The C167 has another control signal setting (RD,
WRL, WRH, ALE) which is also supported by the
PSD.
PSD4256G6V
54/94
Figure 26. Interfacing the PSD with a C167CR
XTAL1
XTAL2
P8.0/CC16IO
P8.1/CC17IO
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO
P8.5/CC21IO
P8.6/CC22IO
P8.7/CC23IO
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PA0
PA2
PA1
PA3
PA4
PA5
PA6
PA7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0 (WR)
CNTL1 (RD)
CNTL2 (BHE)
PD0 (ALE)
PD1 (CLKIN)
PD2 (CSI)
RESET
RD
WR/WRL
P312/BHE/WRH
ALE
RESET
31
32
33
34
35
36
37
38
3
138
137
9
10
11
12
13
14
15
16
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
59
39
60
40
79
80
1
21
22
23
24
25
26
27
28
PSD
C167CR
A19-A16 A[19:16]
95
96
79
98
RD
WR
BHE
ALE
RESET
51
52
53
54
55
56
57
58
AI04955
AD15-AD0 AD[15:0]
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC2
PC1
PC3
PC4
PC5
PC6
PC7
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
PD3 (WRH)
2
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
71
72
73
74
75
76
77
78
8 30495070
GNDGNDGNDGNDGND
92969
VCC VCC VCC
VCC
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
100
101
102
103
104
105
106
107
108
111
112
113
114
115
116
117
P4.0/A16
P4.1/A17
P4.2/A18
P4.3/A19
85
86
87
88
140
EA 99
RSTIN
P7.0/POUT0
P7.1/POUT1
P7.2/POUT2
P7.3/POUT3
P7.4/CC28IO
P7.5/CC29IO
P7.6/CC30IO
P7.7/CC31IO
19
20
21
22
23
24
25
26
P6.0/!CS0
P6.1/!CS1
P6.2/!CS2
P6.3/!CS3
P6.4/!CS4
P6.5/!HOLD
P6.6/!HLDA
P6.7/!BREQ
1
2
3
4
5
6
7
8
A16
A17
A18
A19
A16
A17
A18
A19
P5.8/AN8
P5.9/AN9
P5.10/AN10/T6UED
P5.11/AN11/T5UED
P5.12/AN12/T6IN
P5.13/AN13
P5.14/AN14/T4UED
P5.15/AN15/T2UED
35
36
39
40
41
42
43
44
P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.6/AN6
P5.7/AN7
27
28
29
30
31
32
33
34
P3.8/MRST
P3.9/MTSR
P3.10/TXD0
P3.11/RXD0
P3.12
P3.13/SCLK
P3.15/CLKOUT
75
76
77
78
79
80
81
P3.0/T0IN
P3.1/T6OUT
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3UED
P3.5/T4IN
P3.6/T3IN
P3.7/T2IN
65
66
67
68
69
70
73
74
Vref
READY
37
97
P1H7
P1H6
P1H5
P1H4
P1H3
P1H2
P1H1
P1H0
135
134
133
132
131
130
129
128
P1L7
P1L6
P1L5
P1L4
P1L3
P1L2
P1L1
P1L0
125
124
123
122
121
120
119
118
P2.0/CC0IO
P2.1/CC1IO
P2.2/CC2IO
P2.3/CC3IO
P2.4/CC4IO
P2.5/CC5IO
P2.6/CC6IO
P2.7/CC7IO
47
48
49
50
51
52
53
54
P2.8/CC8IO/EX0IN
P2.9/CC9IO/EX1IN
P2.10/CC10IO/EX2IN
P2.11/CC11IO/EX3IN
P2.12/CC12IO/EX4IN
P2.13/CC13IO/EX5IN
P2.14/CC14IO/EX6IN
P2.15/CC15IO/EX7IN
57
58
59
60
61
62
63
64
RSTOUT
NMI
141
142
P4.4/A20
P4.5/A21
P4.6/A22
P4.7/A23
89
90
91
92
143139127110 94 83 71 55 45 18
VssVssVssVssVssVssVssVssVssVss
AGND
38
144136129109 93 82 72 56 46 17
VccVccVccVccVccVccVccVccVccVcc
Vcc
55/94
PSD4256G6V
I/O PORTS
There are seven programmable I/O ports: Ports A,
B, C, D, E, F and G. Each port pin is individually
user configurable, thus allowing multiple functions
per port. The ports are configured using PSDsoft
or by the MCU writing to on-chip registers in the
CSIOP space.
The topics discussed in this section are:
General Port architecture
Port operating modes
Port Configuration Registers (PCR)
Port Data Registers
Individual Port functionality.
General Port Architecture
The general architecture of the I/O Port block is
shown in Figure 27. Individual Port architectures
are shown in Figure 29 to Figure 31. In general,
once the purpose for a port pin has been defined,
that pin is no longer available for other purposes.
Exceptions are noted.
As shown inFigure 27, the ports contain an output
multiplexer whose select signals are driven by the
configuration bits in theControl Registers (Ports E,
F and G only) and PSDsoft Configuration. Inputs
to the multiplexer include the following:
Output data from the Data Out register
Latched address outputs
CPLD Macrocell output
External Chip Select from the CPLD.
Figure 27. General I/O Port Architecture
INTERNAL DATA BUS
DATA
OUT
REG.
DQ
D
G
Q
DQ
DQ
WR
WR
WR
ADDRESS
MACROCELL OUTPUTS
ENABLE PRODUCT TERM (.OE)
EXT CS
ALE
READ MUX
P
D
B
CPLD-INPUT
CONTROL REG.
DIR REG.
INPUT
MACROCELL
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT PIN
DATA OUT
ADDRESS
AI02885
PSD4256G6V
56/94
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to theInternal
Data Bus for feedback and can be read by the
MCU. The Data Out and Macrocell outputs, Direc-
tion Register and ControlRegister, and port pin in-
put are all connected to the Port Data Buffer
(PDB).
The Port pin’s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs are not defined
and that port pin is not defined as a CPLD output
in the PSDabel file, the DirectionRegister has sole
control of the buffer that drives the port pin.
The contents of these registers can be altered by
the MCU. The Port Data Buffer (PDB) feedback
path allows the MCU to check the contents of the
registers.
Ports A, B, and C have embedded Input Macro-
cells (IMC). The Input Macrocells (IMC) can be
configured as latches, registers,or direct inputs to
the PLDs. The latches and registers are clocked
by Address Strobe (ALE/AS, PD0) or a product
term from the PLD AND Array. The outputs from
the InputMacrocells (IMC) drive thePLD input bus
and can be read by the MCU. See the section en-
titled “Input Macrocell”, on page 43.
Port Operating Modes
The I/O Ports have several modes of operation.
Some modes can be defined using PSDsoft, some
by the MCU writing to the registers in CSIOP
space, and some by both. The modes that can
only be defined using PSDsoft must be pro-
grammed into the device and cannot be changed
unless the device is reprogrammed. The modes
that can be changed by the MCU can be done so
dynamically at run-time. The PLD I/O, Data Port,
Address Input, Peripheral I/O and MCU Reset
modes are the only modes that must be defined
before programming the device. All other modes
can be changed by the MCU at run-time. See Ap-
plication Note
AN1171
for more detail.
Table 39 summarizes which modes are available
on each port. Table 40 shows how and where the
different modes are configured. Each of the port
operating modes are described in the following
sections.
MCU I/O Mode
In the MCU I/O mode, the MCU uses the PSD
Ports toexpand its own I/O ports. By setting up the
CSIOP space, the ports on the PSD are mapped
into the MCU address space. The addresses of
the ports are listed in Table 6.
A port pin canbe put into MCU I/O mode by writing
a 0 tothe corresponding bitin the Control Register
(for Ports E, F and G). The MCU I/O direction may
be changed by writing to the corresponding bit in
the Direction Register, or by the output enable
product term. See the section entitled “Port Oper-
ating Modes”, on page 56. When the pin is config-
ured as an output, the content of the Data Out
Register drivesthe pin.When configured as an in-
put, the MCU can read the port input through the
Data In buffer. See Figure 27.
Ports A, B and C do not have Control Registers,
and are in MCU I/O mode by default. They can be
used for PLD I/O if they are specified in PSDsoft.
PLD I/O Mode
The PLD I/O Mode uses a port as an input to the
CPLD’s Input Macrocells (IMC), and/or as an out-
put from the CPLD’s Output Macrocells (OMC).
The output can be tri-stated with a control signal.
This output enable control signal can be defined
by a product term from the PLD, or by resetting the
corresponding bit in the Direction Register to 0.
The corresponding bit in the Direction Register
must not be set to 1 if the pin is defined for a PLD
input signal in PSDsoft. The PLD I/O mode is
specified in PSDsoft by declaring the port pins,
and then specifying an equation in PSDsoft.
Address Out Mode
For MCUs with a multiplexed address/data bus,
Address Out mode can be used to drive latched
addresses onto the port pins. These port pins can,
in turn, drive external devices. Either the output
enable orthe corresponding bits of both the Direc-
tion Register and Control Register must be set to
a 1 for pins to use Address Out mode. This must
be done by the MCU at run-time. See Table 41 for
the address outputpin assignments on Ports E, F
and G for various MCUs.
Note: Do not drive address signals with Address
Out Mode to an external memory device if it is in-
tended for the MCU to Boot from the external de-
vice. The MCU must first Boot from PSD memory
so the Direction and Control register bits can be
set.
57/94
PSD4256G6V
Table 39. Port Operating Modes
Note: 1. Can be multiplexed withother I/O functions.
2. Available to Motorola 16-bit 683xx and HC16 families of MCUs.
Table 40. Port Operating Mode Settings
Note: 1. N/A = Not Applicable
2. The direction of the Port A,B,C, and F pins are controlled by the Direction Register ORed withthe individual output enable product
term (.oe) from the CPLD AND Array.
3. Any of these three methods enables the JTAG pins on Port E.
4. Control Register setting is not applicable to Ports A, B and C.
Port Mode Port A Port B Port C Port D Port E Port F Port G
MCU I/O Yes Yes Yes Yes Yes Yes Yes
PLD I/O
McellA Outputs
McellB Outputs
Additional Ext. CS Outputs
PLD Inputs
Yes
No
No
Yes
Yes
Yes
No
Yes
No
No
Yes
Yes
No
No
No
Yes
No
No
No
No
No
No
Yes
Yes
No
No
No
No
Address Out No No No No Yes(A7 0) Yes(A7 0) Yes (A7 0)
or (A15 8)
Address In Yes Yes Yes Yes No Yes No
Data Port No No No No No Yes Yes
Peripheral I/O Yes No No Yes No Yes No
JTAG ISP No No No No Yes1No No
MCU Reset Mode2No No No No No Yes Yes
Mode Defined in PSDsoft Control
Register
Setting
Direction
Register
Setting
VM Register
Setting JTAG Enable
MCU I/O Declare pins only 0 (Note 4)1 = output,
0 = input
(Note 2)N/A N/A
PLD I/O Declare pins and
Logic equations N/A (Note 2)N/A N/A
Data Port (Port F,G) Selected for MCU
with non-multiplexed
bus N/A N/A N/A N/A
Address Out
(Port E, F, G) Declare pins only 1 1 (Note 2)N/A N/A
Address In
(Port A, B, C, D, F)
Declare pins or Logic
equation for Input
Macrocells N/A N/A N/A N/A
Peripheral I/O
(Port F) Logic equations
(PSEL0 and PSEL1) N/A N/A PIO bit = 1 N/A
JTAG ISP 3Declare pins only N/A N/A N/A JTAG_Enable
MCU Reset Mode Specific pin logic level N/A N/A N/A N/A
PSD4256G6V
58/94
Table 41. I/O Port Latched Address Output Assignments
Note: 1. N/A = Not Applicable.
Address In Mode
For MCUs that have more than 16 address sig-
nals, the higher addresses can be connected to
Port A, B,C, D orF, andare routed as inputsto the
PLDs. The address input can be latched in the In-
put Macrocell (IMC) by Address Strobe (ALE/AS,
PD0). Any input that is included in the DPLD equa-
tions for the primary Flash memory, secondary
Flash memory or SRAM isconsidered to be an ad-
dress input.
Data Port Mode
Ports F and G can be used as a data bus port for
a MCU with a non-multiplexed address/data bus.
The Data Port is connected to the data bus of the
MCU. The general I/O functions are disabled in
Ports Fand Gif theports are configured as a Data
Port. Data Port mode is automatically configured
in PSDsoft when a non-multiplexed bus MCU is
selected.
Peripheral I/O Mode
Peripheral I/O mode can be used to interface with
external 8-bit peripherals. In this mode, all of Port
F servesas a tri-state, bi-directional data bufferfor
the MCU. Peripheral I/O mode is enabled by set-
ting bit 7 of the VM Register to a 1. Figure 28
shows howPort A actsas abi-directional buffer for
the MCU data bus if Peripheral I/O mode is en-
abled. An equation for PSEL0 and/or PSEL1 must
be specified in PSDsoft. The buffer is tri-stated
when PSEL0 or PSEL1 is not active.
JTAG In-System Programming (ISP)
Port E is JTAG compliant, and can be used for In-
System Programming (ISP). You can multiplex
JTAG operations with other functions on Port E
because In-System Programming (ISP) is not per-
formed duringnormal systemoperation. For more
information on the JTAG Port, see the section en-
titled “Reset (RESET) Timing”, on page 69.
MCU Reset Mode
Ports F and G can be configured to operate in
MCU Reset mode. This mode is available when
PSD is configured for the Motorola 16-bit 683xx
and HC16 family and is activeonly during reset.
At the rising edge of the Reset input, the MCU
reads the logic level on the data bus (D15-D0)
pins. The MCU then configures some of its I/O pin
functions according to the logic level input on the
data bus lines. Two dedicated buffers are usually
enabled during reset to drive the data bus lines to
the desired logic level.
The PSD can replace the two buffers by configur-
ing Ports F and G to operate in MCU Reset mode.
In this mode, the PSD will drive the pre-defined
logic level or data pattern on to the MCU data bus
when Reset is active and there is no ongoing bus
cycle. After reset, Ports F and G returnto the nor-
mal Data Port mode.
The MCU Reset mode is enabled and configured
in PSDsoft. The user defines the logic level (data
pattern) that will be drive out from Ports F and G
during reset.
Port Configuration Registers (PCR)
Each Port has a set of Port Configuration Regis-
ters (PCR) used for configuration. The contents of
the registers canbe accessed by theMCU through
normal read/write bus cycles at the addresses giv-
en inTable6. The addressesin Table6 are theoff-
sets in hexadecimal from the base of the CSIOP
register.
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, bit 0 in a register refers to bit 0 of its
port. The three Port Configuration Registers
(PCR), shown in Table 42, are used for setting the
Port configurations. The default Power-upstate for
each register in Table 42 is 00h.
Table 42. Port Configuration Registers (PCR)
Note: 1. See Table 46 for Drive Register bit definition.
Control Register
Any bit reset to 0 in the Control Register sets the
corresponding port pin to MCU I/O mode, and a 1
sets it to Address Out mode. The default mode is
MCU I/O. Only Ports E, F and G havean associat-
ed Control Register.
MCU Port E
(PE3-PE0) Port E
(PE7-PE4) Port F
(PF3-PF0) Port F
(PF7-PF4) Port G
(PG3-PG0) Port G
(PG7-PG4)
80C51XA N/A1Address
a7-a4 N/A Address
a7-a4 Address
a11-a8 Address
a15-a12
All Other
MCU with Multiplexed Bus Address
a3-a0 Address
a7-a4 Address
a3-a0 Address
a7-a4 Address
a11-a8 Address
a15-a12
Register Name Port MCU Access
Control E, F,G Write/Read
Direction A, B, C, D,E, F,G Write/Read
Drive Select1A, B, D, E, G Write/Read
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PSD4256G6V
Figure 28. Peripheral I/O Mode
Direction Register
The Direction Register controls the direction of
data flow in the I/O Ports. Any bit set to 1 in the Di-
rection Register causes the corresponding pin to
be an output, and any bit set to 0 causes it to be
an input.The defaultmode for all port pinsis input.
Table 43. Port Pin Direction Control, Output
Enable P.T. Not Defined
Table 44. Port Pin Direction Control, Output
Enable P.T. Defined
Table 45. Port Direction Assignment Example
Figure 29 and Figure 31 show the Port Architec-
ture diagrams for Ports A/B/C and E/F/G, respec-
tively. The direction of data flow for Ports A, B, C
and F are controlled not only by the direction reg-
ister, but also by the output enable product term
from the PLD AND Array. If the output enable
product term is not active, the Direction Register
has sole control of a given pin’s direction.
An example of a configuration for a Port with the
three leastsignificant bits set tooutput and the re-
mainder set to input is shown in Table 45. Since
Port D only contains four pins, the Direction Reg-
ister for Port D has only the four least significant
bits active.
Drive Select Register
The Drive Select Register configures the pin driver
as Open Drainor CMOS. Anexternal pull-up resis-
tor should be used for pins configured as Open
Drain.
A pin can be configured as Open Drain if its corre-
sponding bit in the Drive Select Register is set to a
1. The default pin drive is CMOS.
Table 46 shows the Drive Register for Ports A, B,
D, E and G. It summarizes which pins can be con-
figured as Open Drain outputs.
RD
PSEL0
PSEL1
PSEL
VM REGISTER BIT 7
WR
PA0 -PA7
D0 -D7
DATA BUS
AI02886
Direction Register Bit Port Pin Mode
0 Input
1 Output
Direction
Register Bit Output Enable
P.T. Port Pin Mode
0 0 Input
0 1 Output
1 0 Output
1 1 Output
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00000111
PSD4256G6V
60/94
Table 46. Drive Register Pin Assignment
Note: 1. NA = Not Applicable.
Table 47. Port Data Registers
Port Data Registers
The Port Data Registers, shown in Table 47, are
used by the MCU to write data to or read data from
the ports. Table 47 shows the register name, the
ports having each register type, and MCU access
for each register type. Theregisters are described
next.
Data In
Port pinsareconnected directly tothe Data In buff-
er. In MCU I/O Input mode, the pin input is read
through the Data In buffer.
Data Out Register
Stores output data written by the MCU in the MCU
I/O Output mode. The contents of the Register are
driven out to the pins if the Direction Register or
the output enable product term is set to 1. The
contents of the register can also be read back by
the MCU.
Output Macrocells (OMC)
The CPLD Output Macrocells (OMC) occupy a lo-
cation in the MCU’s address space. The MCU can
read the output of the Output Macrocells (OMC). If
the Mask Macrocell Register bits are not set, writ-
ing to the Macrocell loads data to the Macrocell
flip-flops. See the section entitled Macrocell and I/
O Port”, on page 39.
Mask Macrocell Register
Each Mask Macrocell Register bit corresponds to
an Output Macrocell (OMC) flip-flop. When the
Mask Macrocell Register bit is set to a 1, loading
data into the Output Macrocell (OMC) flip-flop is
blocked. The default value is 0, or unblocked.
Input Macrocells (IMC)
The Input Macrocells (IMC) can be used to latch or
store external inputs. The outputs of the Input
Macrocells (IMC) are routed to the PLD input bus,
and can be read by the MCU. See the section en-
titled “Input Macrocells (IMC)”, on page 43.
Drive
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port A Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain
Port B Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain
Port D NA1NA1NA1NA1Open
Drain Open
Drain Open
Drain Open
Drain
Port E Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain
Port G Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain
Register Name Port MCU Access
Data In A, B, C, D,E, F, G Read input on pin
Data Out A, B, C, D, E, F,G Write/Read
Output Macrocell A, B Read outputs of Macrocells
Write loading Macrocells Flip-flop
Mask Macrocell A, B Write/Read prevents loading into a given
Macrocell
Input Macrocell A, B, C Read outputs of the Input Macrocells
Enable Out A, B, C, F Read the output enable control of the port driver
61/94
PSD4256G6V
Figure 29. Port A, B and C Structure
Enable Out
The Enable Out register can be read by the MCU.
It contains the output enable values for a given
port. A 1 indicates the driver is in output mode. A
0 indicates the driver is intri-state and the pin is in
input mode.
Ports A, B and C Functionality and Structure
Ports A, B and C have similar functionality and
structure, asshown in Figure 29. The ports can be
configured to perform one or more of the following
functions:
MCU I/O Mode
CPLD Output Macrocells McellA7-McellA0
can be connected to Port A. McellB7-McellB0
can be connected to Port B. External Chip
Select (ECS7-ECS0) can be connected to Port
C or Port F.
CPLD Input Via the Input Macrocells (IMC).
Address In Additional high address inputs
using the Input Macrocells (IMC).
Open Drain pins PA7-PA0 can be configured
to Open Drain mode.
INTERNAL DATA BUS
DATA
OUT
Register
DQ
DQ
WR
WR
MCELL7-MCELL0 (Port
A)
MCELLB7-MCELLB0 (Port
B)
Ext.CS (Port C)
ENABLE PRODUCT TERM (.OE)
READ MUX
P
D
B
CPLD-INPUT
DIR Register
INPUT
MACROCELL
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT Pin
DATA OUT
AI04936
PSD4256G6V
62/94
Figure 30. Port D Structure
Port D Functionality and Structure
Port D has fourI/O pins. See Figure30. PortD can
be configured to perform one ormore of the follow-
ing functions:
MCU I/O mode
CPLD Input direct input to the CPLD, no Input
Macrocells (IMC)
Port D pins can be configured in PSDsoft as in-
put pins for other dedicated functions:
Address Strobe (ALE/AS, PD0)
CLKIN (PD1) as input to the Macrocells Flip-
flops and APD counter
PSD Chip Select Input (CSI, PD2). Driving this
signal High disables the Flash memory, SRAM
and CSIOP.
Write EnableHigh-byte (WRH, PD3)input, oras
DBE input from a MC68HC912.
Port E Functionality and Structure
Port E can be configured to perform one or more
of the following functions (see Figure 31):
MCU I/O Mode
In-System Programming (ISP) JTAG port can
be enabled for programming/erase of the PSD
device. (See the section entitled “Reset
(RESET) Timing”, on page 69, for more
information on JTAG programming.)
Open Drain pins can be configured in Open
Drain Mode
Battery Backup features
PE6 canbe configured for a battery input sup-
ply, Voltage Stand-by (VSTBY).
PE7 can be configured as a Battery-on Indi-
cator (VBATON), indicating when VCC is less
than VBAT.
Latched Address output Provide latched
address output.
INTERNAL DATA BUS
DATA
OUT
Register
DQ
DQ
WR
WR
READ MUX
P
D
B
CPLD-INPUT
DIR Register
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT D PIN
DATA OUT
AI04937
63/94
PSD4256G6V
Figure 31. Port E, F and G Structure
Port F Functionality and Structure
Port F can be configured to perform one or more
of the following functions:
MCU I/O Mode
CPLD Output External Chip Select (ECS7-
ECS0) can be connected to Port F or Port C.
CPLD Input direct input to the CPLD, no Input
Macrocells (IMC)
Latched Address output Provide latched
address outputas per Table 41.
Data Port connected to D7-D0 when Port F is
configured as DataPort for a non-multiplexed
bus
Peripheral Mode
MCU Reset Mode for 16-bit Motorola 683xx
and HC16 MCUs
Port G Functionality and Structure
Port G can be configured to perform one or more
of the following functions:
MCU I/O Mode
Latched Address output Provide latched
address output as per Table 41.
Open Drain pins can be configured in Open
Drain Mode
Data Port connected to D15-D8 when Port G
is configured asData Port for anon-multiplexed
bus
MCU Reset Mode for 16-bit Motorola 683xx
and HC16 MCUs
INTERNAL DATA BUS
DATA
OUT
Register
DQ
D
G
Q
DQ
DQ
WR
WR
WR
ADDRESS
Ext. CS (Port F)
ENABLE PRODUCT TERM (.OE)
ALE
READ MUX
P
D
B
CPLD-INPUT (Port F)
CONTROL Register
DIR Register
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT Pin
DATA OUT
ADDRESS
A[7:0] OR A[15:8]
AI04938
ISP or Battery Back-Up (Port E)
Configuration Bit
PSD4256G6V
64/94
POWER MANAGEMENT
The PSD device offers configurable power saving
options. These options may be used individually or
in combinations, as follows:
All memory blocks in a PSD (primary Flash
memory, secondaryFlash memory, andSRAM)
are builtwith powermanagement technology.In
addition to using special silicon design
methodology, power management technology
puts the memories into standby mode when
address/data inputs are not changing (zero DC
current). As soon as a transition occurs on an
input, the affected memory “wakes up”,
changes and latches itsoutputs,thengoesback
to standby. The designer does
not
have to do
anything special to achieve memory Stand-by
mode whenno inputsarechanging—it happens
automatically.
The PLD sections can also achieve Stand-by
mode when its inputs are not changing, as de-
scribed for the Power Management Mode Reg-
isters (PMMR), later.
The Automatic PowerDown (APD)blockallows
the PSD to reduce to stand-by current
automatically. The APD Unit also blocks MCU
address/data signals from reaching the
memories and PLDs. This feature is available
on all PSD devices. The APD Unit is described
in more detail in the section entitled “APD Unit”,
on page 65.
Built in logic monitors the Address Strobe of the
MCU for activity. If there is no activity for a cer-
tain period (the MCU is asleep), the APD Unit
initiates Power-down mode (ifenabled). Once in
Power-down mode,all address/data signals are
blocked from reaching the PSD memories and
PLDs, and the memories are deselected inter-
nally. This allows the memories and PLDs tore-
main in Stand-by modeeven if the address/data
signals are changing state externally (noise,
other devices on the MCU bus, etc.). Keep in
mind that any unblocked PLD inputsignals that
are changing states keeps the PLD out of
Stand-by mode, but not the memories.
PSD Chip Select Input (CSI, PD2) can be used
to disable the internal memories, placing them
in Stand-by modeeven if inputs are changing.
This feature does not block any internal signals
or disable the PLDs. This is a good alternative
to using the APD Unit, especially if your MCU
has a chip select output. There is a slight
penalty in memoryaccess time when PSD Chip
Select Input (CSI, PD2) makes its initial
transition from deselected to selected.
The Power Management Mode Registers
(PMMR) can be written by the MCU at run-time
to manage power. All PSD devices support
“blocking bits” in these registers that are set to
block designated signals from reaching both
PLDs. Current consumption of the PLDs is
directly related to the composite frequency of
the changes on their inputs (see Figure 35).
Significant power savings can be achieved by
blocking signals that are not used in DPLD or
CPLD logic equations at run-time. PSDsoft cre-
ates a fuse map that automatically blocks the
low address byte (A7-A0) or the control signals
(CNTL0-CNTL2, ALE and Write Enable High-
byte (WRH/DBE, PD3)) if none ofthese signals
are used in PLD logic equations.
PSD devices have a Turbo bit in PMMR0. This
bit canbeset toturn theTurbo mode off(the de-
fault is withTurbo mode turned on). WhileTurbo
mode is off, thePLDs can achieve Stand-by cur-
rent when no PLD inputs are changing (zero DC
current). Even when inputs do change, signifi-
cant power can be saved at lower frequencies
(AC current), compared to when Turbomode is
on. When the Turbo mode is on, there is a sig-
nificant DC current component, and the AC
component is higher.
65/94
PSD4256G6V
Figure 32. APD Unit
Automatic Power-down (APD) Unit and Power-
down Mode
The APD Unit, shown in Figure 32, puts the PSD
into Power-down mode by monitoring the activity
of Address Strobe (ALE/AS, PD0). If the APD Unit
is enabled, as soon as activity on Address Strobe
(ALE/AS, PD0) stops, a four bit counter starts
counting. If Address Strobe (ALE/AS, PD0) re-
mains inactive for fifteen clock periods of CLKIN
(PD1), Power-down (PDN) goes High, and the
PSD enters Power-down mode, as discussed
next.
Table 48. Effect of Power-down Mode on Ports
Power-down Mode
By default, if you enable the APD Unit, Power-
down mode is automatically enabled. The device
enters Power-down mode if AddressStrobe (ALE/
AS, PD0) remains inactive for fifteen periods of
CLKIN (PD1).
The following should be kept in mind when the
PSD is in Power-down mode:
If Address Strobe (ALE/AS, PD0) starts pulsing
again, thePSD returnsto normaloperation. The
PSD also returns to normal operation if either
PSD ChipSelect Input (CSI, PD2) is Low or the
Reset (RESET) input is High.
The MCU address/data bus is blocked from all
memory and PLDs.
Various signals can be blocked (prior to Power-
down mode) from entering the PLDs by setting
the appropriate bits in the Power Management
Mode Registers (PMMR). The blocked signals
include MCU control signals and the common
CLKIN (PD1). Note that blocking CLKIN (PD1)
fromthe PLDs does notblock CLKIN (PD1)
fromthe APD Unit.
AllPSD memoriesenter Stand-by modeand are
drawing Stand-by current. However, the PLDs
and I/O ports blocks do
not
go into Stand-by
mode because you do not want to have to wait
for the logic and I/O to “wake-up” before their
outputs can change. See Table 48 for Power-
down mode effects on PSD ports.
Typical Stand-by current is or the order of µA.
ThisStand-by currentvalue assumes that there
are no transitions on any PLD input.
APD EN
PMMR0 BIT 1=1
ALE
RESET
CSI
CLKIN
TRANSITION
DETECTION
EDGE
DETECT
APD
COUNTER
POWER DOWN
(PDN) Select
DISABLE BUS
INTERFACE
Secondary
Flash
Memory Select
Primary
Flash
Memory Select
SRAM Select
PD
CLR
PD
DISABLE Primary and Secondary
FLASH Memory and SRAM
PLD
AI04939
Port Function Pin Level
MCU I/O No Change
PLD Out No Change
Address Out Undefined
Data Port Tri-State
Peripheral I/O Tri-State
PSD4256G6V
66/94
Table 49. PSD Timing and Stand-by Current during Power-down Mode
Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo bit.
2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo bit is 0.
Figure 33. Enable Power-down Flow Chart
Other Power Saving Options
The PSD offers other reduced power saving op-
tions that are independent of the Power-down
mode. Except for the SRAM Stand-by and PSD
Chip Select Input(CSI, PD2) features, they areen-
abled by setting bits in PMMR0 and PMMR2 (as
summarised in Table 23 and Table 24).
PLD Power Management
The power and speed of the PLDs are controlled
by the Turbo bit (bit 3) in PMMR0. By setting the
bit to 1, the Turbo mode is off and the PLDs con-
sume the specified Stand-by current when the in-
puts are not switching for an extended time of
70 ns. The propagation delay time is increased af-
ter the Turbo bitis set to 1 (turnedoff) when the in-
puts change at a composite frequency of less than
15 MHz. When the Turbo bit is reset to 0 (turned
on), the PLDs run at full power and speed. The
Turbo bit affects the PLD’s DC power, AC power,
and propagation delay. See the AC and DC char-
acteristics tables for PLD timing values (Table 67).
Blocking MCU control signalswith the PMMR2 bits
can further reduce PLD AC power consumption.
SRAM Stand-by Mode (Battery Backup)
The PSD supports a battery backup mode in which
the contents ofthe SRAM are retainedin the event
of a power loss. The SRAM has Voltage Stand-by
(VSTBY, PE6) that can be connected to an exter-
nal battery. When VCC becomeslower thanVSTBY
then the PSD automatically connects to Voltage
Stand-by (VSTBY, PE6) as a power source to the
SRAM. The SRAM Stand-by current(ISTBY) is typ-
ically 0.5 µA. The SRAM data retention voltage is
2 V minimum. TheBattery-on Indicator (VBATON)
can be routed to PE7. This signal indicates when
the VCC has dropped below VSTBY, and that the
SRAM is running on battery power.
PSD Chip Select Input (CSI, PD2)
PD2 of Port D can be configured in PSDsoft as
PSD Chip Select Input (CSI). When Low, the sig-
nal selects and enables the internal primary Flash
memory, secondary Flash memory, SRAM, and I/
O blocks for Read or Write operations involving
the PSD. A High on PSD Chip Select Input (CSI,
PD2) disables the primary Flash memory, second-
ary Flash memory, and SRAM, and reduces the
PSD power consumption. However, the PLD and
I/O signals remain operational when PSD Chip Se-
lect Input (CSI, PD2) is High.
There may be a timing penalty when using PSD
Chip Select Input (CSI, PD2) depending on the
speed grade of the PSD that you are using. See
the timing parameter tSLQV in Table 67.
Input Clock
The PSD provides the option to turn off CLKIN
(PD1) to thePLD to save AC power consumption.
CLKIN (PD1)is aninput to thePLD ANDArray and
the Output Macrocells (OMC).
During Power-down mode, or, if CLKIN (PD1) is
not being used as part of the PLD logic equation,
the clock should be disabled to save AC power.
CLKIN (PD1) is disconnected from the PLD AND
Array or the Macrocells block by setting bits 4 or 5
to a 1 in PMMR0.
Mode PLD Propagation Delay Memory Access
Time Access Recovery Time to
Normal Access Typical Stand-by
Current
Power-down Normal tPD (Note 1)No Access tLVDV 50 µA (Note 2)
Enable APD
Set PMMR0 Bit 1 = 1
PSD in Power
Down Mode
ALE/AS
idle
for 15 CLKIN
clocks?
RESET
Yes
No
OPTIONAL
Disable desired inputs to
PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 0 to 6.
AI04940
67/94
PSD4256G6V
Table 50. APDCounter Operation
Input Control Signals
The PSD provides the option to turn off the ad-
dress input (A7-A0) and input control signals
(CNTL0, CNTL1, CNTL2, Address Strobe (ALE/
AS, PD0)and Write Enable High-byte (WRH/DBE,
PD3)) to the PLD to save AC power consumption.
These signals are inputs to the PLD AND Array.
During Power-down mode, or, if any of them are
not being used as part of the PLD logic equation,
these control signals should be disabled to save
AC power. They are disconnected from the PLD
AND Array by setting bits 0, 2, 3, 4, 5 and6 to a 1
in PMMR2.
APD Enable Bit ALE PD Polarity ALE Level APD Counter
0 X X Not Counting
1 X Pulsing Not Counting
1 1 1 Counting (Generates PDN after 15 Clocks)
1 0 0 Counting (Generates PDN after 15 Clocks)
PSD4256G6V
68/94
RESET TIMING AND DEVICE STATUS AT RESET
Power On Reset
Upon Power-up, the PSD requires a Reset (RE-
SET) pulse of duration tNLNH-PO (minimum 1 ms)
after VCC is steady. During this period, the device
loads internal configurations, clears some of the
registers and sets the Flash memory into Operat-
ing mode. After the rising edge of Reset (RESET),
the PSD remains in the Reset mode for an addi-
tional period, tOPR (maximum 120 ns), before the
first memory access is allowed.
The PSD Flash memory is reset to the Read mode
upon Power-up. Sector Select (FS0-FS15 and
CSBOOT0-CSBOOT3) must all be Low, Write
Strobe (WR/WRL, CNTL0) High, during Power On
Reset for maximum security of the data contents
and to remove the possibility of data being written
on the first edge of Write Strobe (WR/WRL,
CNTL0). Any Flash memory Write cycle initiation
is prevented automatically when VCC is below VL-
KO.
Warm Reset
Once the device is up and running, the device can
be reset with a pulse of a much shorter duration,
tNLNH (minimum 150 ns). The same tOPR period is
needed before the device is operational after
warm reset. Figure 34 shows the timing of the
Power-up and warm reset.
I/O Pin, Register and PLD Status at Reset
Table 51 shows the I/O pin, register and PLD sta-
tus during Power On Reset, warm reset and Pow-
er-down mode. PLD outputs are always valid
during warm reset, and they are valid in Power On
Reset oncethe internalPSD Configuration bits are
loaded. This loading of PSD iscompleted typically
long before the VCC ramps up to operating level.
Once the PLD is active,the stateof theoutputs are
determined by equations specified in PSDsoft.
Reset of Flash Memory Erase and Program
Cycles
An external Reset (RESET) also resets the inter-
nal Flash memory state machine. During a Flash
memory Program or Erase cycle, Reset (RESET)
terminates the cycle and returns the Flash memo-
ry to the Read mode within a period of tNLNH-A
(minimum 25 µs).
Table 51. Status During Power-On Reset, Warm Reset and Power-down Mode
Note: 1. The SR_code and Peripheral Mode bits in the VM Register are always cleared to 0 on Power-On Reset or Warm Reset.
Port Configuration Power-On Reset Warm Reset Power-down Mode
MCU I/O Input mode Input mode Unchanged
PLD Output Valid after internal PSD
configuration bits are
loaded Valid Depends on inputs to PLD
(addresses are blocked in
PD mode)
Address Out Tri-stated Tri-stated Not defined
Data Port Tri-stated Tri-stated Tri-stated
Peripheral I/O Tri-stated Tri-stated Tri-stated
Register Power-On Reset Warm Reset Power-down Mode
PMMR0 and PMMR2 Cleared to 0 Unchanged Unchanged
Macrocells Flip-flop status Cleared to 0 by internal
Power-On Reset Depends on .re and .pr
equations Depends on .re and .pr
equations
VM Register1Initialized, based on the
selection in PSDsoft
Configuration menu
Initialized, based on the
selection in PSDsoft
Configuration menu Unchanged
All other registers Cleared to 0 Cleared to 0 Unchanged
69/94
PSD4256G6V
Figure 34. Reset (RESET) Timing
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE
The JTAG Serial Interface on the PSD can be en-
abled onPort E(see Table 52). Allmemory blocks
(primary Flash memory and secondary Flash
memory), PLD logic, and PSD Configuration bits
may be programmed through the JTAG-ISC Serial
Interface. A blank device can be mounted on a
printed circuit board and programmed using JTAG
In-System Programming (ISP).
The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, TDI, and TDO. Twoadditional signals,
TSTAT and TERR, are optional JTAG extensions
used to speed up Program and Erase cycles.
By default, on a blank PSD (as shipped from the
factory, or after erasure), four pins on Port E are
enabled for the basic JTAG signals TMS, TCK,
TDI, and TDO
.
See Application Note
AN1153
for more details on
JTAG In-System Programming (ISP).
Standard JTAG Signals
The standard JTAG signals (TMS, TCK, TDI, and
TDO) canbe enabledby any of three different con-
ditions that are logically ORed. When enabled,
TDI, TDO, TCK, and TMS are inputs, waiting for a
serial command from an external JTAG controller
device (such as FlashLINK or Automated Test
Equipment). When the enabling command is re-
ceived from the external JTAG controller device,
TDO becomes an output and the JTAG channel is
fully functional inside the PSD. The same com-
mand that enables the JTAG channel may option-
ally enable the two additional JTAG pins, TSTAT
and TERR.
The following symbolic logic equation specifies the
conditions enabling the four basic JTAG pins
(TMS, TCK, TDI, and TDO) on their respective
Port E pins. For purposes of discussion, the logic
label JTAG_ON is used. When JTAG_ON is true,
the four pins are enabled for JTAG. When
JTAG_ON is false, the four pins can be used for
general PSD I/O.
JTAG_ON = PSDsoft_enabled +
/* An NVM configuration bit inside the
PSD is set by the designer in the
PSDsoft Configuration utility. This
dedicates the pins for JTAG at all
times (compliant with IEEE 1149.1 */
Microcontroller_enabled +
/* The microcontroller can set a bit at
run-time by writing to the PSD
register, JTAG Enable. This register
is located at address CSIOP + offset
C7h. Setting the JTAG_ENABLE bit in
this register will enable the pins for
JTAG use. This bit is cleared by a PSD
reset or the microcontroller. See
Table 21 for bit definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT) inside
the PSD can be used to enable the JTAG
pins. This PT has the reserved name
JTAGSEL. Once defined as a node in
PSDabel, the designer can write an
equation for JTAGSEL. This method is
used when the Port E JTAG pins are
multiplexed with other I/O signals. It
is recommended to tie logically the
node JTAGSEL to the JEN\ signal on the
Flashlink cable when multiplexing JTAG
signals. See Application Note 1153 for
details. */
The state of the PSD Reset (RESET) signal does
not interrupt (or prevent) JTAG operations if the
JTAG pins are dedicated by an NVM configuration
bit (via PSDsoft). However, Reset (RESET) will
prevent or interrupt JTAG operations if the JTAG
Enable Register (as shown in Table 21) is used to
enable the JTAG pins.
The PSD supports JTAG In-System-Programma-
bility (ISP) commands, but not Boundary Scan.
ST’s PSDsoft software tool and FlashLINK JTAG
programming cable implement the JTAG In-Sys-
tem-Programmability (ISP) commands.
tNLNH-PO tOPR
AI02866b
RESET
tNLNH
tNLNH-A tOPR
VCC VCC(min)
Power-On Reset Warm Reset
PSD4256G6V
70/94
Table 52. JTAG Port Signals
JTAG Extensions
TSTAT and TERR aretwoJTAG extensionsignals
enabled by a JTAG command received over the
four standard JTAG pins (TMS, TCK, TDI, and
TDO). They areusedto speed Program andErase
cycles by indicating status on PSD pins instead of
having to scan the status out serially using the
standard JTAG channel. See Application Note
AN1153
.
TERR indicates if an error has occurred when
erasing a sector orprogramming in Flash memory.
This signal goes Low (active) when an Error con-
dition occurs, and stays Low until a specific JTAG
command is executed or a Reset (RESET) pulse
is received after an “ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy (PE4)
described in the section entitled “Ready/Busy
(PE4)”, on page 23. TSTAT is High when the
PSD4256G6V device is in Read mode (primary
Flash memory and secondary Flash memory con-
tents can be read). TSTAT is Low when Flash
memory Program or Erase cycles are in progress,
and also when datais being written to the second-
ary Flash memory .
TSTAT and TERR can be configured as open-
drain type signals with a JTAG command.
Note: The state of Reset (Reset) does not interrupt
(or prevent) JTAG operations if the JTAG signals
are dedicated by an NVM Configuration bit (via
PSDsoft). However, Reset (Reset) prevents or in-
terrupts JTAGoperations if the JTAG Enable Reg-
ister (as shown in Table 21) is used to enable the
JTAG signals.
Security and Flash memory Protection
When the security bit is set, the device cannot be
read on a Device Programmer or through the
JTAG Port. When using the JTAG Port, only a Full
Chip Erase command is allowed.
All other Program, Erase and Verify commands
are blocked. Full Chip Erase returns the device to
a non-secured blank state. The Security Bit can be
set in PSDsoft.
All primary Flash memory and secondary Flash
memory sectors can individually be sector protect-
ed against erasure. The sector protect bits can be
set in PSDsoft.
INITIAL DELIVERY STATE
When delivered from ST, the PSD device has all
bits in the memory and PLDs set to 1. The PSD
Configuration Register bits are set to 0. Thecode,
configuration, and PLD logic are loaded using the
programming procedure. Information for program-
ming the device is available directly from ST.
Please contact your local sales representative.
Port E Pin JTAGSignals Description
PE0 TMS Mode Select
PE1 TCK Clock
PE2 TDI Serial Data In
PE3 TDO Serial Data Out
PE4 TSTAT Status
PE5 TERR Error Flag
71/94
PSD4256G6V
AC/DC PARAMETERS
These tables describe the AD and DC parameters
of the PSD4256G6V:
DC Electrical Specification
AC Timing Specification
PLD Timing
Combinatorial Timing
Synchronous Clock Mode
Asynchronous Clock Mode
Input Macrocell Timing
MCU Timing
Read Timing
Write Timing
Peripheral Mode Timing
Power-down and Reset Timing
The following are issues concerning the parame-
ters presented:
In the DC specification the supply current is
given for different modes of operation. Before
calculating the total power consumption,
determine the percentage of time that the PSD
is in each mode. Also, the supply power is
considerably different if the Turbo bit is 0.
The AC power component gives the PLD, Flash
memory, and SRAM mA/MHz specification.
Figure 35shows thePLD mA/MHz asafunction
of the number of Product Terms (PT) used.
In the PLD timing parameters, add the required
delay when Turbo bit is 0.
Figure 35. PLD ICC /Frequency Consumption
0
10
20
30
40
50
60 VCC =3V
0101552025
I
CC (mA)
TURBO ON (100%)
TURBO ON (25%)
TURBO OFF
TURBO OFF
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
PT
100%
PT 25%
AI04942
PSD4256G6V
72/94
Table 53. Example of PSD Typical Power Calculation at VCC = 3.0 V (with Turbo Mode On)
Conditions
Highest Composite PLD input frequency
(Freq PLD) = 8 MHz
MCU ALE frequency (Freq ALE) = 4 MHz
% Flash memory
Access =80%
% SRAM access = 15%
% I/O access = 5% (no additional power above base)
Operational Modes
% Normal = 10%
% Power-down Mode = 90%
Number of product terms used
(from fitter report) = 54 PT
% of total product terms = 54/217 = 25%
Turbo Mode = ON
Calculation (using typical values)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 1.2 mA/MHz x Freq ALE
+ %SRAM x 0.8 mA/MHz x Freq ALE
+ % PLD x 1.1 mA/MHz x Freq PLD
+ #PT x 200 µA/PT)
=50µA x 0.90 + 0.1 x (0.8 x 1.2 mA/MHz x 4 MHz
+ 0.15 x 0.8 mA/MHz x 4 MHz
+ 1.1 mA/MHz x 8 MHz
+ 54 x 0.2 mA/PT)
=45µA + 0.1 x (3.84 + 0.48 + 8.8 + 10.8 mA)
=45µA + 0.1 x 23.92
=45µA + 2.39 mA
= 2.43 mA
This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based on IOUT
= 0 mA.
73/94
PSD4256G6V
Table 54. Example of PSD Typical Power Calculation at VCC = 3.0 V (with Turbo Mode Off)
Conditions
Highest Composite PLD input frequency
(Freq PLD) = 8 MHz
MCU ALE frequency (Freq ALE) = 4 MHz
% Flash memory
Access =80%
% SRAM access = 15%
% I/O access = 5% (no additional power above base)
Operational Modes
% Normal = 10%
% Power-down Mode = 90%
Number of product terms used
(from fitter report) = 54 PT
% of total product terms = 54/217 = 25%
Turbo Mode = Off
Calculation (using typical values)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 1.2 mA/MHz x Freq ALE
+ %SRAM x 0.8 mA/MHz x Freq ALE
+ % PLD x (from graph using Freq PLD))
=50µA x 0.90 + 0.1 x (0.8 x 1.2 mA/MHz x 4 MHz
+ 0.15 x 0.8 mA/MHz x 4 MHz
+ 15 mA)
=45µA + 0.1 x (3.84 + 0.48 + 15)
=45µA + 0.1 x 18.84
=45µA + 1.94 mA
= 1.98 mA
This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based on IOUT
= 0 mA.
PSD4256G6V
74/94
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings” table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 55. Absolute Maximum Ratings
Note: 1. IPC/JEDEC J-STD-020A
2. JEDEC StdJESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 150 °C
TLEAD Lead Temperature during Soldering (20 seconds max.)1235 °C
VIO Input and Output Voltage (Q = VOH or Hi-Z) 0.6 4.0 V
VCC Supply Voltage 0.6 4.0 V
VPP Device Programmer Supply Voltage 0.6 13.5 V
VESD Electrostatic Discharge Voltage (Human Body model) 22000 2000 V
75/94
PSD4256G6V
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 56. Operating Conditions
Table 57. AC Symbols for PLD Timing
Example: tAVLX Time from Address Valid to ALE Invalid.
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 2.7 3.6 V
TAAmbient Operating Temperature (industrial) –40 85 °C
Ambient Operating Temperature (commercial) 0 70 °C
Signal Letters Signal Behavior
A Address Input t Time
C CEout Output L Logic Level Low or ALE
D Input Data H Logic Level High
E E Input V Valid
I Interrupt Input X No Longer a ValidLogic Level
L ALE Input Z Float
N Reset Input or Output PW Pulse Width
P Port Signal Output
R UDS, LDS, DS, RD,PSEN Inputs
S Chip Select Input
T R/W Input
W WR Input
BVSTBY Output
M Output Macrocell
PSD4256G6V
76/94
Table 58. AC Measurement Conditions
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Table 59. Capacitance
Note: 1. Sampled only, not 100% tested.
2. Typical values are for TA=25°C and nominal supply voltages.
Figure 36. AC Measurement I/O Waveform Figure 37. AC Measurement Load Circuit
Figure 38. Switching Waveforms Key
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 30 pF
Symbol Parameter Test Condition Typ.2Max.Unit
CIN Input Capacitance (for input pins) VIN =0V 46pF
COUT Output Capacitance (for input/
output pins) VOUT =0V 812pF
CVPP Capacitance (for CNTL2/VPP)V
PP =0V 18 25 pF
0.9VCC
0V
Test Point 1.5V
AI04947
Device
Under Test
2.0 V
400
CL=30
pF
(Including Scope and
Jig Capacitance) AI04948
WAVEFORMS INPUTS OUTPUTS
STEADY INPUT
MAY CHANGE FROM
HI TO LO
MAY CHANGE FROM
LO TO HI
DON’T CARE
OUTPUTS ONLY
STEADY OUTPUT
WI LL BE CHANGI NG
FROM HI TO LO
WI LL BE CHANGI NG
LO TO HI
CHANGING, STATE
UNKNOWN
CENTER LINE IS
TRI-STATE
AI03102
77/94
PSD4256G6V
Table 60. DC Characteristics
Note: 1. Reset (Reset) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC .
2. CSI deselected or internal PD is active.
3. PLD is in non-Turbo mode, and none of the inputs are switching.
4. Please see Figure 35 for the PLD current calculation.
5. IOUT =0mA
Symbol Parameter Conditions Min. Typ. Max. Unit
VIH High Level Input Voltage 2.7 V < VCC < 3.6 V 0.7VCC VCC +0.5 V
VIL Low Level Input Voltage 2.7 V < VCC < 3.6 V –0.5 0.8 V
VIH1 Reset High LevelInput Voltage (Note 1)0.8VCC VCC +0.5 V
VIL1 Reset Low Level Input Voltage (Note 1)–0.5 0.2VCC –0.1 V
VHYS Reset Pin Hysteresis 0.3 V
VLKO VCC (min) for Flash Erase and
Program 1.5 2.3 V
VOL Output Low Voltage IOL =20µA,VCC = 2.7 V 0.01 0.1 V
IOL = 4 mA, VCC = 2.7 V 0.15 0.45 V
VOH Output High Voltage Except
VSTBY On IOH = –20 µA,VCC = 2.7 V 2.6 2.69 V
IOH = –1 mA, VCC = 2.7 V 2.3 2.4 V
VOH1 Output High Voltage VSTBY On IOH1 =–1µAV
STBY 0.8 V
VSTBY SRAM Stand-by Voltage 2.0 VCC V
ISTBY SRAM Stand-by Current VCC =0V 0.5 1 µA
IIDLE Idle Current (VSTBY input) VCC >V
STBY –0.1 0.1 µA
VDF SRAM Data Retention Voltage Only on VSTBY 2V
I
SB Stand-by Supply Current
for Power-down Mode CSI >VCC 0.3 V (Notes 2,3)50 100 µA
ILI Input Leakage Current VSS <V
IN <V
CC –1 ±0.1 1 µA
ILO Output Leakage Current 0.45 < VIN <V
CC –10 ±510 µA
I
CC (DC)
(Note 5)
Operating
Supply
Current
PLD Only
PLD_TURBO = Off,
f = 0 MHz (Note 3)0µA/PT
PLD_TURBO = On,
f=0MHz 200 400 µA/PT
Flash memory During Flash memory Write/
Erase Only 10 25 mA
Read Only, f = 0 MHz 0 0 mA
SRAM f = 0 MHz 0 0 mA
ICC (AC)
(Note 5)
PLD AC Adder note 4
Flash memory AC Adder 1.2 1.8 mA/
MHz
SRAM AC Adder 0.8 1.5 mA/
MHz
PSD4256G6V
78/94
Table 61. CPLD Combinatorial Timing
Table 62. CPLD Macrocell Synchronous Clock Mode Timing
Note: 1. CLKIN (PD1) tCLCL =t
CH +t
CL .
Symbol Parameter Conditions -10 PT
Aloc Turbo
Off Unit
Min Max
tPD CPLD Input Pin/Feedback to
CPLD Combinatorial Output 38 + 4 + 20 ns
tEA CPLD Input to CPLD Output
Enable 43 + 20 ns
tER CPLD Input to CPLD Output
Disable 43 + 20 ns
tARP CPLD Register Clear or
Preset Delay 38 + 20 ns
tARPW CPLD Register Clear or
Preset Pulse Width 28 + 20 ns
tARD CPLD ArrayDelay Any
Macrocell 23 + 4 ns
Symbol Parameter Conditions -10 PT
Aloc Turbo
Off Unit
Min Max
fMAX
Maximum Frequency
External Feedback 1/(tS+tCO)22.7 MHz
Maximum Frequency
Internal Feedback (fCNT)1/(tS+tCO–10) 29.4 MHz
Maximum Frequency
Pipelined Data 1/(tCH+tCL)45.0 MHz
tSInput Setup Time 18 + 4 + 20 ns
tHInput Hold Time 0 ns
tCH Clock High Time Clock Input 11 ns
tCL Clock Low Time Clock Input 11 ns
tCO Clock to Output Delay Clock Input 26 ns
tARD CPLD Array Delay Any Macrocell 23 + 4 ns
tMIN Minimum Clock Period 1tCH+tCL 22 ns
79/94
PSD4256G6V
Table 63. CPLD Macrocell Asynchronous Clock Mode Timing
Symbol Parameter Conditions -10 PT
Aloc Turbo
Off Unit
Min Max
fMAXA
Maximum Frequency
External Feedback 1/(tSA+tCOA)23.8 MHz
Maximum Frequency
Internal Feedback (fCNTA)1/(tSA+tCOA–10) 31.25 MHz
Maximum Frequency
Pipelined Data 1/(tCHA+tCLA) 38.4 MHz
tSA Input Setup Time 8 + 4 + 20 ns
tHA Input Hold Time 10 ns
tCHA Clock High Time 15 + 20 ns
tCLA Clock Low Time 12 + 20 ns
tCOA Clock to Output Delay 34 + 20 ns
tARD CPLD Array Delay Any Macrocell 23 + 4 ns
tMINA Minimum Clock Period 1/fCNTA 32 ns
PSD4256G6V
80/94
Figure 39. Input to Output Disable / Enable
Figure 40. Asynchronous Reset / Preset
Figure 41. Synchronous Clock Mode Timing PLD
Figure 42. Asynchronous Clock Mode Timing (product term clock)
tER tEA
INPUT
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
tARP
REGISTER
OUTPUT
tARPW
RESET/PRESET
INPUT
AI02864
tCH tCL
tCO
tH
tS
CLKIN
INPUT
REGISTERED
OUTPUT
AI02860
tCHA tCLA
tCOA
tHAtSA
CLOCK
INPUT
REGISTERED
OUTPUT
AI02859
81/94
PSD4256G6V
Table 64. Input Macrocell Timing
Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX .
Figure 43. Input Macrocell Timing (product term clock)
Symbol Parameter Conditions -10 PT
Aloc Turbo
Off Unit
Min Max
tIS Input Setup Time (Note 1)0ns
t
IH Input Hold Time (Note 1)25 + 20 ns
tINH NIB Input High Time (Note 1)13 ns
tINL NIB Input Low Time (Note 1)12 ns
tINO NIB Input to Combinatorial
Delay (Note 1)55 +4 +20 ns
t
INH tINL
tINO
tIH
tIS
PT CLOCK
INPUT
OUTPUT
AI03101
PSD4256G6V
82/94
Table 65. Read Timing
Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing for 8031.
3. Any input used to select an internal PSD function.
4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
Symbol Parameter Conditions -10 Turbo
Off Unit
Min Max
tLVLX ALE or AS Pulse Width 22 ns
tAVLX Address Setup Time (Note 3)7ns
t
LXAX Address Hold Time (Note 3)8ns
t
AVQV Address Valid to Data Valid (Note 3)100 + 20 ns
tSLQV CS Valid to Data Valid 100 ns
tRLQV
RD to Data Valid 8-Bit Bus (Note 5)35 ns
RD or PSEN to Data Valid 8-Bit Bus,
8031, 80251 (Note 2)45 ns
tRHQX RD Data Hold Time (Note 1)0ns
t
RLRH RD Pulse Width 36 ns
tRHQZ RD to Data High-Z (Note 1)38 ns
tEHEL E Pulse Width 38 ns
tTHEH R/W Setup Time to Enable 10 ns
tELTL R/W Hold Time After Enable 0 ns
tAVPV Address Input Valid to
Address Output Delay (Note 4)35 ns
83/94
PSD4256G6V
Figure 44. Read Timing
Note: 1. tAVLX and tLXAX are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.
tAVLX tLXAX1
tLVLX
tAVQV
tSLQV
tRLQV tRHQX
tRHQZ
tELTL
tEHEL
tRLRH
tTHEH
tAVPV
ADDRESS
VALID
ADDRESS
VALID
DATA
VALID
DATA
VALID
ADDRESS OUT
ALE/AS
A/D
MULTIPLEXED
BUS
ADDRESS
NON-MULTIPLEXED
BUS
DATA
NON-MULTIPLEXED
BUS
CSI
RD
(PSEN, DS)
E
R/W
AI02895
PSD4256G6V
84/94
Table 66. Write Timing
Note: 1. Any input used to select an internal PSD function.
2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active write signal.
5. Assuming write is active before data becomes valid.
6. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
7. tWHAX is 11 ns when writing to the Output Macrocell Registers.
Symbol Parameter Conditions -10 Unit
Min Max
tLVLX ALE or AS Pulse Width 22
tAVLX Address Setup Time (Note 1)7ns
t
LXAX Address Hold Time (Note 1)8ns
t
AVWL Address Valid to Leading
Edge of WR (Notes 1,3)15 ns
tSLWL CS Valid to Leading Edge of WR (Note 3)15 ns
tDVWH WR Data Setup Time (Note 3)40 ns
tWHDX WR Data Hold Time (Note 3,7)5ns
t
WLWH WR Pulse Width (Note 3)40 ns
tWHAX1 Trailing Edge of WR to Address Invalid (Note 3)8ns
t
WHAX2 Trailing Edge of WR to DPLD Address
Invalid (Note 3,6)0ns
t
WHPV Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register (Note 3)45 ns
tDVMV Data Valid to Port Output Valid
Using Macrocell Register Preset/Clear (Notes 3,5)65 ns
tAVPV Address Input Valid to Address
Output Delay (Note 2)35 ns
tWLMV WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear (Notes 3,4)65 ns
85/94
PSD4256G6V
Figure 45. Write Timing
tAVLX tLXAX
tLVLX
tAVWL
tSLWL
tWHDX
tWHAX
tELTL
tEHEL
tWLMV
tWLWH
tDVWH
tTHEH
tAVPV
ADDRESS
VALID
ADDRESS
VALID
DATA
VALID
DATA
VALID
ADDRESS OUT
tWHPV
STANDARD
MCU I/O OUT
ALE/AS
A/D
MULTIPLEXED
BUS
ADDRESS
NON-MULTIPLEXED
BUS
DATA
NON-MULTIPLEXED
BUS
CSI
WR
(DS)
E
R/ W
AI02896
PSD4256G6V
86/94
Table 67. Port F Peripheral Data Mode Read Timing
Figure 46. Peripheral I/O Read Timing
Symbol Parameter Conditions -10 Turbo
Off Unit
Min Max
tAVQV–PF Address Valid to Data Valid (Note 3)50 + 20 ns
tSLQV–PF CSI Valid to Data Valid 50 + 20 ns
tRLQV–PF RD to Data Valid (Notes 1,4)35 ns
RD to Data Valid 8031 Mode 45 ns
tDVQV–PF Data In to Data Out Valid 34 ns
tQXRH–PF RD Data Hold Time 0 ns
tRLRH–PF RD Pulse Width (Note 1)35 ns
tRHQZ–PF RD to Data High-Z (Note 1)38 ns
tQXRH (PF)
tRLQV (PF)
tRLRH (PF)
tDVQV (PF)
tRHQZ (PF)
tSLQV (PF)
tAVQV (PF)
ADDRESS
DATA VALID
ALE/AS
A/D BUS
RD
DATA ON PORT F
CSI
AI05740
87/94
PSD4256G6V
Table 68. Port F Peripheral Data Mode Write Timing
Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN(in 8031 combined mode).
2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port F Data Peripheral mode.
4. Data is already stable on Port F.
5. Data stable on ADIO pins to data on Port F.
Figure 47. Peripheral I/O Write Timing
Table 69. Power-down Timing
Note: 1. tCLCL is the period of CLKIN (PD1).
Symbol Parameter Conditions -10 Unit
Min Max
tWLQV–PF WR to Data Propagation Delay (Note 2)40 ns
tDVQV–PF Data to Port A Data Propagation Delay (Note 5)35 ns
tWHQZ–PF WR Invalid to Port A Tri-state (Note 2)33 ns
tDVQV (PF)
tWLQV (PF) tWHQZ (PF)
ADDRESS
DATA OUT
A/D BUS
WR
PORT F
DATA OUT
ALE/AS
AI05741
Symbol Parameter Conditions -10 Unit
Min Max
tLVDV ALE Access Time from Power-down 128 ns
tCLWH Maximum Delay from APD Enable to
Internal PDN Valid Signal Using CLKIN
(PD1) 15 * tCLCL1µs
PSD4256G6V
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Table 70. Reset (Reset) Timing
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in Read mode.
Figure 48. Reset (RESET) Timing
Table 71. VSTBYON Timing
Note: 1. VSTBYON timing ismeasured at VCC ramp rate of 2 ms.
Table 72. Program, Write and Erase Times
Note: 1. Programmed to all zero before erase.
2. The polling status, DQ7, is valid tQ7VQV timeunits before the data byte, DQ0-DQ7, is valid for reading.
3. DQ7 is DQ15 for Motorola MCU with 16-bit data bus.
Symbol Parameter Conditions Min Max Unit
tNLNH RESET Active Low Time 1300 ns
tNLNH–PO Power On Reset ActiveLow Time 1 ms
tNLNH–A Warm Reset Active Low Time 225 µs
tOPR RESET High to Operational Device 300 ns
Symbol Parameter Conditions Min Typ Max Unit
tBVBH VSTBY Detection to VSTBYON Output High (Note 1)20 µs
tBXBL VSTBY Off Detection to VSTBYON Output
Low (Note 1)20 µs
Symbol Parameter Min. Typ. Max. Unit
Flash Program 8.5 s
Flash Bulk Erase1(pre-programmed) 330s
Flash Bulk Erase (not pre-programmed) 10 s
tWHQV3 Sector Erase (pre-programmed) 1 30 s
tWHQV2 Sector Erase (not pre-programmed) 2.2 s
tWHQV1 Byte Program 14 1200 µs
Program / Erase Cycles (per Sector) 100,000 cycles
tWHWLO Sector Erase Time-Out 100 µs
tQ7VQV DQ7 Valid to Output (DQ7-DQ0) Valid(Data Polling)2,3 30 ns
tNLNH-PO tOPR
AI02866b
RESET
tNLNH
tNLNH-A tOPR
VCC VCC(min)
Power-On Reset Warm Reset
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PSD4256G6V
Table 73. ISC Timing
Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For Program or Erase PLD only.
Figure 49. ISC Timing
Symbol Parameter Conditions -10 Unit
Min Max
tISCCF Clock (TCK, PC1) Frequency (except for PLD) (Note 1)15 MHz
tISCCH Clock (TCK, PC1) High Time (except forPLD) (Note 1)30 ns
tISCCL Clock (TCK, PC1) Low Time (except for PLD) (Note 1)30 ns
tISCCFP Clock (TCK, PC1) Frequency (PLD only) (Note 2)2 MHz
tISCCHP Clock (TCK, PC1) High Time (PLD only) (Note 2)240 ns
tISCCLP Clock (TCK, PC1) Low Time (PLD only) (Note 2)240 ns
tISCPSU ISC Port Set Up Time 11 ns
tISCPH ISC Port Hold Up Time 5 ns
tISCPCO ISC Port Clock to Output 26 ns
tISCPZV ISC Port High-Impedance to Valid Output 26 ns
tISCPVZ ISC Port Valid Output to
High-Impedance 26 ns
ISCCH
TCK
TDI/TMS
ISC OUTPUTS/TDO
ISC OUTPUTS/TDO
t
ISCCL
t
ISCPH
t
ISCPSU
t
ISCPVZ
t
ISCPZV
tISCPCO
t
AI02865
PSD4256G6V
90/94
PACKAGE MECHANICAL
TQFP80 - 80 lead Plastic Quad Flatpack
Note: Drawing is not to scale.
TQFP80 - 80 lead Plastic Quad Flatpack
Symb. mm inches
Typ. Min. Max. Typ. Min. Max.
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 0.950 1.050 0.0374 0.0413
α3.5°0.0°7.0°3.5°0.0°7.0°
b 0.220 0.170 0.270 0.0087 0.0067 0.0106
c 0.090 0.200 0.0035 0.0079
D 14.000 0.5512
D1 12.000 0.4724
D2 9.500 0.3740
E 14.000 0.5512
E1 12.000 0.4724
E2 9.500 0.3740
e 0.500 0.0197
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
CP 0.080 0.0031
N80 80
Nd 20 20
Ne 20 20
QFP-A
Nd
E1
CP
b
e
A2
A
N
LA1 α
D1
D
1
ENe
c
D2
E2
L1
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PSD4256G6V
Table 74. Pin Assignments TQFP80
Pin No. Pin
Assign
ments Pin No. Pin
Assign
ments Pin No. Pin
Assign
ments Pin No. Pin
Assign
ments
1 PD2 21 PG0 41 PC0 61 PB0
2 PD3 22 PG1 42 PC1 62 PB1
3 AD0 23 PG2 43 PC2 63 PB2
4 AD1 24 PG3 44 PC3 64 PB3
5 AD2 25 PG4 45 PC4 65 PB4
6 AD3 26 PG5 46 PC5 66 PB5
7 AD4 27 PG6 47 PC6 67 PB6
8 GND 28 PG7 48 PC7 68 PB7
9V
CC 29 VCC 49 GND 69 VCC
10 AD5 30 GND 50 GND 70 GND
11 AD6 31 PF0 51 PA0 71 PE0
12 AD7 32 PF1 52 PA1 72 PE1
13 AD8 33 PF2 53 PA2 73 PE2
14 AD9 34 PF3 54 PA3 74 PE3
15 AD10 35 PF4 55 PA4 75 PE4
16 AD11 36 PF5 56 PA5 76 PE5
17 AD12 37 PF6 57 PA6 77 PE6
18 AD13 38 PF7 58 PA7 78 PE7
19 AD14 39 RESET 59 CNTL0 79 PD0
20 AD15 40 CNTL2 60 CNTL1 80 PD1
PSD4256G6V
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PART NUMBERING
Table 75. Ordering Information Scheme
For a list of available options (speed, package,
etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Of-
fice.
Example: PSD42 5 6 G 6 V 90 U I T
Device Type
PSD42 = Flash PSD for 16-bit MCUs (with CPLD)
SRAM Size
0 = none 3 = 64 Kbit
1 = 16 Kbit 4 = 128 Kbit
2 = 32 Kbit 5 = 256 Kbit
Flash Memory Size
1 = 256 Kbit 4 = 2 Mbit
2 = 512 Kbit 5 = 4 Mbit
3 = 1 Mbit 6 = 8 Mbit
I/O Count
F = 27 I/O
G=52 I/O
2nd Non Volatile
Memory
1 = 256 Kbit EEPROM
2 = 256 Kbit Flash memory
3 = none
6 = 512 Kbit Flash memory
Operating Voltage
V=V
CC = 2.7 to 3.6V
Speed
70=70ns 12=120ns
90 = 90 ns 15 = 150 ns
10 = 100 ns 20 = 200 ns
Package
U = TQFP80
Temperature Range
blank = 0 to 70 °C (commercial)
I = –40 to 85 °C (industrial)
Option
T = Tape & Reel Packing
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PSD4256G6V
REVISION HISTORY
Table 76. Document Revision History
Date Rev. Description of Revision
06-Aug-2001 1.0 Document written
13-Sep-2001 1.1 Package mechanical data updated
14-Dec-2001 1.2 Added 100ns specification; removed 90 and 120 ns specifications. Updated AC specification
and Port C and F functions
PSD4256G6V
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