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ST10F269
June 2002
■HIGH PERFORMANCE 40MHz CPU WITH DSP
FUNCTION
– 16-BIT CPU WITH 4-STAGE PIPELINE
– 50ns INSTRUCTION CYCLE TIME AT 40MHz MAX
CPU CLOCK
– MULTIPLY/ACCUMULATE UNIT (MAC) 16 x 16-BIT
MULTIPLICATION, 40-BIT ACCUMULATOR
– REPEAT UNIT
– ENHANCED BOOLEAN BIT MANIPULATION FA-
CILITIES
– ADDITIONAL INSTRUCTIONS TO SU PPORT HLL
AND OPERATING SYSTEMS
– SINGLE-CYCLE CONTEXT SWITCHING SUP-
PORT
■MEMORY ORGANIZATION
– 256K BYTE ON-CHIP FLASH MEMORY SINGLE
VOLT AG E WITH E RASE/ PROG RAM CONTR OL LER.
– 100K ERASING/PROGRAMMING CYCLES.
– UP TO 16M BY TE LIN EAR AD DRE SS SPAC E FOR
CO DE AND DATA (5M BYTES WI TH CAN)
– 2K BYTE ON-CHI P INTERNAL RAM (IRAM)
– 10K BYTE ON-CHIP EXTENSION RAM (XRAM)
■FAST AND FLEXIBLE BUS
– PROGRAMMABLE EXTERNAL BUS CHARACTE -
RISTICS FOR DIFFERENT ADDRESS RANGES
– 8-BIT OR 16-BIT EX TERNAL DATA BUS
– M ULTIPL EXED OR DEM ULTIPLEXED EXTERNAL
AD DRESS/DATA BUSES
– FIVE PROGRAMMABLE CHIP-SELECT SIGNALS
– HOLD- A CK NOW L E DG E BU S ARBITRATION SU P-
PORT
■INTERRUPT
– 8-CHANNEL PERIPHERAL EVENT CONTROLLER
FOR SINGLE CYCLE INTERRUPT DRIVEN DATA
TRANSFER
– 16-PRIORITY-LEVEL IN TERRUPT SY STEM WITH
56 SOURCES, SAMPLING RATE DOWN TO 25ns
■TIMERS
– TWO MULTI-FUNCTIONAL GENERAL PURPOSE
TIMER UNITS WITH 5 T IMERS
■TWO 16-CHANNEL CAPTURE / C OMPARE UNITS
■A/D CONVERTER
– 16-CHANNEL 10-BIT
– 4.85
µ
s CONVERSION TIME AT 40MHz CPU CLOCK
■4-CHANNEL PW M UNIT
■SERIAL CHANNELS
– SYNCHRONOUS / ASYNCHRONOUS SE RIAL
CHANNEL
– HIGH- SPEED SYNCHRONOUS CHANNEL
■TWO CAN 2.0B INTERFACES OPERATING ON ONE
OR TWO CAN BUSSES (30 OR 2x15 MESSAGE
OBJECTS)
■FAIL-SAFE PROTECTION
– PROGRAMMABLE WATCHDOG TIMER
– OSCILLATOR WA TCHDOG
■ON- CH I P BO OTST RA P LOADER
■CLOCK GENERATION
– ON-CHIP PLL
– DIRECT OR PRESCALED CLOCK INPUT
■REAL TIM E CLOCK
■UP TO 111 GENERAL PURPOSE I/O LINES
– INDIVIDUALLY PROGRAMMABLE AS INPUT,
OUTPUT OR SPECIAL FUNCTION
– PROGRAMMABLE THRESHOLD (HYSTERESIS)
■IDLE AND POWER DOWN MODES
■SINGLE VOLTAGE SUPPLY: 5V ±10% (EMBEDDED
R EGULATOR FOR 3. 3 V CORE SUPPLY).
■TEMPER ATURE RA NGE: -40 +125°C
■144-PIN PQFP PACKAGE
PQFP144 (28 x 28 mm)
(Plastic Q u ad Flat Pack )
O RDER CODE: ST10F269-Q3
CAN2_TXD
CAN1_TXD
CAN1_RXD
CAN2_RXD
Port 0
Port 1Por t 4
Port 6 Port 5 Port 3
Port 2
GPT1
ASC usart
BRG
CPU -Core and MAC Unit Internal
RAM
Watchdog
Interrupt Controller
8
32 16
PEC
16
16
CAN1
Port 7 Port 8
External Bus
10-Bit ADC
BRG
SSC
PWM
CAPCOM2
CAPCOM1
16
Oscillator
Controller
16
16
256K Byte
and PLL
Flash Mem ory
XTAL1 XTAL2
2K Byte
16 15 88
8
16
3.3V Voltage
Regulator
10K Byte
XRAM
CAN2
GPT2
16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM
PRELIMINARY DATA
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
ST10F269
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TABLE OF CONTENTS PAGE
1 - INTRO DUCTIO N .... ............ ....... ............ ....... ............ ............ ....... ............ ....... ............ 6
2 - PIN DATA ................................................................................................................... 7
3 - FUNCTIONAL DESCRI PTION .. ........................ ....... ....... ........................ ....... ....... ..... 13
4 - MEMOR Y ORGANIZATION ....................................................................................... 14
5 - INTERNAL FLASH MEMORY ........... ........ ....... ................................... ....... ....... ........ 17
5.1 - OVERVIEW ................................................................................................................ 17
5.2 - OPERATIONAL OVERVIEW ...................................................................................... 17
5.3 - ARCHITECTURAL DESCRIPTION ............................................................................ 19
5.3.1 - Read Mode ................................................................................................................. 19
5.3.2 - Command Mode ......................................................................................................... 19
5.3.3 - Ready/B usy Signal ..................................................................................................... 19
5.3.4 - Flash Status Register ................................................................................................. 19
5.3.5 - Flash Protection Register ........................................................................................... 21
5.3.6 - Instructions Descrip tion .............................................................................................. 21
5.3.7 - Reset Process ing and Initial State . ............................................................................. 25
5.4 - FLASH MEMORY CONF IGURATION ........................................................................ 25
5.5 - APPLICATION EXAMPLES ....................................................................................... 25
5.5.1 - Handling of Flash Add resses ...................................................................................... 25
5.5.2 - Basic Flash Access Control ........................................................................................ 26
5.5.3 - Programmin g Examples ............................................................................................. 27
5.6 - BOOTSTRAP LOADER ............................................................................................ 30
5.6.1 - Entering the Bootstrap Loade r .................................................................................... 30
5.6.2 - Memory Configuration After Reset ............................................................................. 31
5.6.3 - Loading the Startup Code ........................................................................................... 32
5.6.4 - Exiting Bootstrap Loader Mode ....................................................... ................... ........ 32
5.6.5 - Choosin g the Baud Rate for the BSL ......................................................................... 33
6 - CENTRAL PROCESSING UNIT (CPU) ..................................................................... 34
6.1 - MULTIPLIER-ACCUMULATOR UNIT (MAC) ............................................................. 35
6.1.1 - Features ..................................................................................................................... 36
6.1.1. 1 - Enhanced A ddres sing Capabilit ies.............................................. ............................... . 36
6.1.1.2 - Multiply-Accum ulate Unit............................................................................................. 36
6.1.1 .3 - Pr o g r a m Cont r o l............. ............ ....... ............ ....... ............ ....... ............ ............ ....... ..... 36
6.2 - INSTRUCTION SET SUM MARY ................................................................................ 37
6.3 - MAC COPROCESSOR SPECIFIC INSTRUCTIONS ................................................. 38
7 - EXTERNAL BUS CONTROLLER .. ................................... ....... ....... ........................ ... 42
7.1 - PROGRAMMABLE CHIP SELECT TIMING CONTROL ............................................ 42
7.2 - READY PROGRAMMABLE POLARITY ..................................................................... 42
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TABLE O F CONTENTS PAGE
8 - INTERRUPT SYSTEM .............. ....... ............ ....... ............ ....... ............ ............ ....... ..... 44
8.1 - EXTERNAL INTERRUPTS ......................................................................................... 44
8.2 - INTERRUPT REGIST ERS AND VECTORS L OCATION LIST .................................. 45
8.3 - INTERRUPT CONTROL REGISTERS ....................................................................... 46
8.4 - EXCEPTION AND ERROR TRAPS LIST ................................................................... 47
9 - CAPTURE/COMPARE (CAPCOM) UNITS ................................................................ 48
10 - GENERAL PURPOSE T IMER UNIT .......................................................................... 51
10.1 - GPT1 .......................................................................................................................... 51
10.2 - GPT2 .......................................................................................................................... 52
11 - PWM MODULE ........ ........ ........... ............ ....... ............ ....... ............ ....... ............ .......... 54
12 - PARALLEL PORTS .... ............ ....... ............ ....... ............ ....... ........... ............ ....... ........ 55
12.1 - INTRODUCTION ........................................................................................................ 55
12.2 - I/O’ S SPECIAL FEATURES ....................................................................................... 57
12.2.1 - Open Drain Mode ....................................................................................................... 57
12.2.2 - Input Threshold Control ............................................................................................ 57
12.2.3 - Output D river Control ................................................................................................58
12.2.4 - Alte rnate Port Functio ns ............................................................................................. 60
12.3 - PORT0 ........................................................................................................................ 61
12.3.1 - Alte rnate Functi ons of PORT0 .................................................................................... 62
12.4 - PORT1 ........................................................................................................................ 64
12.4.1 - Alte rnate Functi ons of PORT1 .................................................................................... 64
12.5 - PORT 2 ....................................................................................................................... 66
12.5.1 - Alte rnate Functi ons of Port 2 ...................................................................................... 66
12.6 - PORT 3 ....................................................................................................................... 69
12.6.1 - Alte rnate Functi ons of Port 3 ...................................................................................... 70
12.7 - PORT 4 ....................................................................................................................... 73
12.7.1 - Alte rnate Functi ons of Port 4 ...................................................................................... 74
12.8 - PORT 5 ....................................................................................................................... 77
12.8.1 - Alte rnate Functi ons of Port 5 ...................................................................................... 78
12.8.2 - Port 5 Schmitt Trigger Analog Inp uts .... ...................................................................... 79
12.9 - PORT 6 ....................................................................................................................... 79
12.9.1 - Alte rnate Functi ons of Port 6 ...................................................................................... 80
12.1 0 - PORT 7 .............. ....... ............ ....... ............ ....... ............ ............ ....... ............ ....... .......... 83
12.10.1 - Alte rnate Functi ons of Port 7 ...................................................................................... 84
12.1 1 - PORT 8 .............. ....... ............ ....... ............ ....... ............ ............ ....... ............ ....... .......... 87
12.11.1 - Alte rnate Functi ons of Port 8 ...................................................................................... 88
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TABLE OF CONTENTS PAGE
13 - A/D CONVERTER ................ ............ ....... ............ ....... ............ ....... ............ ............ ..... 90
14 - SER IAL CHANNELS ......... ....... ............ ....... ............ ............ ....... ............ ....... ............ 91
14.1 - ASYNCHRONOUS / SYNCHRONOUS SERIAL INTERFACE (ASCO ) .................... 91
14.1.1 - ASCO in Asynchronous Mode ........................................... .............. ................... ........ 91
14.1.2 - ASCO in Synchronous Mode ............................................. .............. ................... ........ 93
14.2 - HIGH SPEED SYNCHRONOUS SERIAL CHANNEL (SSC) ............... ....... ....... ........ 95
15 - CAN MODULES ... ....... ............ ....... ....... ............ ....... ............ ....... ............ ....... ............ 97
15.1 - CAN MODULES MEMORY MAPPIN G ...................................................................... 97
15.1.1 - CAN1 .......................................................................................................................... 97
15.1.2 - CAN2 .......................................................................................................................... 97
15.2 - CAN BUS CONFIGURATIONS .................................................................................. 97
16 - REAL TIM E CLOCK .................................................................................................. 99
16.1 - RTC REGISTERS ...................................................................................................... 100
16.1.1 - RTCCON: RTC Control Register ................................................................................ 100
16.1.2 - RTCPH & RT CPL: RTC PRESCALER Registers ....................................................... 101
16.1.3 - RTCDH & RTCDL: R TC DIVIDER Counters .............................................................. 101
16.1.4 - RTCH & R TCL: RTC Programmable COUNTER Registers ....................................... 102
16.1.5 - RTCAH & RT CAL: RTC ALARM Registers ................................................................ 1 03
16.2 - PROGRAMMING THE RTC ....................................................................................... 103
17 - WATCHDOG TIMER ..... ....... ............ ....... ............ ....... ............ ....... ............ ....... .......... 105
18 - SYSTEM RESET ........................................................................................................ 1 07
18.1 - LONG HARDWARE RESET ...................................................................................... 107
18.1.1 - Asynchronous Re set .................................................................................................. 107
18.1.2 - Synchronous Reset (RSTIN pulse > 1040TCL and RPD pin at high level) ................ 108
18.1.3 - Exit of Long Ha rdware R eset ...................................................................................... 1 09
18.2 - SHORT HARDWARE RESE T .................................................................................... 1 09
18.3 - SOFTWARE RESET .................................................................................................. 110
18.4 - WATCHDOG TIMER RESET ..................................................................................... 110
18.5 - RSTOUT, RSTIN, BIDIRECTIONAL RESET ............................................................ 111
18.5.1 - RSTOUT Pin ............................................................................................................... 1 11
18.5.2 - Bidirectional Reset . ..................................................................................................... 111
18.5.3 - RSTIN p in ................................................................................................................... 111
18.6 - RESET CIRCUITRY ................................................................................................... 1 11
19 - POWER REDUCTION MODES ................................................................................. 1 14
19.1 - IDLE M ODE ................................................................................................................114
19.2 - POWER DOWN MODE .............................................................................................. 114
19.2.1 - Protected Power Down Mode . .................................................................................... 1 14
19.2.2 - Interruptable Power Down Mode ................................................................................ 1 14
ST10F269
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TABLE O F CONTENTS PAGE
20 - SPECIAL FUNCTION REGISTER OVERVIEW ......................................................... 117
20.1 - IDENTIFICAT ION REGISTERS ................................................................................. 1 23
20.2 - SYSTEM CONFIGURATION REGISTERS ................................................................ 1 24
21 - ELECT RICAL CHARACTERI STI CS .... ....... ............................................... ....... ........ 131
21.1 - ABSOLUTE MAXIMUM RATINGS ............................................................................. 131
21.2 - PARAMETER INTERPRETATION ............................................................................. 131
21.3 - DC CHARACTERISTICS ........................................................................................... 1 31
21.3.1 - A/D Converter Characteristics .................................................................................... 1 34
21.3.2 - Conversion Timing Control ....................................................................................... 135
21.4 - AC CHARACTERISTICS ............................................................................................ 1 36
21.4.1 - Test Waveforms .......................................................................................................136
21.4.2 - Definition of Internal Ti ming ........................................................................................ 136
21.4.3 - Clock Generat ion Modes ............................................................................................ 1 37
21.4.4 - Prescaler Operation ....................................................................................................138
21.4.5 - Direct Drive ................................................................................................................. 1 38
21.4.6 - Oscillator Watchdog (OW D) ....................................................................................... 1 38
21.4.7 - Phas e Locked Loop .................................................................................................... 1 38
21.4.8 - External Clock Drive XT AL1 ....................................................................................... 1 39
21.4.9 - Memory Cycle Variables ............................................................................................. 140
21.4.10 - Multiplexed Bus .......................................................................................................... 1 41
21.4.11 - Demultiplexed Bus ...................................................................................................... 147
21.4.12 - CLKOUT and READY ................................................................................................. 153
21.4.13 - External Bus Arbitration ..............................................................................................155
21.4.14 - High-Spee d Synchronou s Serial Interface (SSC) Timing . .......................................... 157
21.4.14.1 Master Mo de................................................................................................................ 157
21.4.14.2 Slave mode.................................................................................................................. 158
22 - PACKAGE MECHANICAL DATA ..................................... ....... ....... ....... ....... .......... 159
23 - ORDERING IN FORMATION ...................................................................................... 159
ST10F269
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1 - INTRODUCTION
The ST10F269 is a derivative of the
STMicroelectronics ST10 family of 16-bit
single-chip CMOS microcontrollers. It combines
high CPU performance (up to 20 million
instructions per second) with high peripheral
funct ionality and enhanced I/O-capabili ties. It also
provides on-chip high-speed single voltage Flash
memory, on-chip high-speed RAM, and clock
generation via PLL.
ST10F269 is processed in 0.35µm CMOS
technology. The MCU core and the logic is
supplied with a 5V to 3.3V on chip voltage
regulator. The part is supplied with a single 5V
supply and I/Os work at 5V.
The device is upward compatible with the
ST10F168 device, with the following set of
differences:
– The Multiply/Accumulate unit is available as
standard. This MAC unit adds powerful DSP
functions to the ST10 architecture, but maintains
full compatibility for existing code.
– Flash control interface is now based on
STMicroelectronics third generation of
stand-alone Flash memories, with an embedded
Erase/Program Controller. This completely
frees up the CPU during programming or
erasing the Flash.
– Two dedicated pins (DC1 and DC2) on the
PQFP-144 package are used for decoupling the
internally generated 3.3V core logic supply. Do
not connec t these two pins to 5.0V exter nal
supply. Instead, these pins should be
connected to a decoupling capacitor (ceramic
type, value ≥ 330 nF).
– The A/D Converter characteristics are different
from previous ST10 derivatives ones. Refer to
Section 21.3.1 - A/D Converter Characteristics.
– The A C and DC pa rameters are adapt ed to the
40MHz maximum CPU frequency. The
characterization is performed with CL = 50pF
max on output pins. Refer to Section 21.3 DC
Characteristics.
– In order to reduce EMC, the rise/fall time and the
sink/source capability of the drivers of the I/O
pads are programmable. Refer to Secti on 12.2 I /
O’s Special Features.
– T he Real Ti me Clock functionnality is added.
– The ex t ernal interrupt sources can be selected
with the EXIS EL register.
– The reset source is identified by a dedicated
status bit in the WDTCON register.
Fi gure 1 : Logic Sym bol
XTAL1
RSTIN
XTAL2
RSTOUT
NMI
EA
READY
ALE
RD
WR/WRL
Port 5
16-bit
Port 6
8-bit
Port 4
8-bit
Port 3
15-bit
Port 2
16-bit
Port 1
16-bit
Port 0
16-bit
VDD VSS
Po rt 7
8-bit
Port 8
8-bit
VAREF
VAGND
RPD
DC1 DC2
ST10F269
ST10F269
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2 - PIN DATA
Fi gure 2 : Pin Configuration (top view)
P6.0/CS0
P6.1/CS1
P6.2/CS2
P6.3/CS3
P6.4/CS4
P6.5/HOLD
P6.6/HLDA
P6.7/BREQ
P8.0/CC16IO
P8.1/CC17IO
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO
P8.6/CC22IO
P8.7/CC23IO
DC2
VSS
P7.0/POUT0
P7.1/POUT1
P7.2/POUT2
P7.3/POUT3
P8.5/CC21IO
RPD
P7.4/CC28I0
P7.5/CC29I0
P7.6/CC30I0
P7.7/CC31I0
P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.6/AN6
P5.7/AN7
P5.8/AN8
P5.9/AN9
P0H.0/AD8
P0L.7/AD7
P0L.6/AD6
P0L.5/AD5
P0L.4/AD4
P0L.3/AD3
P0L.2AD2
P0L.A/AD1
P0L.0/AD0
EA
ALE
READY
WR/WRL
RD
VSS
VDD
P4.7A23/CAN2_TxD
P4.6A22/CAN1_TxD
P4.5A21/CAN1_RxD
P4.4A20/CAN2_RxD
P4.3/A19
P4.2/A18
P4.1/A17
P4.0/A16
VSS
VDD
P3.15/CLKOUT
P3.13/SCLK
P3.12/BHE/WRH
P3.11/RXD0
P3.10/TXD0
P3.9/MTSR
P3.8/MRST
P3.7/T2IN
P3.6/T3IN
V
AREF
V
AGND
P5.10/AN10/T6EUD
P5.11/AN11/T5EUD
P5.12/AN12/T6IN
P5.13/AN13/T5IN
P5.14/AN14/T4EUD
P5.15/AN15/T2EUD
VSS
VDD
P2.0/CC0IO
P2.1/CC1IO
P2.2/CC2IO
P2.3/CC3IO
P2.4/CC4IO
P2.5/CC5IO
P2.6/CC6IO
P2.7/CC7IO
VSS
DC1
P2.8/CC8IO/EX0IN
P2.9/CC9IO/EX1IN
P2.10/CC10IOEX2IN
P2.11/CC11IOEX3IN
P2.12/CC12IO/EX4IN
P2.13/CC13IO/EX5IN
P2.14/CC14IO/EX6IN
P2.15/CC15IO/EX7IN/T7IN
P3.0/T0IN
P3.1/T6OUT
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3EUD
P3.5/T4IN
VSS
VDD
VSS
NMI
VDD
RSTOUT
RSTIN
VSS
XTAL1
XTAL2
VDD
P1H.7/A15/CC27IO
P1H.6/A14/CC26IO
P1H.5/A13/CC25IO
P1H.4/A12/CC24IO
P1H.3/A11
P1H.2/A10
P1H.1/A9
P1H.0/A8
VSS
VDD
P1L.7/A7
P1L.6/A6
P1L.5/A5
P1L.4/A4
P1L.3/A3
P1L.2/A2
P1L.1/A1
P1L.0/A0
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
P0H.2/AD10
P0H.1/AD9
VSS
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
ST10F269-Q3
ST10F269
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Table 1 : Pin Descriptio n
Symbol Pin Type Function
P6.0 - P6.7 1 - 8 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. P r ogrammin g a n I/ O p in a s inp ut fo rces the corr espon ding out put dr iver to h igh
impedance state. Port 6 outputs can be configured as push-pull or open drain
drivers. The following Port 6 pins have alternate functions:
1 O P6.0 CS0 Chip Select 0 Output
... ... ... ... ...
5 O P6.4 CS4 Chip Select 4 Output
6 I P6.5 HOLD External Master Hold Request Input
7 O P6.6 HLDA Hold Acknowledge Output
8 O P6.7 BREQ Bus Request Output
P8.0 - P8.7 9-16 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. P r ogrammin g a n I/ O p in a s inp ut fo rces the corr espon ding out put dr iver to h igh
impedance state. Port 8 outputs can be configured as push-pull or open drain
drivers. The input threshold of Port 8 is selectable (TTL or special).
The following Port 8 pins have alternate functions:
9 I/O P8.0 CC16IO CAPCOM2: CC16 Capture Input / Compare Output
... ... ... ... ...
16 I/O P8.7 CC23IO CAPCOM2: CC23 Capture Input / Compare Output
P7.0 - P7.7 19-26 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. P r ogrammin g a n I/ O p in a s inp ut fo rces the corr espon ding out put dr iver to h igh
impedance state. Port 7 outputs can be configured as push-pull or open drain
drivers. The input threshold of Port 7 is selectable (TTL or special).
The following Port 7 pins have alternate functions:
19 O P7.0 POUT0 PWM Channel 0 Output
... ... ... ... ...
22 O P7.3 POUT3 PWM Channel 3 Output
23 I/O P7.4 CC28IO CAPCOM2: CC28 Capture Input / Compare Output
... ... ... ... ...
26 I/O P7.7 CC31IO CAPCOM2: CC31 Capture Input / Compare Output
P5.0 - P5.9
P5.10 - P5.15 27-36
39-44 I
I16-bit in put-o nly port wi th Sch mitt-Tr ig ger cha racter istic s. The pins of Port 5 can be
the a nalog inp ut c hann els ( up to 1 6) for the A/D co nverter, wh ere P5.x equ als A Nx
(Analog input channel x), or they are timer inputs:
39 I P5.10 T6EUD GPT2 Timer T6 External Up / Down Control Input
40 I P5.11 T5EUD GPT2 Timer T5 External Up / Down Control Input
41 I P5.12 T6IN GPT2 Timer T6 Count Input
42 I P5.13 T5IN GPT2 Timer T5 Count Input
43 I P5.14 T4EUD GPT1 Timer T4 External Up / Down Control Input
44 I P5.15 T2EUD GPT1 Timer T2 External Up / Down Control Input
ST10F269
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P2.0 - P2.7
P2.8 - P2.15 47-54
57-64 I/ O 16-bit bidirectional I/O por t, bit-wise programmable for input or output via direc tion
bit. P r ogrammin g a n I/ O p in a s inp ut fo rces the corr espon ding out put dr iver to h igh
impedance state. Port 2 outputs can be configured as push-pull or open drain
drivers. The input threshold of Port 2 is selectable (TTL or special).
The following Port 2 pins have alternate functions:
47 I/O P2.0 CC0IO CAPCOM: CC0 Capture Input / Compare Output
... ... ... ... ...
54 I/O P2.7 CC7IO CAPCOM: CC7 Capture Input / Compare Output
57 I/O P2.8 CC8IO CAPCOM: CC8 Capture Input / Compare Output
I EX0IN Fast External Interrupt 0 Input
... ... ... ... ...
64 I/O P2.15 CC15IO CAPCOM: CC15 Capture Input / Compare Output
I EX7IN Fast External Interrupt 7 Input
I T7IN CAPCOM2 Timer T7 Count Input
P3.0 - P3.5
P3.6 - P3.13,
P3.15
65-70,
73-80,
81
I/O
I/O
I/O
15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input for ces the corresponding
output driver to high impedance state. Port 3 outputs can be configured as push-pull
or open drain drivers. The input threshold of Port 3 is selectable (TTL or special).
The following Port 3 pins have alternate functions:
65 I P3.0 T0IN CAPCOM Timer T0 Count Input
66 O P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output
67 I P3.2 CAPIN GPT2 Register CAPREL Capture Input
68 O P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output
69 I P3.4 T3EUD GPT1 Timer T3 External Up / Down Control Input
70 I P3.5 T4IN GPT1 Timer T4 Input for Count / Gate / Reload / Capture
73 I P3.6 T3IN GPT1 Timer T3 Count / Gate Input
74 I P3.7 T2IN GPT1 Timer T2 Input for Count / Gate / Reload / Capture
75 I/O P3.8 MRST SSC Master-Receiver / Slave-Transmitter I/O
76 I/O P3.9 MTSR SSC Master-Transmitter / Slave-Receiver O/I
77 O P3.10 TxD0 ASC0 Clock / Data Output (Asynchronous /
Synchronous)
78 I/O P3.11 RxD0 ASC0 Data Input (Asynchronous) or I/O (Synchronous)
79 O P3.12 BHE External Memory High Byte Enable Signal
WRH External Memory High Byte Write Strobe
80 I/O P3.13 SCLK SSC Master Clock Output / Slave Clock Input
81 O P3.15 CLKOUT System Clock Output (=CPU Clock)
Symbol Pin Type Function
ST10F269
10/160
P4.0 –P4.7 85-92 I/O P o rt 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output
via direction bit. Pro gramming an I/O pin as input forces the corresponding output
driver to hig h impedance state. The input threshold is selectable (TTL or special).
Port 4.6 & 4.7 outputs can be configured as push-pull or open drain drivers.
In case of an extern al bus confi guration , Por t 4 ca n b e u sed to o utpu t the se gmen t
address lines:
85 O P4.0 A16 Segment Address Line
86 O P4.1 A17 Segment Address Line
87 O P4.2 A18 Segment Address Line
88 O P4.3 A19 Segment Address Line
89 O P4.4 A20 Segment Address Line
I CAN2_RxD CAN2 Receive Data Input
90 O P4.5 A21 Segment Address Line
I CAN1_RxD CAN1 Receive Data Input
91 O P4.6 A22 Segment Address Line
O CAN1_ TxD CAN1 Transmit Data Outpu t
92 O P4.7 A23 Most Significant Segment Address Line
O CAN2_ TxD CAN2 Transmit Data Outpu t
RD 95 O External Memory Read Strobe. RD is activated for ev ery external instruction or data
read access.
WR/WRL 96 O Exte rnal M emor y Write Str obe. In WR- mode this pin is a ctivated for every ex terna l
data write access. In WRL mode this pin is activated for low Byte data write
accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See
WRCFG in the SYSCON register for mode selection.
READY/
READY 97 I Ready Input. The active level is programmable. When the Ready function is
enabled, the selected inactive level at this pin, during an ex terna l memor y acc ess,
will for ce the insertion of wait state c ycles until t he pin returns to the se lected active
level.
ALE 98 O Address Latch Enable Output. In case of use of external addressing or of multi-
plexed mode, this signal is the latch command of the address lines.
EA 99 I Exte rnal Acces s Enable pin. A low level applied to this pin during and after Rese t
forces the ST 10F2 69 t o start the pro gram fro m t he exter na l me mory space. A high
level forces the MCU to start in the internal memory space.
Symbol Pin Type Function
ST10F269
11/160
P0L.0 - P0L.7,
P0H.0
P0H.1 - P0H.7
100-107,
108,
111-117
I/O Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input for ces the corresponding
output driver to high impedance state.
In c ase of an exter nal bus configu ra tion, PORT0 ser ves as the address (A) and as
the address / data (AD) bus in multiplexed bus modes and as the data (D) bus in
demultiplexed bus modes.
Demultiplexed bus modes
Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: D0 – D7 D0 - D7
P0H.0 – P0H.7 I/O D8 - D15
Multip lexed bus modes
Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7
P0H.0 – P0H.7 A8 – A15 AD8 - AD15
P1L.0 - P1L.7
P1H.0 - P1H.7 118-125
128-135 I/O Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input for ces the corresponding
output driver to high impedance state. PORT1 is used as the 16-bit address bus (A)
in demultiplexed bus modes and also after switching from a demultiple x ed bus mode
to a multiplexed bus mode.
The following PORT1 pins have alternate functions:
132 I P1H.4 CC24IO CAPCOM2: CC24 Capture Input
133 I P1H.5 CC25IO CAPCOM2: CC25 Capture Input
134 I P1H.6 CC26IO CAPCOM2: CC26 Capture Input
135 I P1H.7 CC27IO CAPCOM2: CC27 Capture Input
XTAL1 138 I XTAL1 Oscillator amplifier and/or external clock input.
XTAL2 137 O XTAL2 Oscillator amplifier circuit output.
To clock the device from an external source, drive XTAL1 while leaving XTAL2
unconnected. Minimum and maximum high / low and rise / fall times specified in the
AC Characteristics must be observed.
RSTIN 140 I Reset Input with Schmitt-Trigger characteristics. A low lev el at this pin f or a specified
duration while the oscillator is running resets the ST10F269. An internal pull-up
resistor permits power-on reset using only a capacitor connected to VSS. In bidi rec-
tional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the
RSTIN line is pulled low for the duration of the internal reset sequence.
RSTOUT 141 O Internal Reset Indication Output. This pin is driven to a low level during hardware,
software or watchdo g timer res et.
RSTOUT
remains low until the EINI T (end of ini-
tialization) instruction is executed.
NMI 142 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to
vector to th e NMI trap routine. If bi t PWDCFG = ‘0’ in SYSCON register, when the
PWRD N ( power d own) i nstr uctio n is exe cuted, the NMI pin mu st b e low in or der to
force the ST10F269 to go into power down mode. If NMI is high and PWDCFG =’0’,
when PWRDN is executed, the part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
VAREF 37 - A/D converter reference voltage.
VAGND 38 - A/D converter reference ground.
RPD 84 - Timing pin for the return from interruptible powerdown mode and synchronous /
asynchronous reset selection.
Symbol Pin Type Function
ST10F269
12/160
VDD 46, 72,
82,93,
109,
126,
136, 144
- Digital Supply Voltage:
= + 5V during normal operation and idle mode.
VSS 18,45,
55,71,
83,94,
110,
127,
139, 143
- D igital Groun d.
DC1
DC2 56
17 -
-3.3V Decoupling pin: a decoupling capacitor of ≥ 330 nF must be connected
between this pin and nearest VSS pin.
Symbol Pin Type Function
ST10F269
13/160
3 - FUNCTIONAL DESCRIPTION
The architecture of the ST10F269 combines
advantages of both RISC and CISC processors
and an advanced peripheral subsystem. The
block diagram gives an overview of the different
on-chip components and the high bandwidth
inte rnal bus structure of the ST10F269.
Fi gure 3 : Block Diagram
P4.7 CAN2_TXD
P4.6 CAN1_TXD
P4.5 CAN1_RXD
P4.4 CAN2_RXD
Port 0
Port 1Port 4
Port 6 Port 5 Port 3
Port 2
GPT1
GPT2
ASC usa rt
BRG
CPU-Co re and MAC Uni t Internal
RAM
Watchdog
Interrupt Controller
8
32 16
PEC
16
16
CAN1
Port 7 Port 8
Exte rnal Bus
10-Bit ADC
BRG
SSC
PWM
CAPCOM2
CAPCOM1
16
Oscillator
Controller
16
16
256K Byt e
and PLL
Flash Memory
XTAL1 XTAL2
2K Byte
16 15 88
8
16
3.3V Voltage
Regulator
10K Byte
XRAM
CAN2
ST10F269
14/160
4 - MEMO RY ORGA NI ZA T IO N
The memory space of the ST10F269 is configured
in a unified memory architecture. Code memory,
data memory, registers and I/O ports are
organized within the same linear address space of
16M Bytes. The entire memory space can be
accessed Byte wise or Word wise. Particular
portions of the on-chip memory have additionally
been mad e directly bit addressable.
Flash: 256K Bytes of on-chip Flash memory.
IRAM: 2K Bytes of on-chip internal RAM
(dual-port) is provided as a storage for data,
system sta ck, general purpose register banks and
cod e. A register bank is 16 Wordwide (R0 to R15)
and / or Bytewide (RL0, RH0, …, RL7, RH7)
general purpose registers.
XRAM: 10K Bytes of on-chip extension RAM
(single port XRAM) is provided as a storage for
data, us er stack and code.
The XRAM is divided into 2 areas, the first 2K
Bytes named XRAM1 and the second 8K Bytes
named XRAM2, connected to the internal XBUS
and are accessed like an external memory in
16-bit demultiplexed bus-mode without wait state
or read/write delay (50ns access at 40MHz CPU
clock). Byte and Word acc ess es are allowed.
The XRAM1 address range is 00’E000h
- 00’E7FFh if XPEN (bit 2 of SYSCON register),
and XRAM1EN (bit 2 of XPERCON register) are
set. If XRAM1EN or XPEN is cleared, then any
access in the address r ange 00’E000h - 00’E7FFh
will be directed to external memory interface,
using the BUSCONx register corresponding to
addres s matching AD DRSELx register
The XRAM2 address range is 00’C000h
- 00’DFFFh if XPEN (bit 2 of SYSCON register),
and XRAM 2 (bit 3 of X PERCON register are set).
If bit XRAM2EN or XPEN is cleared, then any
access in the address range 00’C000h
- 00’DFFFh will be directed to external memory
interface, using the BUSCONx register
corresponding to address matching ADDRSELx
register.
As the XRAM appears like external memory, it
cannot be used as system stack or as register
banks. The XRAM is not provided for single bit
storage and therefore is not bit addressable.
SFR/ESFR: 1024 Bytes (2 x 512 Bytes) of
addre ss space i s res erved for the speci al fu nction
register areas. SFRs are Wordwide registers
which are used to control and to monitor the
funct ion of the different on-chip units.
CAN1: Address range 00’EF00h - 00’EFFFh is
reserved for the CAN1 Module access . The CAN1
is enabled by setting XPEN bit 2 of the SYSCON
register and by setting CAN1EN bit 0 of the new
XPERCON register. Accesses to the CAN Module
use demultiplexed addresses and a 16-bit data
bus (Byte acc esse s are pos sible). Two wait states
give an access time of 100ns at 40MHz CPU
clock. No tri-state wait states are used.
CAN2: Address range 00’EE00h - 00’EEFFh is
reserved for the CAN2 Module access . The CAN2
is enabled by setting XPEN bit 2 of the SYSCON
register and by setting CAN2EN bit 1 of the new
XPERCON register. Accesses to the CAN Module
use demultiplexed addresses and a 16-bit data
bus (Byte acc esse s are pos sible). Two wait states
give an access time of 100ns at 40MHz CPU
clock. No tri-state wait states are used.
In order to meet the needs of designs where more
memory is required than is provided on chip , up to
16M Bytes of external RAM and/or ROM can be
connected to the microcontroller .
Note If one or the two CAN modules are used,
Port 4 c an not be programmed t o output al l
8 segment address lines. Thus, only 4
segment address lines can be used,
reducing the external memory space to 5M
Byte s (1M Byte per CS line).
Visibility of XBU S Periphe rals
In order to keep the ST10F269 compatible with
the ST10C167 and with the ST10F167, the XBUS
peri phera ls can be selected to be visible and / or
accessible on the external address / data bus.
CAN1EN and CAN2EN bits of XPERCON register
must be set. If these bits are cleared before the
global enabling with XPEN-bit in SYSCON
register, the corresponding address space, port
pins and interrupts are not occupied by the
peripheral, thus the peripheral is not visible and
not available. Refer to Chapter 20 - Special
Funct ion Register Overv iew.
ST10F269
15/160
Fi gure 4 : ST10F2 69 On-c hip Memo ry Mapping
14
07
06
05
04
00’4000
01
00
00’0000
02
00’C000
00’FFFF
SFR : 51 2 Bytes
00’FE00
00’FDFF
IRAM : 2K Bytes
00’F600
* Bank 0L may be remapped from segm ent 0 to s egm ent 1 (B ank 1L) by set t in g SY SC ON-ROM S 1 (befor e EI NIT)
RAM, SFR and X-pheripherals are
mapped int o the addres s sp ace.
Segment 4Segment 3Segment 2Segment 1Segme nt 0
Data
Page
Number
Absolute
Memory
Address
00’6000
00’F1FF
ES F R : 51 2 By t es
00’F000
00’EFFF
CAN1 : 25 6 By t e s
00’EF00
00’EEFF
CAN2 : 25 6 By t e s
00’EE00
00’E7FF
XRAM1 : 2K Byte s
00’E000
00’DFFF
XRAM2 : 8K Byte s
00’C000
03
00’EC14
Real Time Clock
00’EC00
Block 2 = 8K Bytes
Internal
Flash
Memory
Block 1 = 8K Bytes
Block 0 = 16K Bytes
Bank OL
01’0000
01’8000
02’0000
03’0000
0C
04’0000
10
05’0000
Block 6 = 64K Bytes
Block 5 = 64K Bytes
Block 4 = 64K Bytes
Block 3 = 32K B yt es
Block2*
Block1*
Block0* Bank 1L
Bank 1H
Data Page Num ber and Abs ol ute Memory A ddress ar e hexadec i m al values.
08
ST10F269
16/160
XPERCON (F02 4h / 12h ) ESFR Reset Value: - - 05h
Note: - When both CAN are disabled via XPER-
CON setting, then any access in the
address range 00’EE00h - 00’EFFFh will
be directed to external memory interface,
using the BUSCONx register correspond-
ing to address matchi ng ADDRSELx regis-
ter. P4.4 and P4.7 can be used as General
Purpose I/O when CAN2 is disabled, and
P4.5 and P4.6 can be used as General
Purpose I/O when CAN1 is disabled.
- The default XPER selection after Reset is
identical to XBUS configuration of
ST10C167: XCAN1 is enabled, XCAN2 is
disabled, XRAM1 (2K Byte compatible
XRAM) is enabled, XRAM2 (new 8K Byte
XRAM) is disa bled.
- Register XPERCON cannot be changed
after the global enabling of XPeripherals,
i.e. after the setting of bit XPEN in the
SYSCON register.
- In EMUla tion mode, all the XPERipherals
are enabled (XPERCON bit are all set).
The access to external memory and/or
XBus is controlled by the bondout chip.
- When the Real Time Clock is disabled
(RTCEN = 0), the clock oscillator is
switch-off if the ST10 enters in
power-down mode. Otherwise, when the
Real Time Clock is enabled, the bit
RTCOFF of the RTCCON register allows
to choose the power-down mode of the
clock oscillator (See Chapter 16 - Real
Time Clock).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-----------
RTCEN XRAM2EN XRAM1EN CAN2EN CAN1EN
RW RW RW RW RW
CAN1EN CAN1 Enable Bit
‘0’: Accesses to the on-chip CAN1 XP eripheral and its functions are disabled. P4.5 and P4.6 pins can be
used as general purpose I/Os. Address range 00’EF00h-00’EFFFh is only directed to external memory if
CAN2EN is also ‘0’.
‘1’: The on-chip CAN1 XPeripheral is enabled and can be accessed.
CAN2EN CAN2 Enable Bit
‘0’: Accesses to the on-chip CAN2 XP eripheral and its functions are disabled. P4.4 and P4.7 pins can be
used as general purpose I/Os. Address range 00’EE00h-00’EEFFh is only directed to external memory if
CAN1EN is also ‘0’.
‘1’: The on-chip CAN2 XPeripheral is enabled and can be accessed.
XRAM1EN XRAM1 Enable Bit
‘0’: Accesses to external memory within space 00’E000h to 00’E7FFh. The 2K Bytes of internal XRAM1
are disabled.
’1’: Accesses to the internal 2K Bytes of XRAM1.
XRAM2EN XRAM2 Enable Bit
‘0’: Accesses to the external memory within space 00’C000h to 00’DFFFh. The 8K Bytes of internal
XRAM2 are disabled.
’1’: Accesses to the internal 8K Bytes of XRAM2.
RTCEN RTC Enable Bit
’0’: Accesses to the on-chip Real Time Clock are disabled, external access is performed. Address range
00’EC00h-00’ECFFh is only directed to external memory if CAN1EN and CAN2EN are ’0’ also
’1’: The on-chip Real Time Clock is enabled and can be accessed.
ST10F269
17/160
5 - INTERNAL FLASH MEMORY
5.1 - Overview
– 256K Byte on-chip Flash memory
– Two possibilities of Flash mapping into the CPU
address space
– Flash memory can be used for code and data
storage
– 32-bit, zero waitstate read access (50ns cycle
time at fCPU = 40 MHz)
– Erase-Program Controller (EPC) similar to
M29F400B S TM ’s stand-alone Flash m emo ry
• W ord-by-Word P rogrammabl e (16µs t ypic a l)
• Data polling and Toggle Protocol for EPC
Status
• Ready/Busy signal connected on XP2INT
inte r ru pt line
• Int ernal Power-On detec tion circuit
– M em ory Erase in blocks
• O ne 16K Byte, two 8K Byte, o ne 3 2K By te,
three 64K Byte blocks
• Each block can be erased separately
(1.5 second typical)
• C hip erase (8.5 second typical )
• Each block can be separately protected
against programming and erasing
• Each protected block can be temporary unpro-
tected
• When enabled, the read protection prevents
access to data in Flash memory using a pro-
gram running out of the Flash memory space.
Access to data of internal Flash can only be per-
formed with an inner protected program
– E ras e Su spend and Resume Modes
• Read and Program another Block during erase
suspend
– S ing le V oltage operation , no need of dedicat ed
supply pin
– Low Power Consum ption:
• 4 5mA max . Read current
• 6 0mA m ax. Program or Erase current
• Automatic Stand-by-mode (50µA maximum)
– 100,000 Erase-Program Cycles per block,
20 years of data retention time
– Operat ing tempe rature: -40 to +125oC
5.2 - Operational Overview
Read Mode
In standard mode (the normal operating mode)
the Flash appears like an on-chip ROM with the
same timing and functionality. The Flash module
offers a fast access time, allowing zero waitstate
access with CPU frequency up to 40MHz.
Instruction fetches and data operand reads are
performed with all addressing modes of the
ST 10F2 69 instr uction set.
In order to optimize the programming time of the
internal Flash, blocks of 8K Bytes, 16K Bytes,
32K Bytes, 64K Bytes can be used. But the size of
the blocks does not apply to the whole memory
spa ce, see details in Table 2.
Table 2 : 256K Byte Flash Mem ory Block Organisation
Block Addresses (Segment 0) Addresses (Segment 1) Size (byte)
0
1
2
3
4
5
6
00’0000h to 00’3FFFh
00’4000h to 00’5FFFh
00’6000h to 00’7FFFh
01’8000h to 01’FFFFh
02’0000h to 02’FFFFh
03’0000h to 03’FFFFh
04’0000h to 04’FFFFh
01’0000h to 01’3FFFh
01’4000h to 01’5FFFh
01’6000h to 01’7FFFh
01’8000h to 01’FFFFh
02’0000h to 02’FFFFh
03’0000h to 03’FFFFh
04’0000h to 04’FFFFh
16K
8K
8K
32K
64K
64K
64K
ST10F269
18/160
Instruction s and Command s
All operations besides normal read operations are
initiated and controlled by command sequences
wr itten t o the Flash Com mand Interface (CI). T he
Command Interface (CI) interprets words written
to the Flash memory and enables one of the
following operations:
– Read me mory ar r ay
– P rogram Word
– Block Erase
– Chip Erase
– E ras e Su spend
– E ras e Resum e
– B lock Pro tection
– B lock Tem porary Unprot ection
– Code Protection
Commands are composed of several write cycles
at specific addresses of the Flash memory. The
different write cycles of such command
sequences offer a fail-safe feature to protect
against an inadvertent write.
A command only starts when the Command
Interface has decoded the last write cycle of an
operation. Until that last wr ite is perform ed, Flash
memory remains in Read Mode
Notes: 1. As it is not possible to perform write
operations in the Flash while fetching code
from Flash, the Flash commands must be
written by instructions executed from
internal RAM or external memory.
2. Command write cycles do not need to
be consecutively received, pauses are
allowed, save for Block Erase command.
During this operation all Erase Confirm
commands must be sent to complete any
block erase operation before time-out
period expires (typically 96µs). Command
sequencing must be followed exactly. Any
in valid combination of commands will reset
the Command Interface to Read Mode.
Status R e gister
This register is used to flag the status of the
memory and the result of an operation. This
register can be accessed by read cycles during
the Erase-Program Controller (EPC) operation.
Erase Operation
This Flash memory features a block erase
architecture with a chip erase capability too . Erase
is accomplished by executing the six cycle erase
command sequence. Additional command write
cycles can then be perfor m ed to erase more than
one block in parallel. When a time-out period
elaps (96µs) after the last cycle, the
Erase-Program Controller (EPC) automatically
starts and times the erase pulse and executes the
erase operation. There is no nee d to program the
block to be erased with ‘0000h’ before an erase
operation . Ter mination of operation is indicated i n
the Flash status register. After erase operation,
the Flash memory locations are read as 'FFFFh’
value.
Erase Suspend
A block erase operation is typically executed
within 1.5 second for a 64K Byte block. Erasure of
a memory block may be suspended, in order to
read data from another block or to program data in
anoth er bl ock, and then resumed.
In-System P rogramming
In-system programming is fully supported. No
special program ming voltage is required. Because
of the automatic execution of erase and
programming algorithms, write operations are
reduced to transferring commands and data to the
Flash and reading the status. Any code that
programs or erases Flash mem ory lo cations (that
writes data to the Flash) must be executed from
memory outside the on-chip Flash memory itself
(on-chip RAM or external memory).
A boot mechanism is provided to support
in-system programming. It works using serial link
via USAR T interface and a PC compatib le or other
prog ramming host.
Read/W rite Protection
The Flash module supports read and write
protection in a very comfortable and advanced
protection functionality. If Read Protection is
installed, the whole Flash memory is protected
against any "external" read access; read
accesses are only possible with instructions
fetched directly from program Flash memory. For
update of the Flash memory a temporar y disabl e
of Flash Read Protection is supported.
The device also features a block write protection.
Software locking of selectable memory blocks is
provided to protect code and data. This feature
will d isable b oth program and erase op erations in
the selected block(s) of the memory. Block
Protection is accomplished by block specific
lock-bit which are programmed by executing a
four cycle command sequence. The locked state
of blocks is indicated by specific flags in the
according bl oc k status registers. A block may only
be temporarily unlocked for update (write)
operations.
ST10F269
19/160
With the two possibilities for write protection -
whole memory or block specific - a flexible
installation of write protection is supported to
protect the Flash memory or parts of it from
unauthorized programming or erase accesses
and to provide virus-proof protection f or all system
code blocks. All write protection also is enabled
during boot operation.
Power Supply, Reset
The Flash module uses a single power supply for
both read and write functions. Internally generated
and regulated voltages are provided for the
program and erase operations from 5V supply.
Once a program or erase cycle has been
completed, the device resets to the standard read
mode . At po wer-on, the Fla sh memory has a setup
phase of some microseconds (dependent on the
power supply ramp-up). During this phase, Flash
can not be read. Thus, if EA pin is high (execution
will start from Flash me mory), the CPU will remains
in reset stat e until th e Fl ash can be accessed .
5.3 - Architectural Description
The Flash module distinguishes two basic
operating modes, the standard read mode and the
command mode. The initial state after power-on
and after reset is the standard read mode.
5.3.1 - Read Mode
The Flash module enters the standard operating
mode, the read mode:
– After Reset command
– A f ter every completed erase operation
– A f ter every completed programm ing operation
– After every other completed command
execution
– Few microseconds after a CPU-reset has
started
– After incorrect address and data values of
command sequences or writing them in an
improper sequence
– After incorrect write access to a read protected
Flash memory
The read mode remains active until the last
command of a command sequence is decoded
which starts directly a Flash array operation, such
as:
– eras e one or several block s
– program a word into Flash array
– prot ect / temporary unprotect a block.
In the standard read mode read accesses are
directly controlled by the Flash memory array,
delivering a 32-bit double Word from the
addressed position. Read accesses are always
aligned to double Word boundaries. Thus, both
low order address bit A1 and A0 are not used in
the Fl ash array for read access es. The high order
addres s bit A17/ A 16 d efine t he physical 64K By t e
segment being accessed within the Flash array.
5.3.2 - Command Mode
Every operation besides standard read operations
is initiated by commands written to the Flash
command register. The addresses used for
command cycles define in conjunction with the
actual state the specific step within command
sequences. With the last command of a command
sequence, the Erase-Program Controller (EPC)
starts the execution of the command. The EPC
status is indicated during command execution by:
– T he Stat us Register,
– The Ready/ Bu sy signal.
5.3.3 - Ready/Busy Signal
The Ready/Busy (R/B) signal is connected to the
XPER2 i nterrupt node (XP2IC). When R/B is high,
the Flash is busy with a Program or Erase
operation and will not accept any additional
program or erase instruction. When R/B is Low,
the Flash is ready for any Read/Write or Erase
operation. The R/B will also be low when the
mem ory is put in Erase Suspend mode.
This signal can be polled by reading XP2IC
register, or can be used to trigger an interrupt
when the Flash goes from Busy to Ready.
5.3.4 - Flash Status Register
The Flash Status register is used to flag the status
of the Flash memory and the result of an
operation. This register can be accessed by Read
cycles during the program-Erase Controller
operations. The program or erase operation can
be controlled by data polling on bit FSB.7 of
Status Register, detection of Toggle on FSB.6 and
FSB.2, or Error on FSB.5 and Erase Timeout on
FSB.3 bit. Any read attempt in Flash during EPC
operation will automatic ally output these five bits.
The EPC sets bit FSB.2, FSB.3, FSB.5, FSB.6
and FSB.7. Other bits are reserve d for future use
and sho uld be masked.
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Flash S tatus (see note for address)
Note: The Address of Flash Status Register is the address of the word being programmed when
Programming operation is in progress, or an address within block being erased when Erasing
operation is in progress.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------- FSB.7 FSB.6 FSB.5 - FSB.3 FSB.2 - -
RRR R R
FSB.7 Flash Status bit 7: Data Polling Bit
Programming Operation: this bit outputs the complement of the bit 7 of the word being
programmed, and after completion, will output the bit 7 of t he word programm ed.
Erasing Operation: outputs a ‘0’ during erasing, and ‘1’ after erasing compl etion.
If the block sel ected for erasure is (are) protected, FSB.7 will be set to ‘0’ for about 100 µs, and
then return to the pre vious addressed memory data value.
FSB.7 will also flag the Erase Suspend Mode by switching from ‘0’ to ‘1’ at the start of the
Erase Suspend.
During P rogram operation in Erase Susp end M ode, FSB.7 will have the same behaviour as in
nor m al Program execution outside the Suspend mode.
FSB.6 Flas h S ta tus bi t 6: Toggl e B it
Programming or Erasing Operations: successive read operations of Flash Status register will
deliver complementary values. FSB.6 will toggle each time the Flash Status register is read.
The Program operation is completed when two successive reads yield the same value. The
next read will output the bit last programmed, or a ‘1’ after Erase operation
FSB.6 will be set to‘1’ if a read operation is attempted on an Erase Suspended block. In
addition, an Erase Suspen d/Re sume com mand will cause FSB.6 to toggle.
FSB.5 Flash Status bit 5: Erro r Bit
This bit is set to ‘1’ whe n there is a failure of Program, block or chip erase operations.This bit
will also be set if a user tries to program a bit to ‘1’ to a Flash location that is currently
prog rammed with ‘0’.
The error bit resets after Read/Reset instruction.
In case o f suc ces s, the Err or bit wil l be se t to ‘0’ dur i ng P rogram or Erase and t hen will outpu t
the bit last programmed or a ‘1’ after erasing
FSB.3 Flash Status bit 3: Erase Time-out Bit
This bit is cleared by the EPC when the last Block Erase comm and has been entered to the
Command Interface and it is awaiting the Erase start. When the time-out period is finished,
after 96 µs, FSB.3 returns back to ‘1’.
FSB.2 Flas h S ta tus bi t 2: Toggl e B it
This toggle bit, together with FSB .6, can be used to det ermine the chip status during the Erase
Mode or Erase Suspend Mode. It can be used also to identify the block being Erased
Suspended. A Read operation will cause FS B.2 to Toggle dur ing the E rase Mode. If the Flash
is in Erase Suspend Mode, a Read operation from the Erase suspended block or a Program
operation into the Erase suspe nded block will c ause FS B.2 to toggle.
When the Flash is in Program Mode during Erase Suspend, FSB.2 will be read as ‘1’ if address
used is the address of the word being programmed.
After Erase complet ion with an Error status, FSB.2 will toggle when r eadi ng the faul ty se ctor.
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5.3.5 - Flash Protection Register
The Flash Protection register is a non-volatile register that contains the protection status. This register
can be read by using the Read Protection Status (RP) command, and programmed by using the dedi-
cated S et Protection com ma nd.
Flash Protection Register (PR)
5.3.6 - Instructions Description
Twelve instructions dedicated to Flash memory
accesses are defined as follow:
Read/Reset (RD). The Read/Reset instruction
consist of one write cycle with data XXF0h . it can
be optionally preceded by two CI enable
coded
cycles (data xxA8h at address 1554h + data
xx54h at address 2AA8h). Any successive read
cycle following a Read/Reset instruction will read
the memory array. A Wait cycle of 10µs is
necessary after a Read/Reset command if the
mem ory was in program or Erase mode.
Program Word (PW). This instruction uses four
write cycles . After the t wo Cl enabl e coded cycl es,
the Program Word command xxA0h is written at
addres s 1554h. The following write cycle will latch
the address and data of the word to be
pro gramm ed. Mem ory programming can be do ne
only by writing 0's instead of 1's, otherwise an
error occurs. During programming, the Flash
Status is checked by reading the Flash Status bit
FSB.2, FSB.5, FSB.6 and FSB.7 which show the
status of the EPC. FSB.2, FSB.6 and FSB.7
determine if programming is on going or has
comple ted, and FSB.5 allows a check to be made
for any possible error.
Block Erase (BE). This instruction uses a
minimum of six command cycles. The erase
enable command xx80h is written at address
1554h after the two-cycle CI enable sequence.
The erase confir m code xx30h must be wr itten at
an address related to the block to be erased
pre ceded by the exe cution of a sec ond CI enable
sequence. Additional erase confirm codes must
be give n to erase m ore tha n one block in parallel.
Additional erase confirm commands must be
wr itten within a def ined time-ou t peri od. The input
of a new Block Erase command will restart the
time-out period.
W hen this time-out period has elapsed, the erase
starts. The status of the internal timer can be
monitored through the level of FSB.3, if FSB.3 is
‘0’, the Block Erase command has been giv en and
the timeout is r unning; if FSB.3 is ‘1’, the timeout
has expired and the EPC is erasing the block(s).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP - - - - - - - - BP6 BP5 BP4 BP3 BP2 BP1 BP0
BPx Block x Protection Bit (x = 0...6)
‘0’: the Block Protection is enabled for block x. Programming or erasing the block is not
possible, unless a Block Temporary Unprotection command is issued.
1’: the Block Protection is disabled for block x.
Bit is ‘1’ by default, and can be programmed permanently to ‘0’ using the Set Protection
command but then cannot be set to ‘1’ again. It is therefore possible to temporally disable the
Block Protection using the Block Temporary Unprotection instruction.
CP Code Protection Bit
‘0’: the Flash Code Protection is enabled. Read accesses to the Flash for execution not
performed in the Flash itself are not allowed, the returned value will be 009Bh, whatever the
content of the Flash is.
1’: the Flash Code Protection is disabled: read accesses to the Flash from external or internal
RAM are allowed
Bit is ‘1’ by default, and can be programmed permanently to ‘0’ using the Set Protection
command but then cannot be set to ‘1’ again. It is therefore possible to temporally disable the
Code Protection using the Code Temporary Unprotection instruction.
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If the second command given is not an erase
confirm or if the coded cycles are wrong, the
instruction abor ts, and the dev ice is reset t o Read
Mode. It is not necessary to progr am the b lock with
0000h as the EPC will do this automatically before
the erasing to FFFFh. Read operations after the
EPC has started, output the Flash Statu s Register .
Durin g the execution of the erase by the EP C, the
device accepts only the Erase Suspend and
Read/Reset instructions. Data Polling bit FSB.7
returns ‘0’ while the erasure is in progress, and ‘1’
when it has completed. The Toggle bit FSB.2 and
FSB.6 toggle during the erase operation. They
stop when erase is completed. After completion,
the Error bit FSB.5 returns ‘1’ if there has been an
erase failure because erasure has not completed
even after the maximum number of erase cycles
have been executed by the EPC, in this case, it
will be necessary to input a Read/Reset to the
Command Interface in order to reset the EPC.
Chip Erase (CE). This instruction uses six write
cycles. The Erase Enable command xx80h, must
be written at address 1554h after CI-Enable
cycles. The Ch ip Erase com mand xx10h must be
given on the sixth cycle after a second CI-Enable
sequence. An error in command sequence will
reset the CI to Read mode. It i s NOT necessary to
program the block with 0000 h as the EPC will do
this automatically before the erasing to FFFFh.
Read operations after the EPC has sta r t ed out put
the Flash Stat us Register. Durin g the exec ution of
the erase by the EPC, Data Polling bit FSB.7
returns ‘0’ while the erasure is in progress, and ‘1’
when it has completed. The FSB.2 and FSB.6 bit
toggle during the erase operation. They s top when
erase is finished. The FSB.5 error bit returns "1" in
case of failure of the erase operation. The error
flag is set after the maximum number of erase
cycles have been executed by the EPC. In this
case, it will be necessary to input a Read/Reset to
the Comma nd Interface in order to reset the EPC.
Erase Suspend (ES). This instruction can be
used to suspend a Block Erase operation by
giving the command xxB0h without any specific
address. No CI-Enable cycles is required. Erase
Suspend operation allows reading of data from
another block and/or the programming in another
block while erase is in progress. If this com ma nd
is given during the time-out period, it will terminate
the time-out per iod in addition to erase Suspend.
The Toggle bit FSB.6, when monitored at an
address that belongs to the block being erased,
stops togg ling when Erase Suspend Com mand is
effective, It happens between 0.1µs and 15µs
after the Erase Suspend Command has been
written. The Flash will then go in normal Read
Mode, and read from blocks not being erased is
valid, while read from block being erased will
output FSB.2 toggling. During a Suspend phase
the only instruction s valid are Erase Resume a nd
Program Word. A Read / Reset instruct ion during
Erase s uspend wi ll definitely abor t t he Erase a nd
result in invalid data in the bl ock being erased.
Erase Resume (ER). This instruction can be
given when the memory is in Erase Suspend
State. Erase can be resumed by writing the
command xx30h at any address without any
Cl-enable sequence.
Program during Erase Suspend. The Program
Word instruction during Erase Suspend is allowed
only on bloc ks that are not Erase-suspended. This
instruction is the same than the Program Word
instruction.
Set Protect ion (SP). This instruction can be used
to enable both Block Protection (to protect each
block independently from accidental Erasing-Pro-
gramming Operation) and Code Protection (to
avoid code dump). The Set Protection Command
must be given after a special CI-Protection Enab le
cycles (see in stru ction table). The following Write
cycle, will program the Pro tection Regi ster. To pro-
tect the block x (x = 0 t o 6), the dat a bit x must be
at ‘ 0’. To prote ct the c ode, bit 15 of the dat a must
be ‘0’. Enabling Block or Code Protection is per-
manent and can be cleared only by STM. Block
Temporary Unprotection and Code Temporary
Unprotection instructions are av ailabl e to allow the
customer to update the code.
Not es: 1. The new va lue pr ogrammed i n protec tio n
register will only become active after a reset.
2. Bit that are already at ’0’ in protection
register must be confirmed at ’0’ also in
data latched during the 4th cycle of set
protection command, otherwise an error
may occur.
Read Protection Status (RP). This in stru ct ion is
used to read the Block Protection status and the
Code Protection status. To read the protection
register (see Table 3), the CI-Protection Enable
cycles must be executed followed by the
command xx90h at address x2A54h. The
following Read Cycles at any odd word address
will output t he Block Protection Status. The Read/
Reset command xxF0h must be written to reset
the protection interface.
Note: After a modification of protection register
(using Set Protection command), the Read
Protection Status will return the new PR
value only after a rese t.
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Block Temporary Unprotection (BTU). This Instruction can be used to temporary unprotect all the
blocks from Program / Erase protection. The Unprotection is disabled after a Reset cycle. The Block
Temporary Unprotection command xxC1h must be given to enable Block Temporary Unprotection. The
Command must be preceded by the CI-Protection Enable cycles and followed by the Read/Reset
comm and x xF0h.
Set Co de Protec tion ( SCP). This kind of protection allows the customer to protect the proprieta ry co de
written in Flash. If installed and active, Flash Code Protection prevents data operand accesses and
program branches into the on-chip Flash area from any location outside the Flash memory itself. Data
operand accesses and branches to Flash locations are only and exclusively allowed for instructions
executed from the Flash memory itself . Ev ery read or jump to Flash performed from another memory (like
inte rnal RA M , external m emo ry ) w hile C ode Prot ect ion i s enabled, will give the opcode 009B h re lat ed to
TRAP #00 illegal instruction. The CI-Protection Enable cycles m ust be sent to set the Code Protection. By
wr iting d ata 7 FFFh at any odd word address, the Code Prot ecte d status is stored in the Flash Prot ec tion
Register (PR). Protection is permanent and cannot be cleared by the user. It is possible to temporarily
disable the Code Protection us ing Code Te mpo rary Unprotection instr uct ion.
Note: Bits that are already at ’0’ in protection register must be confirmed at ’0’ also in data latched during
the 4th cycle of set protection command, otherwise an error may occur.
Code Temporary Unprotection (CTU). This instruction must be used to temporary disable Code
Protection. This instruction is effective only if executed from Flash memory space. To restore the
protection status, without using a reset, it is necessar y to use a Code Te mporary Protection instruction.
Sys tem res et w ill res et als o t he Code Tem porary Unpr otec ted status. The Code Tem porary U nprot ecti on
comm and consists of the following write cycle:
MOV MEM, Rn ; This instruction MUST be executed from Flash memory space
W here MEM is an absolute address inside memory space, Rn is a register loaded with data 0FFFFh .
Code Temporary Protection (CTP). This instruction allows to restore Code Protection. This operation is
effective only if executed from Flash memor y and is necessary to restore the protection status after the
use of a Code Temporary Unprotection instruction.
The Code Temp orary Protection com ma nd con sists of the following write cycle:
MOV MEM, Rn ; This instruction MUST be executed from Flash memory space
W here MEM is an absolute address inside memory space, Rn is a register loaded with data 0FFFBh.
Note that Code Temporary Unprotection instruction must be used when it is necessary to modify the
Flash with protected code (SCP), since the write/erase routines must be executed from a memory
exte r nal to Flash space. Usually, the write/erase routines, exec uted in RAM , ends with a retur n to Flash
spa ce where a CTP instruction restore the protection.
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Table 3 : Instructions
Notes 1. Ad dress bi t A1 4, A1 5 and above are don’t c are for cod ed address input s.
2. X = Do n’ t Care.
3. WA = Write A ddres s: address of memory locat i on to be programm ed.
4. WD = Write Data: 16-bit d at a to be programm ed
5. Optional, additional blocks address es must be entered w i thin a time- out delay (96 µs ) afte r l ast write entry, ti meout st at us can be
verified through FSB.3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspend ed.
6. Read Data P olling or Toggle bit until Erase completes.
7. WP R = Write prot ect io n regist er. To protec t co de, bit 15 of WP R m ust b e ‘ 0’ . To protec t block N (N=0, 1,. ..), bit N of WP R must be
‘0’. Bit that are already at ‘0’ in protection register must also be ‘0’ in WPR, else a writing error will occurs (it is not possible to writ e a
‘1’ in a bit already programmed at ‘0’).
8. MEM = any address i nsi de th e F l ash m em ory space. Abso l ute addressi ng mode must be used (M OV MEM, R n), and inst ruct i on
must be executed from F l ash m em ory space.
9. Odd word address = 4n-2 where n = 0, 1, 2, 3..., ex. 000 2h, 0006h...
Instruction Mne Cycle 1st
Cycle 2nd
Cycle 3rd
Cycle 4th Cycle 5th
Cycle 6th
Cycle 7th
Cycle
Read/Reset RD 1+ Addr.1X 2Read Memory Array until a new write cycle is initiated
Data xxF0h
Read/Reset RD 3+ Addr.1x1554h x2AA8h xxxxxh Read Memory Array until a new write
cycle is initiated
Data xxA8h xx54h xxF0h
Program Word PW 4 Addr.1x1554h x2AA8h x1554h WA 3Read Data Polling or Tog-
gle bit until Program com-
pletes.
Data xxA8h xx54h xxA0h WD 4
Block Erase BE 6 Addr.1x1554h x2AA8h x1554h x1554h x2AA8h BA BA’ 5
Data xxA8h xx54h xx80h xxA8h xx54h xx30h xx30h
Chip Erase CE 6 Addr.1x1554h x2AA8h x1554h x1554h x2AA8h x1554h N ote 6
Data xxA8h xx54h xx80h xxA8h xx54h xx10h
Erase Suspend ES 1 Addr.1X2Read until Toggle stops, then read or program all data needed
from block(s) not being erased then Resume Erase.
Data xxB0h
Erase Resume ER 1 Addr.1X2Read Data Polling or Toggle bit until Erase completes or Erase is
supended another time.
Data xx30h
Set Block/Code
Protection SP 4
Addr.1x2A54h x15A8h x2A54h Any odd
word
address 9
Data xxA8h xx54h xxC0h WPR 7
Read
Protection
Status RP 4
Addr.1x2A54h x15A8h x2A54h Any odd
word
address 9Read Protection Register
until a new write cycle is
initiated.
D ata xxA 8h xx5 4h x x90h R ead PR
Block
Temp orary
Unprotection BTU 4 Addr.1x2A54h x15A8h x2A54h X2
Data xxA8h xx54h xxC1h xxF0h
Code
Temp orary
Unprotection CTU 1 Addr.1MEM 8Write cycles must be executed from Flash.
Data FFFFh
Code
Temporary
Protection CTP 1 Addr.1MEM 8Write cycles must be executed from Flash.
Data FFFBh
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– Generally, command sequences cannot be
written to Flash by in structions fe tched from the
Flash itself. Thus, the Flash commands must be
written by instructions, executed from internal
RAM or external memo ry.
– Command cycles on the CPU in terface need not
to be consecutively received (pauses allowed).
The CPU interface delivers dummy read data for
not used cycles within command se quences .
– All addresses of command cycles shall be
defined only with Register-indirect addressing
mode in the acco rding move instructi on s. Di re ct
addressing is not allowed for command
sequences. Address segment or data page
pointer are taken in to accoun t for the com ma nd
address value.
5.3.7 - Reset Processi ng and Initial State
The Flash m odule distinguishes two kinds of CPU
reset types
The lengtheni ng of CPU reset:
– Is not reported to external devices by
bidirectional pin
– Is not enabled in case of external start of CPU
after reset.
5.4 - Flash Memory Configuration
The default memory configuration of the
ST10F269 Memory is determined by the state of
the EA pin at reset. This value is stored in the
Internal ROM Enable bit (named ROMEN) of the
SYSCON register.
When ROMEN = 0, the inter nal Flash is disabled
and external ROM is used for startup control.
Flash m em ory can l ate r be enabled by setting t he
ROMEN bit of SYSCON to 1. The code
performing this setting must not run from a
seg men t of the extern al ROM to be repla ce d by a
segment of the Flash memory, otherwise
unexpected behaviour may occur .
For example, if external ROM code is located in
the first 32K Bytes of segment 0, the first
32K Bytes of the Flash must then be enabled in
segment 1. This is done by setting the ROMS1 bit
of SYSCON to 0 before or simultaneously with
setting of ROMEN bit. This must be done in the
externally supplied program before the execution
of the EIN IT instruction.
If program execution starts from external memor y,
but access to the Flash memory mapped in
segment 0 is later required, then the code that
performs the setting of ROMEN bit must be
executed either in the segment 0 but above
addres s 00’8000h, or from the inter nal RAM.
Bit ROMS1 only affects the mapping of the first
32K B ytes of the Flash memory. All other par ts of
the Flash memory (addresses 01’8000h -
04’FFFFh) remain unaffected.
The SGTDIS Segmentation Disable / Enable must
also be set to 0 to allow the use of the full
256K Bytes of on-chip memory in addition to the
external boot memory. The correct procedure on
changing the segmentation registers must also be
obs erved to prevent an unwanted trap condition:
– Instructions that configure the internal memory
must only be executed from external memory or
from the internal RAM.
– An Absolute Inter-Segment Jump (JMPS)
instruction must be executed after Flash
enabling, to the next instruction, even if this next
instruction is located in the consecutive address.
– Whenever the internal Memory is disabled,
enabled or remapped, the DPPs must be
explicitly (re)loaded to enable correct data
accesses to the internal memory and/or external
memory.
5.5 - Application Examples
5.5.1 - Handling of Flash Addresses
All comma nd, Block, D ata and register addresses
to the Flash have to be located within the active
Flash memory space. The active space is that
address range to which the physical Flash
addresses are mapped as defined by the user.
When using data page pointer (DPP) for block
addresses make sure that address bit A15 and
A14 of the block address are reflected in both
LSBs of the selected DPPS.
Note: - For Command Instructions, address bit
A14, A15, A16 and A17 are don’t care.
This sim plify a lot the application sof tware,
becau se it minimize the use of DPP regis-
ters when using Command in the Com-
mand Interfac e.
- Direct addressing is not allowed for
Command sequence operations to the
Flash. Only Register-indirect addressing
can be used for command, block or
write-data accesses.
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5.5.2 - Basic Flash Access Control
When accessing the Flash all command write addresses have to be located within the active Flash
memory space. The active Flash memory space is that logical address range which is covered by the
Flash after mapping. When using data page pointer (DPP) for addressing the Flash, make sure that
address bit A15 and A14 of t he command addresses are reflected in both LSBs of t he selected data page
pointer (A15 - DPPx.1 and A14 - DPPx.0).
In case of the command write addresses, address bit A14, A15 and above are don’ t care. Thus, command
wr ites can be perfor m ed by onl y using one DPP register. This allow t o have a m ore simple and compact
application sof tware.
Another - advantageous - possibility is to use the ext ende d seg men t instruct ion for addres sing.
Note: The direct addressing mode is not allowed for write access to the Flash address/command
register. Be aware that the C compiler may use this kind of addressing. For write accesses to
Flash modu le alway s the indirect addressing m ode has to be selected.
The following basic instruction sequence s show ex amp les for different addressing poss ibilities.
Princ iple example of address gen erati on for Flash comm an ds an d registers:
W hen using data page pointer (D PP0 is this example)
MOV DPP0,#08h ;adjust data page pointers according to the
;addresses: DPP0 is used in this example, thus
;ADDRESS must have A14 and A15 bit set to ‘0’.
MOV Rwm,#ADDRESS ;ADDRESS could be a dedicated command sequence
;address 2AA8h, 1554h ... ) or the Flash write
;address
MOV Rwn,#DATA ;DATA could be a dedicated command sequence data
;(xxA0h,xx80h ... ) or data to be programmed
MOV [Rwm],Rwn;indirect addressing
W hen using the extended segm ent instru ction:
MOV Rwm,#ADDRESS ;ADDRESS could be a dedicated command sequence
;address (2AA8h, 1554h ... ) or the Flash write
;address
MOV Rwo,#DATA ;DATA could be a dedicated command sequence data
;(xxA0h,xx80h ... ) or data to be programmed
MOV Rwn,#SEGMENT ;the value of SEGMENT represents the segment
;number and could be 0, 1, 2, 3 or 4 (depending
;on sector mapping) for 256KByte Flash.
EXTS Rwn,#LENGTH ;the value of Rwn determines the 8-bit segment
;valid for the corresponding data access for any
;long or indirect address in the following(s)
;instruction(s). LENGTH defines the number of
;the effected instruction(s) and has to be a value
;between 1...4
MOV [Rwm],Rwo;indirect addressing with segment number from
;EXTS
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5.5.3 - Programming Examp les
Most of the microcontroller programs are written in the C language where the data page pointers are
automatically set by the compiler. But because the C compiler ma y use the not allowed direct addressing
mode f or F lash write addresses, it i s necessary to program the organisational Flash accesses (command
seq uences) with assembler in-line routines which use indirect addres sing.
Example 1 Performing the com ma nd Read/ Reset
We assume that in the initialization pha se the lowest 32K Bytes of Flash memor y (sector 0) have be en
mapp ed to segm ent 1.
According to the usual way of ST10 data addressing with data page pointers, address bit A15 and A14 of
a 16-bi t command write address select the data pag e pointer (DP P) which con tains the up per 10-bit for
building the 24-bit physical data address. Address bit A13...A0 represent the address offset. As the bit
A14...A17 are "don’t care" when written a Flash command in the Command Interf ace (CI), we can choose
the mos t conveniant DPPx registe r for address handli ng.
The following examples are making usage of DPP0. We just have to make sure, that DPP0 points to
active Flash memory space.
To be independent of mapping of sector 0 we choose for all DPPs which are used for Flash address
handling, to point to segment 2.
For this reason we load DPP0 with va lue 08h (00 0000 l000b).
MOV R5, #01554h ;load auxilary register R5 with command address
;(used in command cycle 1)
MOV R6, #02AA8h ;load auxilary register R6 with command address
;(used in command cycle 2)
SCXT DPPO, #08h ;push data page pointer 0 and load it to point to
;segment 2
MOV R7, #0A8h ;load register R7 with 1st CI enable command
MOV [R5], R7 ;command cycle 1
MOV R7, #054h ;load register R7 with 2cd CI enable command
MOV [R6], R7 ;command cycle 2
MOV R7, #0F0h ;load register R7 with Read/Reset command
MOV [R5], R7 ;command cycle 3. Address is don’t care
POP DPP0 ;restore DPP0 value
In the example above the 16-bit registers R5 and R6 are used as auxilary registers for indirect
addressing.
Example 2 Performing a Program Wo rd comm and
We assume that in the initialization pha se the lowest 32K Bytes of Flash memor y (sector 0) have be en
mapp ed to se gme nt 1.The dat a to be written is loaded i n regist er R13, the addres s to b e programmed is
loaded in register R11/R12 (segment number in R11, segment offset in R12).
MOV R5, #01554h ;load auxilary register R5 with command address
;(used in command cycle 1)
MOV R6, #02AA8h ;load auxilary register R6 with command address
;(used in command cycle 2)
SXCT DPPO, #08h ;push data page pointer 0 and load it to point to
;segment 2
MOV R7, #0A8h ;load register R7 with 1st CI enable command
MOV [R5], R7 ;command cycle 1
MOV R7, #054h ;load register R7 with 2cd CI enable command
MOV [R6], R7 ;command cycle 2
MOV R7, #0A0h ;load register R7 with Program Word command
MOV [R5], R7 ;command cycle 3
ST10F269
28/160
POP DPP0 ;restore DPP0: following addressing to the Flash
;will use EXTended instructions
;R11 contains the segment to be programmed
;R12 contains the segment offset address to be
;programmed
;R13 contains the data to be programmed
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV [R12], R13 ;command cycle 4: the EPC starts execution of
;Programming Command
Data_Polling:
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV R7, [R12] ;read Flash Status register (FSB) in R7
MOV R6, R7 ;save it in R6 register
;Check if FSB.7 = Data.7 (i.e. R7.7 = R13.7)
XOR R7, R13
JNB R7.7, Prog_OK
;Check if FSB.5 = 1 (Programming Error)
JNB R6.5, Data_Polling
;Programming Error: verify is Flash programmed
;data is OK
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV R7, [R12] ;read Flash Status register (FSB) in R7
;Check if FSB.7 = Data.7
XOR R7, R13
JNB R7.7, Prog_OK
;Programming failed: Flash remains in Write
;Operation.
;To go back to normal Read operations, a Read/Reset
;command
;must be performed
Prog_Error:
MOV R7, #0F0h ;load register R7 with Read/Reset command
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV [R12], R7 ;address is don’t care for Read/Reset command
... ;here place specific Error handling code
...
...
;When programming operation finished succesfully,
;Flash is set back automatically to normal Read Mode
Prog_OK:
....
....
ST10F269
29/160
Example 3 Performing the Block Erase command
We assume that in the initialization pha se the lowest 32K Bytes of Flash memor y (sector 0) have be en
mapped to segment 1.The registers R11/R12 contain an address related to the block to be erased
(segment number in R11, segment offset in R12, for e xample R11 = 01h, R12= 4000h will erase the bloc k
1 - first 8K byte block).
MOV R5, #01554h ;load auxilary register R5 with command address
;(used in command cycle 1)
MOV R6, #02AA8h ;load auxilary register R6 with command address
;(used in command cycle 2)
SXCT DPPO, #08h ;push data page pointer 0 and load it to point ;to
;segment 2
MOV R7, #0A8h ;load register R7 with 1st CI enable command
MOV [R5], R7 ;command cycle 1
MOV R7, #054h ;load register R7 with 2cd CI enable command
MOV [R6], R7 ;command cycle 2
MOV R7, #080h ;load register R7 with Block Erase command
MOV [R5], R7 ;command cycle 3
MOV R7, #0A8h ;load register R7 with 1st CI enable command
MOV [R5], R7 ;command cycle 4
MOV R7, #054h ;load register R7 with 2cd CI enable command
MOV [R6], R7 ;command cycle 5
POP DPP0 ;restore DPP0: following addressing to the Flash
;will use EXTended instructions
;R11 contains the segment of the b lock to be erased
;R12 contains the segment offset address of the
;block to be erased
MOV R7, #030h ;load register R7 with erase confirm code
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV [R12], R7 ;command cycle 6: the EPC starts execution of
;Erasing Command
Erase_Polling:
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV R7, [R12] ;read Flash Status register (FSB) in R7
;Check if FSB.7 = ‘1’ (i.e. R7.7 = ‘1’)
JB R7.7, Erase_OK
;Check if FSB.5 = 1 (Erasing Error)
JNB R7.5, Erase_Polling ;Programming failed: Flash remains in Write
;Operation.
;To go back to normal Read operations, a Read/Reset
;command
;must be performed
Erase_Error:
MOV R7, #0F0h ;load register R7 with Read/Reset command
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV [R12], R7 ;address is don’t care for Read/Reset command
... ;here place specific Error handling code
...
...
;When erasing operation finished succesfully,
;Flash is set back automatically to normal Read Mode
Erase_OK:
....
....
ST10F269
30/160
5 .6 - Boot st rap Loade r
The built-in bootstrap loader (BSL) of the
ST10F269 provides a mechanism to load the
star tup program through the serial interface after
reset. In this case, no external memory or internal
Flash memory is required for the initialization
code starting at location 00’0000h (see Figure 5).
The bootstrap loader moves code/data into the
internal RAM, but can also transfer data via the
serial interface into an external RAM using a
second level loader routine. Flash Memory
(internal or exter nal) is not necessar y, but it may
be used to provide lookup tables or “core-code”
like a set of general purpose subroutines for I/O
operations, number crunching, system
in it ializat io n, et c.
The bootstrap loader can be used to load the
complete application software into ROMless
systems, to load temporary software into
complete systems for testing or calibration, or to
load a programming routine f or Flash devices.
The BSL mechanism can be used for standard
system startup as well as for special occasions
like system maintenance (firmer update) or
end-of-line programming or testing.
5.6.1 - Entering the Bootstrap Loader
The ST10F 269 enters BSL mod e whe n pin P 0L. 4
is s ampled low at t he end o f a hard ware reset. I n
this case the built-in bootstrap loader is a ctivated
independent of the selected bus mode.
The bootstrap loader code is stored in a special
Boot-ROM. No part of the standard mask Memory
or Flash Memory area is required for this.
After entering BSL mode and the respective
initialization the ST10F269 scans the RXD0 line to
receive a zero Byte , one start bit, eight ‘0’ data bits
and one stop bit.
From the duration of this zero Byte it calculates
the corresponding Baud rate f act or with respect to
the current CPU clock, initializes the serial
interface ASC0 accordingly and switches pin
TxD0 to output.
Using this Baud rate, an identification Byte is
returned to the host that provides the loaded data.
This identification Byte identifies the device to
be booted. The identification byte is D5h for
ST10F269.
Fi gure 5 : Bootstrap Loader Sequence
RSTIN
TxD0
Internal Boot Memory (BSL) routine 32 Byte user software
2)
3)
RxD0
CSP:IP
4)
6)
P0L.4
1) BSL initialization time
2) Z ero B yt e (1 st art bi t, ei ght ‘0’ data bi ts, 1 st op bi t), sent by host .
3) Identification Byte (D5h), sent by ST10F269.
4) 32 By tes of code / data, sent by hos t.
5) Cau t i o n: TxD0 is on l y dri ven a cert ai n t i m e after reception of t he zer o B yte.
6) Internal Bo ot ROM.
1)
5)
ST10F269
31/160
W hen the ST1 0F26 9 has ent ered B SL m ode, the following configuration is auto maticall y se t (values that
deviate from the normal reset values, are
marked
):
In this case, the watchdog timer is disabled, so the
bootstrap loading sequence is not time limited.
Pin TXD0 is configured as output, so the
ST10F269 can return the identification Byte.
Even if the internal Fl ash is enabled, no c ode can
be executed out of it.
The h ardware that activates the BSL during res et
may be a simple pull-down resistor on P0L.4 for
systems that use this feature upon every
hardware reset.
A switchable solution (via jumper or an external
signal) can be used for systems that
only temporarily use the bootstrap loader (see
Figure 6).
After sending the identification Byte the
ASC0 receiver is enabled and is ready to
receive the initial 32 Bytes from the host. A half
duplex connection is therefore sufficient to feed
the BSL .
5.6.2 - Memory Conf iguration After Reset
The configuration (and the accessibility) of the
ST10F269’s memory areas after reset in
Bootstrap-Loader mode differs from the standard
case. Pin EA is n ot evaluated when BSL mode is
selec ted, and accesses to the in tern al Flash area
are partly redirected, while the ST10F269 is in
BSL mode (see Figure 7). All code fetches are
made from the special Boot-ROM, while data
accesses read from the internal user Flash. Data
accesses will return undefined values on
ROMless d evices.
The code in the Boot-ROM is not an invariant
feature of the ST10F269. User software should
not try to execute code from the internal Flash
area while the BSL mode is still active, as these
fetches will be redirected to the Boot-ROM. The
Boot-ROM will also “move” to segment 1, when
the internal Flash area is mapped to segment 1
(see Figure 7).
Watchdog Timer:
Disabled
Register SYSCON: 0E00h
Context Pointer CP: FA00h Register STKUN: FA40h
Stack Pointer SP: FA40h Register STKOV: FA0Ch 0<->C
Register S0CON:
8011h
Register BUSCON0: acc. to startup configuration
Register S0BG: Acc. to ‘00’ Byte P3.10 / TXD0: ‘1’
DP3.10: ‘1’
Fi gure 6 : Hardware Provisions to Activate the BSL
RPOL.4
8kΩ
Circuit 1
POL.4 POL.4 Normal Boot
BSL
External
Signal
RPOL.4
8kΩ
Circuit 2
ST10F269
32/160
Fi gure 7 : Memory Configuration after Reset
5.6.3 - Loading the Startup Code
After sending the identification Byte the BSL
enters a loop to receive 32 Bytes via ASC0. These
Byte are stored sequentially into locations
00’FA40h through 00’FA5Fh of the internal RAM.
So up to 16 instructions may be placed into the
RAM area. To execute the loaded code the BSL
then jum ps to location 00’FA4 0h, which i s the first
loaded instruction.
The bootstrap loading sequence is now
ter minated, the ST10F269 rem ains in B SL mode,
however. Most probably the initially loaded routine
will load additional code or data, as an average
application is likely to require substantially more
than 16 instructions. This second receive loop
may directly use the pre-initialized interface ASC0
to receive data and store it to arbitrary
user -defined lo cations.
This sec ond level of loade d c ode may be t he f ina l
application code. It may also be another, more
sophisticated, loader routine that adds a
transmission protocol to enhance the integrity of
the loaded code or data. It may also contain a
code sequence to change the system
configuration and enable t he bus interface to store
the received data into exter nal memory.
This proces s may go through several iterations or
may directly execute the final application. In all
cases the ST10F269 will still run in BSL mode,
that m eans with the watchd og timer disable d and
limited access to the internal Flash area.
All code fetches from the internal Flash area
(00’0000h...00’7FFFh or 01’0000h...01’7FFFh, if
mapped to segment 1) are redirected to the
special Boot-ROM. Data fetches access will
access the i nterna l Bo ot -ROM of th e ST10F269, if
any is available, but will return undefined data on
ROMless d evices.
5.6.4 - Exiting Bootstr ap Lo ader Mode
In order to e xecute a program in normal mode, the
BSL mode must be terminated first. The
ST 10F269 ex its BSL m ode upon a software reset
(ignores the level on P0L.4) or a hardware reset
(P0L.4 mu st be high). After a reset the S T 10F2 69
will start executing from location 00’0000h of the
internal Flash or the external memory, as
pro grammed via pin E A .
16M B ytes 16M Bytes 16M Bytes
BSL mode active Yes (P0L.4=’0’) Yes (P0L.4=’0’) No (P0L.4=’1’)
EA pin High Low Access to application
Code fetch from internal
Flash area Test-Flash access Test-Flash access User Flash access
Data fetch from internal
Flash area User Flash access User Flash access User Flash access
IRAM
1
0
User
Flash
Test
Flash
Segment
2
255
Access to:
external
bus
disabled
internal
enabled
Flash
1
0
User
Flash
Test
Flash
Segment
2
255
Access to:
external
bus
enabled
internal
enabled
Flash
IRAM
1
0User
Flash
Segment
2
255
Access:
depends on
reset config
EA, Port0
depends on
reset config
EA, Port0
IRAM
ST10F269
33/160
5.6.5 - Choosing the Baud Rate for the BSL
The calculation of the serial Baud rate for ASC0
from the length of the first zero Byte that is
received, allows the operation of the bootstrap
loader of the ST10F269 with a wide range of Baud
rates. However, the upper and lower limits have t o
be kept, in order to insure proper data transf er.
The ST10F269 uses timer T6 to measure the
length of the initial zero Byte. The quantization
uncertainty of this measurement implies the first
deviation from the real Baud rate, the next
deviation is implied by the computation of the
S0BR L reloa d value f rom the timer c ontents. The
formula below shows the association:
For a correct data transfer from the host to the
ST10F269 the maximum deviation between the
internal initialized Baud rate for ASC0 and the real
Baud rate of the host shoul d be below 2.5%. The
deviation (FB, in percen t) bet ween host Ba ud rate
and ST10F269 Baud rate can be calculated via
the formu la below:
Note: Function (FB) does not consider the
tolerances of os cillators and other devices
supp ort ing the serial commun ication.
This Baud rate deviation is a nonlinear function
depending on the CPU clock and the Baud rate of
the host. The maxima of the function (FB)
increase with the host Baud rate due to the
smaller Baud rate pre-scaler factors and the
implied higher quantization error (see Figure 8).
The minimu m Baud rate (BLow in the Figure 8) is
determined by the maximum count capacity of
timer T6, when measuring the zero Byte, and it
depends on the CPU clock. Using the maximum
T6 count 216 in the formula the minimum Baud
rate can be calculated. T he lowest standard Ba ud
rate i n this c ase would be 1200 B au d. B aud rates
below BLow would cause T6 to overflow. In this
case AS C 0 cannot be initialized properly.
The maximum Baud rate (BHigh in the Figure 8)
is the highest Baud rate where the deviation still
does not exceed the limit, so all Baud rates
between BLow and BHigh are below the deviation
limit. The maximum standard Baud rate that fulfills
this requirement is 19200 Baud.
Higher Baud rates, however, may be used as
long as the actual deviation does not exceed the
limit. A cer tain Baud rate (marked ’I’ in Figure 8)
may violate the deviation limit, while an even
higher Baud rate (marked ’II’ in Figure 8) stays
very well below it. This depends on the host
interface.
fCPU
32 S0BRL 1
+()×
------------------------------------------------
BST10F269 =
S0BRL T6 36
–
72
--------------------
=T6 9
4
--- fCPU
BHost
-----------------
×
=
,
FBBContr BHost
–
BContr
-------------------------------------------- 100
×=%,
FB2.5
≤%
Fi gure 8 : Baud Rate Deviation Betw een Host and ST10F269
BLow
2.5%
FB
BHigh
I
II BHOST
ST10F269
34/160
6 - CE NTRA L PROCESSI NG UNI T (CPU )
The CPU includes a 4-stage instruction pipeline, a
16-bit arithmetic and logic unit (ALU) and dedi-
cated SFRs. Additional hardware has been added
for a separate multiply and di vide un it, a bit-mask
generator and a barrel shifter.
Most of the ST10F269’s instructions can be exe-
cuted in one instruction cycle which requires 50ns
at 40MHz CPU clock. For example, shift and
rotate instructions are processed in one instruc-
tion cycl e inde penden t o f the number o f b its to be
shifted.
Multiple-cycle instructions have been optimized:
branches are carried out in 2 cycles, 16 x 16-bit
multiplication in 5 cycles and a 32/16-bit division
in 10 cycles .
The jump cache reduces the execution time of
repeatedly performed jumps in a loop, from
2 cycles to 1 cycle.
The CP U uses a bank of 16 word registers to run
the current conte xt . This bank of General Purpose
Registers (GPR) is physically stored within the
on-chip Internal RAM (IRAM) area. A Context
Pointer (CP) register determines the base
address of t he act i v e register bank to be accessed
by the CPU.
The num ber of register banks is on ly restr icte d by
the available Internal RAM space. For easy
parameter passing, a register bank may overlap
others.
A system stack of up to 1024 bytes is provided as
a storage for temporar y d ata. Th e system stack is
allocated in the on-chip RAM area, and it is
accessed by the CPU via the stack pointer (SP)
register.
Two separate SFRs, STKOV and STKUN, are
implicitly compared against the stack pointer
value upon each sta ck acce ss for the detec tion of
a stack overflow or underflow.
Fi gure 9 : CPU Block Diagram (MAC Unit not included)
32
Internal
RAM
2K Byte
General
Purpose
Registers
R0
R15
MDH
MDL
Barrel-Shift
Mul./Div.-HW
Bit-Mask Gen.
ALU
16-Bit
CP
SP
STKOV
STKUN
Exec. Unit
Instr. Ptr
4-Stage
Pipeline
PSW
SYSCON
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Data Pg. Ptrs Code Seg. Ptr.
CPU
256K Byte
Flash
memory
16
16
Bank
n
Bank
i
Bank
0
ST10F269
35/160
The System Configuration Register SYSC ON
This bit-addressable register provides general system configuration and control functions. The reset
v a l ue for reg i ste r SYSCON depends on the state of the PORT0 pins during reset.
SYSCON (FF12h / 89h) S F R Reset Value: 0xx0h
Notes : 1. These bi t s are set dir ectly or i ndi rect l y acc ordi ng to P ORT0 and EA pin conf i guration duri ng reset sequence.
2. Register SYSCON cannot be chan ged afte r execution of the EINIT instructio n.
6.1 - Multiplier-ac cumulator Unit (MAC)
The MAC co-processor is a specialized co-pro-
cessor added to the ST10 CPU Core in order to
improve the performances of the ST10 Family in
signal proces sing algor ithms.
Signal processing needs at least three specialized
units operating in parallel to achieve maximum
performance :
– A Multiply - Acc u m u late U nit,
– An Address Generation Unit, able to feed the
MAC Unit with 2 operands per cy cle,
– A Rep eat Unit, to execute series of multiply-ac-
cumulate instructions.
The existing ST10 CPU has been modified to
include new addressing capabilities which enable
the CPU to supply the new co-processor with up
to 2 operands per instruction cy cle.
This new co-processor (so-called MAC) contains
a fas t multiply-accumula te unit and a repeat unit.
The co-processor instructions extend the ST10
CPU instruction set with multiply, multiply-accu-
mulate, 32-bit signed arithm etic operations.
A new transfer instruction CoMOV has also been
added to take benefit of the new addressing capa-
bilities.
1514131211109876543210
STKSZ ROM
S1 SGT
DIS ROM
EN BYT
DIS CLK
EN WR
CFG CS
CFG PWD
CFG OWD
DIS BDR
STEN XPEN VISI
BLE XPER-
SHARE
RW RW RW RW1RW1RW RW1RW RW RW RW RW RW RW
Bit Function
XPEN 0
1
XBUS Peripheral Enable Bit
Accesses to the on-chip X-Peripherals and their functions are disabled
The on-chip X-Peripherals are enabled and can be accessed.
BDRSTEN 0
1
Bidirectional Reset Enable
RSTIN pin is an input pin only. SW Reset or WDT Reset have no effect on this pin
RSTIN pin is a bidirectional pin. This pin is pulled low during 1024 TCL during reset sequence.
OWDDIS 0
1
Oscillator Watchdog Disable Control
Oscillato r Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monito rs XTAL1 activity. If
there is no activity on XTAL1 for at least 1 µs, the CPU clock is switched automatically to PLL’s
base frequency (2 to 10MHz).
OWD is disabled. If the PLL is bypassed, the CPU clock is always driven by XTAL1 signal. The
PLL is turned off to reduce power supply current..
PWDCFG 0
1
Power Down Mode Configuration Control
Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low, oth-
erwise the instr uction has no effect. To exit Power Down Mode, an external reset must occurs by
as serting the R STIN pin.
Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast
external interrupt EXxIN pins are in their inactive level. Exiting this mode can be done by asserting
one enabled EXxIN pin.
CSCFG 0
1
Chip Select Configuration Control
Latched Chip Select lines: CSx change 1 TCL after rising edge of ALE
Unlatched Chip Slect lines : CSx change with rising edge of ALE
ST10F269
36/160
6.1.1 - Features
6.1.1.1 - Enhanced Addressing Capabilities
– New addressing m odes including a double in di-
rect addressing mode with pointer post-modifi-
cation.
– Parallel Data Move : this mechanism allows one
operand move during Multiply-Accumulate in-
structions without penalty.
– New tranfer instructions CoS TOR E (for f ast ac -
cess to the MAC SFRs) and CoMOV (for fast
memory to memory table transfer).
6.1.1.2 - Multiply-Accumulate Unit
– One-cycle execution for all MAC operations.
– 16 x 16-bit signed/unsigned parallel multiplier.
– 40-bit signed arithmetic unit with automatic sat-
uration mode.
– 40-b it ac c umu lat o r.
– 8-bi t left/right shifter.
– Full in s t r uctio n set with multiply and mu lt iply - ac -
cumulate, 32-bit signed arithmetic and compare
instructions.
6.1.1. 3 - Program Con trol
– Repeat Unit : allows some MAC co-processor in-
structions to be re peated up to 8192 tim es. Re-
peated instructions ma y be interrupted.
– M A C interrupt (Class B Trap) on MAC condition
flags.
Fi gure 1 0 : M AC Unit Architecture
Note: * Shared with sta ndard ALU.
Operand 2Operand 1
Con tr ol Un it
Repeat Unit
ST10 CPU
Interrupt
Controller
MSW
MRW
MAH MAL
MCW
Flags MAE
Mux
8-b it Le ft/ Ri gh t
Shifter
Mux
Mux
Sign Ext end
16 x 16
Concatenation
signed/unsigned
Multiplier
40-bit Signed Arithmetic Unit
0h 0h08000h
40
16
40 40
32 32
16
40
40
40
40
40
Scaler
AB
40
GPR P ointers *
IDX0 Pointer
IDX1 Pointer
QR0 GPR Off set Register
QR1 GPR Off set Register
QX0 ID X Offs et Register
QX1 ID X Offs et Register
ST10F269
37/160
6.2 - Instruction Set S u mm ar y
The Table 4 lists the inst ruct ions of th e ST10F269. The various add re ssing m odes, instr uct ion ope ration,
paramet ers for condit ional exec ution of instr uctions, opcodes an d a detailed des cript ion of each instr uc-
tion can be found in the “ST10 Fami ly Programming Ma nual”.
Table 4 : Instruction Set Summary
Mnemonic Description Bytes
ADD(B) Add word (byte) operands 2 / 4
ADDC(B) Add word (byte) operands with Carry 2 / 4
SUB(B) Subtract word (byte) operands 2 / 4
SUBC(B) Subtract word (byte) operands with Carry 2 / 4
MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2
DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
CPL(B) Complement direct word (byte) GPR 2
NEG(B) Negate direct word (byte) GPR 2
AND(B) Bit-wise AND, (word/byte operands) 2 / 4
OR(B) Bit-wise OR, (word/byte operands) 2 / 4
XOR(B) Bit-wise XOR, (word/byte operands) 2 / 4
BCLR Clear direct bit 2
BSET Set direct bit 2
BMOV(N) Move (negated) direct bit to direct bit 4
BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4
BCMP Compare direct bit to direct bit 4
BFLDH/L Bit-wise modify masked high/low byte of bit-addressable direct word memory
with immediate data 4
CMP(B) Compare word (byte) operands 2 / 4
CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4
CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4
PRIOR Determine number of shift cycles to normalize direct word GPR and store result
in direct word GPR 2
SHL / SHR Shift left/right direct word GPR 2
ROL / ROR Rotate left/right direct word GPR 2
ASHR Arithmetic (sign bit) shift right direct word GPR 2
MOV(B) Move word (byte) data 2 / 4
MOVBS Move byte operand to word operand with sign extension 2 / 4
MOVBZ Move byte operand to word operand with zero extension 2 / 4
JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4
JMPS Jump absolute to a code segment 4
J(N)B Jump relative if direct bit is (not) set 4
JBC Jump relative and clear bit if direct bit is set 4
ST10F269
38/160
6.3 - MAC Coprocessor Specific Instructions
The following tabl e gives an over view of the MAC
instruction set. All the mnemonics are listed with
the addressing modes that can be used with each
instruct ion .
For each combination of mnemonic and address-
ing mode this table indicates if it is repeatable or
not.
New addressing capabilities enable the CPU to
supply the MAC with up to 2 operands per instruc-
tion cycle. MAC instructions: multiply, multi-
ply-accum ulate , 32-bit s igned arit hm etic op erations
and the CoMOV transfer instruction have been
added to the standard instruction set. Full details
are provided in the ‘ST10 Family Programming
Manual’. Double indirect addressing requires two
poin ters. A ny GPR c an be use d fo r one point er, the
other pointer is provided by one of two specific
SFRs IDX0 and ID X1. Two pairs of offset registers
QR 0/ QR 1 an d QX0/ QX 1 are as so cia te d wi t h ea ch
poi nter (GP R or I DX
i
).
The GPR pointer allows access to the entire
mem ory space, but IDXi are limit e d t o t he int e rn al
Dual-Port RAM, except for the CoMOV instruction.
JNBS Jump relative and set bit if direct bit is not set 4
CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met 4
CALLS Call absolute subroutine in any code segment 4
PCALL Push direct word register onto system stack and call absolute subroutine 4
TRAP Call interrupt service routine via immediate trap number 2
PUSH, POP Push/pop direct word register onto/from system stack 2
SCXT Push direct word register onto system stack and update register with word
operand 4
RET Return from intra-segment subroutine 2
RETS Return from inter-segment subroutine 2
RETP Return from intra-segment subroutine and pop direct
word register from system stack 2
RETI Return from interrupt service subroutine 2
SRST Software Rese t 4
IDLE Enter Idle Mode 4
PWRDN Enter Power Down Mode (supposes NMI-pin being low) 4
SRVWDT Service Watchdog Timer 4
DISWDT Disable Watchdog Timer 4
EINIT Signify End-of-Initialization on RSTOUT-pin 4
ATOMIC Begin ATOMIC sequence 2
EXTR Begin EXTended Register sequence 2
EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4
EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4
NOP Null operation 2
Table 4 : Instruction Set Summary
Mnemonic Description Bytes
ST10F269
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Mnemonic Addressing Modes Repeatability
CoMUL
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
No
No
No
CoMULu
CoMULus
CoMULsu
CoMUL-
CoMULu-
CoMULus-
CoMULsu-
CoMUL, rnd
CoMULu, rnd
CoMULus, rnd
CoMULsu, rnd
CoMAC
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
No
Yes
Yes
CoMACu
CoMACus
CoMACsu
CoMAC-
CoMACu-
CoMACus-
CoMACsu-
CoMAC, rnd
CoMACu, rnd
CoMACus, rnd
CoMACsu, rnd
CoMACR
CoMACRu
CoMACRus
Rwn, Rwm
[IDXi⊗], [Rwn⊗]
Rwn, [RWm⊗]
No
No
No
CoMACRsu
CoMACR, rnd
CoMACRu, rnd
CoMACRus, rnd
CoMACRsu, rnd
CoNOP
[Rwm⊗] Yes
[IDXi⊗]Yes
[IDXi⊗], [Rwm⊗] Yes
CoNEG -NoCoNEG, rnd
CoRND
CoSTORE Rwn, CoReg No
[Rwn⊗], Coreg Yes
CoMOV [IDXi⊗], [Rwm⊗] Yes
ST10F269
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CoMACM
[IDXi⊗], [Rwm⊗] Yes
CoMACMu
CoMACMus
CoMACMsu
CoMACM-
CoMACMu-
CoMACMus-
CoMACMsu-
CoMACM, rnd
CoMACMu, rnd
CoMACMus, rnd
CoMACMsu, rnd
CoMACMR
CoMACMRu
CoMACMRus
CoMACMRsu
CoMACMR, rnd
CoMACMRu, rnd
CoMACMRus, rnd
CoMACMRsu, rnd
CoADD
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
No
Yes
Yes
CoADD2
CoSUB
CoSUB2
CoSUBR
CoSUB2R
CoMAX
CoMIN
CoLOAD
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
CoLOAD- No
CoLOAD2 No
CoLOAD2- No
CoCMP
CoSHL Rwm
#data4
[Rwm⊗]
Yes
No
Yes
CoSHR
CoASHR
CoASHR, rnd
CoABS
-
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
No
No
No
Mnemonic Addressing Modes Repeatability
ST10F269
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The Table 5 shows the various combinations of pointer post-modification for each of these 2 new
addressing modes. In this document the symbols “[Rwn⊗]” and “[IDXi⊗]” refer to these addressing
mode s.
Table 5 : Poi nte r Po st-m odification Com binations for IDXi and Rwn
Symbol Mnemonic Address Pointer Operation
“[IDXi⊗]” stands for [IDXi] (IDXi) ← (IDXi) (no-op)
[IDXi+] (IDXi) ← (IDXi) + 2 (i=0,1)
[IDXi-] (IDXi) ← (IDXi) - 2 (i=0,1)
[IDXi + QXj] (IDXi) ← (IDXi) + (QXj) (i, j =0,1)
[IDXi - QXj] (IDXi) ← (IDXi) - (QXj) (i, j =0,1)
“[Rwn⊗]” stands for [Rwn] (Rwn) ← (Rwn) (no-op)
[Rwn+] (Rwn) ← (Rwn) + 2 (n=0-15)
[Rwn-] (Rwn) ← (Rwn) - 2 (n=0-15)
[Rwn + QRj] (Rwn) ← (Rwn) + (QRj) (n=0-15; j =0,1)
[Rwn - QRj] (Rwn) ← (Rwn) - (QRj) (n=0-15; j =0,1)
Table 6 : MAC Registers Refe renced as ‘CoR eg‘
Registers Description Address in Opcode
MSW MAC-Unit Status Word 00000b
MAH MAC-Unit Accumulator High 00001b
MAS “limited” MAH /signed 00010b
MAL MAC-Unit Accumulator Low 00100b
MCW MAC-Unit Control Word 00101b
MRW MAC-Unit Repeat Word 00110b
ST10F269
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7 - EXTERNAL BUS CONTROLL ER
All of the external memory accesses are
performed by the on-chip ex ternal bu s controller.
The EBC can be progr ammed to single chip mode
when no external memory is required, or to one of
four di fferent exter nal memory acces s modes:
– 16- / 18- / 20- / 24-bit addresses and 16-bit data,
demultiplexed
– 16- / 18- / 20- / 24-bit addresses and 16-bit data,
multiplexed
– 16- / 18- / 20- / 24-bit a ddres ses and 8-bit data,
multiplexed
– 16- / 18- / 20- / 24-bit a ddres ses and 8-bit data,
demultiplexed
In demultiplexed bus modes addresses are output
on PORT1 and data is input / output on PORT0 or
P0L, respectively. In the multiplexed bus modes
both addresses and data use PORT0 for input /
output.
Timing characteristics of the external bus
interface (memory cycle time, memory tri-state
time, length of ALE and read / write delay) are
programmable giving the choice of a wide range
of memories and external perip herals.
Up to 4 independent address windows may be
defined (using register pairs ADDRSELx /
BUSC ONx) to access different resources an d bus
characte ristics.
These address windows are arranged
hierarchically where BUSCON4 overrides
BUS CON3 and BUSCON2 overrides BUSCON1.
All accesses to locations not covered by these 4
address windows are controlled by BUSCON0.
Up to 5 external CS signals (4 windows plus
default) can be generated in order to save
ext ernal glue logic. Access to v ery slow memories
is supported by a ‘Ready’ function.
A HOLD / HLDA protocol is available for bus
arbitration which shares external resources with
other bus masters.
The bus arbitration is enabled by setting bit
HLDEN in register PSW. After setting HLDEN
onc e, pins P6.7...P6.5 (BREQ, HL DA, HO L D) are
automatically controlled by the EBC. In master
mode (default after reset) the HLDA pin is an
output. By setting bit DP6.7 to’1’ the slav e mode is
selected where pin HLDA is switched to input.
This directly connects the slave controller to
anoth er master controller without glue logic.
For applications which require less external
memory space, the address space can be
restricted to 1M Byte, 256K Bytes or to 64K Bytes.
Port 4 outputs all 8 address lines if an address
space of 16M Bytes is used, otherwise four, two or
no address lines.
Chip select timing can be made programmable.
By default (after reset), the CSx lines change half
a CPU clock cycle after the rising edge of ALE.
With the CSCFG bit set in the SYSCON register
the CSx lines change with the rising edge of ALE.
The active le v el of the READY pin can be set by bit
RDYPOL in the BUSCONx registers. When the
READY function is enabled for a specific address
window, each bus cycle within the window must
be terminated with the active level defined by bit
RDYPOL in the associated BUSCON register.
7.1 - Programmable Chip Select Timing
Control
The ST10F269 allows the user to adjust the
pos ition of t he CS x l ine changes. By default (after
reset), the CSx lines change half a CPU clock
cycle (12.5ns at 40MHz of CPU clock) after the
r ising edge of ALE . With t he CSCFG bit s et in the
SYSCON register the CSx lines change with the
rising edge of ALE, thus the CSx lines and the
address lines change at the same time (see
Figure 11).
7.2 - READY Pro grammable Polarity
The active level of the READY pin can be selected
by software via the RDY POL bit in the B USCONx
registers.
When the READY function is enabled for a
specific address window, each bus cycle within
this window must be terminated with the active
le vel defined by t his RDYPOL bit in the associated
BUSCON registe r.
BUSCONx registers are described in Section 20.2
- System Configuration Registers.
Note ST10F269 as no internal pull-up resistor
on READY pin.
ST10F269
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Fi gure 1 1 : Chip S ele c t Del ay
Nor mal CSx
RD
Address (P1)
ALE
Segment (P4)
Normal Demultiplexed
Bus Cycle
ALE Lengthen Demultiplexed
Bus Cycle
Unlatched CSx
WR
Read/Write
Delay
Data Data
Data Data
BUS (P0)
BUS (P0)
Read/Write
Delay
ST10F269
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8 - IN TE RRUPT SYSTEM
The interrupt response time for internal program
exe cu tio n is from 125ns to 300ns at 40MHz CPU
clock.
The ST10F269 architecture supports several
mechanisms for fast and flexible response to
service requests that can be generated from
various sources (internal or external) to the
microcontroller. Any of these interrupt requests
can be serviced by the Interrupt Controller or by
the Per iph eral Eve nt Controller (PEC).
In contrast to a standard interrupt service where
the current program execution is suspended and a
branch to the interrupt vector table is performed,
just one cycle is ‘stolen’ from the current CPU
activity to perfor m a PEC service. A PEC ser vice
implies a single Byte or Word data transfer
between any two memory locations with an
additional increment of either the PEC source or
destination pointer. An individual PEC transfer
counter is implicitly decremented for each PEC
service except when perfor mi ng in the cont inuous
transfer m ode. When this counter reac hes zero, a
standard interrupt is performed to the
corresponding source related vector location.
PEC services are very well suited to perform the
transmission or the reception of blocks of data.
The ST10F269 has 8 PEC channels, each of
them off ers suc h fast interrupt-driv en data transfer
capabilities.
An interrupt control register which contains an
inte rrupt request flag, a n interrup t en able flag and
an interrupt priority bit-field is dedicated to each
existing interrupt source. Thanks to its related
register, each source can be programmed to one
of sixteen inte rrupt prio rity levels. Once star t ing to
be processed by the CPU, an interrupt service
can only be interrupted by a higher prioritized
service request. For the standard interrupt
processing, each of the possible interrupt sources
has a dedicated vector location.
Software interrupts are supported by means of the
‘TRAP’ instruction in combination with an
individu al trap (interrupt ) number.
8.1 - External Interrupts
Fast external interrupt inputs are provided to
service external interrupts with high precision
requirements. These fast interrupt inputs feature
pro gramm able e dge detection (rising edge, falli ng
edge or both edges).
Fast external interrupts may also have interrupt
sources selected from other peripherals; for
example the CANx controller receive signal
(CANx_RxD) can be used to interru pt the syst em.
This new function i s controlled usin g the ‘External
Interrupt Source Selection’ register EXISEL.
EXISEL (F1DA h / EDh) ESFR Reset Value: 0000h
1514131211109876543210
EXI7SS EXI6SS EXI5SS EXI4SS EXI3SS EXI2SS EXI1SS EXI0SS
RW RW RW RW RW RW RW RW
EXIxSS External Interrupt x Source Selection (x=7...0)
‘00’: Input from associated Port 2 pin.
‘01’: Input from “alternate source”.
‘10’: Input from Port 2 pin ORed with “alternate source”.
‘11’: Input fr om Port 2 pin ANDed with “alter nate source”.
EXIxSS Port 2 pin Alternate Source
0 P2.8 CAN1_RxD
1 P2.9 CAN2_RxD
2 P2.10 RTCSI (Timed)
3 P2.11 RTCAI (Alarm)
4...7 P2.12...15 Not used (zero)
ST10F269
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8.2 - Interrupt Registers and Vectors Location List
Table 7 shows all the available ST10F269 interrupt sources and the corresponding hardware-related
interr upt flags, ve ctors, vector locations and trap (interrupt) numbers:
Table 7 : Interrupt Sources
Source of Interrupt or PEC
Service Request Request
Flag Enable
Flag Interrupt
Vector Vector
Location Trap
Number
CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040h 10h
CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044h 11h
CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048h 12h
CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004Ch 13h
CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050h 14h
CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054h 15h
CAPCOM Register 6 CC6IR CC6IE CC6INT 00’0058h 16h
CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005Ch 17h
CAPCOM Register 8 CC8IR CC8IE CC8INT 00’0060h 18h
CAPCOM Register 9 CC9IR CC9IE CC9INT 00’0064h 19h
CAPCOM Register 10 CC10IR CC10IE CC10INT 00’0068h 1Ah
CAPCOM Register 11 CC11IR CC11IE CC11INT 00’006Ch 1Bh
CAPCOM Register 12 CC12IR CC12IE CC12INT 00’0070h 1Ch
CAPCOM Register 13 CC13IR CC13IE CC13INT 00’0074h 1Dh
CAPCOM Register 14 CC14IR CC14IE CC14INT 00’0078h 1Eh
CAPCOM Register 15 CC15IR CC15IE CC15INT 00’007Ch 1Fh
CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0h 30h
CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4h 31h
CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8h 32h
CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CCh 33h
CAPCOM Register 20 CC20IR CC20IE CC20INT 00’00D0h 34h
CAPCOM Register 21 CC21IR CC21IE CC21INT 00’00D4h 35h
CAPCOM Register 22 CC22IR CC22IE CC22INT 00’00D8h 36h
CAPCOM Register 23 CC23IR CC23IE CC23INT 00’00DCh 37h
CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0h 38h
CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4h 39h
CAPCOM Register 26 CC26IR CC26IE CC26INT 00’00E8h 3Ah
CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00ECh 3Bh
CAPCOM Register 28 CC28IR CC28IE CC28INT 00’00F0h 3Ch
CAPCOM Register 29 CC29IR CC29IE CC29INT 00’0110h 44h
CAPCOM Register 30 CC30IR CC30IE CC30INT 00’0114h 45h
CAPCOM Register 31 CC31IR CC31IE CC31INT 00’0118h 46h
CAPCOM Timer 0 T0IR T0IE T0INT 00’0080h 20h
ST10F269
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Hardware traps are exceptions or error cond itions
that ar ise du ring r un-time. They cause im mediate
non-maskable system reaction similar to a
standard interrupt service (branching to a
dedicated vector table location).
The occurrence of a hardware trap is additionally
signified by an individual bit in the trap flag
register (TFR). Except when another higher
prio ritized trap service is in progress, a hardware
trap will interrupt any other program execution.
Hardware trap ser vices cannot not be interr upted
by standard interrupt or by P EC interr upts.
8.3 - Interrupt Control Registers
All interrupt control registers are identically
organized. The lower 8 bits of an interr upt control
register contain the complete interrupt status
information of the associated source, which is
required during one round of prioritization, the
upper 8 bits of the respective register are
reserved. All interrupt control registers are
bit-ad dressa ble and all bi ts can be rea d or written
via soft ware.
This allows each interrupt source to be
programmed or modified with just one instruction.
When accessing interrupt control registers
through instructions which operate on Word data
types, their upper 8 bits (15...8) will return zeros,
when read, and will discard written data.
The layout of the Interrupt Control registers shown
below applies to each xxIC register, where xx
stands for the mnemonic for the respective
source.
CAPCOM Timer 1 T1IR T1IE T1INT 00’0084h 21h
CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4h 3Dh
CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8h 3Eh
GPT1 Timer 2 T2IR T2IE T2INT 00’0088h 22h
GPT1 Timer 3 T3IR T3IE T3INT 00’008Ch 23h
GPT1 Timer 4 T4IR T4IE T4INT 00’0090h 24h
GPT2 Timer 5 T5IR T5IE T5INT 00’0094h 25h
GPT2 Timer 6 T6IR T6IE T6INT 00’0098h 26h
GPT2 CAPREL Register CRIR CRIE CRINT 00’009Ch 27h
A/D Conversion Complete ADCIR ADCIE ADCINT 00’00A0h 28h
A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4h 29h
ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8h 2Ah
ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011Ch 47h
ASC0 Receive S0RIR S0RIE S0RINT 00’00ACh 2Bh
ASC0 Error S0EIR S0EIE S0EINT 00’00B0h 2Ch
SSC Transmit SCTIR SCTIE SCTINT 00’00B4h 2Dh
SSC Receive SCRIR SCRIE SCRINT 00’00B8h 2Eh
SSC Error SCEIR SCEIE SCEINT 00’00BCh 2Fh
PWM Channel 0...3 PWMIR PWMIE PWMINT 00’00FCh 3Fh
CAN1 Interface XP0IR XP0IE XP0INT 00’0100h 40h
CAN2 Interface XP1IR XP1IE XP1INT 00’0104h 41h
FLASH Ready / Busy XP2IR XP2IE XP2INT 00’0108h 42h
PLL Unlock/OWD XP3IR XP3IE XP3INT 00’010Ch 43h
Table 7 : Interrupt Sources (continued)
Source of Interrupt or PEC
Service Request Request
Flag Enable
Flag Interrupt
Vector Vector
Location Trap
Number
ST10F269
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xxIC (yyyyh / zzh) SFR Area Reset Value: - - 00h
8.4 - Exception an d Error Tr aps List
Table 8 shows all of the possible exceptions or error conditions that can arise during r un-time :
* - All the class B traps have the same trap number (and vector) and the same lower priority compare to the class A traps and to the resets.
- Eac h class A trap s has a dedicat ed trap nu m ber (and vec tor). They are prioriti zed in the seco nd pri ority level.
- Th e reset s have the hi ghest priori ty level and the s am e trap number.
- Th e PSW. ILVL CP U prio ri ty i s forced to t he hig h est leve l (15) when t hese exeptions are s ervic ed.
1514131211109876543210
--------
xxIR xxIE ILVL GLVL
RW RW RW RW
Bit Function
GLVL Group Level
Defines the internal order for simultaneous requests of the same priority.
3: Highest group priority
0: Lowest group priority
ILVL Interrupt Priority Level
Defines the priority level for the arbitration of requests.
Fh: Highest priority level
0h: Lowest priority level
xxIE Interrupt Enable Control Bit (individually enables/disables a specific source)
‘0’: Interrupt Request is disabled
‘1’: Interrupt Request is enabled
xxIR Interrupt Request Flag
‘0’: No request pending
‘1’: This source has raised an interrupt request
Table 8 : Trap Priorit ies
Excep tion Cond ition Trap
Flag Trap
Vector Vector
Location Trap
Number Trap*
Priority
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
RESET
RESET
RESET
00’0000h
00’0000h
00’0000h
00h
00h
00h
III
III
III
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
NMI
STKOF
STKUF
NMITRAP
STOTRAP
STUTRAP
00’0008h
00’0010h
00’0018h
02h
04h
06h
II
II
II
Class B Hardware Traps:
Undefined Opcode
Protected Instruction Fault
Illegal word Operand Access
Illegal Instruction Access
Illegal External Bus Access
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
0Ah
0Ah
0Ah
0Ah
0Ah
I
I
I
I
I
Reserved [002Ch - 003Ch] [0Bh - 0Fh]
Software Traps
TRAP Instruction Any
0000h – 01FCh
in steps of 4h
Any
[00h - 7Fh] Current
CPU
Priority
ST10F269
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9 - CAPTURE/COMPARE (CAPCOM) UNITS
The ST10F269 has two 16 channels CAPCOM
units as described in Figure 12. These support
genera tion and control of tim ing sequenc es on up
to 32 channels with a maximum resolution of
200ns at 40MHz CPU clock. The CAPCOM units
are typically used to handle high speed I/O tasks
such as pulse and waveform generation, pulse
width modulation (PMW), Digital to Analog (D/A)
conversion, software timing, or time recording
relative to external events.
Four 16-bit timers (T0/T1, T7/T8) with reload
registers provide two independent time bases for
the capture/compare register array (See Figures
13 and 14).
The input clock for the timers is programmable to
several prescaled values of the internal system
clock, or may be derived from an overflow/
underflow of timer T6 in module GPT2. This
provides a wide range of variation for the timer
period and resolution and allows precise
adjust ments to application specific requi rements.
In addition, external count inputs for CAPCOM
timers T0 and T7 allow event scheduling for the
capture/compare registers relative to external
events.
Each of the two capture/compare register arrays
contain 16 dual purpose capture/compare
registers, each of which may be individually
allocated to either CAPCOM timer T0 or T1 (T7 or
T8, respectively), and programmed for capture or
compare functions. Each of the 32 registers has
one as sociated por t pin which ser ves as an input
pin for triggering the capture function, or as an
output pin to indicate the occurrence of a compare
event. Figure 12 shows the basic structure of the
two CAPCOM units.
* Th e CA PCOM2 uni t provides 16 capt ure in puts, but only 12 compare outputs. CC 24I to CC27I ar e i nputs onl y.
Fi gure 1 2 : CAPCOM Unit Block Diagram
Pin Tx
Input
Control
2
n
n = 3 ...10
GPT2 Timer T6
Pin
TxIN
CPU
Clock
Mode
Control
(Capture
or
Compare)
16
Capture in puts
Co m par e outp uts
Pin
Ty
Input
Control
2
n
n = 3 ...10
GPT2 Timer T6
Over / Underflow
CPU
Clock
Re load R egister TxREL
CAPCO M Timer Tx
Interrupt
Request
Sixteen 16-bit
(Capture/Compare)
Registers
Over / Underflow
CAPCO M Timer Ty
Re load R egister TyREL
16
Capture / Compare*
Interrupt Requests
Interrupt
Request
x = 0, 7
y = 1, 8
ST10F269
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Fi gure 1 3 : Block Diagram of CAPCOM Timers T0 and T7
Fi gure 1 4 : Block Diagram of CAPCOM Timers T1 and T8
Note: When an external input signal is
connected to the input lines of both T0 and
T7, these timers count the input signal
synchronously. Thus the two timers can be
regarded as one timer whose contents can
be compared with 32 capture registers.
When a capture/compare register has been
selected f or capture mode, the current contents of
the allocated timer will be latched (captured) into
the capture/compare register in response to an
exter nal event at the por t pin which is associated
with this register. In addition, a specific interrupt
request for this capture/compare register is
generated.
Either a positive , a negative, or both a positiv e and
a negat ive external signal transition at the pi n c an
be selected as the trigger ing eve nt. The contents
of all registers which have been selected for one
of the five compare modes are continuously
compared with the contents of the allocated
timers.
When a match occurs between the timer value
and the value in a capture /compare register,
specific actions will be taken based on the
selected compare mode (see Table 9).
The input frequencies fTx, for the timer input
selector Tx, are determined as a function of the
CPU clocks. The timer input frequencies,
resolution and periods which result from the
selected pre-scaler option in TxI when using a
40MHz CP U clock are listed in the Table 10.
The numbe rs for the timer period s are based on a
reload value of 0000h. Note that some numbers
may be rounded to 3 significant figures.
Pin
X
Txl
CPU
Clock
TxR
MUX
GP T2 Tim er T6
Over / Underflow
Edge S elect
TxIN
Txl
Txl TxM
Input
Control
Reload Register TxREL
CAPCOM Timer Tx TxIR Interrupt
Request
x = 0, 7
X
Txl
CPU
Clock
TxR
MUX
GPT2 Timer T6
Over / Un d erflow
TxM
Reload Register TxREL
CAPCOM Timer Tx TxIR Interrupt
Request
x = 1, 8
ST10F269
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Table 9 : Compare Modes
Compare Modes Function
Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible
Mode 1 Pin toggles on each compare match; several compare events per timer period are possible
Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated
Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare event per timer
period is generated
Double Register
Mode Two registers operate on one pin; pin toggles on each compare match; several compare events
per timer per iod are possible.
Table 10 : CAPCOM Timer Input Frequencies, Resolution and P eriods
fCPU = 40MHz Timer Input Selection TxI
000b 001b 010b 011b 100b 101b 110b 111b
Pre-scaler for fCPU 8 16 32 64 128 256 512 1024
Input Frequency 5MHz 2.5MHz 1.25MHz 625kHz 312.5kHz 156.25kHz 78.125kHz 39.1kHz
Resolution 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs 25.6µs
Period 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms 1.678s
ST10F269
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10 - GENERAL PURPOSE TIMER UNIT
The GPT unit is a flexible multifunctional timer/
counter structure which is used for time related
tasks such as event timing and counting, pulse
width and duty cycle measurements, pulse
generation, or pulse multiplication. The GPT unit
contains five 16-bit timers organized into two
separate modules GPT1 and GPT2. Each timer in
each module may operate independently in
several different modes, or may be concatenated
with another timer of the same module.
10.1 - GP T1
Each of the three timers T2, T3, T4 of the GPT1
module can be configured individually for one of
four basic modes of operation: timer, gated
timer,
coun ter mod e and increm en tal interfa ce
mode.
In timer mode, the input clock f or a timer is derived
from the CPU clock, divided by a programmable
prescaler.
In counter mode, the timer is clocked in reference
to external eve nts.
Pulse width or duty cycle measurement is
supported in gated timer mode where the
operation of a timer is controlled by the ‘gate’ le vel
on an external input pin. For t hese purposes, each
timer has one associated port pin (TxIN) which
serves as gate or clock input.
Table 11 lists the timer input frequencies,
resolution and periods for each pre-scaler option
at 40MHz CPU clock. This also applies to the
Gated Timer Mode of T3 and to the auxiliary
timers T2 and T4 in Timer and Gated Timer Mode.
The count direction (up/down) for each timer is
programmable by software or may be altered
dynamically by an external signal on a port pin
(TxEUD).
In Incremental Interface Mode, the GPT1 timers
(T2, T3, T4) can be directly connected to the
incremental position sensor signals A and B by
thei r respective inputs TxIN and TxEUD.
Direction and count signals are internally der ived
from these two input signals so that the contents
of the respective timer Tx corresponds to the
sensor position. The third position sensor signal
T OP0 can be connected to an interrupt input.
Timer T3 has output t oggle latches (TxOTL) which
changes state on each timer ov er f lo w / underflow.
The st ate of this latch m ay be output on por t p ins
(TxOUT) for time out monitoring of external
hardware components, or may be used internally
to clock timers T2 and T4 for high resolution of
long duration measurem ent s.
In addition to thei r basic operating modes, timers
T2 and T4 ma y be configured as relo ad or capture
registers for timer T3. When used as capture or
reload registers, timers T2 and T4 are stopped.
The cont ents of timer T3 is captured into T2 or T4
in response to a signal at their associated input
pi ns (T xIN ).
Timer T3 is reloaded with the contents of T2 or T4
triggered either by an external signal or by a
selectable state transition of its toggle latch
T3OTL. When both T2 and T4 are configured to
alte r nat ely relo ad T 3 on opposite state transitions
of T3OTL with the low and high times of a PWM
signal, this signal can be constantly generated
without software intervention.
Table 11 : GPT1 Timer Input F requencies, Resolution and P eriods
fCPU = 40MHz Timer Input Selection T2I / T3I / T4I
000b 001b 010b 011b 100b 101b 110b 111b
Pre-scaler factor 8 16 32 64 128 256 512 1024
Input Freq 5MHz 2.5MHz 1.25MHz 625kHz 312.5kHz 156.25kHz 78.125kHz 39.1kHz
Resolution 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs 25.6µs
Period maximum 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms 1.678s
ST10F269
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Fi gure 1 5 : Block Diagram of GPT1
10.2 - GP T2
The GPT2 module provides precise event control
and time measurement. It includes tw o t imers (T5,
T6) and a capture/reload register (CAPREL). Both
timers c an be clo cked with an inp ut clo ck which is
derived from the CPU clock via a programmable
prescaler or with external signals. The count
direction (up/down) for each timer is
programmable by software or may addi tionally be
altered dynamically by an ext ernal signal on a port
pin (TxEUD). Concatenation of the timers is
supported via the output toggle latch (T6OTL) of
timer T6 which changes its state on each timer
ove rflow/underflow.
The st ate of this latch may be used to c lock timer
T5, or it ma y be output on a port pin (T6OUT). The
overflow / underflow of timer T6 can additionally
be used to clock the CAPCOM timers T0 or T1,
and t o cause a reload f rom the CA PREL regist er.
The CAPREL register may capture the contents of
timer T5 bas ed on an external signa l transition on
the corresp onding port pin (CA P IN), an d tim er T 5
may optionally be cleared after the capture
procedure. This allows absolute time differences
to be measured or pulse multiplication to be
performed without software overhead.
The capture trigger (timer T5 to CAPREL) may
also be generated upon transitions of GPT1 timer
T3 inputs T3IN and/or T3EUD. This is
advantageous when T3 operates in Incremental
Interface Mode.
Table 12 lists the timer input frequencies,
resolution and periods for each pre-scaler option
at 40MHz CPU clock. This also applies to the
Gated Timer Mode of T6 and to the auxiliary timer
T5 in Timer and Gated Timer Mod e.
2
n
n=3 ...1 0
2
n
n=3 ...1 0
2
n
n=3...10
T2EUD
T2IN
CPU Clock
CPU Clock
CPU Clock
T3IN
T4IN
T3EUD
T4EUD
T2
Mode
Control
T3
Mode
Control
T4
Mode
Control
GPT1 Timer T2
GPT1 Timer T3
GPT1 Timer T4
T3OTL
Reload
Capture
U/D
U/D
Reload
Capture
Interrupt
Request
Interrupt
Request
Interrupt
Request
T3OUT
U/D
Table 12 : GPT2 Timer Input F requencies, Resolution and P eriod
fCPU = 40MHz Timer Input Selection T5I / T6I
000b 001b 010b 011b 100b 101b 110b 111b
Pre-scaler factor 4 8 16 32 64 128 256 512
Input Freq 10MHz 5MHz 2.5MHz 1.25MHz 625kHz 312.5kHz 156.25kHz 78.125kHz
Resolution 100ns 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs
Period maximum 6.55ms 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms
ST10F269
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Fi gure 1 6 : Block Diagram of GPT2
2
n
n=2 ...9
2
n
n=2 ...9
T5EUD
T5IN
CPU Clock
CPU Clock
T6IN
T6EUD
T5
Mode
Control
T6
Mode
Control
GPT2 Timer T5
GPT2 Timer T6
U/D
Interrupt
Request
U/D
GPT2 CAPREL
T60TL
Toggle FF
T6OUT
CAPIN
Reload Interrupt
Request
to CAPC O M
Timers
Capture
Clear
Interrupt
Request
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11 - PWM MOD U LE
The pulse width mo dulation module c an generate
up to f our PWM output signals using edge-aligned
or centre-aligned PWM. In addition, the PWM
module can generate PWM burst signals and
single shot outputs. The Table 13 shows the PWM
frequencies for different resolutions. The level of
the output signals is selectable and the PWM
modu le can generate interrup t request s.
Fi gure 1 7 : Block Diagram of PWM Mod ule
Table 13 : PWM Unit Freq uencies and Resolution at 40MHz CP U Clock
Mode 0 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit
CPU Clock/1 25ns 156.25kHz 39.1kHz 9.77kHz 2.44Hz 610Hz
CPU Clock/64 1.6 µs 2.44Hz 610Hz 152.6Hz 38.15Hz 9.54Hz
Mode 1 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit
CPU Clock/1 25ns 78.12kHz 19.53kHz 4.88kHz 1.22kHz 305.17Hz
CPU Clock/64 1.6 µs 1.22kHz 305.17Hz 76.29Hz 19.07Hz 4.77Hz
PPx Period Register
Comparator
PTx
16-bit Up/Down Counter
Shadow Register
PWx Pulse Width Register
Input
Run
Control
Cloc k 1
Cloc k 2
Comparator
*
*
*
Up/Down/
Clear Control
Match
Output Control
Match
Write Control
*User readable / writeable register
Enable POUTx
ST10F269
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12 - PARALLEL PORT S
12.1 - Introduction
The S T10F269 M CU provides up to 111 I/O lines
with programmable features. These capabilities
brin g very flexible adaptation of this MCU t o wide
range of applications.
ST10F269 has 9 groups of I/O lines gathered as
following:
– P ort 0 i s a 2 time 8-bit port named P 0L (Low as
less signifi cant Byte) and P0H (high as most sig-
nificant Byte)
– Port 1 is a 2 time 8-bit port named P1L and P1H
– Port 2 is a 16-bit port
– Port 3 is a 15-bit port (P3.14 line is not imple-
mented)
– Port 4 is a 8-bit port
– Port 5 is a 16-bit port input only
– P ort 6, Port 7 and Port 8 are 8-bit port
These ports may be used as general purpose
bidirectionnal input or output, software controlled
with dedicated registers.
For example the output drivers of six of the po rts
(2, 3, 4, 6, 7, 8) can be configured (bit-wise) for
push-pull or open drain operation using ODPx
registers.
In add ition, the sin k and th e s ource capabil ity a nd
the r ise / fall time of the transition of the signal of
some of the push-pull buffers can be programmed
to fit the driving requirements of the application
and t o m ini mize EM I. T his feature is i mp lement ed
on Port 0, 1, 2, 3, 4, 6, 7 and 8 with the control
registers POCONx. The output driv ers capabilities
of ALE, RD, WR control lines are programmable
with the dedicated bits of POCON20 control
register.
The input threshold levels are programmable
(TTL/CMOS) for 5 ports (2, 3, 4, 7, 8). The logic
level of a pin is clocked into the input latch once
per state time, regardless whether the port is
configured for input or output. The threshold is
selec ted with the PICON registe r control bits.
A write operation to a port pin configured as an
input causes the value to be written into the port
output latch, while a read operation returns the
latched state of the pin itself. A read-modify-write
operation reads the value of the pin, modifies it,
and w rites it back to the output latch.
Writing to a pin configured as an output
(DPx. y=‘1’) causes t he output latch and the pin to
have the written value, since the output buffer is
enabled. Reading this pin retur ns the value of the
output latch. A read-modify-write operation reads
the value of the output latch, modifies it, and
writes it back to the output latch, thus also
modifying the le vel at the pin.
I/O lines support an alternate function which is
detailed in the follo wing description of each port.
ST10F269
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Fi gure 1 8 : S FRs and Pins Associated with the Pa rall el Ports
Data Input / Output Register
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
YP0L
----- - - -YYYYYYYYP0H
----- - - - YYYYYYYYP1L
----- - - - YYYYYYYYP1H
YYYYY YYYYYYYYYYYP2
Y-YYY YYYYYYYYYYYP3
----- - - - YYYYYYYYP4
YYYYY YYYYYYYYYYYP5
----- - - - YYYYYYYYP6
----- - - - YYYYYYYYP7
----- - - - YYYYYYYYP8
Direction Control Registers
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
YDP0L
----- - - - YYYYYYYYDP0H
----- - - - YYYYYYYYDP1L
----- - - - YYYYYYYYDP1H
YYYYY YYYYYYYYYYYDP2
Y-YYY YYYYYYYYYYYDP3
----- - - - YYYYYYYYDP4
----- - - -YYYYYYYYDP6
----- - - - YYYYYYYYDP7
----- - - -YYYYYYYYDP8
Threshold / Open Drain Control
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
Y
6
Y
5
-
4
Y
3
Y
2
Y
1
Y
0
YPICON
YYYYY YYYYYYYYYYYODP2
--Y-Y YYYYYYYYYYYODP3
--------YY------ODP4
----- - - -YYYYYYYYODP6
----- - - -YYYYYYYYODP7
----- - - -YYYYYYYYODP8
Output Driver Control Register
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
YPOCON0L
----- - - - YYYYYYYYPOCON0H
----- - - - YYYYYYYYPOCON1L
----- - - - YYYYYYYYPOCON1H
YYYYY YYYYYYYYYYYPOCON2
Y-YYY YYYYYYYYYYYPOCON3
----- - - - YYYYYYYYPOCON4
----- - - -YYYYYYYYPOCON6
----- - - - YYYYYYYYPOCON7
----- - - -YYYYYYYYPOCON8
----- - - -YYYYYYYYPOCON20 *
* RD, WR, ALE lin es only
Y : Bit has an I/O function
- : Bit has no I/O dedicated function or is not implem ented
Regis t er be longs to ES F R are aE:
YYYYY YYYYYYYYYYYP5DIDIS
PICON: P2LIN P2HI N
P3LIN P3HI N
P4LIN
P6 LI N (to be implem ented)
P7LIN
P8LIN
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
ST10F269
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12.2 - I/O’s Special Features
12.2.1 - Open Drain M ode
Some of the I/O ports of ST10F269 support the
open drain capability. This programmable feature
may be used with an external pull-up resistor, in
order to get an AND wired logical function.
This feature is implemented for ports P2, P3, P4,
P6, P7 and P8 (see respective sections), and is
controlled through the respective Open Drain
Control Registers ODPx. These registers allow
the individual bit-wise selection of the open drain
mode for each port line. If the respective control
bit ODPx.y is ‘0’ (default after reset), the output
driver i s in the push-pull mode. If ODPx.y is ‘1’, the
open drain configuration is selected. Note that all
ODPx registers are located in the ESFR space
(See Figure 19).
12.2.2 - Input Threshold Control
The standard inputs of the ST10F269 determine
the status of input signals according to TTL levels.
In order to accept and recognize noisy signals,
CMOS-like input thresholds can be selected
instea d of the sta ndard TT L thresh olds for all pins
of Por t 2, Port 3, Por t 4, Por t 7 and Port 8. Thes e
special thresholds are defined above the TTL
thresholds and feature a defined hysteresis to
prevent the inputs from toggling while the
respectiv e input signal le vel is near the thresholds.
The Port Input Control register PICON is used to
select these thresholds for each Byte of the
indicat ed por ts, this m eans the 8-bit por ts P 4, P7
and P 8 are controlled by one bit each wh ile por ts
P2 and P3 are controlle d by two bits each .
All options for ind ivi dual di rection and output mode
control are available for each pin, independent of
the selected input threshold. The input hysteresis
provides stable inputs from noisy or slowly
changing exter nal signals (See Figure 20).
PICON (F1C4h / E2h) E S F R R e s e t V a l u e: - - 0 0 h
1514131211109876543210
--------P8LINP7LIN-P4LINP3HINP3LINP2HINP2LIN
RW RW RW RW RW RW RW
Bit Function
PxLIN Port x Low Byte Input Level Selection
0: Pins Px.7...Px.0 switch on standard TTL input levels
1: Pins Px.7...Px.0 switch on special threshold input levels
PxHIN Port x High Byte Input Level Selection
0: Pins Px.15...Px.8 switch on standard TTL input levels
1: Pins Px.15...Px.8 switch on special threshold input levels
Fi gure 1 9 : Output Drivers in Push-p ull Mode and in Open Drain Mode
Pin
Q
Push-Pull Output Driver
Q
Open Drain Output Driver
External
Pullup
Pin
ST10F269
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12.2.3 - Output Driver Control
The port output control registers POCONx allow
to sele ct the port output driver cha racteristics of a
port. The aim of these selections is to adapt the
output drivers to the application’s requirements,
and to improve the EMI behaviour of the device.
Two characteristics may be selected:
Edge characteristic defines the rise/fall time for
the respective output. Slow edges reduce the
peak currents that are sinked/sourced when
changing the voltage level of an external
capacitive load. For a bus interface or pins that
are changing at frequency higher than 1MHz,
however, fast edges may still be req uired.
Driver characteristic defines either the general
drivin g capa bility of th e respe ctive driver, or if the
driver strength is reduced after the target output
level has been reached or not. Reducing the
driver strength increases the output’s internal
resistance, which attenuates noise that is
imported via the output line. For driving LEDs or
power transistors, however, a stable high output
current may still be required as described below.
This rise / fall time of 4 I/O pads (a nibble) is
selected using 2-bit named PNxEC. That means
Port Nibble (x = nibble number, it could be 3 as for
Port 2.15 to 2.12) Edge Characteristic.
The sink / source capability of the same 4 I/O
pads is selected using 2-bit named PNxDC. T hat
mean s Port Nibble (x = nibble number) Drive
Characteri stic (See Table 14).
POCONx (F0yyh / zzh) for 8-bit Ports ESFR Reset Value: --00h
POCONx (F0yyh / zzh) for 16-bit Ports ESFR Reset Value: 0000h
Note: In case of reading an 8 bit P0CONX regist er, high Byte ( bit 15..8) is read as 00h
Fi gure 2 0 : Hy steresis for Special Input Thresholds
Input level
Bit state
Hysteresis
1514131211109876543210
--------PN1DC PN1EC PN0DC PN0EC
RW RW RW RW
1514131211109876543210
PN3DC PN3EC PN2DC PN2EC PN1DC PN1EC PN0DC PN0EC
RW RW RW RW RW RW RW RW
Bit Function
PNxEC Por t Nibble x Edge Charac teris tic (rise/fall time)
00: Fast edge mode, rise/fall times depen d on the size of the driver.
01: Slow edge mode, rise/fa ll times ~60 ns
10: Reserved
11: Reserved
PNxDC Port Nibble x Driver Characteristic (output current)
00: High Current mode:
Dr ive r always operates with maximum strength.
01: Dynamic Current mode:
Dr iver strength is reduced after the target level has been reached.
10: Low Current mode:
Dr iver always operates with reduced strength.
11: Reserved
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The table lists the defined PO CON registers and the allocation of control bit-fields and port pins.
Dedicated P ins Output Con trol
Programmable pad drivers also are suppor ted for the ded icated pins ALE, RD and WR. For t hese pads,
a special POCON20 register is provided.
PO CON20 (F0A Ah / 55h) ESFR Reset Value: --00h
Table 14 : Po rt Control Register Allocation
Control
Register Physical
Address 8-bit
Address Controlled Port Nibble
3210
POCON0L F080h 40h P0L.7...4 P0L.3...0
POCON0H F082h 41h P0H.7...4 P0H.3...0
POCON1L F084h 42h P1L.7...4 P1L.3...0
POCON1H F086h 43h P1H.7...4 P1H.3...0
POCON2 F088h 44h P2.15...12 P2.11...8 P2.7...4 P2.3...0
POCON3 F08Ah 45h P3.15, 3.13, 3.12 P3.11...8 P3.7...4 P3.3...0
POCON4 F08Ch 46h P4.7...4 P4.3...0
POCON6 F08Eh 47h P6.7...4 P6.3...0
POCON7 F090h 48h P7.7...4 P7.3...0
POCON8 F092h 49h P8.7...4 P8.3...0
1514131211109876543210
--------PN1DC PN1EC PN0DC PN0EC
RW RW RW RW
PN0EC RD, WR Edge Characteristic (rise/fall time)
00: Fast edge mode, rise/fall times depen d on the size of the driver.
01: Slow edge mode, rise/fa ll times ~60 ns
10: Reserved
11: Reserved
PN0DC RD, WR Driver Characteristic (output current)
00: High Current mode:
Dr ive r always operates with maximum strength.
01: Dynamic Current mode:
Dr iver strength is reduced after the target level has been reached.
10: Low Current mode:
Dr iver always operates with reduced strength.
11: Reserved
PN1EC ALE Edge Characteristic (rise/fall time)
00: Fast edge mode, rise/fall times depen d on the size of the driver.
01: Slow edge mode, rise/fa ll times ~60 ns
10: Reserved
11: Reserved
PN1DC AL E Driver Characteristic (output current)
00: High Current mode:
Dr ive r always operates with maximum strength.
01: Dynamic Current mode:
Dr iver strength is reduced after the target level has been reached.
10: Low Current mode:
Dr iver always operates with reduced strength.
11: Reserved
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12.2.4 - Alternate Port Functions
Each por t line has one associated programmable
alternate input or output function.
– PORT0 and PORT1 may be used as address
and data lines when ac cessing external memory.
– Port 2, Port 7 and Port 8 are associated with the
capture inputs or compare outputs of the CAP-
COM units and/or with the outputs of the PWM
module.
Por t 2 is also used for fast exter nal interrupt in-
puts and for timer 7 input .
– Port 3 includes the alternate functions of timers,
serial interfaces, the optiona l bus control s ignal
BHE and the system clock output (CLKOUT).
– Port 4 outputs the additional segment address
bit A16 to A23 in systems where segmentation
is enabled to access more than 64K Bytes of
memory.
– Port 5 is used as analog input channels of the
A/D co nverter or as time r control signals.
– Port 6 provides optional bus arbitration signals
(BREQ, HLDA, H OL D) and chip select signals.
If an alternate output function of a pin is to be
used, the direction of this pin must be
programmed for output (DPx.y=‘1’), except for
some signals that are used directly after reset and
are configured automatically. Otherwise the pin
remains in the high-impedance state and is not
effected by the alternate output function. The
respectiv e port latch should hold a ‘1’, because its
output is ANDed with the alternate output data
(except for PWM output signals).
If an alternate in put function of a p in is used, the
directio n o f the pin must be program med for input
(DPx.y= ‘0’) if an extern al device is dr iving the pin.
The input direction is the default after reset. If no
external device is connected to the pin, however,
one can also set the direction for this pin to output.
In this case, the pin reflects the state of the port
output latch. Thus, the alternate input function
reads the value stored in the port output latch.
This can be used for testing pur poses to allow a
software trigger of an alternate input function by
writing to the port output latch.
On most of the port lines, the application software
must set the proper direction when using an
alternate input or output function of a pin. This is
done by setting or clearing the direction control bit
DPx.y of the pin before enabling the alternate
function. There are port lines, however, where t he
direction of the port line is switched automatically.
For instance, in the multiplexed external bus
mode s of P ORT0, the direction must be switched
several times for an instruction fetch in order to
output the addresses and to input the data.
Obviously, this cannot be done through
instructions. In these cases, the direction of the
por t line is switched automatically by hardware if
the alternat e function of such a pin is enabled.
To determine the appropriate level of the port
output latches check how the alternate data
output is combined with the respective port latch
output.
There is one basic structure for all port lines
suppor ting onl y one alter nate input function. Por t
lines with only one alternate output function,
however, have different structures. It has to be
adapted to support the normal and the alternate
funct ion features.
All port lin es that are not u sed for these alter nate
functions may be used as general purpose I/O
lines. When using port pins for general purpose
outpu t, the initial output valu e should be written to
the port latch prior to enabling the output drivers,
in order to avoid undesired transitions on the
output pins. This applies to single pins as well as
to pin groups (see exa mples below).
SINGLE_BIT: BSET P4.7 ; Initial output level is "high"
BSET DP4.7 ; Switch on the output driver
BIT_GROUP: BFLDH P4, #24H, #24H ; Initial output level is "high"
BFLDH DP4, #24H, #24H ; Switch on the output drivers
Note: When using se ver al BSET pairs to control more pins of one port, these pairs must be separated by
instructions, which do not apply to the respective por t (See Chapter 6 - Central Processing Unit
(CPU)).
ST10F269
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12.3 - P O RT 0
The two 8-bit ports P0H and P0L represent the
higher and lower part of PORT0, respectively.
Both halves of PORT0 can be written (via a PEC
transfer) without effecting the other half.
If this port is used for general purpose I/O, the
direction of each line can be configured via the
corresponding direction registers DP0H and
DP0L.
P0L (FF00h / 80h) SF R Reset Value: --00h
P0H (FF02h / 81h) SFR Reset Value: --00h
DP0L (F100h / 80h) ESFR Reset Value: --00h
DP0H (F102h / 81h) ESFR Reset Value: --00h
1514131211109876543210
--------P0L.7P0L.6P0L.5P0L.4P0L.3P0L.2P0L.1P0L.0
RW RW RW RW RW RW RW RW
1514131211109876543210
--------P0H.7P0H.6P0H.5P0H.4P0H.3P0H.2P0H.1P0H.0
RW RW RW RW RW RW RW RW
P0X.y Port Data Register P0H or P0L Bit y
1514131211109876543210
--------DP0L.7DP0L.6DP0L.5DP0L.4DP0L.3DP0L.2DP0L.1DP0L.0
RW RW RW RW RW RW RW RW
1514131211109876543210
--------DP0H.7DP0H.6DP0H.5DP0H.4DP0H.3DP0H.2DP0H.1DP0H.0
RW RW RW RW RW RW RW RW
DP0X.y Port Direction Register DP0H or DP0L Bit y
DP0X.y = 0: Port line P0X .y is an input (high-impedance)
DP0X.y = 1: Port line P0X.y is an output
ST10F269
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12.3.1 - Alternate Functions of PORT0
W hen an external bus is enabled, PORT0 is used
as data bus or address/data bus.
Note that an exte r nal 8-bit demultiplexed bus only
use s P0 L, while P0H is f ree for I/ O (provided that
no other bus mode is enabled).
PO RT 0 is also used t o select the system star t-up
configuration. During reset, PORT0 is configured
to input, and each line is held high through an
inte r nal pull -up device.
Each line can now be individually pulled to a low
level (see Section 21.3 - DC Characteristics)
through an external pull-down device. A default
configuration is selected when the respective
PORT0 lines are at a high level. Through pulling
individual lines to a low level, this default can be
changed according to the needs of the
applications.
The in tern al pull-up devices are designed i n such
way that an external pull-down resistors (see Data
Sheet specification) can be used to apply a
correct lo w lev el.
These external pull-down resistors can remain
con nected to the PORT0 pi ns also durin g nor mal
operation, however, care h as to b e taken in order
to not disturb the nor mal function of PORT0 (this
might be the case, for example, if the external
resistor value is too low).
With the end of reset, the selected bus
configuration will be written to the BUSCON0
register.
The configuration of the high byte of PORT0, will
be copied into the special register RP0H. This
read-only register holds the selection for the
number of chip selects and segment addresses.
Software can read this register in order to react
according to the selected configuration, if
required.
When the reset is terminated, the internal pull-up
devices are switched off, and PORT0 will be
switc hed to the appropriate operating mode.
During external accesses in multiplexed bus
modes PORT0 first outputs the 16-bit
intra-segment address as an alternate output
function. PORT0 is then switched to
high-im pedance i nput mode to read the incomi ng
instruction or data. In 8-bit data bus mode, two
memory cycles are required for word accesses,
the first for the low Byte and the second for the
high Byte of the Word.
Durin g write cycles PORT0 output s the data Byte
or Word after outputting the address. During
external accesses in demultiplexed bus modes
PORT0 reads the incoming instruction or data
Word or outputs the data Byte or Word.
Fi gure 2 1 : PORT0 I/O and Alternate Functions
P0H.7
P0H.6
P0H.5
P0H.4
P0H.3
P0H.2
P0H.1
P0H.0
P0L.7
P0L.6
P0L.5
P0L.4
P0L.3
P0L.2
P0L.1
P0L.0
PORT0
P0H
P0L
Alternate Function a) b) c) d)
General Purpose
Input/Output 8-bit
Demulti p l exed Bu s 16-bit
Demulti p lexed Bus 8-bit
Multiplexed Bus 16-bit
Multip lexed Bu s
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A15
A14
A13
A12
A11
A10
A9
A8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
ST10F269
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When an external bus mode is enabled, the
direction of the port pin and the loading of data
into the port output latch are controlled by the bus
controller hardware.
The input of the port output Buffer i s disconnected
from the internal bus and is switched to the line
labeled “Alternate Data Output” via a multiplexer.
The alternate data can be the 16-bit intra-segment
address or the 8/16-bit data information. The
incoming data on PORT0 is read on the line
“Alternate Data Input”. While an external bus
mode is enabled, the user software should not
write to the port output latch, otherwise
unpredict able results may occur.
When the external bus modes are disabled, the
contents of the direction register last written by the
use r becomes ac tive.
The Figure 22 shows the structure of a PORT0
pin.
Fi gure 2 2 : Block Diagram of a PORT0 Pin
Direction
Latch
Write DP0H.y / DP0L.y
Read DP0H.y / DP0L.y
Port Output
Latch
Write P0H.y / P0L.y
Read P0H.y / P0L.y
Internal Bus
MUX
0
1
MUX
0
1
Alternate
Data
Output
MUX
0
1
Alternate
Direction
Input
Latch
Clock
P0H.y
P0L.y
Output
Buffer
y = 7...0
Alternate
Function
Enable
Port Data
Output
ST10F269
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12.4 - P O RT 1
The two 8-bit ports P1H and P1L represent the higher and l ower part of PORT1, r espective ly. Both halv es
of PORT1 can be written (via a PEC transfer) without effecting the other half.
If this port is used for general purpose I/O, the direction of each line can be configured via the
correspon ding direction registers DP1H and DP1L.
P1L (FF04h / 82h) SF R Reset Value: --00h
P1H (FF06h / 83h) SFR Reset Value: --00h
DP1L (F104h / 82h) ESFR Reset Value: --00h
DP1H (F106h / 83h) ESFR Reset Value: --00h
12.4.1 - Alternate Functions of PORT1
W hen a demultiplexed ext ernal bus is enabled, PORT1 is used as address bus.
Note: Dem ultiplexed bus mode s us e P ORT1 as a 16-bit port. Ot herwise a ll 1 6 port lines can be us ed for
general purpose I/O .
The upper 4 pins of PORT1 (P1H.7...P1H.4) are used as capture input lines (CC27IO...CC24 IO).
Durin g extern al accesses in demultiplexed bus m odes PORT1 outputs the 16-bit i ntra-segment address
as an alter nat e out put function.
Durin g exter nal acc esses in mu ltiplexed bus m odes, wh en no B US CON regist er sel ects a demultiplexed
bus mode, PORT1 is not used and is available for gene ral pur pos e I/O.
1514131211109876543210
--------P1L.7P1L.6P1L.5P1L4P1L.3P1L.2P1L.1P1L.0
RW RW RW RW RW RW RW RW
1514131211109876543210
--------P1H.7P1H.6P1H.5P1H.4P1H.3P1H.2P1H.1P1H.0
RW RW RW RW RW RW RW RW
P1X.y Port Data Register P1H or P1L Bit y
1514131211109876543210
- - - - - - - - DP1L.7 DP1L.6 DP1L.5 DP1L.4 DP1L.3 DP1L.2 DP1L.1 DP1L.0
RW RW RW RW RW RW RW RW
1514131211109876543210
- - - - - - - - DP1H.7 DP1H.6 DP1H.5 DP1H.4 DP1H.3 DP1H.2 DP1H.1 DP1H.0
RW RW RW RW RW RW RW RW
DP1X.y Port Direction Register DP1H or DP1L Bit y
DP1X.y = 0: P ort line P1X.y is an input (high-impedance)
DP1X.y = 1: Por t line P1X.y is an output
ST10F269
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Fi gure 2 3 : PORT1 I/O and Alternate Functions
When an external bus mode is enabled, the
direction of the port pin and the loading of data
into the port output latch are controlled by the bus
controller hardware.
The input of the por t Buffer latch is disconnected
from the internal bus and is switched to the line
labeled “Alternate Data Output” via a multiplexer.
The alternate data is the 16-bit intra-segment
address. While an external bus mode is enabled,
the user software should not write to the port
output latch, otherwise unpredictable results may
occur . When the external bus modes are disabled,
the contents of the direction register last written by
the user become s active.
The Figure 24 shows the structure of a PORT1
pin.
PORT1
P1H
P1L
Alternate Function a)
Genera l Purpos e Input/Out put 8/ 16-b it Demult iplexed Bus
b)
CAPCOM2 Capture Inputs only
P1H.7
P1H.6
P1H.5
P1H.4
P1H.3
P1H.2
P1H.1
P1H.0
P1L.7
P1L.6
P1L.5
P1L.4
P1L.3
P1L.2
P1L.1
P1L.0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CC27IO
CC26IO
CC25IO
CC24IO
Fi gure 2 4 : Block Diagram of a PORT1 Pin
Direction
Latch
Write DP1H.y / DP1L.y
Read DP 1 H.y / DP 1L.y
Port Ou tp ut
Latch
W r i t e P 1H.y / P 1L.y
Read P1H.y / P1L.y
Internal Bus
MUX
0
1
MUX
0
1
MUX
0
1
“1”
Input
Latch
Clock
P1H.y
P1L.y
Output
Buffer
y = 7...0
Alternate
Function
Enable
Port Data
Output
Alternate
Data
Output
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12.5 - Port 2
If this 16-bit port is used for general purpose I/O, the direction of each line can be configured via the
correspon ding direction regi ster DP2. Eac h port line ca n be switched into push/pull or open drain mode
via the open drain control register ODP2.
P2 (FF C0h / E0h) SFR Reset Value: 0000h
DP2 (FFC2h / E1h) SFR Reset Value: 0000h
ODP2 (F1C2h / E1h) ESFR Reset Value: 0000h
12.5.1 - Alternate Functions of Port 2
All Port 2 lines (P2.15...P2.0) serve as capture
inputs or compare outputs (CC15IO...CC0IO) for
the CAPC OM 1 unit.
W hen a Port 2 line is us ed a s a capt ure inpu t, t he
state of the input latch, which represents the state
of the port pin, is directed to the CAPCOM unit via
the line “Alternate Pin Data Input”. If an external
capture trigger signal is used, the direction of the
respe ctive pin must be set to input.
If the direction is s et t o output, t he st ate of the port
output latch will be read since the pin represents
the state of the output latch.
This can be used to trigger a capture event
through software by setting or clearing the port
latch. Note that in the output configuration, no
external device may drive the pin, otherwise
confl ic ts wou ld occu r.
When a Port 2 line is used as a compare output
(compare m odes 1 and 3), the com pare event (or
the timer overflow in compare mode 3) directly
effects the por t output latch. In compare mode 1,
when a valid compare match occurs, the state of
the port output latch is read by the CAPCOM
control hardware via the line “Alternate Latch Data
Input”, inverted, and written back to the latch via
the line “Alternate Data Output”.
The port output latch is clocked by the signal
“Compare Trigger” which is generated by the
CAPCOM unit. In compare mode 3, when a match
occurs, the value '1' is written to the port output
latch via the line “Alternate Data Output”. When
an overflow of the corresponding timer occurs, a
'0' is written to the port output latch. In bot h cases,
the output latch is clocked by the signal “Compare
Trigger”.
1514131211109876543210
P2.15 P2.14 P2.13 P2.12 P2.11 P2.10 P2.9 P2.8 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
P2.y Port Data Regist er P2 Bit y
1514131211109876543210
DP2
.15 DP2
.14 DP2
.13 DP2
.12 DP2
.11 DP2
.10 DP2
.9 DP2
.8 DP2
.7 DP2
.6 DP2
.5 DP2
.4 DP2
.3 DP2
.2 DP2
.1 DP2
.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
DP2.y Port Direction Register DP2 Bit y
DP2.y = 0: Port line P2.y is an input (high-impedan ce)
DP2.y = 1: Port line P2.y is an output
1514131211109876543210
ODP2
.15 ODP2
.14 ODP2
.13 ODP2
.12 ODP2
.11 ODP2
.10 ODP2
.9 ODP2
.8 ODP2
.7 ODP2
.6 ODP2
.5 ODP2
.4 ODP2
.3 ODP2
.2 ODP2
.1 ODP2
.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ODP2.y Port 2 Op en Drain Control Register Bit y
OD P2.y = 0: Port line P2.y output dr iver in push/pull mode
OD P2.y = 1: Port line P2.y output dr iver in open drain mo de
ST10F269
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The di rection of the pi n should b e s et to output by
the user, otherwise the pin will be in the
high-im pedanc e state and w ill not r eflec t the state
of the output latch.
A s can be seen f rom the p or t str ucture in Fig ure
26, the user software always has free access to
the port pin even when it is used as a compare
outpu t. This is useful fo r setting up the initial level
of the pin when using compare mode 1 or the
double-register mode. In these modes, unlike in
compare mode 3, the pin is not set to a specific
value when a compare match occurs, but is
toggl ed instead.
When the user wants to write to the port pin at the
same time a compare trigger tries to clock the
output latch, the write operation of the user
software has priority. Each time a CPU write
access to the port output latch occurs, the input
multiplexer of the port output latch is switched to
the line connected to the internal bus. The port
output latch will receive the v alue from the internal
bus and the hardware triggered change will be
lost.
As all other capture inputs, the capture input
funct ion of pins P2.15 ...P2.0 can a lso be used as
external interrupt inputs (200ns sample rate at
40MHz CPU clock).
The upper eight Port 2 lines (P2.15...P2.8) also
can serve as Fast External Interrupt inputs from
EX0I N to EX 7IN (Fast exter nal inte rr upt sampli ng
rate is 25ns at 40MHz CPU clock).
P2.15 in addition serves as input for CAPCOM2
timer T7 (T7IN). The Table 15 summarizes the
alternate functions of Port 2.
Table 15 : Alter nat e Funct ions of Port 2
Port 2 Pin Alternate Function a) Alternate Function b) Alternate Function c)
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
CC0IO
CC1IO
CC2IO
CC3IO
CC4IO
CC5IO
CC6IO
CC7IO
CC8IO
CC9IO
CC10IO
CC11IO
CC12IO
CC13IO
CC14IO
CC15IO
-
-
-
-
-
-
-
-
EX0IN Fast External Interrupt 0 Input
EX1IN Fast External Interrupt 1 Input
EX2IN Fast External Interrupt 2 Input
EX3IN Fast External Interrupt 3 Input
EX4IN Fast External Interrupt 4 Input
EX5IN Fast External Interrupt 5 Input
EX6IN Fast External Interrupt 6 Input
EX7IN Fast External Interrupt 7 Input
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
T7IN T7 External Count Input
Fi gure 2 5 : Port 2 I/O and Alternate Functions
Port 2
Alternate Function a)
Genera l Purpos e
Input / Output CAPCOM1
Capture Input / Compare Output
b)
Fast External
Interrupt Input
c)
CAPCOM2
Timer T7 Input
P2.15
P2.14
P2.13
P2.12
P2.11
P2.10
P2.9
P2.8
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
CC15IO
CC14IO
CC13IO
CC12IO
CC11IO
CC10IO
CC9IO
CC8IO
CC7IO
CC6IO
CC5IO
CC4IO
CC3IO
CC2IO
CC1IO
CC0IO
EX7IN
EX6IN
EX5IN
EX4IN
EX3IN
EX2IN
EX1IN
EX0IN
T7IN
ST10F269
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The pins of Port 2 combine inter n al bus da ta with alter nate data output before the por t latch input.
Fi gure 2 6 : Block Diagram of a Port 2 Pin
Open Drain
Latch
Write ODP2.y
Read O DP2.y
Direction
Latch
Write DP2.y
Read D P2.y
Internal Bus
MUX
0
1
A lte rn a te Data Input
Input
Latch
Clock
P2.y
CCyIO
Output
Buffer
x = 7. ..0
Alternate
Data
Output
MUX
0
1Output
Latch
≥
1
Write Port P2.y
Compare Trigger
Read P2.y
Fast External Interrupt Input
EXxIN
y = 15...0
ST10F269
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12.6 - Port 3
If this 15-bit por t is used for general pur pose I/O,
the direction of each line can be configured by the
corresponding direction register DP3. Most port
lines can be switched into pus h-pull or open drain
mode by the open drain control register ODP2
(pins P3.15, P3.14 and P3.12 do not support open
drain mode).
Due to pin limitations register bit P3.14 is not
conne cted to an output pin.
P3 (FF C4h / E2h) SFR Reset Value: 0000h
DP3 (FFC6h / E3h) SFR Reset Value: 0000h
ODP3 (F1C6h / E3h) ESFR Reset Value: 0000h
1514131211109876543210
P3.15 - P3.13 P3.12 P3.11 P3.10 P3.9 P3.8 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
P3.y Port Data Register P3 Bit y
1514131211109876543210
DP3
.15 - DP3
.13 DP3
.12 DP3
.11 DP3
.10 DP3
.9 DP3
.8 DP3
.7 DP3
.6 DP3
.5 DP3
.4 DP3
.3 DP3
.2 DP3
.1 DP3
.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
DP3.y Port Direction Register DP3 Bit y
DP3.y = 0: Port line P3.y is an input (high-impe dance)
DP3.y = 1: Port line P3.y is an output
1514131211109876543210
- - ODP3
.13 - ODP3
.11 ODP3
.10 ODP3
.9 ODP3
.8 ODP3
.7 ODP3
.6 ODP3
.5 ODP3
.4 ODP3
.3 ODP3
.2 ODP3
.1 ODP3
.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ODP3.y Port 3 Open Drain Control Register Bit y
ODP3.y = 0: Po rt line P3.y output driver i n pus h-pull mode
ODP3.y = 1: Po rt line P3.y output driver i n open drain mode
ST10F269
70/160
12.6.1 - Alternate Functions of Port 3
The pins of Port 3 serve for various functions which include external timer control lines, the two serial
interfaces and the control lines BHE/WRH and CLKO UT.
The structure of the Por t 3 pins depen ds on their
alternate function (see figures 28 and 29). When
the on-chip peripheral associated with a Port 3 pin
is configured to use the alternat e input function, it
reads the input latch, which represents the state
of the pin, via the line labeled “Alternate Data
Input”. Port 3 pins with alternate input functions
are: T0IN, T 2IN, T3IN, T4 IN, T 3EUD and C APIN.
When the on-chip peripheral associated with a
Port 3 pin is configured to use the alternate output
function, its “Alternate Data Output” line is ANDed
with the port output latch line. When using these
alternate functions, the user must set the direction
of the por t line to output (DP3.y=1) and must set
the port output latch (P3.y=1). Otherwise the pin is
in its high-impedance state (when configured as
input) or the pin is stuck at '0' (when the port
output latch is cleared). When t he alternate output
functions are not used, the “Alternate Data
Out put” line is in its inactive state, which is a high
level ('1').
Table 16 : Port 3 Alter nat ive Functions
Port 3 Pin Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P3.14
P3.15
T0IN CAPCOM1 Timer 0 Count Input
T6OUT Timer 6 Toggle Output
CAPIN GPT2 Capture Input
T3OUT Timer 3 Toggle Output
T3EUD Timer 3 External Up/Down Input
T4IN Timer 4 Count Input
T3IN Timer 3 Count Input
T2IN Timer 2 Count Input
MRST SSC Master Receive / Slave Transmit
MTSR SSC Master Transmit / Slave Receive
TxD0 ASC0 Tran smit Data Outpu t
RxD0 ASC0 Receive Data Input (Output in synchronous mode)
BHE/WRH Byte High Enable / Write High Output
SCLK SSC Shift Clock Input/Output
--- No pin assigned
CLKOUT System Clock Output
Fi gure 2 7 : Port 3 I/O and Alternate Functions
Port 3
No Pin
Alternate Function a) b)
Genera l Purpos e Input/Outp ut
P3.15
P3.13
P3.12
P3.11
P3.10
P3.9
P3.8
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
CLKOUT
SCLK
BHE
RxD0
TxD0
MTSR
MRST
T2IN
T3IN
T4IN
T3EUD
T3OUT
CAPIN
T6OUT
T0IN
WRH
ST10F269
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Port 3 pins with alternate output functions are:
T6OUT, T3OUT, TxD0, BHE and CLKOUT.
When the on-chip peripheral associated with
a Port 3 pin is configured to use both the alternate
input and output function, the descriptions above
apply to the respective current operating mode.
The direct ion must be set accordingl y. Port 3 pins
with alternate input/output functions are: MTSR,
MRST, RxD0 and SCLK.
Note: Enabling the CLKOUT function automati-
cally enables the P3.15 output driver. Set-
ting bit DP3.15=’1’ is not required.
Fi gure 2 8 : B lock Diagram of Port 3 Pin with Alternate Input or Alternate Output Function
Open Drain
Latch
Write ODP3.y
Read ODP3.y
Direction
Latch
Write DP3.y
Read DP3.y
Internal Bus
MUX
0
1
Alternate
Data
Input
Input
Latch
Clock
P3.y
Output
Buffer
y = 13, 11...0
Port Output
Latch
Read P3.y
Write DP3.y
&
Alternate
Data Output
Port Data
Output
ST10F269
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Pin P3.12 (BHE/WRH) is another pin with an
alter nate output function, however, its structure is
slightly different.
After reset the BHE or WRH function must be
used depending on the system start-up
con figuration. In either of t hese case s, there is no
possibility to program any port latches before.
Thus, the appropriate alternate function is
selected automatically. If BHE/WRH is not used in
the system, this pin can be used for general
purpose I/O by disabling the alternate function
(BYTDIS = ‘1’ / WRCFG=’0’).
Note: Enabling the BHE or WRH function automatically enables the P3.12 output driver. Setting bit
DP3.12=’1’ is not required.
During bus hold pin P3.12 is switched back to its standard function and is then controlled by
DP3.12 and P3 .12. Ke ep DP3.12 = ’0’ in this case to ensure floating in hold mode.
Fi gure 2 9 : B lock Diagram of Pins P3.15 (CLKOUT) and P3.12 (BHE/WRH)
Direction
Latch
Write DP3.x
Read DP3.x
Port Output
Latch
Write P3.x
Read P3.x
Internal Bus
MUX
0
1
MUX
0
1
Alternate
Data
Output
MUX
0
1
“1”
Input
Latch
Clock
P3.12/BHE
P3.15/CLKOUT
Output
Buffer
x = 15, 12
Alternate
Function
Enable
ST10F269
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12.7 - Port 4
If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the
correspon ding direction register DP4.
P4 (FF C8h / E4h) SFR Reset Value: --00h
DP4 (FFCAh / E5h) SFR Reset Value: --00h
For CAN configuration support (see section 15), Port 4 has an open drain function, controlled with the
ODP 4 re gister:
ODP4 (F1CAh / E5h) ESFR Reset Value: --00h
Note: Only bit 6 and 7 are implemented, all other bit will be read as “0”.
1514131211109876543210
- - - - - - - - P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0
RW RW RW RW RW RW RW RW
P4.y Port Data Register P4 Bit y
1514131211109876543210
- - - - - - - - DP4.7 DP4.6 DP4.5 DP4.4 DP4.3 DP4.2 DP4.1 DP4.0
RW RW RW RW RW RW RW RW
DP4.y Port Direction Register DP4 Bit y
DP4.y = 0: Port line P4.y is an input (high-impe dance)
DP4.y = 1: Port line P4.y is an output
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
--------ODP4.7ODP4.6------
RW RW
ODP4.y Port 4 Open Drain Control Register Bit y
ODP4.y = 0: Port line P4.y output driver in push/pull mode
ODP4.y = 1: Por t line P4.y output driver in open drain mode if P4.y is not a segment
address line output
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12.7.1 - Alternate Functions of Port 4
Durin g exter nal bus cycles that use segment ation
(address space above 64K Bytes) a number of
Port 4 pins may output the segment address lines .
The number of pins that is used for segment
address output determines the external address
spa ce whi ch is direct ly accessible. The other pins
of Por t 4 may be used for general pur pose I/O. If
seg men t addres s lin es are sel ec ted, the alternat e
function of Port 4 may be necessary to access
external memory directly after reset. For this
reason Port 4 will be switched to this alternate
funct ion autom atically.
The numb er of segm ent address lines is selected
via PORT0 during reset. The selected value can
be read from bitfield SALSEL in register RP0H
(read only) in order to check the configuration
during run time.
The CAN interfaces use 2 or 4 pins of Port 4 to
interface each CAN Modules to an external CAN
transceiver. In this case the number of possible
seg men t address lines is reduced.
The Table 17 summarizes the alternate functions
of Port 4 depending on the number of selected
segment address lines (coded via bitfield
SALSEL)
Table 17 : Port 4 Alter nat e Functions
Port 4 Standard Function
SALSEL = 01
64K Bytes
Alternate Function
SALSEL = 11
256K Bytes
Alternate Function
SALSEL = 00
1M Byte
Alternate Function
SALSEL = 10
16M Bytes
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
GPIO
GPIO
GPIO
GPIO
GPIO/CAN2_RxD
GPIO/CAN1_RxD
GPIO/CAN1_TxD
GPIO/CAN2_TxD
Segment Address A16
Segment Address A17
GPIO
GPIO
GPIO/CAN2_RxD
GPIO/CAN1_RxD
GPIO/CAN1_TxD
GPIO/CAN2_TxD
Segment. Address A16
Segment Address A17
Segment Address A18
Segment Address A19
GPIO/CAN2_RxD
GPIO/CAN1_RxD
GPIO/CAN1_TxD
GPIO/CAN2_TxD
Segment Address A16
Segment Address A17
Segment Address A18
Segment Address A19
Segment Address A20
Segment Address A21
Segment Address A22
Segment Address A23
Fi gure 3 0 : Port 4 I/O and Alternate Functions
Port 4
Alternate Function a)
General Purpose
Input / Output
b)
Seg ment Address
Lines Cans I/O and General Purpose
Input / Output
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
A23
A22
A21
A20
A19
A18
A17
A16
CAN2_TxD
CAN1_TxD
CAN1_RxD
CAN2_RxD
-
-
-
-
ST10F269
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Fi gure 3 1 : Block Diagram of a Port 4 Pin
Direction
Latch
Write DP4.y
Read DP4.y
Port Output
Latch
Write P4.y
R ead P4.y
Internal Bus
MUX
0
1
MUX
0
1
Alternate
Data
Output
MUX
0
1
“1”
Input
Latch
Clock
P4.y
Output
Buffer
y = 7...0
Alternate
Function
Enable
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Fi gure 3 2 : Block Diagram of P4.4 and P4.5 Pins
Direction
Latch
Write DP4. x
Read DP4.x
Port Output
Latch
Write P4.x
Read P4.x
Inte rn a l B us
MUX
0
1
MUX
0
1
Alternate
Data
Output
MUX
0
1
“1”
Input
Latch
Clock
P4.x
x = 5, 4
Alternate
Function
Enable 0
1
“0”
MUX
MUX
0
1
“0”
Output
Buffer
&
≤
1y = 1, 2 (CAN Channel )
z = 2, 1
a = 0, 1
b = 1, 0
CANy.RxD
XPERCON.a
XPERCON.b
(CANyEN)
(CANzEN)
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Fi gure 3 3 : Block Diagram of P4.6 and P4.7 Pins
12.8 - Port 5
This 16-bit input port can only read data. There is no output latch and no direction register. Data written to
P5 will be lost.
P5 (F FA 2h / D1h) SFR Reset Value: XXXXh
1514131211109876543210
P5.15 P5.14 P5.13 P5.12 P5.11 P5.10 P5.9 P5.8 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0
RRRRRRRRRRRRRRRR
P5.y Port Data Regi ster P5 Bit y (Read only)
MUX
0
1
"0"
Open Drain
Latch
Write ODP4.x
Read ODP4.x
Direction
Latch
Write DP4.x
Read DP4.x
Internal Bus
MUX0
1
Input
Latch
Clock
P4.xOutput
Buffer
Port Ou tp ut
Latch
Read P4.x
Write P4.x Alternate
Data
Output MUX
0
1
MUX
0
1
"1"
MUX
Alternate
Function
Enable
MUX
0
1
"1" MUX
MUX
0
1
"0"
MUX
0
1
MUX
≤
1
CANy.TxD
XPERCON.a
(CANyEN)
XPERCON.b
(CANzEN)
D ata output
x = 6, 7
y = 1, 2 (CAN Channel)
z = 2, 1
a = 0, 1
b = 1, 0
ST10F269
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12.8.1 - Alternate Functions of Port 5
Each line of Port 5 is also connected to one of the
multiplexer of the Analog/Digital Converter. All
port lines (P5.15...P5.0) can accept analog
signals (AN15...AN0) to be conv erted by the ADC.
No special programming is required for pins that
sha ll be used as anal og inputs. Some pi ns of Port
5 also serve as external timer control lines for
GP T1 and GP T2 .
The Table 18 summarizes the alternate functions
of Por t 5.
Table 18 : Port 5 Alter nat e Functions
Port 5 Pin Alternate Function a) Alternate Function b)
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P5.8
P5.9
P5.10
P5.11
P5.12
P5.13
P5.14
P5.15
Analog Input AN0
Analog Input AN1
Analog Input AN2
Analog Input AN3
Analog Input AN4
Analog Input AN5
Analog Input AN6
Analog Input AN7
Analog Input AN8
Analog Input AN9
Analog Input AN10
Analog Input AN11
Analog Input AN12
Analog Input AN13
Analog Input AN14
Analog Input AN15
-
-
-
-
-
-
-
-
-
-
T6EUD Timer 6 external Up/Down Input
T5EUD Timer 5 external Up/Down Input
T6IN Timer 6 Count Input
T5IN Timer 5 Count Input
T4EUD Timer 4 external Up/Down Input
T2EUD Timer 2 external Up/Down Input
Fi gure 3 4 : Port 5 I/O and Alternate Functions
Port 5
Alternate Function a)
General Purpose Inputs
b)
A/D Conv erter Inputs Timer Inputs
P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
P5.15
P5.14
P5.13
P5.12
P5.11
P5.10
P5.9
P5.8 AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
AN15
AN14
AN13
AN12
AN11
AN10
AN9
AN8
T2EUD
T4EUD
T5IN
T6IN
T5EUD
T6EUD
ST10F269
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Port 5 pins have a special port structure (see Figure 35), first because it is an input only port, and second
because the analog input channels are directly connected to the pins rather than to the input latches.
12.8.2 - Port 5 Schmitt Trigger Analog Inputs
A Sc hmitt tr igge r protection can be ac tivated on each pin of Port 5 by set ting the de dicated bit of register
P5DIDIS.
P5DIDIS (FFA4h / D2h) SFR Reset Value: 0000h
12.9 - Port 6
If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the
correspon ding direction regi ster DP6. Eac h port line ca n be switched into push/pull or open drain mode
via the open drain control register ODP6.
P6 (FFCCh / E6h) SFR Reset Value: --00h
DP6 (FFCEH / E7H) SFR Reset Value: --00h
Fi gure 3 5 : Block Diagram of a Port 5 Pin
1514131211109876543210
P5DI
DIS.15 P5DI
DIS.14 P5DI
DIS.13 P5DI
DIS.12 P5DI
DIS.11 P5DI
DIS.10 P5DI
DIS.9 P5DI
DIS.8 P5DI
DIS.7 P5DI
DIS.6 P5DI
DIS.5 P5DI
DIS.4 P5DI
DIS.3 P5DI
DIS.2 P5DI
DIS.1 P5DI
DIS.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
P5DIDIS.y Po r t 5 Digital Disable Register Bit y
P5DIDIS.y = 0: Port line P5.y digital input is enabled (Schmitt trigge r enabled)
P5DIDIS.y = 1: Port line P5.y digital input is disabled (Schmitt trigger disabled,
necessary for in put leakage cu rrent reduction)
1514131211109876543210
- - - - - - - - P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0
RW RW RW RW RW RW RW RW
P6.y Port Data Regist er P6 Bit y
1514131211109876543210
- - - - - - - - DP6.7 DP6.6 DP6.5 DP6.4 DP6.3 DP6.2 DP6.1 DP6.0
RW RW RW RW RW RW RW RW
Read Port P5.y
Internal Bus
Input
Latch
Clock
P5.y/ANy
Read
Buffer
to Sample + Hold
Circuit
Channel
Select
Analog
Switch
y = 15...0
ST10F269
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ODP6 (F1CEH / E7 H) ESFR Reset Value: --00h
12.9.1 - Alternate Functions of Port 6
A programmable number of chip select signals (CS4...CS0) derived from the bus control registers
(BUSCON4...BUSCON0 ) can be output on 5 pins of Port 6.
The number of chip select signals is selected via PORT 0 during reset. The selected value can be re ad
from bit-field CSSEL in register RP0H (read only) in order to check the configuration durin g run time.
The Table 19 summarizes the alternate functions of Port 6 depending on the number of selected chip
selec t lines (coded via bit-field CSSEL).
Fi gure 3 6 : Port 6 I/O and Alternate Functions
DP6.y Port Direction Register DP6 Bit y
DP6.y = 0: Port line P6.y is an input (high impedance)
DP6.y = 1: Port line P6.y is an output
1514131211109876543210
--------ODP6.7ODP6.6ODP6.5ODP6.4ODP6.3ODP6.2ODP6.1ODP6.0
RW RW RW RW RW RW RW RW
ODP6.y Port 6 Open Drain Control Register Bit y
ODP6.y = 0: Po rt line P6.y output driver i n pus h-pull mode
ODP6.y = 1: Po rt line P6.y output driver i n open drain mode
Table 19 : Port 6 Alter nat e Functions
Port 6 Alternate Function
CSSEL = 10 Alternate Function
CSSEL = 01 Alternate Function
CSSEL = 00 Alternate Function
CSSEL = 11
P6.0
P6.1
P6.2
P6.3
P6.4
General purp ose I /O
General purp ose I /O
General purp ose I /O
General purp ose I /O
General purp ose I /O
Chip select CS0
Chip select CS1
General purpose I/O
General purpose I/O
General purpose I/O
Chip select CS0
Chip select CS1
Chip select CS2
General purpose I/O
General purpose I/O
Chip select CS0
Chip select CS1
Chip select CS2
Chip select CS3
Chip select CS4
P6.5
P6.6
P6.7
HOLD External hold request input
HLDA Hold acknowledge output
BREQ Bus request output
Port 6
Alternate Function a)
General Purpose Input/Output
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
BREQ
HLDA
HOLD
CS4
CS3
CS2
CS1
CS0
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The chip select lines of Port 6 have an internal
weak pull-up device. This device is switched on
duri ng reset. This feature is implemented to dr ive
the chip select lines high during reset in order to
avoi d mu lt iple c hip s elec tion .
After reset the CS function must be used, if
selected so. In this case there is no possibility to
program any port latches before. Thus the
alternate function (CS) is selected automatically in
this case.
Note: The open drain output option can only be
selected via software earliest during the
initialization routine; at least signal CS0
will be in push/pull output driver mode
directly after reset.
Fi gure 3 7 : B lock Diagram of Port 6 Pins with an Alternate Output Function
MUX
0
1
"0"
Open Drain
Latch
Write ODP6.y
R ead ODP6.y
Direction
Latch
W rite DP6.y
Read DP6.y
In ternal Bus
MUX
0
1
Input
Latch
Clock
P6.y
Output
Buffer
Port Ou tp u t
Latch
Read P6. y
Write DP6.y Alternate
Data
Output MUX
0
1
MUX
0
1
"1"
MUX
Alternate
Function
Enable
y = (0...4, 6 , 7)
ST10F269
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Fi gure 3 8 : B lock Diagram of Pin P6.5 (HOLD)
Open Drain
Latch
Wri t e ODP6 . 5
Read ODP6.5
Direction
Latch
Write DP6.5
Read DP6.5
Intern al Bu s
MUX
0
1
Input
Latch
Clock
P6.5/HOLD
Output
Buffer
Port Output
Latch
Read P6.5
Write P6.5
Altern ate Da ta Inpu t
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12.10 - Port 7
If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the
correspon ding direction register DP7. Each por t line can be switched into p ush-pull or open d rain mo de
via the open drain control register ODP7.
P7 (FF D0h / E8h) SFR Reset Value: --00h
DP7 (FFD2h / E9h) SFR Reset Value: --00h
ODP7 (F1D2h / E9h) ESFR Reset Value: --00h
1514131211109876543210
- - - - - - - - P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0
RW RW RW RW RW RW RW RW
P7.y Port Data Register P7 Bit y
1514131211109876543210
- - - - - - - - DP7.7 DP7.6 DP7.5 DP7.4 DP7.3 DP7.2 DP7.1 DP7.0
RW RW RW RW RW RW RW RW
DP7.y Port Direction Register DP7 Bit y
DP7.y = 0: Port line P7.y is an input (high impedan ce )
DP7.y = 1: Port line P7.y is an output
1514131211109876543210
--------ODP7.7ODP7.6ODP7.5ODP7.4 ODP7.3 ODP7.2 ODP7.1 ODP7.0
RW RW RW RW RW RW RW RW
ODP7.y Po rt 7 Open Drain Control Register Bit y
OD P7.y = 0: Port line P7.y output dr iver in push-pull mode
ODP7.y = 1: Port line P7.y output driver in open drain mode
ST10F269
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12.10 .1 - Altern ate Functions of Por t 7
The uppe r 4 lines of Por t 7 (P7.7. ..P7.4) serve as
capture inputs or compare outputs
(CC31IO...CC28IO) for the CAPCOM2 unit.
The usage o f the por t lines by the CAPCO M unit,
its accessibility via software and the precautions
are the same as describ ed for t he Port 2 lines.
As all other capture inputs, the capture input
function of pins P7.7...P7.4 can also be used as
external interrupt inputs (200ns sample rate at
40MHz CPU clock).
The lower 4 lines of Por t 7 (P7.3...P7.0) serve as
outputs from the PWM module
(POUT3...POUT0).
At these pins the value of the respective port
output latch is EXORed with the value of the PWM
outpu t rather than ANDed, as the other pins do.
This allo ws to use the alternate output valu e either
as it is (port latch holds a ‘0’) or to invert its lev el at
the pin (port latch holds a ‘1’).
Note that the PWM outputs must be enabled via
the respecti ve PENx bit in PWMCO N1.
The Table 20 summarizes the alternate functions
of Por t 7.
Table 20 : Port 7 Alter nat e Functions
Port 7 Alternate Function
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
POUT0 PWM mode channel 0 output
POUT1 PWM mode channel 1 output
POUT2 PWM mode channel 2 output
POUT3 PWM mode channel 3 output
CC28I O Capture input / compare outpu t channel 28
CC29I O Capture input / compare outpu t channel 29
CC30I O Capture input / compare outpu t channel 30
CC31I O Capture input / compare outpu t channel 31
Fi gure 3 9 : Port 7 I/O and Alternate Functions
Port 7
Alternate Function
General Purpose Input/ Output
P7.7
P7.6
P7.5
P7.4
P7.3
P7.2
P7.1
P7.0
CC31IO
CC30IO
CC29IO
CC28IO
POUT3
POUT2
POUT1
POUT0
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The structure of Port 7 differs in t he wa y t he output
latches are connected to the internal bus and to
the pin driver. Pins P7.3...P7.0 (POUT3...POUT0)
EXOR the alternate data output with the port latch
output, which allows to use the alternate data
directly or inverted at the pin driver.
Fi gure 4 0 : Block Diagram of Port 7 Pins P7.3...P7.0
Open Drain
Latch
Write ODP7.y
Read ODP7.y
Direction
Latch
Write DP7.y
Read DP7.y
Internal Bus
MUX
0
1
Input
Latch
Clock
P7.y/POUTy
Output
Buffer
y = 0...3
Port Output
Latch
Read P7.y
Write DP7.y
=1
Port Data
Output EXOR
Alternate
Data
Output
ST10F269
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Fi gure 4 1 : Block Diagram of Port 7 Pins P7.7...P7.4
Open Drain
Latch
Write ODP7.y
Read O DP7.y
Direction
Latch
Write DP7. y
Read DP7.y
Internal Bus
MUX
0
1
Al te rnate Lat ch
Data I nput
Input
Latch
Clock
P7.y
CCzIO
Output
Buffer
Alternate
Data
Output
MUX
0
1Output
Latch
≥
1
Write Por t P7.y
Compare Trigger
Read P7.y
y = (4...7)
z = (28.. .31)
Alternate Pin
Data I nput
ST10F269
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12.11 - Port 8
If this 8-bit port is used for general purpose I/O,
the direction of each line can be configured via the
corresponding direction register DP8. Each port
line can be switched into push/pull or open drain
mode via the open drain control register ODP8.
P8 (FF D4h / EAh) SFR Reset Value: --00h
DP8 (FFD6h / EBh) SFR Reset Value: --00h
ODP8 (F1D6h / EBh) ESFR Reset Value: --00h
1514131211109876543210
- - - - - - - - P8.7 P8.6 P8.5 P8.4 P8.3 P8.2 P8.1 P8.0
RW RW RW RW RW RW RW RW
P8.y Port Data Register P8 Bit y
1514131211109876543210
- - - - - - - - DP8.7 DP8.6 DP8.5 DP8.4 DP8.3 DP8.2 DP8.1 DP8.0
RW RW RW RW RW RW RW RW
DP8.y Port Direction Register DP8 Bit y
DP8.y = 0: Port line P8.y is an input (high impedan ce )
DP8.y = 1: Port line P8.y is an output
1514131211109876543210
--------ODP8.7ODP8.6ODP8.5ODP8.4ODP8.3ODP8.2ODP8.1ODP8.0
RW RW RW RW RW RW RW RW
ODP8.y Po rt 8 Open Drain Control Register Bit y
OD P8.y = 0: Port line P8.y output dr iver in push-pull mode
ODP8.y = 1: Port line P8.y output driver in open drain mode
ST10F269
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12.11 .1 - Altern ate Functions of Por t 8
The 8 lines of Port 8 serve as capture inputs or as
compare outputs (CC23IO...CC16IO) for the
CAPC OM 2 unit.
The usage o f the por t lines by the CAPCO M unit,
its accessibility via software and the precautions
are the same as describ ed for t he Port 2 lines.
As all other capture inputs, the capture input
function of pins P8.7...P8.0 can also be used as
external interrupt inputs (200ns sample rate at
40MHz CPU clock).
The Table 21 summarizes the alternate functions
of Por t 8.
Table 21 : Port 8 Alter nat e Functions
Port 7 Alternate Function
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
CC16IO Capture input / compare output channel 16
CC17IO Capture input / compare output channel 17
CC18IO Capture input / compare output channel 18
CC19IO Capture input / compare output channel 19
CC20IO Capture input / compare output channel 20
CC21IO Capture input / compare output channel 21
CC22IO Capture input / compare output channel 22
CC23IO Capture input / compare output channel 23
Fi gure 4 2 : Port 8 I/O and Alternate Functions
Port 8
Alternate FunctionGeneral Purpose Input / Output
P8.7
P8.6
P8.5
P8.4
P8.3
P8.2
P8.1
P8.0
CC23IO
CC22IO
CC21IO
CC20IO
CC19IO
CC18IO
CC17IO
CC16IO
ST10F269
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The structure of Port 8 differs in the way the
output latches are connected to the internal bus
and to the pin driver (see Figure 43). Pins
P8.7...P8.0 (CC23IO...CC16IO) combine internal
bus data and alternate data output bef ore the port
latch input, as do the P ort 2 pins.
Fi gure 4 3 : Block Diagram of Port 8 Pins P8.7...P8.0
Open Drain
Latch
Write O DP 8.y
Read ODP8.y
Direction
Latch
Write DP8. y
Read DP8.y
In te rn a l B u s
MUX
0
1
Alter nate Lat ch
Data Input
Input
Latch
Clock
P8.y
CCzIO
Output
Buffer
Alternate
Data
Output
MUX
0
1Output
Latch
≥
1
Write Port P8.y
Compare Trigge r
Read P8.y
y = (7...0 )
z = (16.. .23)
Alter nate Pin
Data Input
ST10F269
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13 - A/D CONV ERTER
A 10-bit A/D converter with 16 multiplexed input
channels and a sample and hold circuit is
integrated on-chip. The sample time (for loading
the capacitors) and the conversion time is
programmable and can be adjusted to the
external circuitry.
To remove high frequency components from the
analog input signal, a low-pass filter must be con-
nec ted at the ADC input.
Overrun error detection / protection is controlled
by the AD DAT reg ister. Ei ther an in terr upt reques t
is generated when the result of a previous
conversion has not been read from the result
register at the time the next conversion is
complete, or the next conversion is suspended
until the previous result has been read. For
applications which require less than 16 analog
input channels, the remaining chann el inputs can
be used as digital input port pins. The A/D
converter of the ST10F269 supports different
conv ersion modes :
– Single channel single conversion : the analog
level of the selected channel is sampled once
and converted. The result of the conversion is
stored in the ADDAT register.
– Single channel continuous conversion : the
analog level of the selected channel is repeated-
ly sampled and converted. The result of the con-
version is stored in the ADDAT register.
– Auto scan single conversion : the analog level
of the selec ted cha nnels are sampl ed onc e a nd
converted. After each conversion the result is
stored i n the ADDAT regi ster. T he data can be
transfered to the RAM by interrupt software
management or using the powerfull Peripheral
Event Controller (PEC) data transfert.
– Auto scan continuous con version : th e a na-
log level of the selected channels are repeatedly
sampled and converted. The result of the con-
version is stored in the ADDAT register. The
data can be transfered to the RAM by interrupt
software management or using the PEC data
transfert.
– Wait for ADDAT read mode : when using c on-
tinuous modes, in order to avoid to overwrite
the result of the current conversion by the next
one, the ADWR bit of ADCON control register
must be activated. Then, until the ADDAT regis-
ter is rea d, the new result is stored in a tempo-
rary buffer and the con version is on hold.
– Channel injection mode : when using
continuous modes, a selected channel can be
converted in between without changing the
current operating mode. The 10-bit data of the
conversion are stored in ADRES field of
ADDAT2. The current continuous mode remains
active after the single conversion is completed.
Notes: 1. Section 21.4.5 - Direct Dr ive for TCL definition.
2. tCC = TCL x 24
Table 22 : ADC Sample Clock and Conversion Clock
ADCTC Conversion Clock tCC ADSTC Sample Clock tSC
TCL1 = 1/2 x fXTAL At fCPU = 40MHz tSC = At fCPU = 40MHz
00 TCL x 24 0.3µs00 t
CC 0.3µs 2
01 Reserved, do not use Reserved 01 tCC x 2 0.6µs 2
10 TCL x 96 1.2 µs10t
CC x 4 1.2µs 2
11 TCL x 48 0.6 µs11t
CC x 8 2.4µs 2
ST10F269
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14 - SERIAL CHANNELS
Serial communication with other microcontrollers,
microprocessors, terminals or external peripheral
components is provided by two serial interfaces: the
asynchronous / synchronous serial channel (ASCO)
and the high-speed synchronous serial channel
(SSC). Two dedicated Baud rate generators set up
all standard Baud rates without the requirement of
oscillator tuning. For transmission, reception and
erroneous reception, 3 separate interrupt vectors
are provided for each serial channel.
1 4.1 - As ynchronous / Sync hrono us S eri a l
Interface (ASCO)
The asynchronous / synchronous serial interface
(ASCO) provides serial communication between
the ST10F269 and other microcontrollers,
microprocessors or external peripherals.
A set of registers is used to configure and to
con trol the ASCO serial interfac e:
– P 3, DP3, ODP3 for pin configuration
– SOBG for Baud rate generator
– SOTBUF for transmit buffer
– S OT IC for transmit interrupt control
– S OT B IC for transmit buffer interrupt control
– S OC ON for control
– SORBUF for rec eive buffer (r ead o nly)
– S ORIC for receive interrupt control
– SOEIC for error interrupt control
14.1.1 - ASCO in Asynch ron ous Mode
In asynchronous mode, 8 or 9-bit data transfer,
parity generation and the number of stop bit can
be selected. Parity framing and overrun error
detection is provided to increase the reliability of
data transfers . Transmission and reception of data
is double-buffered. Full-duplex communication up
to 1.25M Bauds (at 40MHz of fCPU) is supported
in this mode.
Figure 44 : Asynchron ous Mode of Ser ial Chan nel ASC0
Pin
2
CPU
Clock
S0R
B aud Rate Time r
Reload Register
16
Clock
Serial P ort Co ntrol
S h ift Clo c k
S0M S0STP S0FE S0OE
S0PE
S0REN
S0FEN
S0PEN
S0OEN
S0LB
S0RIR
S0TIR
S0EIR
Receive Interrupt
Request
Transmit Interrupt
Request
E rror Interrupt
Request
T ransm it Shift
Register
Re c e iv e S h ift
Register TX D0 / P3.10
Transmit Buffer
Register S0TBUF
Receive Buffer
Register S0RBUF
SamplingMUX
0
1
Pin
Input
Internal Bus
RXD0/P3.11
Output
ST10F269
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As y nchrono us M ode Ba ud ra tes
For asynchronous operation, the Baud rate
generator provides a clock with 16 times the rate
of the es tablished Baud rate. Every rec ei ved bit is
sampled at the 7th, 8th and 9th cycle of this clock.
The Baud rate for asynchronous operation of
serial channel ASC0 and the required reload
value for a given Baud rate can be deter mined by
the following fo r mulas:
(S0BRL) represents the content of the reload
register, taken as unsigned 13-bit integer,
(S0BRS) represents the value of bit S0BRS (‘0’ or
‘1’), taken as integer.
Using the above equation, the maximum Baud
rate can be calcul ate d for any give n clock speed.
Baud rate versus reload register v al ue (SOBRS=0
and SO BRS=1) is described in Table 23.
Note: The deviation errors gi ven in the Table 23 are rounded. To avoid deviation errors us e a B aud rate
crystal (providing a multiple of the ASC0/SSC sampling frequency).
BAsync = fCPU
16 x [2 + (S0BRS )] x [(S0BRL) + 1]
S0BRL = ( fCPU
16 x [2 + (S0BRS)] x B Async ) - 1
Table 23 : Commonly Used Baud Rates by Reload Value and Deviation Errors
S0BRS = ‘0’, fCPU = 40MHz S0 BRS = ‘1’, fCPU = 40MHz
Baud Rate (Baud) Deviation Error Re load Val ue
(hexa) Baud Rate (Baud) Deviation Error Reload Value
(hexa)
1 250 000 0.0% / 0.0% 0000 / 0000 833 333 0.0% / 0.0% 0000 / 0000
112 000 +1.5% / -7.0% 000A / 000B 112 000 +6.3% / -7.0% 0006 / 0007
56 000 +1.5% / -3.0% 0015 / 0016 56 000 +6.3% / -0.8% 000D / 000E
38 400 +1.7% / -1.4% 001F / 0020 38 400 +3.3% / -1.4% 0014 / 0015
19 200 +0.2% / -1.4% 0040 / 0041 19 200 +0.9% / -1.4% 002A / 002B
9 600 +0.2% / -0.6% 0081 / 0082 9 600 +0.9% / -0.2% 0055 / 0056
4 800 +0.2% / -0.2% 0103 / 0104 4 800 +0.4% / -0.2% 00AC / 00AD
2 400 +0.2% / -0.0% 0207 / 0208 2 400 +0.1% / -0.2% 015A / 015B
1 200 0.1% / 0.0% 0410 / 0411 1 200 +0.1% / -0.1% 02B5 / 02B6
600 0.0% / 0.0% 0822 / 0823 600 +0.1% / -0.0% 056B / 056C
300 0.0% / 0.0% 1045 / 1046 300 0.0% / 0.0% 0AD8 / 0AD9
153 0.0% / 0.0% 1FE8 / 1FE9 102 0.0% / 0.0% 1FE8 / 1FE9
ST10F269
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1 4.1. 2 - ASC O in Sy nc hrono us M ode
In synch ronous mo de, data are transmitted or received synchronously to a shift clock which is generated
by the ST10F269. Half-duplex communication up to 5M Baud (at 40MHz of fCPU) is possible in this mode.
Figure 45 : Synchronous Mode of Serial Channel ASC0
2
CPU
Clock
S0R
Baud Rate Timer
Reload Register
4
Clock
Serial Port Con trol
Shift Clock
S0 M = 000 B S0OE
S0REN
S0OEN
S0LB
S0RIR
S0TIR
S0EIR
R eceive Interrupt
Request
Transm it Interrupt
Request
Error Inte rrupt
Request
Tra nsm i t Shift
Register
Receive Shift
Register
Transmit Buffer
Register S0T BU F
Receive Buffer
Register S0RBUF
MUX
0
1
Pin
In te r nal B u s
Receive
Output
Transmit
Pin
Input/Output
TDX0/P3.10
RXD0/P3.11
ST10F269
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Synchronous Mode Baud Rates
For synchronous operation, the Baud rate
generator provides a clock with 4 times the rate of
the established Baud rate. The Baud rate for
synchronous operation of serial channel ASC0
can be determined by the following formula:
(S0BRL) represents the content of the reload
register, taken as unsigned 13-bit integers,
(S0BRS) represents the value of bit S0BRS (‘0’ or
‘1’), taken as integer.
Using the above equation, the maximum Baud
rate can be calculated for any clock speed as
gi ven i n Table 2 4.
Note: The deviation errors gi ven in the Table 24 are rounded. To avoid deviation errors us e a B aud rate
crystal (providing a multiple of the ASC0/SSC sampling frequency)
BSync =
S0BRL = ( fCPU
4 x [2 + (S0BRS)] x BSync ) - 1
fCPU
4 x [2 + (S 0B RS)] x [(S0BR L) + 1]
Table 24 : Commonly Used Baud Rates by Reload Value and Deviation Errors
S0BRS = ‘0’, fCPU = 40MHz S0 BRS = ‘1’, fCPU = 40MHz
Baud Rate (Baud) Deviation Error Re load Val ue
(hexa) Baud Rate (Baud) Deviation Error Reload Value
(hexa)
5 000 000 0.0% / 0.0% 0000 / 0000 3 333 333 0.0% / 0.0% 0000 / 0000
112 000 +1.5% / -0.8% 002B / 002C 112 000 +2.6% / -0.8% 001C / 001D
56 000 +0.3% / -0.8% 0058 / 0059 56 000 +0.9% / -0.8% 003A / 003B
38 400 +0.2% / -0.6% 0081 / 0082 38 400 +0.9% / -0.2% 0055 / 0056
19 200 +0.2% / -0.2% 0103 / 0104 19 200 +0.4% / -0.2% 00AC / 00AD
9 600 +0.2% / -0.0% 0207 / 0208 9 600 +0.1% / -0.2% 015A / 015B
4 800 +0.1% / -0.0% 0410 / 0411 4 800 +0.1% / -0.1% 02B5 / 02B6
2 400 0.0% / 0.0% 0822 / 0823 2 400 +0.1% / -0.0% 056B / 056C
1 200 0.0% / 0.0% 1045 / 1046 1 200 0.0% / 0.0% 0AD8 / 0AD9
900 0.0% / 0.0% 15B2 / 15B3 600 0.0% / 0.0% 15B2 / 15B3
612 0.0% / 0.0% 1FE8 / 1FE9 407 0.0% / 0.0% 1FFD / 1FFE
ST10F269
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14.2 - High Speed Synchronous Serial Channel
(SSC)
The High-Speed Synchronous Serial Interface
SSC provides flexible high-speed serial
commun ication between the ST10F269 and ot her
microcontrollers, microprocessors or external
peripherals.
The SSC supports full-duplex and half-duplex
synchronous communication. The serial clock
signal can be genera ted by the SSC itself (master
mode) or be received from an external master
(slave mode). Data width, shift direction, clock
polarity and phase are programmable.
This allows communication with SPI-compatible
devices. Transmission and reception of data is
double-buffered. A 16-bit Baud rate generator
provides the SSC with a separate serial clock
signal. The serial channel SSC has its own
dedicated 16-bit Baud rate generator with 16-bit
reload capability, allowing Baud rate generation
independent from the timers.
Fi gure 4 6 : S ynchronous Serial Channel SSC Block Diagram
Baud Rat e Gene rator
SSC Control
Block
Pin
Internal Bus
Clock Control
CPU
Clock
Slave Clock
Master Clock SCLK
Shift
Clock
Status Control
Recei ve Int errupt Reque st
Transmit Interrupt Request
Error Interrupt Request
16-Bit Shift Register
Pin
Control
Pin
Pin
MTSR
MRST
Transmit Buffer
Regi ster SSCT B Receive Buffer
Register SSCRB
ST10F269
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Baud Rate Generation
The Baud rate generator i s c locked by f CPU/2. The
timer is counting downwards and can be started
or stopped through the global enable bit SSCEN
in register SSCCON. Register SSCBR is the
dual-function Baud Rate Generator/Reload
register. Reading SSCBR, while the SSC is
enabled, retur ns the content of the timer. Readi ng
SSCBR, while the SSC is disabled, returns the
programmed reload value. In this mode the
desired reload value can be written to SSCBR.
Note Never write to SSCBR, while the SSC is
enabled.
The formulas below calculate the resulting Baud
rate for a given reload value and the required
reload value for a given B aud rate:
(SSCBR) represents the content of the reload
register, taken as unsigned 16-bit integer.
Table 25 lists some possible Baud rates against
the required reload values and the resulting bit
times for a 40MHz CPU clock.
Baud rateSSC = fCPU
2 x [(SSCBR ) + 1]
SSCBR = ( fCPU
2 x Baud rateSSC ) - 1
Table 25 : Synchronous B aud Rate and Reload
Values
Baud Rate Bit Time Reload Value
Reserved use a
reload value > 0. --- ---
10M Baud 100ns 0001h
5M Baud 200ns 0003h
2.5M Baud 400ns 0007h
1M Baud 1µs 0013h
100K Baud 10µs 00C7h
10K Baud 100µs 07CFh
1K Baud 1ms 4E1Fh
306 Baud 3.26ms FF4Eh
ST10F269
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15 - CAN MODULES
The two integrated CAN modules (CAN1 and
CAN2) are identical and handle the completely
autonomous transmission and reception of CAN
frames according to the CAN specification V2.0
part B (active).
Each on-chip CAN module can receive and
transmit standard f rames with 11 -bit identifiers as
well as extended frames with 29-bit identifiers.
These t wo CAN modul es are both identical to the
CAN module of the ST10F167.
Because of duplication of the CAN controllers, the
following adjustments are to be considered:
– Same internal register addresses of both CAN
controllers, but with base addres ses differing in
address bit A8; separate chip select for each
CAN module. Refer to Chapter 4 - Memory Or-
ganization.
– The CAN1 transmit line (CAN1_TxD) is the
alternate function of the Port P4.6 pin and the
receive line (CAN1_RxD) is the alternate
function of the Port P4.5 pin.
– The CAN2 transmit line (CAN2_TxD) is the
alternate function of the Port P4.7 pin and the
receive line (CAN2_RxD) is the alternate
function of the Port P4.4 pin.
– Interrupt request line of the CAN1 module is
connected to the XBUS interrupt line XP0,
interrupt of the CAN2 module is connected to
the line XP1.
– The CAN modules must be selected with
corresponding CANxEN bit of XPERCON register
before the bit XPEN of SYSCON register is set.
– The reset default configuration is : CAN1 is
enabled, CAN2 is disabled.
15.1 - CAN Modules Memory Mapping
15.1.1 - CAN1
Address range 00’EF00h - 00’EFFFh is reserved
for the CAN1 Module access. CAN1 is enabl ed by
setti ng XPEN b it 2 of th e SYSCON reg iste r and b y
setting bit 0 of the XPERCON register. Accesses
to the CAN Module use demultiplexed addresses
and a 16-bit data bus (Byte accesses are
possible). Two wait states give an access time of
125ns at 40MHz CPU clock. No tri-state wait
states are used.
15.1.2 - CAN2
Address range 00’EE00h - 00’EEFFh is reserved
for the CAN2 Module access . CAN2 is enabled by
setti ng XPEN b it 2 of th e SYSCON reg iste r and b y
setting bit 1 of the XPERCON register. Accesses
to the CAN Module use demultiplexed addresses
and a 16-bit data bus (Byte accesses are
possible). Two wait states give an access time of
125ns at 40MHz CPU clock. No tri-state wait
states are used.
Note: If one or both CAN modules is used,
Port 4 cann ot be p ro grammed to output al l
8 segment address lines. Thus, only
4 segment address lines can be used,
reducing the external memory space to
5M Bytes (1M Byte p er CS line).
15.2 - CAN Bus Configurations
Dependi ng on application, CA N bus configuration
may be one single bus with a single or multiple
interfaces or a multiple bus with a single or
multiple interfaces. The ST10F269 is able to
support these 2 cases.
Single CAN Bus
The single CAN Bus multiple interfaces
configuration may be implemented using 2 CAN
transceives as shown in Figure 47.
Fi gure 4 7 : Single CAN Bus Multiple Interfaces,
Multip le Tran s c e iver s
CAN1
RxD TxD CAN2
RxD TxD
CAN
Transceiver CAN
Transceiver
CAN_H
CAN_H CAN bus
ST10F269
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The ST10F269 also supports single CAN Bus
multiple (dual) interfaces using the open drain
option of the CANx_TxD output as shown in
Figure 48. Thanks to the OR-Wired Connection,
only one transceiver is required. In this case the
des ign of t he ap plicat ion mus t take in account t he
wire length and the noise environment.
Multiple CAN Bus
The ST10F269 provides 2 CAN interfaces to
support such kind of bus configuration as shown
in Figure 49.
Fi gure 4 8 : Single CAN Bus, Dual Interfaces,
Sing le Tr an s c eiv e r
CAN1
RxD TxD CAN2
RxD TxD
CAN
Transceiver
CAN_H
CAN_H CAN bu s
* O pen drain ou tput
+5V
2.7k
Ω
**
Fi gure 4 9 : Connection to Two Different CAN
Buses (e.g. for gateway application)
CAN1
RxD TxD CAN2
RxD TxD
CAN
Transceiver CAN
Transceiver
CAN_H
CAN_H CAN
CAN bus 2
bus 1
ST10F269
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16 - REAL TIME CLOCK
The Real Time Clock is an independent timer,
which clock is directly derived from the clock
oscillator on XTAL1 input so that it can keep on
running even in Idle or Power down mode (if
enabled to). Registers access is implemented
onto the XBUS. This module is designed for the
following purp os es:
– Generate the current time and date for the system
– Cyclic time based interrupt, provides Port
2 external interrupts every second and every
n seconds (n is programmable) if enabled.
– 58-bit timer for long term measure men t
– Capable to ex it the ST10 chip from power down
mode (if PWDCFG of SYSCON set) after a pro-
grammed delay .
The real time c lock is base on two ma in blo cks of
counters. The first block is a prescaler which
generates a b asic reference clock (for example a
1 second period). This basic reference clock is
coming out of a 20-bit DIVIDER (4-bit MSB
RTC DH counter and 16-bit LSB RTCDL counte r).
This 20-bit counter is driven by an input clock
derivated from the on-chip high frequency CPU
clock, predivided by a 1/64 fixed counter (see
Figure 51). This 20-bit counter is loaded at each
basic reference clock p eriod with the value of the
20-bit PRESCALER register (4-bit MSB RTCPH
register and 16-bit LSB RTCPL register). The
value of the 20-bit RTCP register determines the
period of the basic reference clock.
A time d interrupt reques t (RTCSI) may be sent on
each basic reference clock period. The second
block of the RT C is a 32-bit counter (16-bit RTCH
and 16-bit RTCL). This counter may be initialized
with the current system time. R TCH/R TCL counter
is driven with the basic reference clock signal. In
ord er to provide an alarm f unct ion the cont ents of
RTCH/RTCL counter is compared with a 32-bit
alarm register (16-bit RTCAH register and 16-bit
RTCAL register). The alarm register may be
loaded with a reference date. An alarm interrupt
request (RTCAI), may be generated when the
value of RTCH/RTCL counter matches the
reference date of RT CAH/RTCAL register.
The timed RTCSI and the alarm RTCAI interrupt
requests can trigger a fast external interrupt via
EXISEL register of port 2 and wake-up the ST10
chip when running power down mode. Using the
RTCOFF bit of RTCCON register, the user may
switch off the clock oscillator when entering the
power down mode.
Fi gure 5 0 : ESFR s and Port Pins Associated with the RTC
Fi gure 5 1 : RTC Block Diagram
----- ---YYYY----
EXISEL
EXISEL Extern al I nterr upt Source Sel ectio n register (Port 2)
1 second timed i nterr upt request (RTCSI) triggers fi rq[2] and alarm in terru pt reques t (RTCAI) tri ggers firq[3]
RTC data and control registers are imple mented onto the XBUS.
----- - - -YYYYYYYY
CCxIC
/64
RTCPLRTCPH
RTCH RTCL RTCDH RTCDL
RTCAH RTCAL
Clock Oscil lator
Reload
=
20 bit DIVIDER32 bi t CO U N T ER
RTCCON
AlarmIT Basic Clock IT
RTCAI RTCSI
Programmable ALARM Regist er Programmable PRESCALER Register
ST10F269
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16.1 - RTC registers
16.1.1 - RTCCON: RTC Control Register
The functions of the RTC are controlled by the RTCCON control register. If the RTOFF bit is set, the R TC
dividers an d counters clock is disabled and registers can be wr itten, when the ST10 chip enters power
down mode the cloc k oscillator will be switch off. The RTC has 2 interrupt sources, one is triggered every
basic clock period, the other one is the alarm.
RTC CON includes an i nterrupt reque st flag an d an interrupt enable bit for e ach of them. Th is register is
read and written via the XBUS.
RTCCON (EC00h) XBUS Reset Value: --00h
Notes : 1. A s RTCCON regist er is not bit-addr essable, the value of th ese bits must be read by che cking th ei r assoc i at ed CCxI C regi st er.
The 2 RTC interrupt signals are connected to Port2 in order to trigger an external interrupt that wake up the chip when in power down
mode.
2. All the bit of RTCCON are act i ve high.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- - - - - - - - RTCOFF - - - RTCAEN RTCAIR RTCSEN RTCSIR
RW RW RW RW RW
RTCOFF 2 RTC Switch Off Bit
‘0’: clock oscillator and RTC keep on running ev en if ST10 in power down mode
‘1’: clock oscillator is switch off if ST10 enters power down mode, RTC dividers and
counters are stopped and registers can be written
RTCAEN 2RTC Alarm Interrupt ENable
‘0’: RTCAI is disabled
‘1’: RT CAI is enabled, it is generated every n seconds
RTCAIR 1RTC Alarm Interrupt Request flag (when the alarm is triggered)
‘0’: the bit was reseted less than a n seconds ago
‘1’: the interru pt was trigge red
RTCSEN 2RTC Se con d interru pt ENable
‘0’: RTCSI is disabled
‘1’: R T CSI is enabled, it is generated every second
RTCSIR 1RTC Second Interrupt Request flag (every second)
‘0’: the bit was reseted less than a second ago
‘1’: the interru pt was trigge red
ST10F269
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16.1.2 - RTCPH & RTCPL: RTC PRESCALER Registers
The 20-bit programmable prescaler divider is loaded with 2 registers.
The 4 most significant bit are stored into RTCP H and the 16 Less significant bit are stored in RT CPL. In
order to keep the system clock, those registers are not reset.
They are wr ite protected by bit RTOFF of RTCCON register, wr ite operation is allowed if RTOFF is set.
RTCPL (EC06h) XBUS Reset Value: XXXXh
RTCPH (EC08h) XBUS Reset Value: ---Xh
The value stored into RTCPH, RTCPL is called RTCP (coded on 20-bit). The dividing ratio of the
pre scalar divider is: ratio = 64 x (RTC P)
16.1.3 - RTCDH & RT CDL: RTC DIVIDER Counters
Every basic reference clock the DIVIDER counters are reloaded with the value stored RTCPH and
RTC PL registers. To get an ac curate time m easurement it is possible to read the value of the DIV IDER,
reading the RTCDH, RTCDL . Those count ers are rea d only. After any bit chang ed in the pro grammable
PRESCALER register, the new value is loaded in the DIVIDER.
RTCDL (EC0Ah) XBUS Reset Value: XXXXh
RTCDH (EC0Ch) XBUS Re set Value: ---Xh
Note: Those registers are not reset, and are read only.
1514131211109876543210
RTCPL
RW
1514131211109876543210
RESERVED RTCPH
RW
Fi gure 5 2 : PRESCALER Register
1514131211109876543210
RTCDL
R
1514131211109876543210
RESERVED RTCDH
R
3 2 1 07 6 5 411 10 9 815 14 13 123 2 1 0
RTCPH
RTCPL
3 2 1 07 6 5 411 10 9 815 14 13 1219 18 17 16
20 bit word counter
ST10F269
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When RT CD increments to reach 00000h, The 20-bit word stored into RTCPH, R TCPL registers is loaded
in RTCD.
Bit 15 to bit 4 of RTCPH and RTCDH are not used. W hen reading, the return value of those bit wi ll be
zeros.
16.1.4 - RTCH & RT CL: RTC Programmable COUNTER Registers
The RTC has 2 x 16-bit programmabl e counters which count rate is based on the basic time refe rence (f or
example 1 second). As the clock oscillator may be kept working, even in power down mode, the RTC
counters may be used as a system clock. In addition RTC counters and registers are not modified at any
system reset. The only way to force their value is to write them via the XBUS.
Those counters are write protected as well. The bit RTOFF of the RTCCON register must be set (RTC
dividers and counte rs are stopped) to enable a write operation on RTCH or RTCL.
A write operation on RTCH or RTCL register loads directly the corresponding counter . When reading, the
current value in the counter (system date) is returned.
The count ers keeps on running while the clock oscillator is working.
RTCL (EC0Eh) XBUS Reset Value: XXXXh
RTCH (EC10h) XBUS Reset Value: XXXXh
Note: Those regist e rs are nor reset
Fi gure 5 3 : DI VIDE R Counters
1514131211109876543210
RTCL
RW
1514131211109876543210
RTCH
RW
3 2 1 07 6 5 411 10 9 815 14 13 123 2 1 0
RTCDH
RTCDL
3210765411 10 9 815 14 13 1219 18 17 16
20 bit word internal value of the prescalar divider
ST10F269
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16.1.5 - RTCAH & RT CAL: RTC ALARM Registers
When the program mable counters reach the 32-bit value stored into RTCAH & RT CAL registers, an alarm
is triggered and the interrupt reques t RTAIR is generated. Those registers are not protected.
RTCAL (EC12h) XBUS Reset Value: XXXXh
RTCAH (EC14h) XBUS Reset Value: XXXXh
Note: T hose regist e rs are not reset
16.2 - Programming the RTC
RTC interrupt reques t signals are connected to Port 2, pad 10 (RTCSI) and pad 11 (RTCAI). An alter nat e
function Port2 is to generate f ast i nterrupts firq[7:0]. To trigger firq[2] and firq[ 3] t he following configuration
has to be set.
EXICON ESFR controls the external interrupt edge selection, RTC interrupt requests are rising edge
active.
EXICON (F1C0h) ESFR Reset Value: 000 0h
Notes : 1. EXI 2ES and EXI3E S mus t be co nfigured as "01b" becaus e RCT i nterrupt request lines are r i si ng edge act i ve.
2. Alar m interr u pt request line (RTCAI) is linked with EXI3ES.
3. Timed i nterrupt request l in e (RTCSI ) i s linke d wi th E XI2 E S.
EXI SEL ESFR enables the Port2 alterna te sources. RTC interru pts are alter nate sources 2 and 3.
EXISEL (F1DAh) ESF R Reset Value: 000 0h
Note s: 1. Adv i se d co nf igu r ation.
2. Alarm i nterrupt reques t (RTCA I) is l in ked with EXI 3SS.
3. Timed inter r upt request (RTCSI) is linked with EXI2SS.
1514131211109876543210
RTCAL
RW
1514131211109876543210
RTCAH
RW
1514131211109876543210
EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES 1 2 EXI2ES 1 3 EXI1ES EXI0ES
RW RW RW RW RW RW RW RW
1514131211109876543210
EXI7SS EXI6SS EXI5SS EXI4SS EXI3SS 2EXI2SS 3EXI1SS EXI0SS
RW RW RW RW RW RW RW RW
EXIxSS External Interrupt x Source Selection (x=7...0)
‘00’: Input from associated Port 2 pin.
‘01’: Input from “alter nate sourc e”. 1
‘10’: Input from Port 2 pin ORed with “alternate source”. 1
‘11’: Input from Port 2 pin ANDed with “alternate source”.
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Interrup t control registers are com m on with CAPCOM 1 Unit: CC10IC (RT CSI) and CC11IC (RTCAI).
CCxIC SFR Reset Value: --00h
CC 10IC: FF8Ch/C6h
CC 11IC: FF8Eh/C7h
1514131211109876543210
--------CCxIR CCxIE ILVL GLVL
RW RW RW RW
Source of interrupt Request Flag Enable Flag Interrupt Vector Vector Location Trap Number
External interrupt 2 CC10IR CC10IE CC10INT 00’0068h 1Ah/26
External interrupt 3 CC11IR CC11IE CC11INT 00’006Ch 1Bh/27
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17 - WATCHDOG TIMER
The Watchdog Timer is a fa il-safe mechanism which prevents the microcont roller from malfunctioni ng for
long periods of time.
The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time
interval until the EINIT (end of initialization) instruction has been executed.
Therefore, the chip start-up procedure is alw ays monitored. The software must be designed to service the
watchdog timer before it overflows. If , due to hardware or software related fai l ures, the softw are fails to do
so, t he wat chdog t imer overflows and generates an internal hardware reset. It pull s the RSTOUT pin low
in order to allow ext ernal hardware components to be reset.
Each of the different reset sources is indicated in the WDTCON register.
The indic ated bits are cleared with the EINIT instruct ion. The or igine of the reset can be ide ntified during
the initialization phase.
WDTCON (FFAEh / D7h) S F R Reset Value : 00xxh
Notes: 1. More than on e reset indication flag may be set. After EINIT, all flags are cleared.
2. Power-on is detec ted when a risi ng edge from VDD = 0 V to VDD > 2.0 V is recognized on t he i nter nal 3 .3V suppl y.
3. These bi t s cannot be di rec tly m odi f i ed by sof t ware.
1514131211109876543210
WDTREL - - PONR LHWR SHWR SWR WDTR WDTIN
RW HR HR HR HR HR RW
WDTIN Watchdog Timer Input Frequency Selection
‘0’: Input Frequency is fCPU/2.
‘1’: Input Frequency is fCPU/128.
WDTR1-3 Watchdog Timer Reset Indication Flag
Set by the watchdog timer on an overflow.
Cleared by a hardware reset or by the SRVWDT instruction.
SWR1-3 Software Reset Indication Flag
Set by the SRST execution.
Cleared by the EINIT instruction.
SHWR1-3 Short Hardware Reset Indication Flag
Set by the input RSTIN.
Cleared by the EINIT instruction.
LHWR1-3 Long Hardware Reset Indication Flag
Set by the input RSTIN.
Cleared by the EINIT instruction.
PONR1- 2-3 Power-On (Asynchronous) Reset Indication Flag
Set by the input RSTIN if a power-on condition has been detected.
Cleared by the EINIT instruction.
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The PONR flag of WDTCON register is set if the output voltage of the internal 3.3V supply falls below the
threshol d (typically 2V) of the power-on detection circuit. This circuit is efficient to detect major failu res of
the external 5V supply but if the internal 3.3V supply does not drop under 2 volts, th e PONR flag is not
set. This could b e the case on fast switch-off / switch-on o f the 5V supply. T he time need ed for such a
seq uence to activate the PON R flag depe nds on the val ue of the capac itors connect ed to the supply and
on the ex act value of the internal threshold of the detection circuit.
Notes : 1. PONR b i t may not be set for short suppl y failu re.
2. For powe r-on reset an d reset af ter s uppl y partia l failur e, as ynchronous r e set mus t be used.
In ca se of bi -direc tional rese t is enabled, a nd if the RSTIN pin is latched low aft er the end of the interna l
reset sequence, then a Shor t hardware reset, a software reset or a watchdog reset will trigger a Long
hardware reset. Thus, Reset Indications flags will be set to indicate a Long Hardware Res et.
The Watchdog Timer is 16-bit, clocked with the system clock divided by 2 or 12 8. The high Byte of the
watchdog timer register can be set to a pre-specified reload value (stored in WDTREL).
Each t ime it is ser viced by the application software, the high byte of the watchdo g t imer is reloaded. For
security, rewrite WDTCON each time before the watchdog timer is serviced
The Table 27 shows the watc hdog time range for 40MHz CPU clock.
The watchdog time r period is calculat ed with the foll owing formula:
Table 26 : WDTCON Bit Value on Different Resets
Reset Source PONR LHWR SHWR SWR WDTR
Power On Reset X X X X
Power on after partial supply failure 1) 2) XXX
Long Hardware Reset X X X
Short Hardware Reset X X
Software Reset X
Watchdog Reset XX
Table 27 : WDTREL Reload Va lue
Reload value in WDTREL Prescaler for fCPU = 40MHz
2 (WDTIN = ‘0’) 128 (WDTIN = ‘1’)
FFh 12.8µs819.2ms
00h 3.276ms 209.7ms
PWDT 1
fCPU
--------------- 512
×1WDTIN
]
63)256 WDTREL])[–(××[
+
(×
=
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18 - SYSTEM RESET
Syste m reset initializes the MCU in a predef ine d sta te. There are f ive ways to activate a reset state. T he
system start-up configuration is different for each case a s shown in Table 28.
Table 28 : Reset Event Definition
18.1 - Long Hardware Reset
The reset is triggered when RSTIN pin is pulled low,
then the MCU is immediately forced in reset default
state. It pulls low RSTOUT pin, it cancels pending internal hold states if any, it aborts external bus cycle, it
switches buses (data, address and control signals) and I/O pin dr ivers to high-impedance, it pulls high PORT0
pins and the reset sequence starts.
To get a long hardware reset, the duration of the ex ternal RST IN signa l must be longer than 1040 T C L.
The level of RPD pin is sampled during the whole RSTIN pulse duration. A low level on RPD pin
determines an asy nchronous reset while a high level leads to a sy nchronous reset.
Note A reset can be entered as synchronous and exit as asynchronous if VRPD voltage drops below the
RPD pin threshold (typically 2.5V for VDD = 5V) when RSTIN pin is low or when RSTIN pin is
internally pulled low.
18.1.1 - Asynchronous Reset
Figure 54 and Figure 55 show asynchro nous reset condition (RPD pin is at low level).
Fi gure 5 4 : Asynchronou s Reset Sequ ence External Fetch
Note: 1) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(f
CPU
=f
XTAL
/ 2), else i t is 4 CPU clock cycles (8 TCL).
Reset Source Short-cut Conditions
Power-on reset PONR Power-on
Long Hardware reset (synchronous & asynchronous) LHWR t RSTIN > 1040 TCL
Short Hardware reset (synchronous reset) SHWR 4 TCL < t RSTIN < 1038 TCL
Watchdog Timer reset WDTR WDT overflow
Software reset SWR SRST execution
6 or 8 TCL
1)
CPU Clock
RSTIN Asynchronous
Reset Condition
RPD
RSTOUT
ALE
PORT0 Reset Configuration 1st Instruction External Fetch
Latching poi nt of PORT0
for system start-up
configuration
81234 6759
RD
EXTERNAL FETCH
Internal reset
5 TCL
ST10F269
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Fi gure 5 5 : Asynchronou s Reset Sequ ence Internal Fetch
Note: 1) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(f
CPU
=f
XTAL
/ 2), else i t is 4 CPU clock cycles (8 TCL).
2 ) 2. 1µs typi cal value.
Power-on rese t
The asynchronous reset must be used during the power-on of the MCU . Depending on the crystal frequency,
the on -chip oscillat or nee ds ab out 10 ms to 50m s to stabiliz e. The logic of th e MCU doe s not n eed a s tabilize d
clock signal t o det ect an asy nchronous r eset, so it is suita ble for power -on condition s. To en sure a proper
r eset seq uen ce, t he
RSTIN
pin and the RPD pin must be held at low level until the MCU clock signal is
stabilized and t h e s ystem configur ation v alu e on PORT0 is set tled.
Ha rdware reset
The asynchronous reset must be used to recov er from catastrophic situations of the application. It ma y be
triggerred by the hardware of the application. Internal hardware logic and application circuitry are
described in Section 18.6 - Reset Circuitry and Figure 58, Figure 59 and Figure 60.
18.1.2 - Synchronous Reset (RSTIN pulse > 1040TCL and RPD pin at high level)
The synchronous reset is a warm reset. It may be generated synchronously to the CPU clock. To be
detected by the reset logic, the RSTIN pulse must be low at least for 4 TCL (2 periods of CPU clock).
Then the I/O pins are set to high impedance and
RSTOUT
pin is driven low. After the
RSTIN
level is
detected, a short duration of 12 TCL (6 CPU clocks) maximum elapses, during which pending internal
hold states are cancelled and the current internal access cycle, if any, is completed. External bus cycle is
aborted.
The internal pull-down of
RSTIN
pin is a ctiv at ed if bi t BD RSTEN of SYSC ON reg ister wa s pre vi ousl y set
by software. This bit is always cleared on powe r-o n or after any reset sequen ce.
The internal sequence lasts f or 1024 TCL (512 periods of CPU cloc k). After this duration the pull-do wn of
RSTIN pin fo r the bidirection al reset function is released and th e RSTIN pi n level is sampled. At this step
the sequence lasts 1040 TCL (4 TCL + 12 TCL + 1024 TCL). If the
RSTIN
pin level is low, the reset
seq uence is extended unt il
RSTIN
level becomes high. Refer to Figure 56
Note If VRPD vo ltage drops below the RPD pin threshold (ty pically 2.5V for VDD = 5V) wh en RS TIN pi n
is low or when RSTIN pin is internally pulled low, the ST10 reset circuitry disab les the bidirectional
reset function and RSTIN pin is no m ore pulled low. T he reset is proces sed as an asynchronous
reset.
6 or 8 TCL
1)
CPU Clock
RSTIN
Asynchronous
Reset Condit i on
RPD
RSTOUT
PORT0 Rese t Conf igur ation
INTERNAL FETCH
Internal reset signal
Flash read signal
PLL fact or
lat ch command
Flash under reset for internal charge pump ramping up
1st fe tch
from Flash
Latching poi nt of PORT0
for PLL configuration
Latching point of PORT0
for remaining bits
123
2.5µs max.
2)
ST10F269
109/160
Fi gure 5 6 : Synchron ous Reset Sequenc e External Fetch (RSTIN pulse > 1040 TCL)
Note 1) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(fCPU =f
XTAL / 2
),
else it is 4 CPU clock cycles (8 TCL).
2) RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCO N register) wa s previously set by software. Bit BDRSTEN is cleared after
reset.
3) If during the reset condition (RSTIN low), VRPD voltage drops below the threshold voltage (typically 2.5V for 5V operation), the the
ST10 reset c ircui try disables the bidir ect io nal reset functi on and RS T IN pin is no more pulled low.
18.1.3 - Exit of Long Hardware Reset
- If the RPD pin level is low when the RSTIN pin is sampled high, the MCU completes an
asynchronous reset sequence.
- If the RPD pin level is high when the RSTIN pin is sampled high, the MCU completes a
synchronous rese t sequence.
The system configuration is latched from PORT0 after a duration of 8 TCL / 4 CPU clocks (6 TCL / 3 CPU
clocks if PLL is bypassed) and in case of ex ternal fet ch, ALE, RD and R/W pi ns are driven to their i nactiv e
level. The MCU starts program execution from memory location 00'0000h in code segment 0. This
starting location will typically point to the general initialization routine. Refer to Table 29 for PORT0
latched configuration.
18.2 - Short Hard ware Reset
A short hardware reset is a warm reset. It may be generated synchronously to the CPU clock
(synchronous rese t).
The shor t hardware is triggered when RSTIN signal duration is shorter or equal to 1038 TCL, the
RP D pi n must be pul led hig h.
To properly ac tivate the inter nal reset logic of the M C U, the
RSTIN
pin must be held low, at least, during
4 TCL (2 per iods of CP U clock). The I/O pins are se t to h igh impedance a nd
RSTOUT
pin is dr iven low.
After
RSTIN
le vel is detected, a short duration of 12 TCL (6 CPU clocks) maximum elapses, during which
pending internal hold states are cancelled and the current internal access cycle if any is completed.
External bus cycle is aborted. The internal pull-down of
RSTIN
pin is activated if bit BDRSTEN of
SYSCON register was previously set by software. This bit is always cleared on power-on or after any
reset sequenc e.
The internal reset sequence starts for 1024 TCL (512 periods of CPU clock).
After that duration the pull-down of RSTIN pin for the bidirectional reset function is released and the
RSTIN pin level is sam pled h igh w hile R P D level is hig h.
CPU Clock
RSTIN
RPD
RSTOUT
ALE
PORT0
Latching point of PORT0
for system start-up configuration
6 or 8 TCL
1)
4 TCL 12 TCL
min. max.
1024 TCL
Reset Conf ig ur at i on
If V
RPD
> 2.5 V A s ynchronous
200
µ
A Discharge
3)
RD
4321
5
678 9
Reset is not entered.
Internal reset signal
Internally pulled low
2)
5 TCL
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The short h ardware reset ends and the MCU restar ts.To be processed as a shor t hardware reset, the
external RSTIN signa l must la st a maxi mum of 1038 TCL (4 TCL + 10 TCL + 1024 TCL). T he s ystem
configuration i s latched from PORT0 after a duration of 8 TCL / 4 CPU clocks (6 TCL / 3 CPU clocks if PLL
is bypassed) and in case of external fetch, ALE, RD and R/W pins are driven to their inactive level.
Program execution starts from m em ory locat ion 00'0000h in code s egmen t 0. Thi s starting lo ca tion will
typically point to the general initialization routine. Timings of synchronous reset sequence are
summ ari zed in Figure 57. Refer to Table 29 for PORT0 latched configuration.
Note - If th e
RSTIN
pin level is sampled low, the reset sequence is extended unt il
RSTIN
level becomes
high leading to a long hardware reset (synchronous or asynchronous reset) because RSTIN
signal duration has lasted longer than 1040TCL .
- If the VRPD voltage has droped below the RPD pin threshold, the reset is processed as an
asynchronous rese t.
Fi gure 5 7 : S ynchronous Warm Reset Sequence External Fetch (4 TCL <
RSTIN pulse < 1038 TCL)
Not e 1 ) RS T IN asse rtion can be released the re.
2) Maximum internal synchron isa ti o n is 6 CPU cycl e s (12 TCL).
3) RSTIN pin is pul led l o w if bit BDRS TEN (bi t 3 of SYSC ON re gis te r) wa s p reviousl y se t b y soft w ar e . Bit BDRSTEN i s cle ar ed af te r
reset.
4) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(fCPU =f
XTAL / 2
),
else it is 4 CPU clock cycles (8 TCL).
5) If during the reset condition (RS TIN low), V RPD volt age drops below the thre shol d voltage (ty pically 2. 5V fo r 5V operation), the
ST10 reset c ir cuitry disables the bidir ect io nal reset funct i on and RS T IN pin is no more pulled low.
18.3 - Software Reset
The reset sequence can b e trigge red at any time us ing the protected instr uction SRS T (software reset).
This instruction can be executed deliberately within a program, for example to leave bootstrap loader
mode, or upon a hardware trap that reveals a system failure.
Upon execution of the SRST instruction, the internal reset sequence (1024 TCL) is started. The
microcontroller behavior is the same as for a short hardware reset, except that only P0.12...P0.6 bits are
latche d at the end of the reset sequen ce, while pr ev iou sly latched values of P0.5 ...P0.2 are cleared.
18.4 - Watchdog Timer Reset
When the watchdog timer is not disabled during the initialization or when it is not regularly serviced during
program execution it wi ll overflow and it will trigger the reset sequence.
CPU Clock
RSTIN
RPD
RSTOUT
ALE
PORT0 1st Instr.
Latching point of PORT0
for system start-up configuration
6 or 8 TCL
4)
4 TCL 10 TCL
2)
min. min. 1024 TCL
1)
Reset Configuration
If V
RPD
> 2.5V Asynchronous
200µA Dis cha rge
5)
RD
4321
5
6789
Reset is not entered.
Internal reset signal
Internally pulled low
3)
5 TCL
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Unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this
bus cycle either does not use READY, or if READY is sampled active (low) after the programmed wait
states. When READY is sampled inactive (high) after the programmed wait states the running external
bus cycle is aborted. Then the internal reset sequence (1024 TCL) is started. The microcontroller
behaviour is the same as for a short hardware reset, except that only P0.12...P0.6 bits are latched, while
previously latched va lues of P0.5 ...P0.2 are cleared.
18 .5 - RSTOUT, RSTIN, Bidirectional Reset
18.5.1 - RSTOUT Pin
The RSTOUT pin is driven active (low level) at the beginning of any reset sequence (synchronous/
asynchron ous hardware, software and wat chdog t imer reset s). RSTO UT pin st ays active low beyond t he
end of the initialization routine, until the protected EINIT instruction (End of Initialization) is completed.
18.5.2 - Bidirectional Reset
The bidirectional reset function is enabled by setting SYSCON.B DRSTEN (bi t 3). Thi s functi on is disab le d
by any reset sequence which always clears the SYSCON.BDRSTEN bit.
It can only be enabled duri ng the initialisation routine, before EINIT instruction is completed.
If VRPD voltage drops below the RPD pin threshold (t ypically 2.5V for VDD = 5V) when RSTIN pin is lo w or
when RSTIN pin is in ter nally pul led low, the S T 10 res et c ircuitry disables the bidi rectional reset f unction
and RS TIN pin is no more pulled low. The reset is processed as an asynchronou s reset.
The bidirectiona l res et function is useful for ex ter nal peripherals with on-chip memor y because the reset
signal output on RSTIN pin is de-activated before the CPU starts its first instruct ion fetch.
18.5.3 - RSTIN pin
When the bidirectional reset function is enabled, the open-drain of the RSTIN pin is activated, pulling
down the reset signal, f or the duration of the internal reset sequence. See Figure 56 and Figure 57. At the
end of the sequenc e the pull-down is released and th e RSTIN pin gets back its input function.
The bidirectional reset function can be used:
– to convert SW or WD resets to a hardware reset so that the configuration can be (re-)latched from
PORT0.
– to make visible SW or WDT resets at RSTIN pin whenever RS TIN is the only res et s igna l u sed by the
application (RSTOUT not used).
– t o get a de-activated reset signal before CPU starts its first instruction fetch.
The configuration latched from PORT0 is deter mined by the kind of reset generated by the application.
(Refer t o Table 29).
Conve rt ing a S W or WDT res et to a hardware reset al lows the PLL to re-lock or the PLL conf iguration to
be re-latched, provided a SW or WDT reset is generated by the application program is case of PLL unlock
o r inp u t clo ck fail.
18.6 - Reset Circuitry
The internal reset circuitry is described in Figure 58.
An internal pull-up resistor is implemented on RSTIN pin. (50kΩ minimum, to 250kΩ maximum). The
minimum reset time must be calculated using the lowest value. In addition, a programmable pull-down
(SYSCON.BDRSTEN bit 3) drives the RSTIN pi n a ccording t o the interna l reset st ate. The RSTOUT pi n
provides a signals to the application. (Refer to Se ction 18.5 - RS TOUT, RSTIN, Bidirectional Reset).
A weak internal pull-down is connected to the RPD pin to discharge ext ernal capacitor to VSS at a rate of
100µA to 200µA. This Pull-down is turned on when RSTIN pin is low
If bit PWDCFG of SYSCON register is set, an internal pull-up resistor is acti vated at the end of the reset
seq uence. This pull-up charges the capacitor connecte d to RPD pin.
If th e bidirectional reset f unction is not used, the s implest way to reset S T10F269 is to connect externa l
compon ents as shown in Figu re 59. It works wit h reset from application (hard ware or manual) and with
power-on. The value of C1 capacitor, connected on RSTIN pin with internal pull-up resistor (50kΩ to
ST10F269
112/160
250kΩ), must lead to a charging time long enought to let the internal or external oscillator and / or the
on-chip PLL to stabilize.
The R0-C0 com ponents o n RPD pin are ma inly i mp lement ed to prov ide a tim e del ay to exit Power down
mode (see Chapter 19 - Power Reduc tion Mo des). Nervertheless, they dr ive RPD p in level during resets
and they lead to different reset modes as explained hereafter. On power-on, C0 is totaly discharged, a
low level on RPD pin forces a n as ynchronous hardware reset. C0 c apacitor starts to charge throug ht R0
and at the end of rese t sequence ST10F 269 resta r t s. RPD pin threshold is typically 2.5V.
Depending on the delay of the next applied reset, the MCU can enter a synchronous reset or an
asynchron ous reset . If RPD pin is below 2. 5V an asynchrono us res et s tarts, i f RP D pi n i s above 2.5V a
synchrono us reset starts. (See Section 18.1 - L ong Hardware Reset and Section 18. 2 - Shor t Hardware
Reset).
Note that an i nte rnal pull-down is connected to RPD pin and can d rive a 100µA to 200µA current. This
Pull-down is turned on when RS TIN pin is low.
To properly use the bidirectional reset features, the schematic (or equivalent) of Figure 60 must be
implemented. R1-C1 only work for power-on or manual reset in the s ame w ay as explai ned previously. D1
diode brings a faster discharge of C1 capacitor at power-off during repetitive switch-on / switch-off
seq uences. D2 diode perform s an OR-wired connection , it can be replaced with an open drain buffer. R2
resistor may be added to increase the pull-up current to the open drain in order to get a f aster rise time on
RSTIN pin when bidirectional function is activated.
The sta rt -up configurations and som e system features are selected on res et seque nces as descr ibed in
Tab le 29 and Table 30.
Table 29 describes what is the system configuration latched on PORT0 in the five different reset ways.
Table 30 summ ari zes the state of bits of PORT 0 latched in RP0H, SYSCON, BUSCON0 registers.
Fi gure 5 8 : Internal (simplified) Reset Circuitry.
RSTOUT
EINIT Instruction
Trigger
Clr
Clock
Reset State
Machine
Internal
Reset
Signal
Reset Sequence
(512 CPU Clock Cycles)
SRST instruction
watchdog overflow RSTIN
V
DD
BDRSTEN
V
DD
RPD
Weak pul l-dow n
(~200µA)
From/ to E xit
Powerdown
Circuit
Asynchronous
Reset
Clr Q
Set
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Fi gure 5 9 : Minimum External Reset Circuitry
Fi gure 6 0 : External Reset Hardware Circuitry
Table 29 : PORT0 Latched Conf iguration for the Different Resets
Notes: 1. Not latched from PORT0.
2. Onl y RP0H low byte is used and th e bi t-fi el ds are l at ched f rom PORT0 hi gh byt e to RP 0H low byte.
3. In di rect l y depend on PORT0.
4. Bits set if EA pi n i s 1.
X : Pin is sampled
- : Pin is not sampled
PORT0
Clock Options
Segm . Ad dr. Li ne s
Chip Sele cts
WR config.
Bus Type
Reserved
BSL
Reserved
Reserved
Adapt Mode
Em u Mode
Sample event
P0H.7
P0H.6
P0H.5
P0H.4
P0H.3
P0H.2
P0H.1
P0H.0
P0L.7
P0L.6
P0L.5
P0L.4
P0L.3
P0L.2
P0L.1
P0L.0
Software Reset - - - X X X X X X X - - - - - -
Watchdog Reset - - - X X X X X X X - - - - - -
Short Hardware Reset - - - X X X X X X X X X X X X X
Long Hardware Reset XXXXXXXXXXXXXXXX
Power-On Reset X X X X X X X X X X X X X X X X
Table 30 : PORT0 Bits Latched into the Different Regist ers After R eset
PORT0 bit
nber h7 h6 h5 h4 h3 h2 h1 h0 I7 I6 I5 I4 I3 I2 I1 I0
PORT0 bit
Name CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC BUSTYP BUSTYP R BSL R R ADP EMU
RP0H
2X
1X
1X
1X
1X
1X
1X
1X
1CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC
SYSCON X
1X
1X
1X
1X
1X
1BYTDIS
3X
1WRCFG
3X
1X
1X
1X
1X
1X
1X
1
BUSCON0 X
1X
1X
1X
1-BUS
ACT0
4ALE
CTL0
4-BTYPBTYPX
1X
1X
1X
1X
1X
1
Internal
Logic To Clock Generator To Port 4 Logic To Port 6 Logic X 1X 1X 1X 1Internal X 1X 1Internal Internal
+
+
RSTOUT
RSTIN
RPD
C0
R0
V
DD
C1
External
Hardware
ST10F269
a) Manual hardware reset1
b) Fo r automatic po w er -u p and
a)b)
i nterruptibl e power-down mo de
D2
RSTOUT RSTIN
RPD
Open - drain
D1
+
C0
R0
V
DD
ST10F269
V
DD
External
Hardware
Inverter
+C1
R1
V
DD
Reset Source
External
R2
ST10F269
114/160
19 - POWER REDUCTION MODES
Two different power reduction modes with
different levels of power reduction have been
implem ente d in the ST10F269. In Idle mode o nly
CPU is stopped, while peripheral still operate. In
Power Down mode bot h CPU and periph erals are
stopped.
Both mode are software activated by a protected
instruction and are terminated in different ways as
described in the foll owi ng sections.
Note: All external bus actions are completed
before Idle or Power Down mode is
entered. However, Idle or Power Down
mode i s not ent ered i f READY is enabled,
but has n ot been activated (driven low for
negative polarity, or driven high for
positive polarity) during the last bus
access.
19.1 - Idle Mode
Idle mode is entered by running IDLE protected
instruction. The CPU operation is stopped and the
peripherals still run.
Idle mode is terminate by any interrupt request.
Whatever the interrupt is serviced or not, the
instruction following the IDLE instruction will be
executed after return from interrupt (RETI)
instruction, then the CPU resumes the normal
program.
Note that a PEC transfer keep the CPU in Idle
mode. If the PEC transfer does not succeed, the
Idle m ode is ter mina ted. Watchdog t imer must be
properly programmed to avoid any disturbance
during Idle mode.
19.2 - P o wer Down Mode
Power Down mode starts by running PWRDN
pro tected i nstr uc tion. In ter n al clock is s topped, al l
MCU parts are on hold including the watchdog
timer.
There are two different operating Power Down
modes : protected mode and interruptible mode.
The internal RAM contents can be preserved
through the voltage supplied via the VDD pins. To
verify RAM integrity, some dedicated patterns
may be written before entering the Power Down
mode and have to be checked after Power Down
is resumed.
It is mandatory to keep VDD = +5V ±10 % du r in g
power-down mode, because the on-chip
voltage regulator is turned in power saving
mode and it delivers 2.5V to the core logic, but
it must be supplied at nominal VDD = +5V.
19.2.1 - Protected Power Down Mode
This mode is selected when PWDCFG (bit 5) of
SYSCON register is cleared. The Protected
Power Down mo de is only a ctivated if the NMI pin
is pulled low when executing PWRDN instruction
(this means that the PW RD in str uction bel ongs to
the NMI software routine). This mode is only
desactivated with an external hardware reset on
RSTIN pin.
Note: During power down the on-chip voltage
regulator automatically lowers the internal
logic supply voltage to 2 .5V, to save power
and to keep internal RAM and registers
contents.
1 9.2. 2 - Interr upta ble Power D own M ode
This mode is selected when PWDCFG (bit 5) of
SYSCON r egist er is set (See C hapte r 20 - Speci al
Funct ion Register Overv iew).
The Interruptable Power Down mode is only
activated if all the enabled Fast External Interrupt
pins are in their inactive level (see EXICON
register descri ption below).
This mode is desactivated with an external reset
applied to R STIN pin or with an interrupt request
applied to one of the Fast Exter nal Interrupt pins.
To allow the internal PLL and clock to stabilize,
the RSTIN pin must be held low according
the recommandations described in Chapter 18 -
System Reset.
ST10F269
115/160
EXICON (F1C0h / E0h ESFR Reset Value: 000 0h
EXxIN inputs are normally sampled interrupt
inputs. However, the Power Down mode circuitry
use s them as level -sen sitive inputs.
An EXxIN (x = 3...0) Interrupt Enable bit (bit
CCxIE in respective CCxIC register) need not be
set to br ing the device out of Power Down mode.
An external RC c ircuit must be connect ed t o RPD
pin, as shown in the Figure 61.
To exit Power Down mode with an external
interrupt, an EXxIN (x = 7...0) pin has to be
asserted for at least 40ns.
This signal enables the internal oscillator and PLL
circuitry, and also turns on the weak pull-down
(see Figure 62).
The discharge of the external capacitor provides a
delay that allows the oscillator and PLL circuits to
stabilize before the internal CPU and Peripheral
clocks are enabled. When the RPD voltage drops
below the threshold voltage (about 2.5V), the
Schmitt trigger clears Q2 flip-flop, thus enabling
the CPU and Peripheral clocks, and the device
resumes code execution.
If the Interrupt was enabled (bit CCxIE=’1’ in the
respective CCxIC register) before entering Power
Down mode, the device executes the interrupt
ser v ice rout ine, and then resumes execution after
the PWRDN intruction (see note below).
If the interrupt was disabled, the device executes
the instruction following PWRDN instruction, and
the Interrupt Request Flag (bit CCxIR in in the
respective CCxIC register) remains set until it is
cleared by software.
Note: Due to the internal pipeline, the
instruction that follows the PWRDN
intruction is executed before the CPU
performs a call of the interrupt service
routine when exiting power-down m ode
1514131211109876543210
EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXI0ES
RW RW RW RW RW RW RW RW
EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7...0)
0 0: Fast external interrupts disabled: standard mode
EXxIN pin not taken in account for entering/exiting Power Down mode.
0 1: Interrupt on positive edge (rising)
Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as ‘high’ active level)
1 0: Interrupt on negative edge (falling)
Enter Power Down mode if EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred as ‘low’ active level)
1 1: Interrupt on any edge (rising or falling)
Always enter Power Down mode, exit if EXxIN level changed.
Fi gure 6 1 : External R0C0 Circuit on RPD Pin For
Exiting Powerdown Mode with External Interrupt
RPD
VDD
C0
R0
220kΩ minimum
1µF Typical
ST10F269-Q3
+
ST10F269
116/160
Fi gure 6 2 : Simplified Powerdown Exit Circuitry
Fi gure 6 3 : Powerdown Exit Sequence When Using an External Interrupt (PLL x 2)
DQ
Q
V
DD
enter cd
external
interrupt
reset
stop pll
stop oscillator
VDD
DQ
Q
cd Syste m clock
CPU and Peripherals clocks
RPD
VDD Pull-up
Weak Pull-down
(~ 200µA)
PowerDown
Q1
Q2
CPU clk
Internal
External
RPD
ExitPwrd
XTAL1
Interrupt
(internal)
~ 2.5 V
delay fo r o s cillator/pll
stabilization
signal
Powerdown
ST10F269
117/160
20 - SPECIAL FUNCTION REGISTER OVER VIEW
The following table lists all SFRs which are
implemented in the ST10F269 in alphabetical
order. Bit-addressable SFRs are marked with the
letter “b” in column “Name”. SFRs within the
Extended SFR-Space (ESFRs) are marked with
the letter “E” in colum n “Physical Address”.
A SFR can be specified by its individual
mnemonic name. Depending on the selected
addressing mode, a SFR can be accessed via its
physical address (using the Data Page Pointers),
or via its short 8-bit address (without using the
Data Page Poi nters).
The reset value is defined as fol lowing:
X : Means the full nibble is not defined at reset.
x : Means some bits of the nibble are not
defined at reset.
Table 31 : Special Function Registers Listed by Name
Name Physical
address 8-bit
address Description Reset
value
ADCIC b FF98h CCh A/D Converter end of Conversion Interrupt Control Register - - 00h
ADCON b FFA0h D0h A/D Converter Control Register 0000h
ADDAT FEA0h 50h A/D Converter Result Register 0000h
ADDAT2 F0A0h E 50h A/D Converter 2 Result Register 0000h
ADDRSEL1 FE18h 0Ch Address Select Register 1 0000h
ADDRSEL2 FE1Ah 0Dh Address Select Register 2 0000h
ADDRSEL3 FE1Ch 0Eh Address Select Register 3 0000h
ADDRSEL4 FE1Eh 0Fh Address Select Register 4 0000h
ADEIC b FF9Ah CDh A/D Converter Overrun Error Interrupt Control Register - - 00h
BUSCON0 b FF0Ch 86h Bus Configuration Register 0 0xx0h
BUSCON1 b FF14h 8Ah Bus Configuration Register 1 0000h
BUSCON2 b FF16h 8Bh Bus Configuration Register 2 0000h
BUSCON3 b FF18h 8Ch Bus Configuration Register 3 0000h
BUSCON4 b FF1Ah 8Dh Bus Configuration Register 4 0000h
CAPREL FE4Ah 25h GPT2 Capture/Reload Register 0000h
CC0 FE80h 40h CAPCOM Register 0 0000h
CC0IC b FF78h BCh CAPCOM Register 0 Interrupt Control Register - - 00h
CC1 FE82h 41h CAPCOM Register 1 0000h
CC1IC b FF7Ah BDh CAPCOM Register 1 Interrupt Control Register - - 00h
CC2 FE84h 42h CAPCOM Register 2 0000h
CC2IC b FF7Ch BEh CAPCOM Register 2 Interrupt Control Register - - 00h
CC3 FE86h 43h CAPCOM Register 3 0000h
CC3IC b FF7Eh BFh CAPCOM Register 3 Interrupt Control Register - - 00h
CC4 FE88h 44h CAPCOM Register 4 0000h
CC4IC b FF80h C0h CAPCOM Register 4 Interrupt Control Register - - 00h
CC5 FE8Ah 45h CAPCOM Register 5 0000h
CC5IC b FF82h C1h CAPCOM Register 5 Interrupt Control Register - - 00h
CC6 FE8Ch 46h CAPCOM Register 6 0000h
CC6IC b FF84h C2h CAPCOM Register 6 Interrupt Control Register - - 00h
CC7 FE8Eh 47h CAPCOM Register 7 0000h
CC7IC b FF86h C3h CAPCOM Register 7 Interrupt Control Register - - 00h
CC8 FE90h 48h CAPCOM Register 8 0000h
CC8IC b FF88h C4h CAPCOM Register 8 Interrupt Control Register - - 00h
ST10F269
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CC9 FE92h 49h CAPCOM Register 9 0000h
CC9IC b FF8Ah C5h CAPCOM Register 9 Interrupt Control Register - - 00h
CC10 FE94h 4Ah CAPCOM Register 10 0000h
CC10IC b FF8Ch C6h CAPCOM Register 10 Interrupt Control Register - - 00h
CC11 FE96h 4Bh CAPCOM Register 11 0000h
CC11IC b FF8Eh C7h CAPCOM Register 11 Interrupt Control Register - - 00h
CC12 FE98h 4Ch CAPCOM Register 12 0000h
CC12IC b FF90h C8h CAPCOM Register 12 Interrupt Control Register - - 00h
CC13 FE9Ah 4Dh CAPCOM Register 13 0000h
CC13IC b FF92h C9h CAPCOM Register 13 Interrupt Control Register - - 00h
CC14 FE9Ch 4Eh CAPCOM Register 14 0000h
CC14IC b FF94h CAh CAPCOM Register 14 Interrupt Control Register - - 00h
CC15 FE9Eh 4Fh CAPCOM Register 15 0000h
CC15IC b FF96h CBh CAPCOM Register 15 Interrupt Control Register - - 00h
CC16 FE60h 30h CAPCOM Register 16 0000h
CC16IC b F160h E B0h CAPCOM Register 16 Interrupt Control Register - - 00h
CC17 FE62h 31h CAPCOM Register 17 0000h
CC17IC b F162h E B1h CAPCOM Register 17 Interrupt Control Register - - 00h
CC18 FE64h 32h CAPCOM Register 18 0000h
CC18IC b F164h E B2h CAPCOM Register 18 Interrupt Control Register - - 00h
CC19 FE66h 33h CAPCOM Register 19 0000h
CC19IC b F166h E B3h CAPCOM Register 19 Interrupt Control Register - - 00h
CC20 FE68h 34h CAPCOM Register 20 0000h
CC20IC b F168h E B4h CAPCOM Register 20 Interrupt Control Register - - 00h
CC21 FE6Ah 35h CAPCOM Register 21 0000h
CC21IC b F16Ah E B5h CAPCOM Register 21 Interrupt Control Register - - 00h
CC22 FE6Ch 36h CAPCOM Register 22 0000h
CC22IC b F16Ch E B6h CAPCOM Register 22 Interrupt Control Register - - 00h
CC23 FE6Eh 37h CAPCOM Register 23 0000h
CC23IC b F16Eh E B7h CAPCOM Register 23 Interrupt Control Register - - 00h
CC24 FE70h 38h CAPCOM Register 24 0000h
CC24IC b F170h E B8h CAPCOM Register 24 Interrupt Control Register - - 00h
CC25 FE72h 39h CAPCOM Register 25 0000h
CC25IC b F172h E B9h CAPCOM Register 25 Interrupt Control Register - - 00h
CC26 FE74h 3Ah CAPCOM Register 26 0000h
CC26IC b F174h E BAh CAPCOM Register 26 Interrupt Control Register - - 00h
CC27 FE76h 3Bh CAPCOM Register 27 0000h
CC27IC b F176h E BBh CAPCOM Register 27 Interrupt Control Register - - 00h
CC28 FE78h 3Ch CAPCOM Register 28 0000h
CC28IC b F178h E BCh CAPCOM Register 28 Interrupt Control Register - - 00h
CC29 FE7Ah 3Dh CAPCOM Register 29 0000h
CC29IC b F184h E C2h CAPCOM Register 29 Interrupt Control Register - - 00h
Table 31 : Special Function Registers Listed by Name (continued)
Name Physical
address 8-bit
address Description Reset
value
ST10F269
119/160
CC30 FE7Ch 3Eh CAPCOM Register 30 0000h
CC30IC b F18Ch E C6h CAPCOM Register 30 Interrupt Control Register - - 00h
CC31 FE7Eh 3Fh CAPCOM Register 31 0000h
CC31IC b F194h E CAh CAPCOM Register 31 Interrupt Control Register - - 00h
CCM0 b FF52h A9h CAPCOM Mode Control Register 0 0000h
CCM1 b FF54h AAh CAPCOM Mode Control Register 1 0000h
CCM2 b FF56h ABh CAPCOM Mode Control Register 2 0000h
CCM3 b FF58h ACh CAPCOM Mode Control Register 3 0000h
CCM4 b FF22h 91h CAPCOM Mode Control Register 4 0000h
CCM5 b FF24h 92h CAPCOM Mode Control Register 5 0000h
CCM6 b FF26h 93h CAPCOM Mode Control Register 6 0000h
CCM7 b FF28h 94h CAPCOM Mode Control Register 7 0000h
CP FE10h 08h CPU Context Pointer Register FC00h
CRIC b FF6Ah B5h GPT2 CAPREL Interrupt Control Register - - 00h
CSP FE08h 04h CPU Code Segment Pointer Register (read only) 0000h
DP0L b F100h E 80h P0L Direction Control Register - - 00h
DP0H b F102h E 81h P0h Direction Control Register - - 00h
DP1L b F104h E 82h P1L Direction Control Register - - 00h
DP1H b F106h E 83h P1h Direction Control Register - - 00h
DP2 b FFC2h E1h Port 2 Direction Control Register 0000h
DP3 b FFC6h E3h Port 3 Direction Control Register 0000h
DP4 b FFCAh E5h Port 4 Direction Control Register 00h
DP6 b FFCEh E7h Port 6 Direction Control Register 00h
DP7 b FFD2h E9h Port 7 Direction Control Register 00h
DP8 b FFD6h EBh Port 8 Direction Control Register 00h
DPP0 FE00h 00h CPU Data Page Pointer 0 Register (10-bit) 0000h
DPP1 FE02h 01h CPU Data Page Pointer 1 Register (10-bit) 0001h
DPP2 FE04h 02h CPU Data Page Pointer 2 Register (10-bit) 0002h
DPP3 FE06h 03h CPU Data Page Pointer 3 Register (10-bit) 0003h
EXICON b F1C0h E E0h External Interrupt Control Register 0000h
EXISEL b F1DAh E EDh External Interrupt Source Selection Register 0000h
IDCHIP F07Ch E 3Eh Device Identifier Register (n is the device revision) 10Dnh
IDMANUF F07Eh E 3Fh Manufacturer Identifier Register 0401h
IDMEM F07Ah E 3Dh On-chip Memory Identifier Register 3040h
IDPROG F078h E 3Ch Programming Voltage Identifier Register 0040h
IDX0 b FF08h 84h MAC Unit Address Pointer 0 0000h
IDX1 b FF0Ah 85h MAC Unit Address Pointer 1 0000h
MAH FE5Eh 2Fh MAC Unit Accumulator - High Word 0000h
MAL FE5Ch 2Eh MAC Unit Accumulator - Low Word 0000h
MCW b FFDCh EEh MAC Unit Control Word 0000h
MDC b FF0Eh 87h CPU Multiply Divide Control Register 0000h
MDH FE0Ch 06h CPU Multiply Divide Register – High Word 0000h
MDL FE0Eh 07h CPU Multiply Divide Register – Low Word 0000h
Table 31 : Special Function Registers Listed by Name (continued)
Name Physical
address 8-bit
address Description Reset
value
ST10F269
120/160
MRW b FFDAh EDh MAC Unit Repeat Word 0000h
MSW b FFDEh EFh MAC Unit Status Word 0200h
ODP2 b F1C2h E E1h Port 2 Open Drain Control Register 0000h
ODP3 b F1C6h E E3h Port 3 Open Drain Control Register 0000h
ODP4 b F1CAh E E5h Port 4 Open Drain Control Register - - 00h
ODP6 b F1CEh E E7h Port 6 Open Drain Control Register - - 00h
ODP7 b F1D2h E E9h Port 7 Open Drain Control Register - - 00h
ODP8 b F1D6h E EBh Port 8 Open Drain Control Register - - 00h
ONES b FF1Eh 8Fh Constant Value 1’s Register (read only) FFFFh
P0L b FF00h 80h PORT0 Low Register (Lower half of PORT0) - - 00h
P0H b FF02h 81h PORT0 High Register (Upper half of PORT0) - - 00h
P1L b FF04h 82h PORT1 Low Register (Lower half of PORT1) - - 00h
P1H b FF06h 83h PORT1 High Register (Upper half of PORT1) - - 00h
P2 b FFC0h E0h Port 2 Register 0000h
P3 b FFC4h E2h Port 3 Register 0000h
P4 b FFC8h E4h Port 4 Register (8-bit) 00h
P5 b FFA2h D1h Port 5 Register (read only) XXXXh
P6 b FFCCh E6h Port 6 Register (8-bit) - - 00h
P7 b FFD0h E8h Port 7 Register (8-bit) - - 00h
P8 b FFD4h EAh Port 8 Register (8-bit) - - 00h
P5DIDIS b FFA4h D2h Port 5 Digital Disable Register 0000h
POCON0L F080h E 40h PORT0 Low Outpout Control Register (8-bit) - - 00h
POCON0H F082h E 41h PORT0 High Output Control Register (8-bit) - - 00h
POCON1L F084h E 42h PORT1 Low Output Control Register (8-bit) - - 00h
POCON1H F086h E 43h PORT1 High Output Control Register (8-bit) - - 00h
POCON2 F088h E 44h Port2 Output Control Register 0000h
POCON3 F08Ah E 45h Port3 Output Control Register 0000h
POCON4 F08Ch E 46h Port4 Output Control Register (8-bit) - - 00h
POCON6 F08Eh E 47h Port6 Output Control Register (8-bit) - - 00h
POCON7 F090h E 48h Port7 Output Control Register (8-bit) - - 00h
POCON8 F092h E 49h Port8 Output Control Register (8-bit) - - 00h
POCON20 F0AAh E 55h ALE, RD, WR Output Control Register (8-bit) 0000h
PECC0 FEC0h 60h PEC Channel 0 Control Register 0000h
PECC1 FEC2h 61h PEC Channel 1 Control Register 0000h
PECC2 FEC4h 62h PEC Channel 2 Control Register 0000h
PECC3 FEC6h 63h PEC Channel 3 Control Register 0000h
PECC4 FEC8h 64h PEC Channel 4 Control Register 0000h
PECC5 FECAh 65h PEC Channel 5 Control Register 0000h
PECC6 FECCh 66h PEC Channel 6 Control Register 0000h
PECC7 FECEh 67h PEC Channel 7 Control Register 0000h
PICON b F1C4h E E2h Port Input Threshold Control Register - - 00h
Table 31 : Special Function Registers Listed by Name (continued)
Name Physical
address 8-bit
address Description Reset
value
ST10F269
121/160
PP0 F038h E 1Ch PWM Module Period Register 0 0000h
PP1 F03Ah E 1Dh PWM Module Period Register 1 0000h
PP2 F03Ch E 1Eh PWM Module Period Register 2 0000h
PP3 F03Eh E 1Fh PWM Module Period Register 3 0000h
PSW b FF10h 88h CPU Program Status Word 0000h
PT0 F030h E 18h PWM Module Up/Down Counter 0 0000h
PT1 F032h E 19h PWM Module Up/Down Counter 1 0000h
PT2 F034h E 1Ah PWM Module Up/Down Counter 2 0000h
PT3 F036h E 1Bh PWM Module Up/Down Counter 3 0000h
PW0 FE30h 18h PWM Module Pulse Width Register 0 0000h
PW1 FE32h 19h PWM Module Pulse Width Register 1 0000h
PW2 FE34h 1Ah PWM Module Pulse Width Register 2 0000h
PW3 FE36h 1Bh PWM Module Pulse Width Register 3 0000h
PWMCON0 b FF30h 98h PWM Module Control Register 0 0000h
PWMCON1 b FF32h 99h PWM Module Control Register 1 0000h
PWMIC b F17Eh E BFh PWM Module Interrupt Control Register - - 00h
QR0 F004h E 02h MAC Unit Offset Register QR0 0000h
QR1 F006h E 03h MAC Unit Offset Register QR1 0000h
QX0 F000h E 00h MAC Unit Offset Register QX0 0000h
QX1 F002h E 01h MAC Unit Offset Register QX1 0000h
RP0H b F108h E 84h System Start-up Configuration Register (read only) - - XXh
S0BG FEB4h 5Ah Serial Channel 0 Baud Rate Generator Reload Register 0000h
S0CON b FFB0h D8h Serial Channel 0 Control Register 0000h
S0EIC b FF70h B8h Serial Channel 0 Error Interrupt Control Register - - 00h
S0RBUF FEB2h 59h Serial Channel 0 Receive Buffer Register (read only) - - XXh
S0RIC b FF6Eh B7h Serial Channel 0 Receive Interrupt Control Register - - 00h
S0TBIC b F19Ch E CEh Serial Channel 0 Transmit Buffer Interrupt Control Register - - 00h
S0TBUF FEB0h 58h Serial Channel 0 Transmit Buffer Register (write only) 0000h
S0TIC b FF6Ch B6h Serial Channel 0 Transmit Interrupt Control Register - - 00h
SP FE12h 09h CPU System Stack Pointer Register FC00h
SSCBR F0B4h E 5Ah SSC Baud Rate Register 0000h
SSCCON b FFB2h D9h SSC Control Register 0000h
SSCEIC b FF76h BBh SSC Error Interrupt Control Register - - 00h
SSCRB F0B2h E 59h SSC Receive Buffer (read only) XXXXh
SSCRIC b FF74h BAh SSC Receive Interrupt Control Register - - 00h
SSCTB F0B0h E 58h SSC Transmit Buffer (write only) 0000h
SSCTIC b FF72h B9h SSC Transmit Interrupt Control Register - - 00h
STKOV FE14h 0Ah CPU Stack Overfl ow Pointe r Register FA00h
STKUN FE16h 0Bh CPU Stack Underflow Pointer Register FC00h
SYSCON b FF12h 89h CPU System Configuration Register 0xx0h 1
Table 31 : Special Function Registers Listed by Name (continued)
Name Physical
address 8-bit
address Description Reset
value
ST10F269
122/160
Notes : 1. The sys t em co nfiguration i s s el ect ed duri ng reset.
2. Bit WDT R i ndi cate s a wat chdog tim er tr iggered res et.
3. The XPnIC Interrupt Control Registers control interrupt requests from integrated X-Bus peripherals. Some software controlled
interrupt reques ts may be ge nerated by setting th e XPn IR bi ts (o f XPnI C regi ste r) of the unused X -peri pheral nodes.
T0 FE50h 28h CAPCOM Timer 0 Register 0000h
T01CON b FF50h A8h CAPCOM Timer 0 and Timer 1 Control Register 0000h
T0IC b FF9Ch CEh CAPCOM Timer 0 Interrupt Control Register - - 00h
T0REL FE54h 2Ah CAPCOM Timer 0 Reload Register 0000h
T1 FE52h 29h CAPCOM Timer 1 Register 0000h
T1IC b FF9Eh CFh CAPCOM Timer 1 Interrupt Control Register - - 00h
T1REL FE56h 2Bh CAPCOM Timer 1 Reload Register 0000h
T2 FE40h 20h GPT1 Timer 2 Register 0000h
T2CON b FF40h A0h GPT1 Timer 2 Control Register 0000h
T2IC b FF60h B0h GPT1 Timer 2 Interrupt Control Register - - 00h
T3 FE42h 21h GPT1 Timer 3 Register 0000h
T3CON b FF42h A1h GPT1 Timer 3 Control Register 0000h
T3IC b FF62h B1h GPT1 Timer 3 Interrupt Control Register - - 00h
T4 FE44h 22h GPT1 Timer 4 Register 0000h
T4CON b FF44h A2h GPT1 Timer 4 Control Register 0000h
T4IC b FF64h B2h GPT1 Timer 4 Interrupt Control Register - - 00h
T5 FE46h 23h GPT2 Timer 5 Register 0000h
T5CON b FF46h A3h GPT2 Timer 5 Control Register 0000h
T5IC b FF66h B3h GPT2 Timer 5 Interrupt Control Register - - 00h
T6 FE48h 24h GPT2 Timer 6 Register 0000h
T6CON b FF48h A4h GPT2 Timer 6 Control Register 0000h
T6IC b FF68h B4h GPT2 Timer 6 Interrupt Control Register - - 00h
T7 F050h E 28h CAPCOM Timer 7 Register 0000h
T78CON b FF20h 90h CAPCOM Timer 7 and 8 Control Register 0000h
T7IC b F17Ah E BEh CAPCOM Timer 7 Interrupt Control Register - - 00h
T7REL F054h E 2Ah CAPCOM Timer 7 Reload Register 0000h
T8 F052h E 29h CAPCOM Timer 8 Register 0000h
T8IC b F17Ch E BFh CAPCOM Timer 8 Interrupt Control Register - - 00h
T8REL F056h E 2Bh CAPCOM Timer 8 Reload Register 0000h
TFR b FFACh D6h Trap Flag Register 0000h
WDT FEAEh 57h Watchdog Timer Register (read only) 0000h
WDTCON b FFAEh D7h Watchdog Timer Control Register 00xxh 2
XP0IC b F186h E C3h CAN1 Module Interrupt Control Register - - 00h 3
XP1IC b F18Eh E C7h CAN2 Module Interrupt Control Register - - 00h 3
XP2IC b F196h E CBh Flash ready/busy interrupt control register - - 00h 3
XP3IC b F19Eh E CFh PLL unlock Interrupt Control Register - - 00h 3
XPERCON F024h E 12h XPER Configuration Register - - 05h
ZEROS b FF1Ch 8Eh Constant Value 0’s Register (read only) 0000h
Table 31 : Special Function Registers Listed by Name (continued)
Name Physical
address 8-bit
address Description Reset
value
ST10F269
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20.1 - Identification Registers
The ST10F269 has four I dentif ication registers, mapped in ESFR sp ace. These register contain:
– A ma nufacturer identifier,
– A chip identifier, with its revision,
– A internal memory and size identifier and programmin g voltage description.
IDMANUF (F07Eh / 3Fh) 1ESFR Reset Value: 0401h
IDCHIP (F07Ch / 3Eh) 1ESFR Reset Value: 10DXh
IDME M (F07Ah / 3Dh) 1ESF R Reset Value: 3040h
IDPROG (F078h / 3Ch) 1ESFR Reset Value: 0040h
Note : 1. All i dentifi cat i on words are read only regi st ers.
1514131211109876543210
MANUF 00001
R
MANUF Manufacturer Identifier - 020h: STMicroelectronics Manufacturer (JTAG worldwide
normalisation).
1514131211109876543210
CHIPID REVID
RR
REVID Device Revision Identifier
CHIPID Devi ce Identifier - 10Dh: ST10F269 iden tifier.
15 14131211109876543210
MEMTYP MEMSIZE
RR
MEMSIZE Internal Memory Size is calculated using the following for m ula:
Size = 4 x [ MEM S IZE] (in K Byte) - 040h for ST10F 269 (256K Byte)
MEMTYP Internal Memory Type - 3h for ST10F 269 (Flash mem ory ).
1514131211109876543210
PROGVPP PROGVDD
RR
PROGVDD Prog ramming VDD Voltage
VDD voltage when programming EPROM or FLASH devices is calculated using the
fol lowing for mula: VDD = 20 x [PROGVD D] / 256 (volts) - 40h for ST10F269 (5V ).
PROGVPP Programmin g VPP Voltage (no need of external VPP) - 00h
ST10F269
124/160
20.2 - System Configuration Registers
The ST10F269 has registers used for different configuration of the overall system. These registers are
described below.
SYSCON (FF12h / 89h) S F R Reset Value : 0xx0h
Notes: 1. T hese bit are set di rectly or indir e ctly a cc ordi ng to PORT0 an d EA pin conf ig uration duri ng reset sequence.
2. Register SYSCON cannot be chan ged afte r execution of the EINIT instructio n.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STKSZ ROMS1 SGTDIS ROMEN BYTDIS CLKEN WRCFG CSCFG PWD
CFG OWD
DIS BDR
STEN XPEN VISIBLE XPER-
SHARE
RW RW RW RW1RW1RW RW1RW RW RW RW RW RW RW
XPER-SHARE XBUS Peripheral Share Mode Control
‘0’: External accesses to XBUS peripherals are disabled
‘1’: XBUS peripherals are accessible via the external bus during hold mode
VISIBLE Vis ible Mode Control
‘0’: Accesses to XBUS peripherals are done internally
‘1’: XBUS peripheral accesses are made visible on the external pins
XPEN XBUS Peripheral Enable bit
‘0’: Accesses to the on-chip X-Peripherals and XRAM are disabled
‘1’: The on-chip X-Peripherals are enabled.
BDRSTEN Bidirectional Reset Enable
‘0’: RSTIN pin is an input pin only. (SW Reset or WDT Reset have no effect on this pin)
‘1’: RSTIN pin is a bidirectional pin. This pin is pulled low during 1024 TCL during reset sequence.
OWDDIS Oscillator Watchdog Disable Control
‘0’: Oscillator Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monitors XTAL1 activity.
If there is no activity on XTAL1 for at least 1 µs, the CPU clock is switched automatically to PLL’s
base frequency (from 2 to 10MHz).
‘1’: OWD is disabled. If the PLL is bypassed, the CPU clock is always driven by XTAL1 signal. The
PLL is turned off to reduce power supply current.
PWDCFG Power Down Mode Configuration Control
‘0’: Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low,
otherwise the instruction has no effect. Exit power down only with reset.
‘1’: Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast
external interrupt EXxIN pins are in their inactive level. Exiting this mode can be done by asserting
one enabled EXxIN pin or with external reset.
CSCFG Chip Select Configuration Control
‘0’: Latched Chip Select lines: CSx change 1 TCL after rising edge of ALE
‘1’: Unlatched Chip Select lines: CSx change with rising edge of ALE.
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BU SCON 0 (FF0Ch / 86h) SF R Reset Value: 0xx0h
BU SCON1 (FF14h / 8Ah) SFR Reset Value: 0000h
BU SCON2 (FF16h / 8Bh) SFR Reset Value: 0000h
BU SCON3 (FF18h / 8Ch) SFR Reset Value: 0000h
WRCFG Write Configuration Control (Inverted copy of bit WRC of RP0H)
‘0’: Pins WR and BHE retain their normal function
‘1’: Pin WR acts as WRL, pin BHE acts as WRH.
CLKEN System Clock Output Enable (CLKOUT)
‘0’: CLKOUT disabled: pin may be used for general purpose I/O
‘1’: CLKOUT enabled: pin outputs the system clock signal.
BYTDIS Disable/Enable Control for Pin BHE (Set according to data bus width)
‘0’: Pin BHE enabled
‘1’: Pin BHE disabled, pin may be used for general purpose I/O.
ROMEN Internal Memory Enable (Set according to pin EA during reset)
‘0’: Internal Memory disabled: accesses to the Memory area use the external bus
‘1’: Internal Memory enabled.
SGTDIS Segmentation Disable/Enable Control
‘0’: Segmentation enabled (CSP is saved/restored during interrupt entry/exit)
‘1’: Segmentation disabled (Only IP is saved/restored).
ROMS1 Internal Memory Mapping
‘0’: Internal Memory area mapped to segment 0 (00’0000H...00’7FFFH)
‘1’: Internal Memory area mapped to segment 1 (01’0000H...01’7FFFH).
STKSZ System Stack Size
Selects the size of the system stack (in the internal RAM) from 32 to 1024 words.
15 14 13 12 11 10 9 876 5 4 3210
CSWEN0 CSREN0 RDYPOL0 RDYEN0 - BUS ACT0 ALE CT L 0 - BTYP MTTC0 RWDC0 MCTC
RW RW RW RW RW2RW2RW1RW RW RW
15 14 13 12 11 10 9 876 5 4 3210
CSWEN1 CSREN1 RDYPOL1 RDYEN1 - BUSACT1 ALECTL1 - BTYP MTTC1 RWDC1 MCTC
RW RW RW RW RW RW RW RW RW RW
15 14 13 12 11 10 9 876 5 4 3210
CSWEN2 CSREN2 RDYPOL2 RDYEN2 - BUSACT2 ALECTL2 - BTYP MTTC2 RWDC2 MCTC
RW RW RW RW RW RW RW RW RW RW
15 14 13 12 11 10 9 876 5 4 3210
CSWEN3 CSREN3 RDYPOL3 RDYEN3 - BUSACT3 ALECTL3 - BTYP MTTC3 RWDC3 MCTC
RW RW RW RW RW RW RW RW RW RW
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BU SCON4 (FF1Ah / 8Dh) SFR Reset Value: 0000h
Notes : 1. BTY P (bit 6 and 7) are set acc ordi ng to t he configurat i on of the bit l 6 and l 7 of PORT0 la t ched at the end of th e reset s equenc e.
2. BUSCON0 is in itialized with 0000h, if EA pi n i s hi gh duri ng reset. If E A pin i s low duri ng reset, bi t BUSACT0 and A LECTRL0 are
set ( ’1 ’ ) and bi t field BTYP is l oaded wi th the bus co nf i guration select ed vi a PORT0.
15 14 13 12 11 10 9 876 5 4 3210
CSWEN4 CSREN4 RDYPOL4 RDYEN4 - BUSACT4 ALECTL4 - BTYP MTTC4 RWDC4 MCTC
RW RW RW RW RW RW RW RW RW RW
MCTC Memory Cycle Time Control (Number of memory cycle time wait states)
0 0 0 0: 15 wait states (Nber = 15 - [MCTC])
. . .
1 1 1 1: No wait state
RWDCx Read/Write Delay Control for BUSCONx
‘0’: With read/write delay: activate command 1 TCL after falling edge of ALE
‘1’: No read/write delay: activate command with falling edge of ALE
MTTCx Memory Tristate Time Control
‘0’: 1 wait state
‘1’: No wait state
BTYP Exte rnal Bus Config urati on
0 0: 8-bit Demultiplexed Bus
0 1: 8-bit Multiplexed Bus
1 0: 16-bit Demultiplexed Bus
1 1: 16-bit Multiplexed Bus
Note: For BUSCON0, BTYP bit-field is defined via PORT0 during reset.
ALECTLx ALE Lengthening Control
‘0’: Normal ALE signal
‘1’: Lengthened ALE signal
BUSACTx Bus Active Control
‘0’: External bus disabled
‘1’: External bus enabled (within the respective address window, see
ADDRSEL)
RDYENx READY Input Enable
‘0’: External bus cycle is controlled by bit field MCTC only
‘1’: External bus cycle is controlled by the READY input signal
RDYPOLx Ready Active Level Control
‘0’: Active level on the READY pin is low, bus cycle terminates with a ‘0’ on
READY pin,
‘1’: Active level on the READY pin is high, bus cycle terminates with a ‘1’ on
READY pin.
CSRENx Read Chip Select Enable
‘0’: The CS signal is independent of the read command (RD)
‘1’: The CS signal is generated for the duration of the read command
CSWENx Write Chip Select Enable
‘0’: The CS signal is independent of the write command (WR,WRL,WRH)
‘1’: The CS signal is generated for the duration of the write command
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RP0H (F108h / 84h) ESFR Reset Value : - -XXH
Not es: 1. RP0H .7 to R P0H .5 b its are lo ade d only d ur ing a lo ng ha rd ware r es et. As pu ll -up r es istor s ar e active on eac h Port P 0H pins
du ri ng reset, RP0H default valu e i s "F F h" .
2. These bi ts are set acco rdi ng to Por t 0 con figuration duri ng any rese t sequenc e.
3. RP 0H i s a read onl y regist er.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------- CLKSEL SALSEL CSSEL WRC
R 1 - 2 R 2R 2R 2
WRC 2Write Configuration Control
‘0’: Pin WR acts as WRL, pin B HE acts as WRH
‘1’: Pins WR and BHE retain their normal function
CSSEL 2Chip Select Line Selection (Number of active CS outputs)
0 0: 3 CS lines: CS2...CS0
0 1: 2 CS lines: CS1...CS0
1 0: No CS line at all
1 1: 5 CS lines: CS4...CS0 (Default without pull-downs)
SALSEL 2Segment Address Line Selection (Number of active segment address outputs)
0 0: 4-bit segment address: A19...A16
0 1: No segment address lines at all
1 0: 8-bit segment address: A23...A16
1 1: 2-bit segment address: A17...A16 (Default without pull-downs)
CLKSEL 1 - 2 Sys tem Clock Selection
000: fCPU = 2.5 x fOSC
001: fCPU = 0.5 x fOSC
010: fCPU = 1.5 x fOSC
011: fCPU = fOSC
100: fCPU = 5 x fOSC
101: fCPU = 2 x fOSC
110: fCPU = 3 x fOSC
111: fCPU = 4 x fOSC
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EXICON (F1C0h / E0h ESFR Reset Value: 000 0h
EXISEL (F1DA h / EDh) ESFR Reset Value: 0000h
XP3IC (F19Eh / CFh) 1ESFR Reset Value: --00h
Note: 1. XP3IC r egister has the same bit field as xx IC inter rupt registers
1514131211109876543210
EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXI0ES
RW RW RW RW RW RW RW RW
EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7...0)
0 0: Fast external interrupts disabled: standard mode
EXxIN pin not taken in account for entering/exiting Power Down mode.
0 1: Interrupt on positive edge (rising)
Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as ‘high’ active level)
1 0: Interrupt on negative edge (falling)
Enter Power Down mode if EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred as ‘low’ active level)
1 1: Interrupt on any edge (rising or falling)
Always enter Power Down mode, exit if EXxIN level changed.
1514131211109876543210
EXI7SS EXI6SS EXI5SS EXI4SS EXI3SS EXI2SS EXI1SS EXI0SS
RW RW RW RW RW RW RW RW
EXIxSS External Interrupt x Source Selection (x=7...0)
‘00’: Input from associated Port 2 pin.
‘01’: Input from “alternate source”.
‘10’: Input from Port 2 pin ORed with “alternate source”.
‘11’: Input from Port 2 pin ANDed with “alternate source”.
EXIxSS Port 2 pin Alternate Source
0 P2.8 CAN1_RxD
1 P2.9 CAN2_RxD
2 P2.10 RTCSI
3 P2.11 RTCAI
4...7 P2.12...15 Not used (zero)
1514131211109876543210
--------
XP3IR XP3IE XP3ILVL GLVL
RW RW RW RW
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xxIC (yyyyh / zzh) SFR Area Reset Value: --00h
XPERCON (F02 4h / 12h ) ESFR Reset Value: --05h
1514131211109876543210
--------
xxIR xxIE ILVL GLVL
RW RW RW RW
Bit Function
GLVL Group Level
Defines the internal order for simultaneous requests of the same priority.
3: Highest group priority
0: Lowest group priority
ILVL Interrupt Priority Level
Defines the priority level for the arbitration of requests.
Fh: Highest priority level
0h: Lowest priority level
xxIE Interrupt Enable Control Bit (individually enables/disables a specific source)
‘0’: Interrupt Request is disabled
‘1’: Interrupt Request is enabled
xxIR Interrupt Request Flag
‘0’: No request pending
‘1’: This source has raised an interrupt request
1514131211109876543210
-
----------
RTCEN XRAM2EN XRAM1EN CAN2EN CAN1EN
RW RW RW RW RW
CAN1EN CAN1 Enable Bit
‘0’: Accesses to the on-chip CAN1 XP eripheral and its functions are disabled. P4.5 and P4.6 pins can be
used as general purpose I/Os. Address range 00’EF00h-00’EFFFh is only directed to external memory if
CAN2EN is also ‘0’.
‘1’: The on-chip CAN1 XPeripheral is enabled and can be accessed.
CAN2EN CAN2 Enable Bit
‘0’: Accesses to the on-chip CAN2 XP eripheral and its functions are disabled. P4.4 and P4.7 pins can be
used as general purpose I/Os. Address range 00’EE00h-00’EEFFh is only directed to external memory if
CAN1EN is also ‘0’.
‘1’: The on-chip CAN2 XPeripheral is enabled and can be accessed.
XRAM1EN XRAM1 Enable Bit
‘0’: Accesses to external memory within space 00’E000h to 00’E7FFh. The 2K Bytes of internal XRAM1
are disabled.
’1’: Accesses to the internal 2K Bytes of XRAM1.
XRAM2EN XRAM2 Enable Bit
‘0’: Accesses to the external memory within space 00’C000h to 00’DFFFh. The 8K Bytes of internal
XRAM2 are disabled.
’1’: Accesses to the internal 8K Bytes of XRAM2.
RTCEN RTC Enable Bit
’0’: Accesses to the on-chip Real Time Clock are disabled, external access performed. Address range
00’EC00h-00’ECFFh is only directed to external memory if CAN1EN and CAN2EN are ’0’ also
’1’: The on-chip Real Time Clock is enabled and can be accessed.
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When both CAN are disabled via XPERCON
setting, then any access in the address range
00’EE00h - 00’EFFFh will be directed to external
memory interface, using the BUSCONx register
corresponding to address matching ADDRSELx
register. P4.4 and P4.7 can be used as General
Purpose I/O when CAN2 is not enabled, and P4.5
and P4.6 can be used as General Purpose I/O
when CAN1 is not enabl ed.
The default XPER selection after Reset is
identical to XBUS configuration of ST10C167:
XCAN1 is enabled, XCAN2 is disabled, XRAM1
(2K Byte compatible XRAM) is enabled, XRAM2
(new 8K Byte XR AM) is disabled.
Register XPERCON cannot be changed after the
global enabling of XP eripherals, i.e . after setting of
bit XPEN in SYSCON register.
In EMUlation mode, all the XPERipherals are
enabled (XPERCON bit are all set).
W hen the Real Time Clock is disabl ed (RT CEN =
0), the clock oscillator is sw itch off if ST10 enters
in power-down mode. Otherwise, when the Real
Time Clock is enabled, the bit RTCOFF of the
RTCCON register allows to choose the
p ower-down mode of the clock oscilla tor.
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21 - ELECTRICAL CHARACTERISTICS
21.1 - Absolute Maximum Ratings
Not e: 1. Stre sses a bove thos e listed under “A bsolute Maximum R ating s” may caus e perm anent d amage to the device. This is a stre ss
rating onl y and f unct i onal operation of t he device at these or any oth er condi tions above thos e i ndi cat ed i n the operati onal sections
of this specification is not implied. Exposure to absolute maximum rating conditions f or extended periods may affect device reliability.
Duri ng overload condition s (V
IN
> V
DD
or V
IN
< V
SS
) the volta ge on pins with res pect t o ground (V
SS
) must no t exceed t he values
defi ned by t he A b s o l ut e M aximum Ratings.
21.2 - Parameter Interpretation
The parameters listed in the following tables represent the characteristics of the ST10F269 and its
demands on the system. Where the ST10F269 logic provides signals with their respective timing
characteristics, the symbol “CC” for Controller Characteristics, is included in the “Symbol” column.
Where the external system must provide signals with their respective timing characteristics to the
ST10F269, the symbol “SR” f or System Requirement, is included in the “Symbol” column.
21.3 - DC Characteristics
VDD = 5V ± 10%, VSS = 0 V, fCPU = 40MHz, Reset active, TA = -40 to + 125°C
Symbol Parameter Value Unit
VDD Voltage on VDD pins with respect to ground1-0.5, +6.5 V
VIO Voltage on any pin with respect to ground1-0.5, (VDD +0.5) V
VAREF Voltage on VAREF pin with respect to ground1-0.3, (VDD +0.3) V
IOV Input Current on any pin during overload condition1-10, +10 mA
ITOV Absolute Sum of all input currents during overload condition1|100| mA
Ptot Power Dissip ation11.5 W
TAAmbient Temperature under bias -40, +125 °C
Tstg Storage Temperature1-65, +150 °C
Symbol Parameter Test
Conditions Min. Max. Unit
VIL SR Input low voltage – -0.5 0.2 VDD -0.1 V
VILS SR Input low voltage (special threshold) – -0.5 2.0 V
VIH SR Input high voltage
(all except RSTIN and XTAL1) –0.2 VDD +
0.9 VDD + 0.5 V
VIH1 SR Input high voltage RSTIN – 0.6 VDD VDD + 0.5 V
VIH2 SR Input high voltage XTAL1 – 0.7 VDD VDD + 0.5 V
VIHS SR Input high voltage (special threshold) – 0.8 VDD
-0.2 VDD + 0.5 V
HYS Input Hysteresis (special threshold) 3– 250 – mV
VOL CC Output low voltage (PORT0, PORT1, Port 4,
ALE, RD, WR, BHE, CLKOUT, RSTOUT) 1IOL = 2.4mA –0.45V
V
OL1 CC Output low voltage (all other outputs) 1IOL1 = 1.6mA –0.45V
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Notes: 1. ST10F269 pins are equipped with low-noise output drivers which significantly improve the device’s EMI performance. These
low -noi se drivers del i ver th ei r m axi m um current onl y until the res pect i ve t arget output l evel i s reach ed. A fter this, the o ut put cu rrent
is r educed. Thi s result s i n in crease d i m pedance of the dri ver, w hi ch at t enuates el ect ri cal noi se fro m the c onnecte d PCB tracks. The
VOH CC Output high voltage (PORT0, PORT1, Port4,
ALE, RD, WR, BHE, CLKOUT, RSTOUT) 1IOH = -500µA
IOH = -2.4mA 0.9 VDD
2.4 –
–V
VOH1 CC Output high voltage (all other outputs) 1/2 IOH = – 250µA
IOH = – 1.6mA 0.9 VDD
2.4 –
–V
V
IOZ1 CC Input leakage current (Port 5) 0V < VIN < VDD – 200 nA
IOZ2 CC Input leakage current (all other) 0V < VIN < VDD –1µA
IOV SR Overload current 3/4 –5mA
R
RST CC RSTIN pull-up resistor 3–50 250 kΩ
IRWH Read / Write inactive current 5/6 VOUT = 2.4V –-40µA
I
RWL Read / Write active current 5/7 VOUT = VOLmax -500 – µA
IALEL ALE inactive current 5/6 VOUT = VOLmax 40 – µA
IALEH ALE active current 5/7 VOUT = 2.4V – 500 µA
IP6H Port 6 inactive current 5/6 VOUT = 2.4V –-40µA
I
P6L Port 6 active current 5/7 VOUT = VOL1max -500 – µA
IP0H PORT0 configuration current
5/6 VIN = VIHmin –-10µA
I
P0L 5/7 VIN = VILmax -100 – µA
IIL CC XTAL1 input current 0V < VIN < VDD –20µA
gm On-chip oscillator transconductance 35 - mA/V
CIO CC Pin capacitance (digital inputs / outputs) 3/5 f = 1MHz,
TA = 25°C –10pF
I
CC Power supply current 8RSTIN = VIH1
fCPU in [MHz] –20 + 2.5 x fCPU mA
IID Idle mode supply current 9RSTIN = VIH1
fCPU in [MHz] –20 + fCPU mA
IPD Power-down mode supply current
10 VDD = 5.5V
TA = 25°C
TA = 125°C
–
_15 11
190 11 µA
µA
IPD2 Power-down mode supply current (Real time
clock enabled, oscillator enabled)
10
12 VDD = 5.5V
TA = 55°C
fOSC = 25MHz –2 + fOSC / 4 mA
Symbol Parameter Test
Conditions Min. Max. Unit
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current sp eci fied i n colu m n “T est Condi tions” is deli vered in any cas es.
2. This specification is not valid for o utputs whic h are switched to op en dr ain mod e. In t his c ase the r espective o utput will float and the
vol tage r esul t s fr om the ex ternal circui tr y.
3. Par t i al l y tes t ed, guarant eed by design charac terizat io n.
4. Overload condition s occ ur if the standa rd operating conditions are exce eded, i.e. the v oltage on any pin exce eds the specifi ed
range (i.e. VOV > VDD+0.5V or VOV < -0.5V). The absolute sum of input overload currents on all port pins may not exceed 50mA. The
supply voltage must remain within the specified limits.
5. This specification is only valid during Reset, or during Hold-mode or Adapt-mode. Port 6 pins are only affected if they are used for
CS outp ut and if the i r open drai n f unct i on is not enabl ed.
6. The max i m um current may be drawn whil e the res pectiv e signal l i ne rem a i ns inact i ve.
7. The m i ni mum current mu st be drawn in order to dr i ve the respect i ve signal l i ne act i ve.
8. The power supply current is a function of the operating frequency. This dependency is illustrated in the Figure 64. These
parameters are tested at V DDmax and 40MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. The chip is
configured with a demul tipl exed 16-bit bus, di rect cl ock dri ve, 5 chip select l i nes and 2 segment address l in es, E A pi n i s l o w duri ng
re set. After res et, POR T 0 is driv en with the va l ue ‘ 00CCh’ that produces inf i ni te ex ecut i on of NOP in st ruct i on with 15 wait-s tate s, R/
W delay, memory tristate wait state, normal ALE. Peripher als are not activa ted.
9. Idle mode supply current is a function of the operating frequency. This dependency is illustrated in the Figure 64. These
param eters are tes ted at VDDmax and 40M Hz CPU clock w i th all output s disconnec ted and all i nputs at VIL or VIH.
10. This parameter value includes leakage currents. With all inputs (including pins configured as inputs) at 0V to 0.1V or at
VDD – 0.1V to V DD, VREF = 0V , a ll out puts (i nclu di ng pi ns co nfigured as outputs) di sconnec ted.
11. Typ i cal
IPD
value is 5
µ
A @ TA=25°C. an d 60
µ
A @ TA=125°C.
12. P artial l y te st ed, guar anted by design ch aracte ri zat io n using 22pF l oadi ng capacitors on cry st al pi ns.
Fi gure 6 4 : S upply / Idle Current as a Function of Operating Frequency
I [mA]
fCPU [MHz]
10 20
100
10
ICCtyp
IIDmax
ICCmax
IIDtyp
40
30
60mA
120mA
0
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21.3.1 - A/D Conv er ter Char acteristic s
V
DD
= 5V ± 10%, V
SS
= 0V, T
A
= -40 t o +125°C , 4.0V ≤ V
AREF
≤ V
DD
+ 0.1V; V
SS
0.1V ≤ V
AGND
≤ V
SS
+ 0.2V
Notes: 1. V
AIN
may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be
X000h or X3FFh, respectively.
2. During the tS sample time the input capacitance Cain can be charged/discharged by the external source. The internal resistance of
the anal og sourc e must al l ow the capac i tanc e to reach its fi nal voltage l evel wit hi n the tS sample time. After the end o f the tS sample
time, chan ges of t he analog in put voltag e have no effect on t he conversion result. Va lues for the t SC samp le clock d epend on the
program ming. Referrin g t o the tC convers i on tim e formul a of S ection 21.3.2 - on page 135 and to Table 33 on page 135:
- tS min = 2 tSC min = 2 tCC min = 2 x 24 x TCL = 48 TCL
- tS max = 2 t SC max = 2 x 8 tCC max = 2 x 8 x 96 TCL = 1536 TCL
TCL is defined i n Sec tion 21.4. 2 -, Section 21.4 .4 -, an d S ection 21. 4.5 - on page 138 :
3. The convers i on t i me formula i s:
- tC = 14 tCC + tS + 4 T CL (= 14 tCC + 2 tSC + 4 TCL)
The tC parameter includes the tS sample time, the time for determining the digital result and the time to load the result register with
the result of th e conversion. Val ues for the tCC co nversion clock depen d on the programming. Referr i ng to Table 33 o n page 135:
- tC min = 14 tCC min + t S m in + 4 T CL = 14 x 24 x TCL + 48 TCL + 4 TCL = 388 TCL
- tC max = 14 tCC max + tS max + 4 TCL = 14 x 96 TCL + 1536 T CL + 4 TCL = 2884 TCL
4. This parameter is fixed by ADC control logic.
5. DNL, INL, TUE are tested at VAREF=5.0V,
V
AGND =0V, V
CC = 4.9V. It is guaranteed by design characterization for all other
voltages within the defined voltage range.
‘LSB’ has a value of V AREF / 1024.
The specified TUE is guaranteed only if an overload condition (see
I
OV specification) occurs on maximum 2 not selected analog input
pins and the abs ol ute sum of i nput over l oad current s on all anal og i nput pins does no t exce ed 10m A.
6. The co upling factor is meas ured on a channe l while an overlo ad condition o ccur s on the adjacen t not selec ted chan nel with an
absol ute overload c urrent less than 10m A.
7. Par t i al l y tes t ed, guarante ed by design charac ter i zat i on.
8.To remove noise and undesirabl e hi gh fre quency co m ponents from the analog i nput signal, a low-pass fi l ter must be connected at
the A DC input. T he cut -of f fr equency of t hi s filter s houl d avoid 2 opposite transi t i ons duri ng t he ts samp ling time of the ST10 ADC :
- fcut-off
≤
1 / 5 ts
to 1/10 t
s
where ts is th e sam pl i ng tim e of the S T 10 AD C and i s not re l ated t o t he Nyqui st fr equency d et erm i ned by t he tc conversion time.
Table 32 : A/D Conv erter Characteristics
Symbol Parameter Test Condition Limit Values Unit
minimum maximum
VAREF SR Analog Reference voltage 4.0 VDD + 0.1 V
VAIN SR Analog input voltage 1 - 8 VAGND VAREF V
IAREF CC Reference supply current
running mode
power-down mode
7–
–500
1µA
µA
CAIN CC ADC input capacitanc e
Not sampling
Sampling
7–
–10
15 pF
pF
tSCC Sample time 2 - 4 48 TCL 1 536 TCL
tCCC Conversion time 3 - 4 388 TCL 2 884 TCL
DNL CC Differential Nonlinearity 5-0.5 +0.5 LSB
INL CC Integral Nonlinearity 5-1.5 +1.5 LSB
OFS CC Offset Error 5-1.0 +1.0 LSB
TUE CC Total unadjusted error 5-2.0 +2.0 LSB
RASRC SR Internal resistance of analog source tS in [ns] 2 - 7 –(t
S
/ 150) - 0.25 kΩ
K CC Coupling Factor between inputs 6 - 7 –1/500
ST10F269
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21.3.2 - Conversion Timing Control
When a conversion is started, first the
capacitances of the converter are loaded via the
respective analog input pin to the current analog
input voltage. The time to load the capacitances is
referred to as the sample time ts. Next the
sample d voltage is converted to a digital val ue in
10 successive steps, which correspond to the
10-bit resolution of the A DC. The next 4 s teps are
used for equalizing internal levels (and are kept
for exact timing matching with the 10-bit A/D
conv erter module implemented in the ST10F168).
The current that has to be drawn from the sources
for sampling and changing charges depends on
the tim e that eac h respect ive step takes, bec ause
the capacitors must reach their final voltage leve l
within the given time, at least with a certain
approximation. The maximum current, however,
that a so urce can deliver, depends on its inter nal
resistance.
The sample time tS (= 2 tSC) and the conversion
time tc (= 14 tCC + 2 tSC + 4 TCL) can be
programmed relatively to the ST10F269 CPU
clock. This allows adjusting the A/D converter of
the ST10F269 to the properties of the system:
Fast Conversion can be achieved by
programming the respective times to their
absolute possible minimum. This is preferable for
scanning high frequency signals. The internal
resistance of analog source and analog supply
must be sufficiently low, however.
High Internal Resistance can be achieved by
programming the respective times to a higher
value, or the possible maximum. This is pref erable
when using analog sources and supply with a high
inter nal resistance in order to keep the current as
low as possible. However the conversion rate in
this case may be conside rably lower.
The conversion times are programmed via the
upper four bit of register ADCON. Bit field ADCTC
(conversion time control) selects the basic
conversion clock tCC, used for the 14 steps of
conv erting. The sample time tS is a multiple of this
conversion time and is selected by bit field
ADSTC (sample time control). The table below
lists the possible combinations. The timings refer
to the unit TCL, where fCPU = 1/2TCL.
A comp lete conversion will take 14 tCC + 2 t SC + 4 TCL (fastest convertion rate = 4.85µs at 40MHz) . This
time includes the conversion itself, the sample time and the time required to transfer the digital value to
the result register.
Table 33 : ADC Sampling and Conversion Timing
ADCTC
Conversion Clock tCC
ADSTC
Sample Clock tSC
TCL = 1/2 x fXTAL At fCPU = 40MHz tSC = At fCPU = 40MHz
and ADCTC = 00
00 TCL x 24 0.3µs00 t
CC 0.3µs
01 Reserved, do not use Reserved 01 tCC x 2 0.6µs
10 TCL x 96 1.2 µs10t
CC x 4 1.2µs
11 TCL x 48 0.6 µs11t
CC x 8 2.4µs
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21.4 - AC characteristics
21.4.1 - Test Wavefo rms
21.4.2 - Definition of Internal Timing
The internal operation of the ST10F269 is
controlled by the internal CPU clock fCPU. Both
edges of the CPU clock can trigger internal (for
example pipeline) or external (for example bus
cycles) operations.
The specification of the external timing (AC
Characteristics) therefore depends on the time
between two consecutive edges of the CPU clock,
called “TCL”.
The CPU clock signal can be generated by
different mechanisms. The duration of TCL and its
variation (and also the derived external timing)
depends on the mechanism used to generate
fCPU.
This influen ce must be regarded when c alcul ating
the timings fo r the ST10F 269.
The example for PLL operation shown in Figure
67 refers to a PLL fact or of 4.
Fi gure 6 5 : Input / Output Wavef orms
Fi gure 6 6 : Float Wa v ef o rms
2.4V
0.45V
Test Points
0.2VDD+0.9 0.2VDD+0.9
0.2VDD-0.1 0.2VDD-0.1
A
C inputs during testing are driven at 2.4V f or a logic ‘1’ and 0.4V for a logic ‘0’.
T
iming measurement s are made at V IH min for a logic ‘1’ and VIL max for a logic ‘0’.
Timin
g
Reference
Points
VLoad +0.1V
VLoad -0.1V
VOH -0.1V
VOL +0.1V
VLoad
VOL
VOH
F or timing purposes a port pin is no longer floating when VLOAD c hanges of ±1 00m V.
It begins to float when a 100m V change from the loaded VOH/VOL level occu rs (IOH/IOL = 20mA).
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The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins
P0.15-13 (P 0H.7-5).
2 1.4. 3 - Clock Gene ra tio n Mode s
The Tab l e 34 associates the combinat io ns of these three bits wit h the resp ect ive clock generation mode .
Notes : 1. The ext ernal clock input range ref ers to a CPU cl ock range of 1... 40M Hz.
2. The m axi m um i nput frequency depends on the dut y c yc l e of th e exte rnal clock signal.
3. Th e maximum input freq uency is 25MHz when u sing an externa l cry sta l w ith the internal oscillator; providin g that interna l serial
resistance of the crystal is less than 40
Ω
. How ever, hi gher frequencies can be appli ed with an ext ernal clock so urce on pin XTAL 1,
but in this cas e, th e in put c l ock signal mus t reach the defined le vel s VIL and VIH2..
Fi gure 6 7 : Generation Mechanisms for the CPU Clock
Table 34 : CPU Frequen cy Gene ration
P0H.7 P0H.6 P0H.5 CPU Frequency fCPU = fXTAL x F External Clock Input Range1Notes
111 f
XTAL x 4 2.5 to 10MHz Default configuration
110 f
XTAL x 3 3.33 to 13.33MHz
101 f
XTAL x 2 5 to 20MHz
100 f
XTAL x 5 2 to 8MHz
011 f
XTAL x 1 1 to 40MHz Direct drive2
010 f
XTAL x 1.5 6.66 to 26.66MHz
001 f
XTAL x 0.5 2 to 80MHz CPU clock via prescaler3
000 f
XTAL x 2.5 4 to 16MHz
TCL TCL
TCL TCL
fCPU
fXTAL
fCPU
fXTAL
Phase locked loop operation
Direct Clock Drive
TCL TCL
fCPU
fXTAL
Prescaler Op eration
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21.4.4 - Prescaler Operation
W hen pins P 0.15-13 (P0H.7-5) equal ’001’ duri ng
reset, the CPU clock is derived from the internal
oscillator (input clock signal) by a 2:1 prescaler.
The frequency of fCPU is half the frequency of
fXTAL and the high and low time of fCPU (i.e. the
duration of an individual TCL) is defined by the
peri od of the input clock fXTAL.
The timings listed in the AC Characteristics that
refer t o TCL therefore can be calculated us ing the
period of fXTAL fo r any TCL.
Note that if the bit OWDDIS in SYSCON register
is cleared, the PLL runs on its free-running
frequency and delivers the clock signal for the
Oscillator Watchdog. If bit OWDDIS is set, then
the PLL is switched off.
21.4.5 - Direct Drive
W hen pins P 0.15-13 (P0H.7-5) equal ’011’ duri ng
reset the on-chip phase locked loop is disabled
and the CPU clock is directly driven from the
inte rnal os c illato r wit h the input clock signal.
The frequency of fCPU directly follows the
frequency of fXTAL so the high and low time of f CPU
(i.e. the duration of an individual TCL) is defined
by the duty cycle of the inp ut clock fXTAL.
Therefore, the timings giv en in this chapter refer to
the minimum TCL. This minimum value can be
calcu lated by the following formu la:
For two consecutive TCLs, the deviation caused
by the duty cycle of fXTAL is compensat ed, so the
duration of 2TCL is always 1/fXTAL.
The minimum value TCLmin has to be used only
once for timings that require an odd number of
TCLs (1,3,...). Timings that require an even
number of TCLs (2,4,...) may use the formula:
Note: The address float timings in Multiplexed
bus mode (t11 and t45) use the maximum
duration of TCL (TCLmax = 1/fXTAL x
DCmax) instead of TCLmin.
If the bit OWDDIS in SYSCON register is
cleared, the PLL runs on its free-running
frequency and deliv ers the clock signal f or
the Oscil lator Watchdog. If bit OWDDIS is
set, then the PLL is swit ched off.
21.4.6 - Oscillator W atchdog (O WD)
An on-chip watchdog oscillator is implemented in
the ST10F269. This feature is used for safety
operation with external crystal oscillator (using
direct drive mode with or without prescaler). This
watchdog oscillator operates as fol lowing :
The reset default configuration enables the
watchdog oscillator. It can be disabled by setting
the OWDDIS (bit 4) of SYSCON register.
When the OWD is enabled, the PLL runs at its
free-running frequency, and it increments the
watchdog counter. The PLL free-running
frequency is between 2 and 10MHz. On each
transition of external clock, the watchdog counter
is c leared. If an ex ternal clock failure occurs, then
the watchdog counter overflows (after 16 PLL
clock cycles).
The CPU clock signal will be switched to the PLL
free-running clock signal, and the oscillator
watchdog Interrupt Request (XP3INT) is flagged.
The CPU clock will not switch back to the exter na l
clock even if a valid exter nal clock exits on XTAL1
pin. Only a hardware reset can switch the CPU
clock source b ack to direct clock input.
When the OWD is disabled, the CPU clock is
always external oscillator clock and the PLL is
switched off to decrease consumption supply
current.
21.4.7 - Phase Locked Loop
For all other combinations of pins P0.15-13
(P0H.7-5) during reset the on-chip phase locked
loop is enab l ed and i t provides the CP U clock (see
Table 34). The PLL multiplies the input frequency
by the factor F which is selected via the
combination of pins P0.15-13 (fCPU = fXTAL x F).
With every F’th transition of fXTAL the PLL circuit
synchronizes the CPU clock to the input clock.
This synchronization is done smoothly, so the
CPU clock frequen cy does not change abruptly.
Due to this adaptation to the input clock the
frequency of fCPU is constantly adjusted so it is
locked to fXTAL. The slight var iation c auses a ji tter
of fCPU which also effects the duration of
individu al TCLs.
The timings listed in the AC Characteristics that
refer to TCLs therefore must be calculated using
the minimum TCL that is possible under the
respe ctive circumst ances.
TCLmin 1f
⁄XTALlxlDCmin
=
DC duty cycle=
2TCL 1 fXTAL
⁄
=
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The real minimum value for TCL depends on the
jitter of the PLL. The PLL tunes fCPU to keep it
locked on fXTAL. The relative deviation of TCL is
the maximum when it is refered to one TCL
peri od. It decreases according to the for mula a nd
to the Figure 68 given belo w . F or
N
periods of TCL
the minimum value is computed using the
correspon ding deviation D
N
:
where N = number of consecutive TCL periods
and 1 ≤ N ≤ 40. So for a period of 3 TCL periods
(N = 3):
D3 = 4 - 3/15 = 3.8%
3TCLmin =3TCL
NOM x (1 - 3.8/100)
=3TCL
NOM x 0.962
3TCLmin = 36.075ns (at fCPU = 40MHz)
This is especially important for bus cycles using wait
states and e.g. for the operation of timers, serial
interfaces, etc. For all slower operations and longer
periods (e.g. pulse train generation or measurement,
lower Baud rates, etc.) the deviation caused by the
PLL jitter is negligible.
21.4.8 - External Clock Drive XTAL1
VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125 °C
Notes : 1. Theoretical m i ni mum. The real m i ni m um val ue depends on t he duty cy cle of t he i nput c l ock signal . 25M Hz i s th e m axi mu m input
frequency when using an ex ter na l cry s tal oscillator. However, 40 MHz can be applied with an ext ernal clock so urce.
2. The i nput clock signal mu st reach th e defined l evels VIL and VIH2.
TCLMIN TCLNOM 1DN
100
-------------–
×=
D
N
4N15)%[]⁄–(±=
Fi gure 6 8 : A pproximated Maximum PLL Jitter
Parameter Symbol fCPU = fXTAL f
CPU = fXTAL / 2 fCPU = fXTAL x F
F = 1.5/2,/2.5/3/4/5 Unit
min max min max min max
Oscillator period tOSC SR 25 1– 12.5 – 40 x N 100 x N ns
High time t1SR 10 2–5 2–10 2–ns
Low time t2SR 10 2–5 2–10 2–ns
Rise time t3SR – 3 2–3 2–3 2ns
Fall time t4SR – 3 2–3 2–3 2ns
3216
8
42
±1
±2
±3
±4
Max.jitter [%]
N
This approximated formula is valid for
1 ≤ N ≤ 40 and 10MHz ≤ fCPU ≤ 40MHz.
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Fi gure 6 9 : External Clock Drive XTAL 1
21.4.9 - Memory Cycle Variables
The t able s below use three variables wh ich are derived from the BUSCON x registers an d represent the
special characteristics of the programmed memory cycle. The following table describes, how these
variables are to be computed.
Description Symbol Values
ALE Extension tATCL x [ALECTL]
Memory Cycle Time wait states tC2TCL x (15 - [MCTC])
Memory Tri-state Time tF2TCL x (1 - [MTTC])
t1t3t4
VIL
t2tOSC
VIH2
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21.4.10 - Multiplexed Bus
VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF,
ALE cycl e time = 6 TCL + 2 tA + tC + tF (75ns at 40MHz CPU clock without wait states).
Table 35 : Multiplexe d Bus C h ara ct eristics
Symbol Parameter
Max. CPU Clock
= 40MHz Variable CPU Clock
1/2 TCL = 1 to 40MHz
Unit
min. max. min. max.
t5CC ALE high time 4 + tA– TCL - 8.5 + tA–ns
t
6
CC Address setup to ALE 2 + tA– TCL - 10.5 + tA–ns
t
7
CC Address hold after ALE 14 + tA– TCL - 8.5 + tA–ns
t
8
CC ALE falling edge to RD, W R
(with RW-delay) 4 + tA– TCL - 8.5 + tA–ns
t
9
CC ALE falling edge to RD, WR (no
RW-delay) -8.5 + tA– -8.5 + tA–ns
t
10 CC Address float after RD, WR
(with RW-delay) 1–6 – 6ns
t
11 CC Address float after RD, WR
(no RW-delay) 1– 18.5 – TCL + 6 ns
t12 CC RD, WR low time
(with RW-delay) 15.5 + tC– 2 TCL -9.5 + tC–ns
t
13 CC RD, WR low time
(no RW-delay) 28 + tC– 3 TCL -9.5 + tC–ns
t
14 SR RD to valid data in
(with RW-delay) –6 + t
C– 2 TCL - 19 + tCns
t15 SR RD to valid data in
(no RW-delay) – 18.5 + tC– 3 TCL - 19 + tCns
t16 SR ALE low to valid data in – 18.5
+ tA + tC– 3 TCL - 19
+ tA + tCns
t17 SR Address/Unlatched CS to valid
data in – 22 + 2tA +
tC
– 4 TCL - 28
+ 2tA + tCns
t18 SR Data hold after RD
rising edge 0– 0 –ns
t
19 SR Data float after RD 1– 16.5 + tF– 2 TCL - 8.5 + tFns
t22 CC Data valid to WR 10 + tC– 2 TCL -15 + tC–ns
t
23 CC Data hold after WR 4 + tF– 2 TCL - 8.5 + tF–ns
t
25 CC ALE rising edge after RD, WR 15 + tF– 2 TCL -10 + tF–ns
t
27 CC Address/Unlatched CS hold
after RD, WR 10 + tF– 2 TCL -15 + tF–ns
t
38 CC ALE falling edge to Latched CS -4 - tA10 - tA-4 - tA10 - tAns
t39 SR Latched CS low to Valid Data In – 18.5 + tC +
2tA
– 3 TCL - 19
+ tC + 2tAns
t40 CC Latched CS hold after RD, WR 27 + tF– 3 TCL - 10.5 + tF–ns
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Note: 1. Partial l y tes t ed, guarante d by des i gn charac terization.
t42 CC ALE fall. edge to RdCS, WrCS
(with RW delay) 7 + tA– TCL - 5.5+ tA–ns
t
43 CC ALE fall. edge to RdCS, WrCS
(no RW delay) -5.5 + tA– -5.5 + tA–ns
t
44 CC Address float after RdCS,
WrCS (with RW delay) 1–0 – 0ns
t
45 CC Address float after RdCS,
WrCS (no RW delay) 1– 12.5 – TCL ns
t46 SR RdCS to Valid Data In
(with RW delay) –4 + t
C– 2 TCL - 21 + tCns
t47 SR RdCS to Valid Data In
(no RW delay) – 16.5 + tC– 3 TCL - 21 + tCns
t48 CC RdCS, WrCS Low Time
(with RW delay) 15.5 + tC– 2 TCL - 9.5 + tC–ns
t
49 CC RdCS, WrCS Low Time
(no RW delay) 28 + tC– 3 TCL - 9.5 + tC–ns
t
50 CC Data valid to WrCS 10 + tC– 2 TCL - 15+ tC–ns
t
51 SR Data hold after RdCS 0– 0 –ns
t
52 SR Data float after RdCS 1– 16.5 + tF– 2 TCL - 8.5+tFns
t54 CC Address hold after
RdCS, WrCS 6 + tF– 2 TCL - 19 + tF–ns
t
56 CC Data hold after WrCS 6 + tF– 2 TCL - 19 + tF–ns
Table 35 : Multiplexe d Bus C h ara ct eristics
Symbol Parameter
Max. CPU Clock
= 40MHz Variable CPU Clock
1/2 TCL = 1 to 40MHz
Unit
min. max. min. max.
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Fi gure 7 0 : External Memo ry Cycle : Multiplexed Bus, With / Without Read / Write Delay, Normal ALE
Data In
Data Out
Address
Address
t
38
t
10
Read Cycle
Write Cycle
t
5
t
16
t
39
t
40
t
25
t
27
t
18
t
14
t
22
t
23
t
12
t
8
t
8
t
6m
t
19
Address
t
17
t
6
t
7
t
9
t
11
t
13
t
15
t
16
t
12
t
13
Address
t
9
t
17
t
6
t
27
CLKOUT
ALE
CSx
A23-A16
(A15-A8)
Address/Data
RD
WR
WRL
BHE
WRH
Bus (P0)
Address/Data
Bus (P0)
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Fi gure 7 1 : External Memo ry Cycle: Multiplexed Mus, With / Without Read / Write Delay, Extended ALE
Data Out
Address
Data In
Address
Address
t
5
t
16
t
6
t
7
t
39
t
40
t
14
t
8
t
18
t
23
t
6
t
27
t
38
t
10
t
19
t
25
t
17
t
9
t
11
t
15
t
12
t
13
t
8
t
10
t
9
t
11
t
12
t
13
t
22
t
27
t
17
t
6
Read Cycle
Write Cycle
CLKOUT
ALE
CSx
A23-A16
(A15-A8)
RD
WR
WRL
BHE
WRH
Address/Data
Bus (P0)
Address/Data
Bus (P0)
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Fi gure 7 2 : E xternal Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Normal ALE,
Read / Write Chip Select
Read Cycle
Write Cycle
CLKOUT
ALE
A23-A16
(A15-A8)
BHE
Data In
Data Out
Address
Address
t
44
t
5
t
16
t
25
t
27
t
51
t
46
t
50
t
56
t
48
t
42
t
42
t
6
t
52
Address
t
17
t
6
t
7
t
43
t
45
t
49
t
47
t
16
t
48
t
49
Address
t
43
RdCSx
WrCSx
Address/Data
Bus (P0)
Address/Data
Bus (P0)
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Fi gure 7 3 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Extended ALE,
Read / Write Chip Select
Data Out
Address
Data In
Address
Address
t
5
t
16
t
6
t
7
t
46
t
42
t
42
t
50
t
18
t
56
t
6
t
54
t
44
t
19
t
25
t
17
t
43
t
45
t
47
t
48
t
49
t
49
t
43
t
48
t
44
t
45
R ead Cycle
Write Cycle
CLKOUT
ALE
A23-A16
(A15-A8)
BHE
RdCSx
WrCSx
Address/Data
Bus (P0)
Address/Data
Bus (P0)
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21.4.11 - De multiplexed Bus
VDD = 5V ± 10%, VSS = 0V , TA = -40 to +125°C , CL = 50pF,
ALE cycl e time = 4 TCL + 2 tA + tC + tF (50ns at 40MHz CPU clock without wait states).
Table 36 : Demultiplexed Bus Characteristics
Symbol Parameter
Maximum CPU Clock
= 40MHz Variable CPU Clock
1/2 TCL = 1 to 40MHz
Unit
Minimum Maximum Minimum Maximum
t5CC ALE high time 4 + tA– TCL - 8.5 + tA–ns
t
6
CC Address setup to ALE 2 + tA– TCL - 10.5 + tA–ns
t
80 CC Address/Unlatched CS setup to
RD, WR
(with RW-delay)
16.5 + 2tA– 2 TCL - 8.5 + 2tA–ns
t
81 CC Address/Unlatched CS setup to
RD, WR
(no RW-d elay)
4 + 2tA– TCL - 8.5 + 2tA–ns
t
12 CC RD, WR low time
(with RW-delay) 15.5 + tC– 2 TCL - 9.5 + tC–ns
t
13 CC RD, WR low time
(no RW-delay) 28 + tC– 3 TCL - 9.5 + tC–ns
t
14 SR RD to valid data in
(with RW-delay) –6 + t
C– 2 TCL - 19 + tCns
t15 SR RD to valid data in
(no RW-delay) – 18.5 + tC– 3 TCL - 19 + tCns
t16 SR ALE low to valid data in – 18.5 + tA +
tC
– 3 TCL - 19
+ tA + tCns
t17 SR Address/U nlatc hed C S to valid
data in – 22 + 2tA +
tC
– 4 TCL - 28
+ 2tA + tCns
t18 SR Data hold after RD
r ising edge 0– 0 –ns
t
20 SR Data float after RD rising edge
(with RW-delay) 1 3 – 16.5 + tF– 2 TCL - 8.5
+ tF + 2tA 1 ns
t21 SR Data float after RD rising edge
(no RW-d elay) 1 3 –4 + t
F– TCL - 8.5
+ tF + 2tA 1 ns
t22 CC Data valid to WR 10 + tC– 2 TCL - 15 + tC–ns
t
24 CC Data hold after WR 4 + tF– TCL - 8.5 + tF–ns
t
26 CC ALE rising edge after RD, WR -10 + tF– -10 + tF–ns
t
28 CC Address/U nlatc hed C S hold
after RD, W R 20 (no tF)
-5 + tF
(tF > 0)
– 0 (no tF)
-5 + tF
(tF > 0)
–ns
t
28h CC Add ress/U nlatc hed C S hold
after WRH -5 + tF–-5 + t
F–ns
t
38 CC ALE falling edge to Latched CS -4 - tA6 - tA-4 - tA6 - tAns
t39 SR Latched C S low to Valid Data In – 18.5
+ tC + 2tA– 3 TCL - 19
+ tC + 2tAns
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Notes : 1. RW-del ay and
t
A refer t o the next follow i ng bus cy cle.
2. R ead data are la tched w ith th e same clock edge that trig gers the addre ss c hange and the rising RD edge. Therefore address
changes befor e the end of RD have no impact on read cy cles.
3. Par tial l y tested, guaranteed by de sign charact erizat ion.
t41 CC Latched C S hold after RD, WR 2 + tF– TCL - 10.5 + tF–ns
t
82 CC Address setup to RdCS, WrCS
(with RW-delay) 14.5 + 2tA– 2 TCL - 10.5 +
2tA–ns
t
83 CC Address setup to RdCS, WrCS
(no RW-d elay) 2 + 2tA– TCL - 10.5 + 2tA–ns
t
46 SR RdCS to Valid Data In
(with RW-delay) –4 + t
C– 2 TCL - 21 + tCns
t47 SR RdCS to Valid Data In
(no RW-d elay) – 16.5 + tC– 3 TCL - 21 + tCns
t48 CC RdCS, WrCS Low Time
(with RW-delay) 15.5 + tC– 2 TCL - 9.5
+ tC–ns
t
49 CC RdCS, WrCS Low Time
(no RW-d elay) 28 + tC– 3 TCL - 9.5 + tC–ns
t
50 CC Data valid to WrCS 10 + tC– 2 TCL - 15 + tC–ns
t
51 SR Data hold after RdCS 0– 0 –ns
t
53 SR Data float after RdCS
(with RW-delay) 3– 16.5 + tF– 2 TCL - 8.5 + tFns
t68 SR Data float after RdCS
(no RW-d elay) 3–4 + t
F– TCL - 8.5 + tFns
t55 CC Address hold after
RdCS, WrCS -8.5 + tF– -8.5 + tF–ns
t
57 CC Data hold after WrCS 2 + tF– TCL - 10.5 + tF–ns
Table 36 : Demultiplexed Bus Characteristics
Symbol Parameter
Maximum CPU Clock
= 40MHz Variable CPU Clock
1/2 TCL = 1 to 40MHz
Unit
Minimum Maximum Minimum Maximum
ST10F269
149/160
Fi gure 7 4 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Normal ALE
Note: 1. Un-latched CSx = t41u = t41 TCL =10.5 + tF
.
Write Cycle
CLKOUT
ALE
A23-A16
A15-A0 (P1)
BHE
WR
WRL
WRH
Data In
Data Out
t
38
t
5
t
16
t
39
t
41
t
18
t
14
t
22
t
12
Address
t
17
t
13
t
15
t
12
t
13
t
21
t
20
t
81
t
80
t
26
t
24
t
17
t
6
t
41u
t
6
t
80
t
81
t
28 (or
t
28h)
CSx
Read Cycle
Data Bus (P0)
RD
1)
(D15-D8) D7-D0
Data Bus (P0)
(D15-D8) D7-D0
ST10F269
150/160
Fi gure 7 5 : E xternal Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Extended ALE
Address
t
5
t
16
t
39
t
41
t
14
t
24
t
6
t
38
t
20
t
26
t
17
t
15
t
12
t
13
t
12
t
13
t
22
Data In
t
18
t
21
t
6
t
17
t
28
t
28
Data Out
t
80
t
81
t
80
t
81
Read Cycle
Write Cycle
CLKOUT
ALE
CSx
RD
WR
WRL
WRH
Data Bus (P0)
(D15-D8) D7-D 0
Data Bus (P0)
(D15-D8) D7-D0
A23-A16
A15-A0 (P1)
BHE
ST10F269
151/160
Fi gure 7 6 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Normal ALE,
Read / Write Chip Select
R ead Cycle
Write Cycle
CLKOUT
ALE
Data In
Data Out
t
5
t
16
t
51
t
46
t
50
t
48
Address
t
17
t
49
t
47
t
48
t
49
t
68
t
53
t
83
t
82
t
26
t
57
t
55
t
6
t
82
t
83
RdCSx
WrCSx
Data Bus (P0)
(D15-D8) D7-D0
Data Bus (P0)
(D15-D8) D7-D0
A23-A16
A15-A0 (P1)
BHE
ST10F269
152/160
Fi gure 7 7 : External Memo ry Cycle: Demultiplexed Bus, no Read / Write Delay, Extended ALE, Read /
Wri te Chip S e lect
Address
t
5
t
16
t
46
t
57
t
6
t
53
t
26
t
17
t
47
t
48
t
49
t
48
t
49
t
50
Data In
t
51
t
68
t
55
Data Out
t
82
t
83
t
82
t
83
Read Cycle
Write Cycle
CLKOUT
ALE
RdCSx
WrCSx
Data Bus (P0)
(D15-D8) D7-D0
Data Bus (P0)
(D15-D8) D7-D0
A23-A16
A15-A0 (P1)
BHE
ST10F269
153/160
21.4.12 - CLKO UT an d READY
VDD = 5V ± 10%, VSS = 0V, TA = -40 to + 125°C , CL = 50pF
Notes : 1. These t i m i ngs are gi ven for test pu rposes o nl y, in order to ass ure reco gni tion at a s peci f i c clock ed ge.
2. Demultiplex ed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time
f or deactivating READ Y.
The 2tA and tC refer to the next following bus cycle, tF refer s t o the cu rrent bus c yc l e.
Table 37 : CLKOUT and READY Characterist ics
Symbol Parameter
Maximum CPU Clock
= 40 MHz Variable CPU Clock
1/2TCL = 1 to 40 MHz
Unit
Minimum Maximum Minimum Maximum
t29 CC CLKOUT cycle time 25 25 2TCL 2TCL ns
t30 CC CLKOUT high time 4 – TCL – 8.5 – ns
t31 CC CLKOUT low time 3 – TCL – 9.5 – ns
t32 CC CLKOUT rise time – 4 – 4 ns
t33 CC CLKOUT fall time – 4 – 4 ns
t34 CC CLKOUT rising edge to
ALE falling edge -2 + tA8 + tA-2 + tA8 + tAns
t35 SR Synchronous READY
setup time to CLKOUT 12.5 – 12.5 – ns
t36 SR Synchronous READY
hold time after CLKOUT 2– 2 –ns
t
37 SR Asynchronous READY
low time 35 – 2T CL + 10 – ns
t58 SR Asynchronous READY
setup time 1) 12.5 – 12.5 – ns
t59 SR Asynchronous READY
hold time 1) 2– 2 –ns
t
60 SR Async. READY hold time after
RD, W R high (Demultiplexed
Bus) 2)
00 + 2tA + tC + tF
2)
0 TCL - 12.5
+ 2tA + tC + tF 2) ns
ST10F269
154/160
Fi gure 7 8 : CLKOUT and READY
Notes : 1. Cycl e as program m ed, includi ng MC T C wai t st ates (Ex am pl e shows 0 MCTC WS ).
2. The leading edge of the respectiv e command depends on RW-delay.
3. READY sampled HIGH a t this samp ling point generates a READY contro lled wait state, READY sampled LOW at th is sampling
point terminates the cu rrently running bus cy cle.
4. READY may be d eact i vate d i n respons e to th e trail i ng (ri sing) edge of th e corresp ondi ng com m and (RD or WR).
5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because
CLKOUT is not enable d), it must fulfill t37 in order to be safely synchronized. This is guaranteed, if READY is removed in response to
the command (s ee Note 4)).
6. M ul tipl exed bus modes have a MUX wai t state added after a bus cycle, and an additional MTT C wait state may be i nserted here.
For a multiplexed bus with MTTC wait state this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC wait state this
delay is zero.
7. The next exter nal bus cy cle may start here.
t30
t34
t35 t36 t35 t36
t58 t59 t58 t59
wait state
READY M UX / Tri -state 6)
t32 t33
t29
Running cycle 1)
t31
t37
3) 3)
5)
t60 4)
6)
2)
7)
3) 3)
CLKOUT
ALE
RD, WR
Synchronous
Asynchronous
READY
READY
ST10F269
155/160
21.4.13 - External Bus Arbitration
VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF
Note: 1. Partial l y tes t ed, guarante ed by design charac ter i zat i on.
Notes: 1. The ST10F269 will complete the currently running bus c ycle before granting bus access.
2. This is the first possibility fo r BREQ to becom e act i ve.
3. The CS outputs will be resistive high (pull-up) after
t
64
.
Symbol Parameter
Maximum CPU Clock
= 40 MHz Variable CPU Clock
1/2TCL = 1 to 40 MHz
Unit
Minimum Maximum Minimum Maximum
t61 SR HOLD input setup time
to CLKOUT 15 – 15 – ns
t62 CC CLKOUT to HLDA high
or BREQ low delay – 12.5 – 12.5 ns
t63 CC CLKOUT to HLDA low
or BREQ high delay – 12.5 – 12.5 ns
t64 CC CSx release 1– 15 – 15 ns
t65 CC CSx drive -4 15 -4 15 ns
t66 CC Other signals release 1– 15 – 15 ns
t67 CC Other signals drive -4 15 -4 15 ns
Fi gure 7 9 : External Bus Arbitration (Releasing the Bus)
t61
t63
t66
1)
t64
1)
2)
t62
3)
CLKOUT
HOLD
HLDA
BREQ
Others
CSx
(P6.x)
ST10F269
156/160
Fi gure 8 0 : External Bus Arbitration (Regaini ng the Bus)
Notes: 1. This is the last chance for BREQ to trigger the indi cat ed regai n-sequenc e. E ven if B RE Q is ac t i vate d earl i er, t he regai n-sequence
is initiated by HOLD going hi gh. Please note t hat HOLD may al so be disact i vate d wi thout the ST10F269 request i ng the bus.
2. The next ST10F269 driven bus cycle may start here.
CLKOUT
HOLD
HLDA
Other
Signals
t62
CSx
(On P6.x)
t67
t62
1)
2)
t65
t61
BREQ
t63
t62
ST10F269
157/160
21.4.14 - High-Speed Synchronous Ser ial Interface (SSC) Timing
21.4.14.1 Master Mode
VCC = 5V ±10%, VSS = 0V, CPU clock = 40MHz, TA = -40 to +125°C, CL = 50pF
Note: 1. Ti m in g guaranteed by design.
The formula for SSC Clock Cycle time is : t300 = 4 TCL * (<SSCBR> + 1)
Where <SSCBR> represents the content of the SSC Baud rate register, tak en as unsigned 16-bit integer.
Notes: 1. The phase and polarity of shift and latch edge of SCLK is progr amm able. This figure uses the leading clock edge as shift edge (drawn
in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low , leading clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
Symbol Parameter Maximum Baud rate = 10M Baud
(<SSCBR> = 0001h) Variable Baud rate
(<SSCBR>=0001h-FFFFh) Unit
Minimum Maximum Minimum Maximum
t300 CC SSC clock cycle time 100 100 8 TCL 262144 TCL ns
t301 CC SSC clock high time 40 – t300/2 - 10 –ns
t
302 CC SSC clock low time 40 – t300/2 - 10 –ns
t
303 CC SSC clock rise time – 10 – 10 ns
t304 CC SSC clock fall time – 10 – 10 ns
t305 CC Write data valid after shift edge – 15 – 15 ns
t306 CC Write data hold after shift edge 1-2 – -2 – ns
t307p SR Read data setup time before
latch edge, phase error
detection on (SSCPEN = 1)
37.5 – 2TCL+12.5 – ns
t308p SR Read data hold time after latch
edge, phase error detection on
(SSCPEN = 1)
50 – 4TCL – ns
t307 SR Read data setup time before
latch edge, phase error
detection off (SSCPEN = 0)
25 – 2TCL – ns
t308 SR Read data hold time after latch
edge, phase error detection off
(SSCPEN = 0)
0–0–ns
Fi gure 8 1 : SSC Master Timing
t
303
t
304
t
305
t
305
t
305
t
306
1st Out Bi t Last O u t Bit2nd Out Bit
t
300
t
302
t
301
1) 2)
t
307
2nd.In Bit
1st.In Bit
t
308
t
307
Las t.I n Bit
t
308
SCLK
MTSR
MRST
ST10F269
158/160
21.4.14.2 Slave mode
VCC = 5V ±10%, VSS = 0V, CPU clo ck = 40M Hz, TA = -40 to +125°C , CL = 50pF
The formula for SSC Clock Cycle time is: t310 = 4 TCL * (< S SCBR > + 1)
Where <SSCBR> represents the content of the SSC Baud rate register, tak en as unsigned 16-bit integer.
Notes: 1. The phase and polarity of shift and latch edge of SCLK is progr amm able. This figure uses the leading clock edge as shift edge (drawn
in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low , leading clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
Symbol Parameter
Maximum Baud rate=10MBd
(<SSCBR> = 0001h) Variable Baud rate
(<SSCBR>=0001h-FFFFh) Unit
Minimum Maximum Minimum Maximum
t310 SR SSC clock cycle time 100 100 8 TCL 262144 TCL ns
t311 SR SSC clock high time 40 – t310/2 - 10 –ns
t
312 SR SSC clock low time 40 – t310/2 - 10 –ns
t
313 SR SSC clock rise time – 10 – 10 ns
t314 SR SSC clock fall time – 10 – 10 ns
t315 CC Write data valid after shift edge – 39 – 2 TCL + 14 ns
t316 CC Write data hold after shift edge 0 – 0 – ns
t317p SR
Read data setup time before lat ch edge,
phase error de tect ion on (S SCPEN = 1)
62 – 4TCL + 12 – ns
t318p1SR
Read data hold time after latch edge,
phase error detection on (SSCPEN = 1)
87 – 6TCL + 12 – ns
t317 SR
Read data setup time before lat ch edge,
phase error de tect ion off (SSCPEN = 0)
6–6–ns
t
318 SR
Read data hold time after latch edge,
phase error detection off (SSCPEN = 0)
31 – 2TCL + 6 – ns
Fi gure 8 2 : SSC Slave Timing
t
313
t
314
t
315
t
315
t
315
t
316
1st Out Bit Last Out Bit2nd Out Bit
t
310
t
312
t
311
1) 2)
t
317
2nd.In Bit1st.In Bit
t
318
t
317
Las t.I n Bit
t
318
SCLK
MRST
MTSR
ST10F269
159/160
22 - PACKAGE MECHANICAL DATA
Note:
1. Pa ck age di m ensi ons are in m m . The di m ensions quote d i n i nches ar e rounded.
23 - ORDERING INF O RMATION
Fi gure 8 3 : Pac kage Outline PQFP144 (28 x 28mm)
Dimensions Millimeters 1Inches (approx)
Minimum Typical Maximum Minimum Typical Maximum
A 4.07 0.160
A1 0.25 0.010
A2 3.17 3.42 3.67 0.125 0.133 0.144
B 0.22 0.38 0.009 0.015
c 0.13 0.23 0.005 0.009
D 30.95 31.20 31.45 1.219 1.228 1.238
D1 27.90 28.00 28.10 1.098 1.102 1.106
D3 22.75 0.896
e 0.65 0.026
E 30.95 31.20 31.45 1.219 1.228 1.238
E1 27.90 28.00 28.10 1.098 1.102 1.106
L 0.65 0.80 0.95 0.026 0.031 0.037
L1 1.60 0.063
K 0° (Minimum), 7° (Maximum)
Salestype Temperature range Package
ST10F269-Q3 -40°C to +125°C PQFP144 (28 x 28 mm)
144 109
D3
e
37 72
1
36
B
A1 A2
A
D1
D
73
108
E3
E1
E
0,10 mm
.004 inch
SEATING PLANE
c
L
K
L1
ST10F269
160/160
F269-Q3.REF
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