Hz Design Guide
DS51139A-page 118 1998 Microchip Technology Inc.
2.0 PROGRAMMING SIGNAL
WAVEFORM
Figure 2-1 shows the waveform of the programming
signal. Once the programmer sends a power-up and
gap signal to the device, the device transmits back a
verification bitstream in FSK. The verification signal
represents the contents of the memory in the device.
The blank device has all ‘1’s in its memory. A bit ‘1’ in
FSK is represented by a low signal level f or five cycles
and a high signal level for an additional five cycles
(Figure 2-1).
The device w i ll respond with a n onm od ulated (no da ta)
signal if the device has not recognized the power-up
signal . In this cas e, the p ow er-up sign al le v el should be
calibr ated to pr ovide a proper signa l le vel to the de vice .
The calibration procedure is explained in Section 3.0.
After the device is verified as blank, the programmer
sends a programming signal to the device. The pro-
gramming da ta is represented by an amplitude modu-
lation signal. Therefore, bit ‘1’ and ‘0’ are represented
by a low-power (level) signal and a high power (level)
signal, respectively, as shown in Figure 2-1. Each data
bit is re presented b y 128 cycl es of the carrier sign al. An
MCRF200 configured for 128 bits uses all bits in the
transfer; an MCRF200 configured for 96 bits ignores
bits 33 through 64, al though they are present in the pro-
gramming sequence. Therefore, for a 125 kHz carrier
signal, it takes 1.024 ms for one data bit (128 cycles x
8 µs/cycles) and 131.072 ms for 128 data bits
(128 cycles/bit x 8 µs/cycle x 128 bits).
A guard-band of ∆t = 10 cy cl es (8 0 µs) should be kept
at each end of a high-power (0) bit as shown in
Figure 2-1. This is to prevent accidental programming
or disturbing of adjacent bits in the array.
The mem ory arr ay is loc ked at the start of the prog ram-
ming cycle. Therefore, when the de vice leaves the pro-
gramming field, it locks the memory permanently,
regardless of the programming status. The device
should not be interrupted during the programming
cycle.
The device transmits the programmed (data contents)
circuits back to the programmer for verification. If the
v erifi ca tio n bi tst r eam is cor r ect , the pr og r am m er s end s
a v eri fie d si gna l (‘ v’) to the hos t c om put er; otherwis e , it
sends an error message (‘n’, see Figure 5-1).
The programming signal level must be within a limit of
the programming voltage window for successful pro-
gramming. The calibration of the signal level is
ex plained in Section 3.0.
2.1 Power-up, Gap, and Verification
Signals
The programming signal star ts with a power-up signal
for 80 ~ 180 µS, followed by a gap signal (0 volt) for
50 ~ 100 µS. The pu r pos e of th ese signa ls is to check
whether the device is blank and establish a program-
ming mo de in the device. Onc e the device reco gnizes
the pow er-up signal, it transmits bac k the contents of its
memory. If the device transmits back with the blank
bitstream (FSK with all ‘1’s), it is ready to be pro-
grammed. If the device is not blank, the programmer
informs the host computer that it is nonprogrammable.
If the power-up signal level is out of the programming
voltage range, the device will transmit back a
non-modulated signal (no data). The nonmodulated
signal has no variation in the amplitude (constant
voltage s igna l). A vari able res ist or, R5 in t he micr oID
programmer, should be adjusted to provide a proper
power-up signal level. A typical signal level is about
22 ± 3 VPP across the tag coil. This calibration
procedure is described in Section 3.0.
2.2 Programming Sequence
Once the device has been verified blank for program-
ming, th e progr ammer sends a progr amming se quence
to the device. The programming data entered in the
RFLAB software is sent to the device via the
programmer. The programming signal waveforms are
shown in Figure 2-1. One bit of data is represented by
128 cycles of the carrier signal. It takes 131.072 ms to
complete one programming cycle for the total of 128
data bits . An MCR F200 c onfigu red for 128 bits uses all
bits in the transfer; an MCRF200 configured for 96 bits
ignores bits 33 through 64, althou gh they a re present in
the programming sequence. After the programming
sequence, the device transmits back a verification
bitstream. The programmer reports to the host
computer the status of the programming.
The data is progr ammed only if the pr ogrammi ng signal
level is within the limit in the programming voltage
requirement of the device. It takes several
prog ram ming/ v erify cy cles to c omple tely pr ogr am e ach
bit of the MCRF2 00. The mic roID progr ammer us es ten
(10) blind program/verify cycles before checking the
final verify sequence for correct programming. Faster
programmers can be designed by checking each
program/verify cycle; after approximately 3 ~ 5 cycles,
the device will verify correctly. Once a correct verify
sequence is received, one additional program cycle
should be run to ensure proper programming margin.