MCP23009/MCP23S09 8-Bit I/O Expander with Open-Drain Outputs Features * Configurable interrupt source: - Interrupt-on-change from configured defaults or pin change * Polarity inversion register to configure the polarity of the input port data * External reset input * Low standby current: - 1 A (-40C TA +85C) - 6 A (+85C TA +125C) * Operating voltage: - 1.8V to 5.5V * 8-bit remote bidirectional I/O port: - I/O pins default to input * Open-drain outputs: - 5.5V tolerant - 25 mA sink capable (per pin) - 200 mA total * High-speed I2CTM interface: (MCP23009) - 100 kHz - 400 kHz - 3.4 MHz * High-speed SPI interface: (MCP23S09) - 10 MHz * Single hardware address pin: (MCP23009) - Voltage input to allow up to eight devices on the bus * Configurable interrupt output pins: - Configurable as active-high, active-low or open-drain Packages 16-pin QFN (3x3 [mm]) 18-pin PDIP (300 mil) 18-pin SOIC (300 mil) 20-pin SSOP Block Diagram MCP23S09 CS SCK SI SO SPI MCP23009 SCL SDA I2C Serializer/ Deserializer RESET 8 INT ADDR Control Multi-bit Decode GPIO GP0 GP1 GP2 GP3 GP4 GP5 GP6 GP7 8 Configuration/ Control Registers (c) 2009 Microchip Technology Inc. DS22121B-page 1 MCP23009/MCP23S09 Package Types: MCP23009 PDIP/SOIC GP5 GP4 15 14 13 VSS GP6 18 16 1 GP7 VDD QFN N/C 2 17 NC SCL 3 16 NC VSS 1 12 GP3 SDA 4 15 GP7 2 11 GP2 ADDR 5 14 GP6 NC VDD 10 GP1 RESET 6 13 GP5 SCL 4 9 GP0 INT 7 12 GP4 GP0 8 11 GP3 GP1 9 10 GP2 12 GP3 11 GP2 10 GP1 9 GP0 8 INT 6 RESET 5 SDA ADDR 3 7 EP 17 SSOP VDD NC SCL SDA ADDR RESET INT GP0 GP1 NC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VSS NC NC GP7 GP6 GP5 GP4 GP3 GP2 NC * Includes Exposed Thermal Pad (EP); see Table 1-1 and.Table 1-2 Package Types: MCP23S09 PDIP/SOIC CS 4 SO 6 13 GP4 RESET 7 12 GP3 INT 8 11 GP2 GP0 9 10 GP1 EP 17 8 3 INT 2 VDD 7 SCK GP5 RESET GP6 6 14 5 15 5 SI 4 SI 1 SO SCK VSS 13 GP7 14 16 GP4 3 15 NC CS GP5 VSS 17 GP6 18 2 16 1 NC GP7 VDD QFN * * Includes Exposed Thermal Pad (EP); see Table 1-1 and.Table 1-2 DS22121B-page 2 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 1.0 DEVICE OVERVIEW The MCP23X09 device provides 8-bit, general purpose parallel I/O expansion for I2C bus or SPI applications. The two devices differ only in the serial interface. * MCP23009 - I2C interface * MCP23S09 - SPI interface The MCP23X09 consists of multiple 8-bit configuration registers for input, output and polarity selection. The system master can enable the I/Os as either inputs or outputs by writing the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the input port register can be inverted with the polarity inversion register. All registers can be read by the system master. The interrupt output can be configured to activate under two conditions (mutually exclusive): 1. 2. When any input state differs from its corresponding input port register state. This is used to indicate to the system master that an input state has changed. When an input state differs from a pre-configured register value (DEFVAL register). The Interrupt Capture register captures port values at the time of the interrupt, thereby saving the condition that caused the interrupt. The Power-on Reset (POR) sets the registers to their default values and initializes the device state machine. The hardware address pin is used to determine the device address. (c) 2009 Microchip Technology Inc. DS22121B-page 3 MCP23009/MCP23S09 1.1 Pin Descriptions I2C PINOUT DESCRIPTION (MCP23009) TABLE 1-1: 18LD PDIP/ SOIC 16LD QFN 20LD SSOP Pin Type VDD VSS SCL SDA ADDR RESET INT 1 18 3 4 5 6 7 3 1 4 5 6 7 8 1 20 3 4 5 6 7 P P I I/O I I O GP0 8 9 8 I/O GP1 9 10 9 I/O GP2 10 11 12 I/O GP3 11 12 13 I/O GP4 12 13 14 I/O GP5 13 14 15 I/O GP6 14 15 16 I/O GP7 15 16 17 I/O NC 2, 16, 17 2 2,10, 11,19,1 8 EP -- 17 Pin Name DS22121B-page 4 Standard Function Power Ground Serial clock input Serial data I/O Hardware address pin allows up to 8 slave devices on the bus Hardware reset Interrupt output for port. Can be configured as active high, active low, or open-drain. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Not connected Exposed Thermal Pad (EP). Do not electrically connect. Can connect to VSS. (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 TABLE 1-2: Pin Name SPI PINOUT DESCRIPTION (MCP23S09) 18LD 16LD Pin PDIP/ QFN Type SOIC 1 18 3 1 P P SCK SI SO RESET INT GP0 3 4 5 6 7 8 9 4 2 5 6 7 8 9 I I I O I O I/O GP1 10 10 I/O GP2 11 11 I/O GP3 12 12 I/O GP4 13 13 I/O GP5 14 14 I/O GP6 15 15 I/O GP7 16 16 I/O NC EP 2, 17 -- -- 17 -- VDD VSS CS (c) 2009 Microchip Technology Inc. Standard Function Power (high current capable) Ground (high current capable) Chip select Serial clock input Serial data input Serial data out Hardware reset (must be externally biased) Interrupt output for port. Can be configured as active high, active low, or open-drain. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Not connected Exposed Thermal Pad (EP). Do not electrically connect, Can connect to VSS. DS22121B-page 5 MCP23009/MCP23S09 1.2 Power-on Reset (POR) The on-chip POR circuit holds the device in reset until VDD has reached a high enough voltage to deactivate the POR circuit (i.e., release the device from reset). The maximum VDD rise time is specified in the electrical specification section. byte during the data transfer. The address pointer automatically rolls over to address 00h after accessing the last register. When the device exits the POR condition (releases reset), device operating parameters (i.e., voltage, temperature, serial bus frequency, etc.) must be met to ensure proper operation. These two modes are not to be confused with single writes/reads and continuous writes/reads which are serial protocol sequences. For example, the device may be configured for Byte Mode and the master may perform a continuous read. In this case, the MCP23X09 would not increment the address pointer and would repeatedly drive data from the same location. 1.3 1.3.2 Serial Interface This block handles the functionality of the I2C (MCP23009) or SPI (MCP23S09) interface protocol. The MCP23X09 contains eleven (11) individual registers which can be addressed through the Serial Interface block (Table 1-3). TABLE 1-3: Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 1.3.1 REGISTER ADDRESSES Access to: IODIR IPOL GPINTEN DEFVAL INTCON IOCON GPPU INTF INTCAP (Read-only) GPIO OLAT BYTE MODE AND SEQUENTIAL MODE The MCP23X09 has the ability to operate in "Byte Mode" or "Sequential Mode" (IOCON.SEQOP). Byte mode and sequential mode are not to be confused with I2C byte operations and sequential operations. The modes explained here relate to the device's internal address pointer and whether or not it is incremented after each byte is clocked on the serial interface. Byte Mode disables automatic address pointer incrementing. When operating in Byte Mode, the MCP23X09 does not increment its internal address counter after each byte during the data transfer. This gives the ability to continually access the same address by providing extra clocks (without additional control bytes). This is useful for polling the GPIO register for data changes or for continually writing to the output latches. 1.3.2.1 I2C INTERFACE I2C Write Operation The I2C write operation includes the control byte and register address sequence, as shown in the bottom of Figure 1-1. This sequence is followed by eight bits of data from the master and an Acknowledge (ACK) from the MCP23009. The operation is ended with a stop (P) or restart (SR) condition being generated by the master. Data is written to the MCP23009 after every byte transfer. If a stop or restart condition is generated during a data transfer, the data will not be written to the MCP23009. Both "byte mode" and "sequential mode" are supported by the MCP23009. If sequential mode is enabled (default), the MCP23009 increments its address counter after each ACK during the data transfer. 1.3.2.2 I2C Read Operation I2C read operations include the control byte sequence, as shown in the bottom of Figure 1-1. This sequence is followed by another control byte (including the Start condition and ACK) with the R/W bit equal to a logic one (R/W = 1). The MCP23009 then transmits the data contained in the addressed register. The sequence is ended with the master generating a Stop or Restart condition. 1.3.2.3 I2C Sequential Write/Read For sequential operations (Write or Read), instead of transmitting a Stop or Restart condition after the data transfer, the master clocks the next byte pointed to by the address pointer (see Section 1.3.1 "Byte Mode and Sequential Mode" for details regarding sequential operation control). The sequence ends with the master sending a Stop or Restart condition. The MCP23009 address pointer will roll over to address zero after reaching the last register address. Refer to Figure 1-1. Sequential Mode enables automatic address pointer incrementing. When operating in Sequential Mode, the MCP23X09 increments its address counter after each DS22121B-page 6 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 1.3.3 SPI INTERFACE The MCP23S09 operates in Mode 0,0 and Mode 1,1. The difference between the two modes is the idle state of the clock. Mode 0,0: The idle state of the clock is LOW. Input data is latched on the rising edge of the clock; output data is driven on the falling edge of the clock. Mode 1,1: The idle state of the clock is HIGH. Input data is latched on the rising edge of the clock; output data is driven on the falling edge of the clock. 1.3.3.1 SPI Write Operation The SPI write operation is started by lowering CS. The write command (slave address with R/W bit cleared) is then clocked into the device. The opcode is followed by an address and at least one data byte. (c) 2009 Microchip Technology Inc. 1.3.3.2 SPI Read Operation The SPI read operation is started by lowering CS. The SPI read command (slave address with R/W bit set) is then clocked into the device. The opcode is followed by an address, with at least one data byte being clocked out of the device. 1.3.3.3 SPI Sequential Write/Read For sequential operations, instead of deselecting the device by raising CS, the master clocks the next byte pointed to by the address pointer. (see Section 1.3.1 "Byte Mode and Sequential Mode" for details regarding sequential operation control). The sequence ends by the raising of CS. The MCP23S09 address pointer will roll over to address zero after reaching the last register address. DS22121B-page 7 MCP23009/MCP23S09 MCP23009 I2CTM DEVICE PROTOCOL FIGURE 1-1: S - Start SR - Restart S OP DIN W ADDR DIN .... P P - Stop w - Write DOUT .... SR OP R OP W ADDR .... DOUT P DIN P R - Read OP - Device opcode SR ADDR - Device address P DOUT - Data out from MCP23009 DIN - Data in to MCP23009 OP S DOUT R SR SR OP W OP DOUT .... R ADDR P DOUT .... DOUT P DIN .... DOUT P P Byte and Sequential Write Byte S OP W ADDR DIN Sequential S OP W ADDR DIN P .... DIN P Byte and Sequential Read Byte S OP W ADDR SR OP R DOUT Sequential S OP W ADDR SR OP R DOUT DS22121B-page 8 P .... DOUT P (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 1.4 Multi-bit Address Decoder The ADDR pin is used to set the slave address of the MCP23009 (I2C only) to allow up to eight devices on the bus using only a single pin. Typically, this would require three pins. The multi-bit Address Decoder employs a basic FLASH ADC architecture (Figure 1-4). The seven comparators generate 8 unique values based on the analog input. This value is converted to a 3-bit code which corresponds to the address bits (A2, A1, A0) in the serial OPCODE. Sequence timings): 1. of Operation (see Figure 1-5 for Upon power up (after VDD stabilizes) the module becomes active after time tADEN. Note, the analog value on the ADDR pin must be stable before this point to ensure accurate address assignment. FIGURE 1-2: 2. 3. The 3-bit address is latched after tADDRLAT. The module powers down after the first rising edge of the serial clock is detected (tADDIS). Once the address bits are latched, the device will keep the slave address until a POR or reset condition occurs. 1.4.1 CALCULATING VOLTAGE ON ADDR When calculating the required voltage on the ADDR pin (V2), the set point should be the mid-point of the LSb of the ADC. The examples in Figure 1-2 and Figure 1-3 show how to determine the mid point voltage (V2) and the range of voltages based on a voltage divider circuit. The maximum tolerance is 20%, however, it is recommended to use 5% tolerance worst case (10% total tolerance). VOLTAGE DIVIDER EXAMPLE VDD ADDR VDD MCP23009 Only A0 R1 A1 A2 V2 R2 VSS VSS (c) 2009 Microchip Technology Inc. DS22121B-page 9 MCP23009/MCP23S09 FIGURE 1-3: VOLTAGE AND CODE EXAMPLE Assume: n = A2, A1, A0 in opcode ratio = R2/(R1+R2) V2 = voltage on ADDR pin V2(min) = V2 - (VDD/8) x %tolerance V2(max) = V2 + (VDD/8) x %tolerance n R2=2n+1 0 1 2 3 4 5 6 7 n R2=2n+1 0 1 2 3 4 5 6 7 n 1 3 5 7 9 11 13 15 R2=2n+1 0 1 2 3 4 5 6 7 n 1 3 5 7 9 11 13 15 R2=2n+1 0 1 2 3 4 5 6 7 DS22121B-page 10 1 3 5 7 9 11 13 15 1 3 5 7 9 11 13 15 10% Tolerance (total) VDD= 1.8 R1=16-R2 R2/(R1+R2) V2 V2(min) V2(max) 0.113 15 0.0625 0.00 0.14 13 0.1875 0.32 0.36 0.338 11 0.3125 0.54 0.59 0.563 0.788 9 0.4375 0.77 0.81 7 0.5625 0.99 1.04 1.013 1.238 5 0.6875 1.22 1.26 3 0.8125 1.44 1.49 1.463 1 0.9375 1.67 1.80 1.688 10% Tolerance (total) VDD= 2.7 R1=16-R2 R2/(R1+R2) V2 V2(min) V2(max) 0.169 15 0.0625 0.00 0.19 13 0.1875 0.48 0.53 0.506 0.844 11 0.3125 0.82 0.87 9 0.4375 1.16 1.20 1.181 7 0.5625 1.50 1.54 1.519 1.856 5 0.6875 1.83 1.88 3 0.8125 2.17 2.22 2.194 2.531 1 0.9375 2.51 2.70 VDD= 3.3 R1=16-R2 R2/(R1+R2) V2 15 0.0625 0.206 13 0.1875 0.619 1.031 11 0.3125 9 0.4375 1.444 1.856 7 0.5625 5 0.6875 2.269 2.681 3 0.8125 1 0.9375 3.094 10% Tolerance (total) V2(min) V2(max) 0.00 0.23 0.60 0.64 1.01 1.05 1.42 1.47 1.83 1.88 2.25 2.29 2.66 2.70 3.07 3.30 VDD= 5.5 10% Tolerance (total) R1=16-R2 R2/(R1+R2) V2 V2(min) V2(max) 15 0.0625 0.00 0.37 0.344 1.031 13 0.1875 1.01 1.05 11 0.3125 1.70 1.74 1.719 9 0.4375 2.38 2.43 2.406 3.094 7 0.5625 3.07 3.12 5 0.6875 3.76 3.80 3.781 4.469 3 0.8125 4.45 4.49 1 0.9375 5.13 5.50 5.156 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 FIGURE 1-4: FLASH ADC BLOCK DIAGRAM VDD analog_in addr_out[6] adc_en addr_out[5] d adc_en adc_en addr_out[4] q addr[6:0] i2c_addr[2:0] en reset '0' set d q adc_en adc_en addr_out[3] i2c_clk adc_en addr_out[2] adc_en addr_out[1] adc_en addr_out[0] adc_en adc_en gnd (c) 2009 Microchip Technology Inc. DS22121B-page 11 MCP23009/MCP23S09 FIGURE 1-5: HARDWARE ADDRESS DECODE TIMING tADEN VDD tADDRLAT adc_en i2c_addr[2:0] tADDIS i2c_clk 1.4.2 ADDRESSING I2C DEVICES (MCP23009) The MCP23009 is a slave I2C device that supports 7bit slave addressing, with the read/write bit filling out the control byte. The slave address contains four fixed bits and three user-defined hardware address bits (configured via ADDR pin). Figure 1-6 shows the control byte format. 1.4.3 ADDRESSING SPI DEVICES (MCP23S09) The MCP23S09 is a slave SPI device. The slave address contains seven fixed bits(no address bits) with the read/write bit filling out the control byte. Figure 1-7 shows the control byte format. I2CTM CONTROL BYTE FORMAT FIGURE 1-6: Control Byte S 0 1 0 0 A2 A1 A0 R/W ACK Slave Address Start bit R/W bit ACK bit R/W = 0 = write R/W = 1 = read FIGURE 1-7: SPI CONTROL BYTE FORMAT CS Control Byte 0 1 0 0 0 0 0 R/W Slave Address R/W bit R/W = 0 = write R/W = 1 = read DS22121B-page 12 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 I2CTM ADDRESSING REGISTERS FIGURE 1-8: S 0 1 0 0 A2 A1 A0 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK R/W = 0 Device Opcode Register Address The ACKs are provided by the MCP23009. FIGURE 1-9: SPI ADDRESSING REGISTERS CS 0 1 0 0 0 Device Opcode (c) 2009 Microchip Technology Inc. 0 0 R/W A7 A6 A5 A4 A3 A2 A1 A0 Register Address DS22121B-page 13 MCP23009/MCP23S09 1.5 GPIO Port The GPIO module is a general purpose 8-bit wide bidirectional port. The outputs are open-drain. The GPIO module contains the data ports (GPIOn), internal pull up resistors and the Output Latches (OLATn). The pull up resistors are individually configured and can be enabled when the pin is configured as an input or output. Reading the GPIOn register reads the value on the port. Reading the OLATn register only reads the latches, not the actual value on the port. Writing to the GPIOn register actually causes a write to the latches (OLATn). Writing to the OLATn register forces the associated output drivers to drive to the level in OLATn. Pins configured as inputs turn off the associated output driver and put it in high-impedance. DS22121B-page 14 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 1.6 Configuration and Control Registers There are eleven (11) registers associated with the MCP23X09 as shown in Table 1-4. TABLE 1-4: CONFIGURATION AND CONTROL REGISTER Address (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 POR/RST value IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111 IPOLA 01 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000 GPINTENA 02 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000 DEFVALA 03 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000 INTCONA 04 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000 IOCON 05 -- -- SEQOP -- -- ODR INTPOL INTCC 0000 0000 GPPUA 06 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000 INTFA 07 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000 INTCAPA 08 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000 GPIOA 09 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 OLATA 0A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000 Register Name (c) 2009 Microchip Technology Inc. DS22121B-page 15 MCP23009/MCP23S09 1.6.1 I/O DIRECTION REGISTER Controls the direction of the data I/O. When a bit is set, the corresponding pin becomes an input. When a bit is clear, the corresponding pin becomes an output. REGISTER 1-1: IODIR - I/O DIRECTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown IO7:IO0: Controls the direction of data I/O <7:0> 1 = Pin is configured as an input 0 = Pin is configured as an output DS22121B-page 16 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 1.6.2 INPUT POLARITY REGISTER This register allows the user to configure the polarity on the corresponding GPIO port bits. If a bit is set, the corresponding GPIO register bit will reflect the inverted value on the pin. REGISTER 1-2: IPOL - INPUT POLARITY PORT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown IP7:IP0: Controls the polarity inversion of the input pins <7:0> 1 = GPIO register bit will reflect the opposite logic state of the input pin 0 = GPIO register bit will reflect the same logic state of the input pin (c) 2009 Microchip Technology Inc. DS22121B-page 17 MCP23009/MCP23S09 1.6.3 INTERRUPT-ON-CHANGE CONTROL REGISTER The GPINTEN register controls the interrupt-onchange feature for each pin. If a bit is set, the corresponding pin is enabled for interrupt-on-change. The DEFVAL and INTCON registers must also be configured if any pins are enabled for interrupt-on-change. REGISTER 1-3: GPINTEN - INTERRUPT-ON-CHANGE PINS R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown GPINT7:GPINT0: General purpose I/O interrupt-on-change pins <7:0> 1 = Enable GPIO input pin for interrupt-on-change event 0 = Disable GPIO input pin for interrupt-on-change event Refer to INTCON and DEFVAL. DS22121B-page 18 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 1.6.4 DEFAULT COMPARE REGISTER FOR INTERRUPT-ON-CHANGE The default comparison value is configured in the DEFVAL register. If enabled (via GPINTEN and INTCON) to compare against the DEFVAL register, an opposite value on the associated pin will cause an interrupt to occur. REGISTER 1-4: DEFVAL - DEFAULT VALUE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown DEF7:DEF0: Sets the compare value for pins configured for interrupt-on-change from defaults <7:0>. Refer to INTCON. If the associated pin level is the opposite from the register bit, an interrupt occurs. Refer to INTCON and GPINTEN. (c) 2009 Microchip Technology Inc. DS22121B-page 19 MCP23009/MCP23S09 1.6.5 INTERRUPT CONTROL REGISTER The INTCON register controls how the associated pin value is compared for the interrupt-on-change feature. If a bit is set, the corresponding I/O pin is compared against the associated bit in the DEFVAL register. If a bit value is clear, the corresponding I/O pin is compared against the previous value. REGISTER 1-5: INTCON - INTERRUPT-ON-CHANGE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown IOC7:IOC0: Controls how the associated pin value is compared for interrupt-on-change <7:0>. 1 = Pin value is compared against the associated bit is DEFVAL register 0 = Pin value is compared against the previous pin value Refer to DEFVAL and GPINTEN. DS22121B-page 20 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 1.6.6 CONFIGURATION REGISTER The Sequential Operation (SEQOP) controls the incrementing function of the address pointer. If the address pointer is disabled, the address pointer does not automatically increment after each byte is clocked during a serial transfer. This feature is useful when it is desired to continuously poll (read) or modify (write) a register. The Open-Drain (ODR) control bit enables/disables the INT pin for open-drain configuration. REGISTER 1-6: The Interrupt Polarity (INTPOL) sets the polarity of the INT pin. This bit is functional only when the ODR bit is cleared, configuring the INT pin as active push-pull. The Interrupt Clearing Control (INTCC) configures how interrupts are cleared. When set (INTCC = 1), the interrupt is cleared when the INTCAP register is read. When cleared (INTCC = 0), the interrupt is cleared when the GPIO register is read. The interrupt can only be cleared when the interrupt condition is inactive. Refer to Section 1.7.4 "Clearing Interrupts" for details. IOCON - I/O EXPANDER CONFIGURATION REGISTER U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 - - SEQOP - - ODR INTPOL INTCC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Reads as 0 bit 6 Unimplemented: Reads as 0 bit 5 SEQOP: Sequential Operation mode bit. 1 = Sequential operation disabled, address pointer does not increment 0 = Sequential operation enabled, address pointer increments bit 4 Unimplemented: Reads as 0 bit 3 Unimplemented: Reads as 0 bit 2 ODR: Configures the INT pin as an open-drain output. 1 = Open-drain output (overrides the INTPOL bit) 0 = Active driver output (INTPOL bit sets the polarity) bit 1 INTPOL: Sets the polarity of the INT output pin. 1 = Active-high 0 = Active-low bit 0 INTCC: Interrupt Clearing Control 1 = Reading INTCAP register clears the interrupt 0 = Reading GPIO register clears the interrupt (c) 2009 Microchip Technology Inc. x = Bit is unknown DS22121B-page 21 MCP23009/MCP23S09 1.6.7 PULL-UP RESISTOR CONFIGURATION REGISTER The GPPU register controls the pull-up resistors for the port pins. If a bit is set the corresponding port pin is internally pulled up with an internal resistor. REGISTER 1-7: GPPU - GPIO PULL-UP RESISTOR REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown PU7:PU0: Controls the internal pull-up resistors on each pin (when configured as an input or output) <7:0>. 1 = Pull-up enabled 0 = Pull-up disabled FIGURE 1-10: TYPICAL PERFORMANCE CURVE FOR THE INTERNAL PULL-UP RESISTORS GPIO Pin Internal Pull-up Current vs VDD 400 350 T = -40C IPU (A) 300 T = +25C 250 200 150 T = +125C 100 T = +85C 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) DS22121B-page 22 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 1.6.8 INTERRUPT FLAG REGISTER The INTF register reflects the interrupt condition on the port pins of any pin that is enabled for interrupts via the GPINTEN register. A `set' bit indicates that the associated pin caused the interrupt. This register is `read only'. Writes to this register will be ignored. REGISTER 1-8: INTF - INTERRUPT FLAG REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown INT7:INT0: Reflects the interrupt condition on the port. Will reflect the change only if interrupts are enabled (GPINTEN) <7:0>. 1 = Pin caused interrupt 0 = Interrupt not pending (c) 2009 Microchip Technology Inc. DS22121B-page 23 MCP23009/MCP23S09 1.6.9 INTERRUPT CAPTURE REGISTER The INTCAP register captures the GPIO port value at the time the interrupt occurred. The register is `read only' and is updated only when an interrupt occurs. The register will remain unchanged until the interrupt is cleared via a read of INTCAP or GPIO. REGISTER 1-9: INTCAP - INTERRUPT CAPTURED VALUE FOR PORT REGISTER R-x R-x R-x R-x R-x R-x R-x R-x ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown ICP7:ICP0: Reflects the logic level on the port pins at the time of interrupt due to pin change <7:0>. 1 = Logic-high 0 = Logic-low DS22121B-page 24 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 1.6.10 PORT REGISTER The GPIO register reflects the value on the port. Reading from this register reads the port. Writing to this register modifies the Output Latch (OLAT) register. REGISTER 1-10: GPIO - GENERAL PURPOSE I/O PORT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown GP7:GP0: Reflects the logic level on the pins <7:0>. 1 = Logic-high 0 = Logic-low (c) 2009 Microchip Technology Inc. DS22121B-page 25 MCP23009/MCP23S09 1.6.11 OUTPUT LATCH REGISTER (OLAT) The OLAT register provides access to the output latches. A read from this register results in a read of the OLAT and not the port itself. A write to this register modifies the output latches that modifies the pins configured as outputs. REGISTER 1-11: OLAT - OUTPUT LATCH REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown OL7:OL0: Reflects the logic level on the output latch <7:0>. 1 = Logic-high 0 = Logic-low DS22121B-page 26 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 1.7 Interrupt Logic If enabled, the MCP23X09 activates the INT interrupt output when one of the port pins changes state or when a pin does not match the pre-configured default. Each pin is individually configurable as follows: * Enable/disable interrupt via GPINTEN * Can interrupt on either pin change or change from default as configured in DEFVAL Both conditions are referred to as Interrupt on Change (IOC). The Interrupt Control Module uses the following registers/bits: * GPINTEN - Interrupt enable register * INTCON - Controls the source for the IOC * DEFVAL - Contains the register default for IOC operation * IOCON (ODR and INTPOL) - configures the INT pin as push-pull, open-drain, and active level (high or low). 1.7.1 1.7.4 CLEARING INTERRUPTS The interrupt will remain active until the INTCAP or GPIO register is read (depending on IOCON.INTCC). Writing to these registers will not affect the interrupt. The interrupt condition will be cleared after the LSb of the data is clocked out during a Read operation of GPIO or INTCAP (depending on IOCON.INTCC). Note: Assuming IOCON.INTCC = 0 (INT cleared on GPIO read): The value in INTCAP can be lost if GPIO is read before INTCAP while another IOC is pending. After reading GPIO, the interrupt will clear and then set due to the pending IOC, causing the INTCAP register to update. IOC FROM PIN CHANGE If enabled, the MCP23X09 will generate an interrupt if a mismatch condition exists between the current port value and the previous port value. Only IOC enabled pins will be compared. See GPINTEN and INTCON registers. 1.7.2 IOC FROM REGISTER DEFAULT If enabled, the MCP23X09 will generate an interrupt if a mismatch occurs between the DEFVAL register and the port. Only IOC enabled pins will be compared. See GPINTEN, INTCON, and DEFVAL registers. 1.7.3 INTERRUPT OPERATION The INT interrupt output can be configured as "active low", "active high", or "open-drain" via the IOCON register. Only those pins that are configured as an input (IODIR register) with interrupt-on-change (IOC) enabled (GPINTEN register) can cause an interrupt. Pins configured as an output have no effect on the interrupt output pin. Input change activity on a port input pin that is enabled for IOC will generate an internal device interrupt and the device will capture the value of the port and copy it into INTCAP. The first interrupt event will cause the port contents to be copied into the INTCAP register. Subsequent interrupt conditions on the port will not cause an interrupt to occur as long as the interrupt is not cleared by a read of INTCAP or GPIO. (c) 2009 Microchip Technology Inc. DS22121B-page 27 MCP23009/MCP23S09 1.7.5 INTERRUPT CONDITIONS FIGURE 1-11: INTERRUPT-ON-PINCHANGE There are two possible configurations to cause interrupts (configured via INTCON): 1. 2. Pins configured for interrupt-on-pin-change will cause an interrupt to occur if a pin changes to the opposite state. The default state is reset after an interrupt occurs. For example, an interrupt occurs by an input changing from 1 to 0. The new initial state for the pin is a logic 0. Pins configured for interrupt-on-change from register value will cause an interrupt to occur if the corresponding input pin differs from the register bit. The interrupt condition will remain as long as the condition exists, regardless if the INTAP or GPIO is read. GPx INT ACTIVE ACTIVE Read GPIO or INTCAP Port value is captured into INTCAP FIGURE 1-12: Port value is captured into INTCAP INTERRUPT-ON-CHANGE FROM REGISTER DEFAULT See Figure 1-11 and Figure 1-12 for more information on interrupt operations. DEFVAL GP: 7 6 5 4 3 2 1 0 X X X X X 1 X X GP2 INT ACTIVE Port value is captured into INTCAP DS22121B-page 28 ACTIVE Read GPIO or INTCAP (INT clears only if interrupt condition does not exist.) (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 2.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings () Ambient temperature under bias.............................................................................................................-40C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.0V Voltage on RESET with respect to VSS ..................................................................................................... -0.3V to +14V Voltage on all other pins with respect to VSS (except VDD and GPIOA/B) ..................................... -0.6V to (VDD + 0.6V) Voltage on GPIO Pins: ................................................................................................................................. -0.6V to 5.5V Total power dissipation (Note 1)...........................................................................................................................700 mW Maximum current out of VSS pin ...........................................................................................................................200 mA Maximum current into VDD pin ..............................................................................................................................125 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Maximum output current sunk by any Output pin....................................................................................................25 mA Maximum output current sunk by any Output pin (VDD = 1.8V) ..............................................................................10 mA Note: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL) NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. (c) 2009 Microchip Technology Inc. DS22121B-page 29 MCP23009/MCP23S09 2.1 DC CHARACTERISTICS DC Characteristics Param No. Characteristic Operating Conditions (unless otherwise indicated): 1.8V VDD 5.5V at -40C TA +125C Sym Min Typ( 2) Max Units D001 Supply Voltage VDD 1.8 -- 5.5 V D002 VDD Start Voltage to Ensure Power-on Reset VPOR -- VSS -- V D003 VDD Rise Rate to Ensure Power-on Reset SVDD 0.05 -- -- V/ms Conditions Design guidance only. Not tested. D004 Supply Current IDD -- -- 1 mA SCL/SCK = 1 MHz D005 Standby (Idle) current IDDS -- -- 1 A -40C TA +85C -- -- 6 A +85C TA +125C VIL VSS -- 0.2 VDD V CS, SCL/SCK, SDA, SI, RESET VIH 0.8 VDD -- VDD V GPIO VIH 0.8 VDD -- 5.5 V IIL -- -- 1 A Input Low-Voltage D031 CS, GPIO, SCL/SCK, SDA, SI, RESET Input High-Voltage D041 Input Leakage Current D060 I/O port pins VSS VPIN VDD, Output Leakage Current D065 I/O port pins ILO -- -- 1 A VSS VPIN VDD, D070 GPIO internal pull-up current IPU -- 220 -- A VDD = 5V, GP Pins = VSS Note 1 VOL -- -- 0.6 V IOL = 8.5 mA, VDD = 4.5V (open-drain) INT -- -- 0.6 V IOL = 1.6 mA, VDD = 4.5V SO, SDA -- -- 0.6 V IOL = 3.0 mA, VDD = 1.8V SDA -- -- 0.8 V IOL = 3.0 mA, VDD = 4.5V VDD - 0.7 -- -- V IOH = -3.0 mA, VDD = 4.5V VDD - 0.7 -- -- Output Low-Voltage D080 GPIO Output High-Voltage D090 INT, SO VOH IOH = -400 A, VDD = 1.8V Capacitive Loading Specs on Output Pins D101 GPIO, SO, INT CIO -- -- 50 pF D102 SDA CB -- -- 400 pF Note 1: 2: This parameter is characterized, not 100% tested. Data in the Typical ("Typ") column is at 5V, +25C unless otherwise stated. DS22121B-page 30 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 2.2 AC CHARACTERISTICS FIGURE 2-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS VDD Pin 1 k SCL and SDA pin MCP23009 50 pF 135 pF RESET AND DEVICE RESET TIMER TIMING FIGURE 2-2: VDD RESET 30 32 31 Internal RESET 34 Output pin TABLE 2-1: RESET AND DEVICE RESET TIMER REQUIREMENTS AC Characteristics Standard Operating Conditions (unless otherwise specified) 1.8V VDD 5.5V at -40C TA +125C. Parameter No. Sym Characteristic 30 TRSTL RESET Pulse Width (low) 32 THLD 31 TPOR POR at device power up 34 Note 1: 2: TioZ Device active after reset high Output Hi-impedance from RESET Low Min Typ( 2) Max Units Conditions 1 -- -- s VDD = 5.0V -- 0 -- s VDD = 5.0V -- 20 -- s VDD = 5.0V -- -- 1 s This parameter is characterized, not 100% tested. Data in the Typical ("Typ") column is at 5V, +25C, unless otherwise stated. (c) 2009 Microchip Technology Inc. DS22121B-page 31 MCP23009/MCP23S09 TABLE 2-2: GP AND INT PINS AC Characteristics Standard Operating Conditions (unless otherwise specified) 1.8V VDD 5.5V at -40C TA +125C. Parameter No. Sym Characteristic 50 tGPOV Serial data to output valid 51 tINTD 52 tGPIV Typ( 2) Max Min Units -- -- 500 ns Interrupt pin disable time -- -- 600 ns GP input change to register valid -- 450 -- ns 53 tGPINT IOC event to INT active -- -- 600 ns 54 tGLITCH Glitch filter on GP pins -- -- 50 ns Note 1: 2: Conditions Note 1 Note 1 This parameter is characterized, not 100% tested. Data in the Typical ("Typ") column is at 5V, +25C, unless otherwise stated. FIGURE 2-3: GPIO AND INT TIMING SCL SDA In D1 D0 LSb of data byte zero during a write or read command, depending 50 on parameter GPn Output Pin 51 INT Pin INT pin active GPn Input Pin INT pin inactive 53 52 Register Loaded DS22121B-page 32 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 TABLE 2-3: HARDWARE ADDRESS LATCH TIMING AC Characteristics Parameter No. Sym 40 tADEN 41 Characteristic Time from VDD stable after POR to ADC enable tADDRLAT Time from ADC enable to address decode and latch 42 Note 1: 2: Standard Operating Conditions (unless otherwise specified) 1.8V VDD 5.5V at -40C TA +125C. tADDIS Time from raising edge of serial clock to ADC disable Min Typ( 2) Max Units Conditions -- 0 -- s Note 1 -- 50 -- ns Note 1 -- 10 -- ns Note 1 This parameter is characterized, not 100% tested. Data in the Typical ("Typ") column is at 5V, +25C, unless otherwise stated.. FIGURE 2-4: HARDWARE ADDRESS LATCH TIMING 40 VDD 41 adc_en i2c_addr[2:0] 42 SCL (c) 2009 Microchip Technology Inc. DS22121B-page 33 MCP23009/MCP23S09 FIGURE 2-5: I2C BUS START/STOP BITS TIMING SCL 93 91 90 92 SDA STOP Condition START Condition Note 1: Refer to Figure 2-1 for load conditions. FIGURE 2-6: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note 1: Refer to Figure 2-1 for load conditions. DS22121B-page 34 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 TABLE 2-4: I2C BUS DATA REQUIREMENTS (SLAVE MODE) I2CTM AC Characteristics Param No. 100 Characteristic Operating Conditions (unless otherwise indicated): 1.8V VDD 5.5V at -40C TA +125C RPU (SCL, SDA) = 1 k, CL (SCL, SDA) = 135 pF. Min Typ Max Units 4.0 -- -- s 1.8V - 5.5V 400 kHz mode 0.6 -- -- s 1.8V - 5.5V 3.4 MHz mode 0.06 -- -- s 2.7V - 5.5V 100 kHz mode 4.7 -- -- s 1.8V - 5.5V 400 kHz mode 1.3 -- -- s 1.8V - 5.5V 3.4 MHz mode 0.16 -- -- s 2.7V - 5.5V -- -- 1000 ns 1.8V - 5.5V -- 300 ns 1.8V - 5.5V -- 80 ns 2.7V - 5.5V -- 300 ns 1.8V - 5.5V Clock High Time: Sym THIGH 100 kHz mode 101 102 Clock Low Time: SDA and SCL Rise Time: 100 kHz mode TLOW TR (Note 1) 400 kHz mode 20 + 0.1 3.4 MHz mode 103 SDA and SCL Fall Time: 100 kHz mode 90 91 92 Note 1: 2: 3: -- CB(2) 400 kHz mode 20 + 0.1 -- 300 ns 1.8V - 5.5V 3.4 MHz mode 10 -- 80 ns 2.7V - 5.5V 100 kHz mode 4.7 -- -- s 1.8V - 5.5V 400 kHz mode 0.6 -- -- s 1.8V - 5.5V 3.4 MHz mode 0.16 -- -- s 2.7V - 5.5V 100 kHz mode 4.0 -- -- s 1.8V - 5.5V 400 kHz mode 0.6 -- -- s 1.8V - 5.5V 0.16 -- -- s 2.7V - 5.5V 0 -- 3.45 s 1.8V - 5.5V START Condition Setup Time: START Condition Hold Time: TSU:STA THD:STA Data Input Hold Time: THD:DAT 100 kHz mode 107 CB(2) 10 TF (Note 1) 3.4 MHz mode 106 Conditions 400 kHz mode 0 -- 0.9 s 1.8V - 5.5V 3.4 MHz mode 0 -- 0.07 s 2.7V - 5.5V Data Input Setup Time: TSU:DAT 100 kHz mode 250 -- -- ns 1.8V - 5.5V 400 kHz mode 100 -- -- ns 1.8V - 5.5V 3.4 MHz mode 0.01 -- -- s 2.7V - 5.5V 100 kHz mode 4.0 -- -- s 1.8V - 5.5V 400 kHz mode 0.6 -- -- s 2.7V - 5.5V 3.4 MHz mode 0.16 -- -- s 4.5V - 5.5V STOP Condition Setup Time: TSU:STO This parameter is characterized, not 100% tested. CB is specified from 10 to 400 (pF). This parameter is not applicable in high-speed mode (3.4 MHz). (c) 2009 Microchip Technology Inc. DS22121B-page 35 MCP23009/MCP23S09 I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) TABLE 2-4: Operating Conditions (unless otherwise indicated): 1.8V VDD 5.5V at -40C TA +125C RPU (SCL, SDA) = 1 k, CL (SCL, SDA) = 135 pF. I2CTM AC Characteristics Param No. Characteristic 109 Min Typ Max Units 100 kHz mode -- -- 3.45 s 400 kHz mode -- -- 0.9 s 1.8V - 5.5V 3.4 MHz mode -- -- 0.18 s 2.7V - 5.5V 4.7 -- -- s 1.8V - 5.5V 1.3 -- -- s 1.8V - 5.5V N/A -- N/A s 2.7V - 5.5V -- -- 400 pF (Note 1) -- -- 100 pF (Note 1) Output Valid From Clock: 110 Bus Free Time: Sym TAA TBUF (NOTE 3) 100 kHz mode 400 kHz mode 3.4 MHz mode Bus Capacitive Loading: 100 kHz and 400 kHz Note 1: 2: 3: 1.8V - 5.5V CB (NOTE 2) 3.4 MHz Input Filter Spike Suppression: (SDA and SCL) Conditions TSP 100 kHz and 400 kHz -- -- 50 ns (Note 1) 3.4 MHz -- -- 10 ns (Note 1) This parameter is characterized, not 100% tested. CB is specified from 10 to 400 (pF). This parameter is not applicable in high-speed mode (3.4 MHz). FIGURE 2-7: SPI INPUT TIMING 3 CS 11 6 1 Mode 1,1 10 7 2 SCK Mode 0,0 4 5 SI MSB in SO DS22121B-page 36 LSB in high impedance (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 FIGURE 2-8: SPI OUTPUT TIMING CS 8 2 9 SCK Mode 1,1 Mode 0,0 12 13 SO MSB out SI (c) 2009 Microchip Technology Inc. 14 LSB out don't care DS22121B-page 37 MCP23009/MCP23S09 TABLE 2-5: SPI INTERFACE AC CHARACTERISTICS SPI Interface AC Characteristics Param No. Characteristic Operating Conditions (unless otherwise indicated): 1.8V VDD 5.5V at -40C TA +125C. Sym Min Typ Max Units Clock Frequency FCLK -- -- 10 MHz 1 CS Setup Time TCSS 50 -- -- ns 2 CS Hold Time TCSH 50 -- -- ns 1.8V - 5.5V 3 CS Disable Time TCSD 50 -- -- ns 1.8V - 5.5V 4 Data Setup Time TSU 10 -- -- ns 1.8V - 5.5V 5 Data Hold Time THD 10 -- -- ns 1.8V - 5.5V 6 CLK Rise Time TR -- -- 2 s Note 1 7 CLK Fall Time TF -- -- 2 s Note 1 8 Clock High Time THI 45 -- -- ns 1.8V - 5.5V 9 Clock Low Time TLO 45 -- -- ns 1.8V - 5.5V 10 Clock Delay Time TCLD 50 -- -- ns 11 Clock Enable Time TCLE 50 -- -- ns 12 Output Valid from Clock Low TV -- -- 45 ns 13 Output Hold Time THO 0 -- -- ns 14 Output Disable Time TDIS -- -- 100 ns Note 1: Conditions 1.8V - 5.5V 1.8V - 5.5V This parameter is characterized, not 100% tested. FIGURE 2-9: TYPICAL PERFORMANCE CURVE FOR SPI TV SPECIFICATION (PARAM #12) TV (ns) TV vs VDD 40 35 30 25 20 15 10 5 0 T = +125C T = +85C T = -40C T = +25C 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) DS22121B-page 38 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 3.0 PACKAGING INFORMATION 3.1 Package Marking Information 16-Lead QFN (3x3 mm) XXX EYWW NNN Example 239 E919 256 18-Lead PDIP (300 mil) Example: XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 18-Lead SOIC (300 mil) XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN YYWWNNN Example: MCP23009 e3 E/SO^^ 0919 256 20-Lead SSOP (300 mil) XXXXXXXXXXX XXXXXXXXXXX MCP23009 e3 E/P^^ 0919256 Example: MCP23009 e3 E/SS^^ 0919 256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2009 Microchip Technology Inc. DS22121B-page 39 MCP23009/MCP23S09 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22121B-page 40 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (c) 2009 Microchip Technology Inc. DS22121B-page 41 MCP23009/MCP23S09 3 & ' !&" & 4# *!( !!& 4 %& &#& && 255***' '5 4 N NOTE 1 E1 1 2 3 D E A2 A L c A1 b1 e b eB 6&! '! 9'&! 7"') %! 7,8. 7 7 & ; < & & 7: 1, = = - 1!& & = = . - - - ##4 "# & 4!! "# >#& ##4>#& . < : 9& << 9 - < ) ? ) < 1 = = & & 9# 6 4!! 9#>#& 9 * 9#>#& : * + - !"#$%&" ' ()"&'"!&) &#*& & & # +%&, & !& - '! !#.# &"#' #%! & "! ! #%! & "! !! &$#/ !# '! #& .0 1,2 1!'! &$& "! **& "&& ! DS22121B-page 42 * ,1 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 ! " !" #$ %&' !"( 3 & ' !&" & 4# *!( !!& 4 %& &#& && 255***' '5 4 D N E E1 NOTE 1 1 2 3 e b h h c A2 A A1 L L1 6&! '! 9'&! 7"') %! 99. . 7 7: 7 ; < & : 8 & = = = = = - ##4 4!! &# %%+ 1, : >#& . ##4>#& . 1, : 9& 1, , '% @ 3 & A &9& 9 3 & & 9 3 & ? -1, = = .3 I B = <B = -- 9#>#& ) - = # %& D B = B # %&1 && ' E B = 9# 4!! B !"#$%&" ' ()"&'"!&) &#*& & & # +%&, & !& - '! !#.# &"#' #%! & "! ! #%! & "! !! &$#'' !# '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 % '! ("!"*& "&& (% % '& " !! (c) 2009 Microchip Technology Inc. * ,1 DS22121B-page 43 MCP23009/MCP23S09 ) !*+, ! " !! '& !!" 3 & ' !&" & 4# *!( !!& 4 %& &#& && 255***' '5 4 D N E E1 NOTE 1 1 2 e b c A2 A A1 L1 6&! '! 9'&! 7"') %! L 99. . 7 7 7: ; & : 8 & = = ? < &# %% = = : >#& . < < ##4>#& . - ? : 9& ? ##4 4!! 3 &9& 9 3 & & 9 9# 3 4!! & 9#>#& ?1, .3 = B B <B ) = -< !"#$%&" ' ()"&'"!&) &#*& & & # '! !#.# &"#' #%! & "! ! #%! & "! !! &$#'' !# - '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 % '! ("!"*& "&& (% % '& " !! DS22121B-page 44 * ,1 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 APPENDIX A: REVISION HISTORY Revision B (May 2009) The following is the list of modifications: 1. 2. Added the 3x3 QFN package (MG package marking). Updated Revision History. Revision A (December 2008) * Original Release of this Document. (c) 2009 Microchip Technology Inc. DS22121B-page 45 MCP23009/MCP23S09 NOTES: DS22121B-page 46 (c) 2009 Microchip Technology Inc. MCP23009/MCP23S09 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device Device X /XX Temperature Range Package MCP23009: MCP23009T: MCP23S09: MCP23S09T: a) b) 8-Bit I/O Expander w/ I2CTM Interface 8-Bit I/O Expander w/ I2C Interface (Tape and Reel) 8-Bit I/O Expander w/ SPI Interface 8-Bit I/O Expander w/ SPI Interface (Tape and Reel) Temperature Range E = -40C to +125C (Extended) * Package MG = Plastic Quad Flat, No Lead Package (3x3x0.9 mm Body), 16-Lead = Plastic DIP (300 mil Body), 18-Lead = Plastic SOIC (300 mil Body), 18-Lead = Plastic SSOP (5.3 mm), 20-Lead P SO SS Examples: c) d) e) f) a) b) c) d) (c) 2009 Microchip Technology Inc. MCP23009-E/P: Extended Temp., 18LD PDIP package. MCP23009-E/SO: Extended Temp., 18LD SOIC package. MCP23009T-E/SO: Tape and Reel, Extended Temp., 18LD SOIC package. MCP23009-E/SS: Extended Temp., 20LD SSOP package. MCP23009T-E/SS: Tape and Reel, Extended Temp., 20LD SSOP package. MCP23009-E/MG: Extended Temp., 16LD QFN package. MCP23S09-E/P: Extended Temp., 18LD PDIP package. MCP23S09-E/SO: Extended Temp., 18LD SOIC package. MCP23S09T-E/SO: Tape and Reel, Extended Temp., 18LD SOIC package. MCP23S09T-E/MG: Tape and Reel, Extended Temp., 16LD QFN package. DS22121B-page 47 MCP23009/MCP23S09 NOTES: DS22121B-page 48 (c) 2009 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2009 Microchip Technology Inc. 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