K6T4016V3B, K6T4016U3B Family CMOS SRAM Document Title 256Kx16 bit Low Power and Low Voltage CMOS Static RAM Revision History History Draft Data Remark 0.0 Initial draft June 28, 1996 Advance 0.1 Revise - Die name change ; A to B September 19, 1996 Preliminary 1.0 Finalize December 17, 1996 Final 2.0 Revise - Operating current update and release. ICC(Read/Write) = 20/40 10/45mA ICC1(Read/Write) = 20/40 10/45mA ICC2 = 90 70mA February 17, 1997 Final 3.0 Revise - Change datasheet format - Erase 70ns part from KM616V4000BI, KM616U4000B and KM616U4000BI Family - Power dissipation improved 0.7 to 1.0W - V IL(MAX) improved 0.4 to 0.6V. - ICC2 decreased 70 to 60mA. - Erase 100ns from KM616V4000B commercial product Error correction January 14, 1998 Final Revision No. 3.01 August 7, 1998 The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 3.01 January 1998 K6T4016V3B, K6T4016U3B Family CMOS SRAM 256Kx16 bit Low Power and Low Voltage CMOS Static RAM FEATURES GENERAL DESCRIPTION * Process Technology: TFT * Organization: 256K x16 * Power Supply Voltage KM68V4000B Family: 3.0~3.6V KM68U4000B Family: 2.7~3.3V * Low Data Retention Voltage: 2V(Min) * Three state output and TTL Compatible * Package Type: 44-TSOP2-400F/R The K6T4016V3B and K6T4016U3B families are fabricated by SAMSUNGs advanced CMOS process technology. The families support various operating temperature range and have small package types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Operating Temperature Product Family K6T4016V3B-B Vcc Range Speed 3.0~3.6V 701)/851)ns 2.7~3.3V 851)/100ns Commercial(0~70C) K6T4016U3B-B K6T4016V3B-F 3.0~3.6V Industrial(-40~85C) K6T4016U3B-F Standby (ISB1, Max) Operating (ICC2, Max) PKG Type 15A 60mA 851)/100ns 44-TSOP2-F/R 20A 2.7~3.3V 1. The parameter is measured with 30pF test load. FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION A4 A3 A2 A1 A0 CS I/O1 I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44-TSOP2 Forward 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 N.C A8 A9 A10 A11 A12 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 N.C A8 A9 A10 A11 A12 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 44-TSOP2 Reverse 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A4 A3 A2 A1 A0 CS I/OI I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A17 A16 A15 A14 A13 Clk gen. Precharge circuit. A13 Vcc Vss A14 A0 A1 A15 A16 Row select Memory array 1024 rows 256x16 columns A17 A2 A3 A4 I/O1~I/O8 Data cont I/O Circuit Column select Data cont I/O9~I/O16 Data cont Name Function Name Function A8 A9 A10 A5 A6 A7 A4 A12 CS Chip Select Input LB Lower Byte (I/O1~8) OE Output Enable Input UB Upper Byte(I/O 9~16) WE Write Enable Input Vcc Power Address Inputs Vss Ground N.C No Connection A0~A17 I/O 1~I/O16 Data Inputs/Outputs WE OE UB Control logic LB CS SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 3.01 January 1998 K6T4016V3B, K6T4016U3B Family CMOS SRAM PRODUCT LIST Commercial Temperature Product(0~70C) Part Name Industrial Temperature Products(-40~85C) Function Part Name Function K6T4016V3B-TB70 K6T4016V3B-TB85 K6T4016V3B-RB70 K6T4016V3B-RB85 44-TSOP2-F, 70ns, 3.3V,LL 44-TSOP2-F, 85ns, 3.3V,LL 44-TSOP2-R, 70ns, 3.3V,LL 44-TSOP2-R, 85ns, 3.3V,LL K6T4016V3B-TF85 K6T4016V3B-TF10 K6T4016V3B-RF85 K6T4016V3B-RF10 44-TSOP2-F, 85ns, 3.3V,LL 44-TSOP2-F, 100ns, 3.3V,LL 44-TSOP2-R, 85ns, 3.3V,LL 44-TSOP2-R, 100ns, 3.3V,LL K6T4016U3B-TB85 K6T4016U3B-TB10 K6T4016U3B-RB85 K6T4016U3B-RB10 44-TSOP2-F, 85ns, 3.0V,LL 44-TSOP2-F, 100ns, 3.0V,LL 44-TSOP2-R, 85ns, 3.0V,LL 44-TSOP2-R, 100ns, 3.0V,LL K6T4016U3B-TF85 K6T4016U3B-TF10 K6T4016U3B-RF85 K6T4016U3B-RF10 44-TSOP2-F, 85ns, 3.0V,LL 44-TSOP2-F, 100ns, 3.0V,LL 44-TSOP2-R, 85ns, 3.0V,LL 44-TSOP2-R, 100ns, 3.0V,LL FUNCTIONAL DESCRIPTION CS OE WE LB UB I/O1~8 I/O9~16 Mode Power 1) 1) High-Z High-Z Deselected Standby 1) H X L H H X X High-Z High-Z Output Disabled Active L X1) X1) H H High-Z High-Z Output Disabled Active L L H L H Dout High-Z Lower Byte Read Active L L H H L High-Z Dout Upper Byte Read Active L L H L L Dout Dout Word Read Active L X1) L L H Din High-Z Lower Byte Write Active L X 1) L H L High-Z Din Upper Byte Write Active L X1) L L L Din Din Word Write Active 1) 1) X X 1) X 1. X means dont care. (Must be in low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Soldering temperature and time Symbol Ratings Unit Remark VIN,VOUT VCC -0.5 to VCC+0.5 V - -0.3 to 4.6 V - PD 1.0 W - TSTG -65 to 150 C - 0 to 70 C Commercial -40 to 85 C Industrial 260C, 10sec (Lead Only) - - TA TSOLDER 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 3.01 January 1998 K6T4016V3B, K6T4016U3B Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Item Symbol Product Min Typ Max Unit Supply voltage Vcc K6T4016V3B Family K6T4016U3B Family 3.0 2.7 3.3 3.0 3.6 3.3 V Ground Vss All Family 0 0 0 V Input high voltage VIH K6T4016V3B, K6T4016U3B Family 2.2 - Vcc+0.3 2) V Input low voltage VIL K6T4016V3B, K6T4016U3B Family - 0.6 V -0.3 3) Note: 1. Commercial Product : TA=0 to 70C, otherwise specified Industrial Product : TA=-40 to 85C, otherwise specified 2. Overshoot : VCC+3.0V in case of pulse width 30ns 3. Undershoot : -3.0V in case of pulse width 30ns 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE 1) (f=1MHz, TA=25C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Symbol Min Test Conditions Typ Max Unit Input leakage current ILI VIL=Vss to Vcc -1 - 1 A Output leakage current ILO CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc -1 - 1 A Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read mA Average operating current ICC1 Cycle time=1s, 100% duty, IIO=0mA CS0.2V, VIN0.2V or VINVcc-0.2V - - 10 Read - - 10 Write - - 45 - - 60 mA mA ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or V IL Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.2 - - V Standby Current(TTL) ISB CS=VIH, Other inputs=VIL or VIH - - 0.5 mA Standby Current(CMOS) ISB1 CSVcc-0.2V, Others inputs = 0~Vcc - - 151) A 1. Industrial product = 20A 4 Revision 3.01 January 1998 K6T4016V3B, K6T4016U3B Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Input/Output Reference) Input pulse level : 0.4 to 2.2V Input rising and falling time : 5ns Input and output reference voltage :1.5V Output load(see right) : C L=100pF+1TTL CL=30pF+1TTL CL1) 1.Including scope and jig capacitance AC CHARACTERISTICS (K6T4016V3B Family: Vcc=3.0~3.6V, K6T4016U3B Family: Vcc=2.7~3.3V, Commercial product : TA=0 to 70C, Industrial product : TA=-40 to 85C) Speed Bins Parameter List Symbol 70ns Min Read Write 1) Max Min Units 100ns 85ns1) Max Min Max Read cycle time tRC 70 - 85 - 100 - ns Address access time tAA - 70 - 85 - 100 ns Chip select to output tCO - 70 - 85 - 100 ns Output enable to valid output tOE - 35 - 40 - 50 ns Chip select to low-Z output tLZ 10 - 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - 5 - ns UB, LB enable to low-Z output tBLZ 5 - 5 - 5 - ns Chip disable to high-Z output tHZ 0 25 0 25 0 30 ns OE disable to high-Z output tOHZ 0 25 0 25 0 30 ns Output hold from address change tOH 10 - 10 - 15 - ns LB, UB valid to data output tBA - 35 - 40 - 50 ns UB, LB disable to high-Z output tBHZ 0 25 0 25 0 30 ns Write cycle time tWC 70 - 85 - 100 - ns Chip select to end of write tCW 60 - 70 - 80 - ns Address set-up time tAS 0 - 0 - 0 - ns Address valid to end of write tAW 60 - 70 - 80 - ns Write pulse width tWP 55 - 55 - 70 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 25 0 25 0 30 ns Data to write time overlap tDW 30 - 35 - 40 - ns Data hold from write time tDH 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 5 - 5 - ns LB, UB valid to end of write tBW 60 - 70 - 80 - ns 1. The parameter is measured with 30pF test load. DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR CSVcc-0.2V Data retention current IDR Vcc=3.0V, CSVcc-0.2V Data retention set-up time tSDR Recovery time tRDR See data retention waveform Min Typ Max Unit 2.0 - 3.6 V - 0.5 151) A 0 - - 5 - - ms 1. Industrial product = 20A 5 Revision 3.01 January 1998 K6T4016V3B, K6T4016U3B Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL , WE=VIH, UB or/and LB=VIL ) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO CS tHZ tBA UB, LB tBHZ tOE OE Data out High-Z tOLZ tBLZ tLZ tOHZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 3.01 January 1998 K6T4016V3B, K6T4016U3B Family TIMING WAVEFORM OF WRITE CYCLE(1) CMOS SRAM (WE Controlled) tWC Address tCW(2) tWR(4) CS tAW tBW UB, LB tWP(1) WE tAS(3) tDW Data in High-Z tDH tWHZ Data out High-Z Data Valid tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS tAW tBW UB, LB tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z 7 Revision 3.01 January 1998 K6T4016V3B, K6T4016U3B Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled) tWC Address tCW(2) tWR(4) CS tAW tBW UB, LB tAS(3) tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(t WP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 3.0/2.7V 2.2V VDR CSVCC - 0.2V CS GND 8 Revision 3.01 January 1998 K6T4016V3B, K6T4016U3B Family CMOS SRAM PACKAGE DIMENSIONS Unit: millimeters(inches) 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) 0~8 0.25 ( ) 0.010 #44 #23 10.16 0.400 0.45 ~0.75 0.018 ~ 0.030 11.760.20 0.4630.008 ( 0.50 ) 0.020 #1 #22 1.000.10 0.0390.004 1.20 MAX. 0.047 ( 0.805 ) 0.032 0.35 0.10 0.0140.004 0.80 0.0315 0.0 0.10 MAX 0.004 0.05 MIN. 0.002 18.81 MAX. 0.741 18.410.10 0.7250.004 0 + 0.1 5 - 0.0 04 .0 +0 06 - 0.002 0.15 0~8 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R) ( #1 0.25 ) 0.010 #22 10.16 0.400 0.45 ~0.75 0.018 ~ 0.030 11.760.20 0.4630.008 ( 0.50 ) 0.020 #44 #23 1.000.10 0.0390.004 1.20 MAX. 0.047 ( 0.805 ) 0.032 0.350.10 0.0140.004 0.80 0.0315 0.05 MIN. 0.002 18.81 MAX. 0.741 18.41 0.10 0.7250.004 9 0 + 0.1 5 - 0.0 04 .0 +0 02 .006 - 0.0 0.15 0 0.10 0.004 MAX Revision 3.01 January 1998