K6T4016V3B, K6T4016U3B Family CMOS SRAM
Revision 3.01
January 1998
1
Document Title
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No.
0.0
0.1
1.0
2.0
3.0
3.01
Remark
Advance
Preliminary
Final
Final
Final
History
Initial draft
Revise
- Die name change ; A to B
Finalize
Revise
- Operating current update and release.
ICC(Read/Write) = 20/40 → 10/45mA
ICC1(Read/Write) = 20/40 → 10/45mA
ICC2 = 90 → 70mA
Revise
- Change datasheet format
- Erase 70ns part from KM616V4000BI, KM616U4000B and
KM616U4000BI Family
- Power dissipation improved 0.7 to 1.0W
- VIL(MAX) improved 0.4 to 0.6V.
- ICC2 decreased 70 to 60mA.
- Erase 100ns from KM616V4000B commercial product
Error correction
Draft Data
June 28, 1996
September 19, 1996
December 17, 1996
February 17, 1997
January 14, 1998
August 7, 1998
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
K6T4016V3B, K6T4016U3B Family CMOS SRAM
Revision 3.01
January 1998
2
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
GENERAL DESCRIPTION
The K6T4016V3B and K6T4016U3B families are fabricated by
SAMSUNG′s advanced CMOS process technology. The fami-
lies support various operating temperature range and have
small package types for user flexibility of system design. The
families also support low data retention voltage for battery
back-up operation with low data retention current.
FEATURES
• Process Technology: TFT
• Organization: 256K x16
• Power Supply Voltage
KM68V4000B Family: 3.0~3.6V
KM68U4000B Family: 2.7~3.3V
• Low Data Retention Voltage: 2V(Min)
• Three state output and TTL Compatible
• Package Type: 44-TSOP2-400F/R
PIN DESCRIPTION
Name Function Name Function
CS Chip Select Input LB Lower Byte (I/O1~8)
OE Output Enable Input UB Upper Byte(I/O9~16)
WE Write Enable Input Vcc Power
A0~A17 Address Inputs Vss Ground
I/O1~I/O16 Data Inputs/Outputs N.C No Connection
PRODUCT FAMILY
1. The parameter is measured with 30pF test load.
Product Family Operating Tempera-
ture Vcc Range Speed Power Dissipation PKG Type
Standby
(ISB1, Max) Operating
(ICC2, Max)
K6T4016V3B-B Commercial(0~70°C) 3.0~3.6V 701)/851)ns 15µA
60mA 44-TSOP2-F/R
K6T4016U3B-B 2.7~3.3V 851)/100ns
K6T4016V3B-F Industrial(-40~85°C) 3.0~3.6V 851)/100ns 20µA
K6T4016U3B-F 2.7~3.3V
A4
A3
A2
A1
A0
CS
I/O1
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
A14
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
N.C
A8
A9
A10
44-TSOP2
Forward 44-TSOP2
Reverse
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
N.C
A8
A9
A10
A11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A13 A12
A11 A12
A4
A3
A2
A1
A0
CS
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
A14
A13
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Row
select
A8 A9 A10 A5 A6 A4A7
A13
A14
A0
A1
A15
A16
A17
A2
I/O1~I/O8
A3
Data
cont
Data
cont
Data
cont
I/O9~I/O16
Vcc
Vss
A4
A12
Precharge circuit.
Memory array
1024 rows
256×16 columns
I/O Circuit
Column select
WE
OE
UB
CS
LB
Control
logic
K6T4016V3B, K6T4016U3B Family CMOS SRAM
Revision 3.01
January 1998
3
PRODUCT LIST
Commercial Temperature Product(0~70°C) Industrial Temperature Products(-40~85°C)
Part Name Function Part Name Function
K6T4016V3B-TB70
K6T4016V3B-TB85
K6T4016V3B-RB70
K6T4016V3B-RB85
K6T4016U3B-TB85
K6T4016U3B-TB10
K6T4016U3B-RB85
K6T4016U3B-RB10
44-TSOP2-F, 70ns, 3.3V,LL
44-TSOP2-F, 85ns, 3.3V,LL
44-TSOP2-R, 70ns, 3.3V,LL
44-TSOP2-R, 85ns, 3.3V,LL
44-TSOP2-F, 85ns, 3.0V,LL
44-TSOP2-F, 100ns, 3.0V,LL
44-TSOP2-R, 85ns, 3.0V,LL
44-TSOP2-R, 100ns, 3.0V,LL
K6T4016V3B-TF85
K6T4016V3B-TF10
K6T4016V3B-RF85
K6T4016V3B-RF10
K6T4016U3B-TF85
K6T4016U3B-TF10
K6T4016U3B-RF85
K6T4016U3B-RF10
44-TSOP2-F, 85ns, 3.3V,LL
44-TSOP2-F, 100ns, 3.3V,LL
44-TSOP2-R, 85ns, 3.3V,LL
44-TSOP2-R, 100ns, 3.3V,LL
44-TSOP2-F, 85ns, 3.0V,LL
44-TSOP2-F, 100ns, 3.0V,LL
44-TSOP2-R, 85ns, 3.0V,LL
44-TSOP2-R, 100ns, 3.0V,LL
ABSOLUTE MAXIMUM RATINGS1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item Symbol Ratings Unit Remark
Voltage on any pin relative to Vss VIN,VOUT -0.5 to VCC+0.5 V-
Voltage on Vcc supply relative to Vss VCC -0.3 to 4.6 V-
Power Dissipation PD1.0 W-
Storage temperature TSTG -65 to 150 °C-
Operating Temperature TA0 to 70 °CCommercial
-40 to 85 °CIndustrial
Soldering temperature and time TSOLDER 260°C, 10sec (Lead Only) - -
FUNCTIONAL DESCRIPTION
1. X means don′t care. (Must be in low or high state)
CS OE WE LB UB I/O1~8 I/O9~16 Mode Power
HX1) X1) X1) X1) High-Z High-Z Deselected Standby
LH H X1) X1) High-Z High-Z Output Disabled Active
LX1) X1) H H High-Z High-Z Output Disabled Active
L L HLHDout High-Z Lower Byte Read Active
L L H H LHigh-Z Dout Upper Byte Read Active
L L HL L Dout Dout Word Read Active
LX1) L L HDin High-Z Lower Byte Write Active
LX1) LHLHigh-Z Din Upper Byte Write Active
LX1) LLL Din Din Word Write Active
K6T4016V3B, K6T4016U3B Family CMOS SRAM
Revision 3.01
January 1998
4
RECOMMENDED DC OPERATING CONDITIONS1)
Note:
1. Commercial Product : TA=0 to 70°C, otherwise specified
Industrial Product : TA=-40 to 85°C, otherwise specified
2. Overshoot : VCC+3.0V in case of pulse width ≤ 30ns
3. Undershoot : -3.0V in case of pulse width ≤ 30ns
4. Overshoot and undershoot are sampled, not 100% tested.
Item Symbol Product Min Typ Max Unit
Supply voltage Vcc K6T4016V3B Family
K6T4016U3B Family 3.0
2.7 3.3
3.0 3.6
3.3 V
Ground Vss All Family 000V
Input high voltage VIH K6T4016V3B, K6T4016U3B Family 2.2 -Vcc+0.32) V
Input low voltage VIL K6T4016V3B, K6T4016U3B Family -0.33) -0.6 V
CAPACITANCE1) (f=1MHz, TA=25°C)
1. Capacitance is sampled, not 100% tested
Item Symbol Test Condition Min Max Unit
Input capacitance CIN VIN=0V -8pF
Input/Output capacitance CIO VIO=0V -10 pF
DC AND OPERATING CHARACTERISTICS
1. Industrial product = 20µA
Item Symbol Test Conditions Min Typ Max Unit
Input leakage current ILI VIL=Vss to Vcc -1 -1µA
Output leakage current ILO CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc -1 -1µA
Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read - - 10 mA
Average operating current ICC1 Cycle time=1µs, 100% duty, IIO=0mA
CS≤0.2V, VIN≤0.2V or VIN≥Vcc-0.2V Read - - 10 mA
Write - - 45
ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL - - 60 mA
Output low voltage VOL IOL=2.1mA - - 0.4 V
Output high voltage VOH IOH=-1.0mA 2.2 - - V
Standby Current(TTL) ISB CS=VIH, Other inputs=VIL or VIH - - 0.5 mA
Standby Current(CMOS) ISB1 CS≥Vcc-0.2V, Others inputs = 0~Vcc - - 151) µA
K6T4016V3B, K6T4016U3B Family CMOS SRAM
Revision 3.01
January 1998
5
CL1)
1.Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage :1.5V
Output load(see right) : CL=100pF+1TTL
CL=30pF+1TTL
AC CHARACTERISTICS (K6T4016V3B Family: Vcc=3.0~3.6V, K6T4016U3B Family: Vcc=2.7~3.3V,
Commercial product : TA=0 to 70°C, Industrial product : TA=-40 to 85°C)
1. The parameter is measured with 30pF test load.
Parameter List Symbol Speed Bins Units
70ns1) 85ns1) 100ns
Min Max Min Max Min Max
Read
Read cycle time tRC 70 -85 -100 -ns
Address access time tAA -70 -85 -100 ns
Chip select to output tCO -70 -85 -100 ns
Output enable to valid output tOE -35 -40 -50 ns
Chip select to low-Z output tLZ 10 -10 -10 -ns
Output enable to low-Z output tOLZ 5-5-5-ns
UB, LB enable to low-Z output tBLZ 5-5-5-ns
Chip disable to high-Z output tHZ 025 025 030 ns
OE disable to high-Z output tOHZ 025 025 030 ns
Output hold from address change tOH 10 -10 -15 -ns
LB, UB valid to data output tBA -35 -40 -50 ns
UB, LB disable to high-Z output tBHZ 025 025 030 ns
Write
Write cycle time tWC 70 -85 -100 -ns
Chip select to end of write tCW 60 -70 -80 -ns
Address set-up time tAS 0-0-0-ns
Address valid to end of write tAW 60 -70 -80 -ns
Write pulse width tWP 55 -55 -70 -ns
Write recovery time tWR 0-0-0-ns
Write to output high-Z tWHZ 025 025 030 ns
Data to write time overlap tDW 30 -35 -40 -ns
Data hold from write time tDH 0-0-0-ns
End write to output low-Z tOW 5-5-5-ns
LB, UB valid to end of write tBW 60 -70 -80 -ns
DATA RETENTION CHARACTERISTICS
1. Industrial product = 20µA
Item Symbol Test Condition Min Typ Max Unit
Vcc for data retention VDR CS≥Vcc-0.2V 2.0 -3.6 V
Data retention current IDR Vcc=3.0V, CS≥Vcc-0.2V -0.5 151) µA
Data retention set-up time tSDR See data retention waveform 0- - ms
Recovery time tRDR 5- -
K6T4016V3B, K6T4016U3B Family CMOS SRAM
Revision 3.01
January 1998
6
Address
Data Out Previous Data Valid Data Valid
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Data Valid
High-Z
tRC
CS
Address
UB, LB
OE
Data out
tAA
tRC
tOH
tOH
tAA
tCO
tBA
tOE
tOLZ
tBLZ
tLZ tOHZ
tBHZ
tHZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
K6T4016V3B, K6T4016U3B Family CMOS SRAM
Revision 3.01
January 1998
7
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
Address
CS
Data Undefined
UB, LB
WE
Data in
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
Address
CS
Data Valid
UB, LB
WE
Data in
Data out High-Z High-Z
tWC
tCW(2) tWR(4)
tAWtBW
tWP(1)
tAS(3) tDH
tDW
tWHZ tOW
tWC
tCW(2)
tAW tBW
tWP(1)
tDH
tDW
tWR(4)
High-Z High-Z
Data Valid
tAS(3)
K6T4016V3B, K6T4016U3B Family CMOS SRAM
Revision 3.01
January 1998
8
Address
CS
Data Valid
UB, LB
WE
Data in
Data out High-Z High-Z
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.
tWC
tCW(2)
tBW
tWP(1)
tDH
tDW
tWR(4)
tAW
DATA RETENTION WAVE FORM
CS controlled
VCC
3.0/2.7V
2.2V
VDR
CS
GND
Data Retention Mode
CS≥VCC - 0.2V
tSDR tRDR
tAS(3)
K6T4016V3B, K6T4016U3B Family CMOS SRAM
Revision 3.01
January 1998
9
Unit: millimeters(inches)
PACKAGE DIMENSIONS
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
0.002
#1
0.05
#22
#44 #23
0.35±0.10
0.014±0.004 0.80
0.0315
MIN.
0.047
1.20 MAX.
0.741
18.81MAX.
18.41± 0.10
0.725±0.004
11.76±0.20
0.463±0.008
+ 0.10
- 0.05
0.50
+ 0.004
- 0.002
0.15
0.006
0.020
10.16
0.400
0.10
0.004
0~8°
0.45 ~0.75
0.018 ~ 0.030
0.25
( )
0.010
( )
0.805
0.032
( )
MAX
1.00±0.10
0.039±0.004
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
0.002
#1
0.05
#22
#44 #23
0.35± 0.10
0.014±0.004 0.80
0.0315
MIN.
0.047
1.20MAX.
0.741
18.81MAX.
18.41±0.10
0.725±0.004
11.76±0.20
0.463±0.008
+ 0.10
- 0.05
0.50
+ 0.004
- 0.002
0.15
0.006
0.020
10.16
0.400
0.10
0.004
0~8°
0.45 ~0.75
0.018 ~ 0.030
0.25
( )
0.010
( )
0.805
0.032
( )
MAX
1.00±0.10
0.039±0.004
