MC14011BDT - ON Semiconductor

 Semiconductor Components Industries, LLC, 2003

March, 2003 - Rev. 3 1Publication Order Number:

MC14001B/D

MC14001B Series

B−Suffix Series CMOS Gates

MC14001B, MC14011B, MC14023B,

MC14025B, MC14071B, MC14073B,

MC14081B, MC14082B

The B Series logic gates are constructed with P and N channel

enhancement mode devices in a single monolithic structure

(Complementary MOS). Their primary use is where low power

dissipation and/or high noise immunity is desired.

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•All Outputs Buffered

•Capable of Driving Two Low-power TTL Loads or One Low-power

Schottky TTL Load Over the Rated Temperature Range.

•Double Diode Protection on All Inputs Except: Triple Diode

Protection on MC14011B and MC14081B

•Pin-for-Pin Replacements for Corresponding CD4000 Series B

Suffix Devices

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1)

Symbol Parameter Value Unit

VDD DC Supply Voltage Range - 0.5 to +18.0 V

Vin, Vout Input or Output Voltage Range

(DC or Transient) - 0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current

(DC or Transient) per Pin ±10 mA

PDPower Dissipation,

per Package (Note 2) 500 mW

TAAmbient Temperature Range - 55 to +125 °C

Tstg Storage Temperature Range - 65 to +150 °C

TLLead Temperature

(8-Second Soldering) 260 °C

1. Maximum Ratings are those values beyond which damage to the device

may occur.

2. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high-impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS  (Vin or Vout)  VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

either VSS or VDD). Unused outputs must be left open.

Device Description

DEVICE INFORMATION

MC14001B Quad 2-Input NOR Gate

MC14011B Quad 2-Input NAND Gate

MC14023B Triple 3-Input NAND Gate

MC14025B Triple 3-Input NOR Gate

MC14071B Quad 2-Input OR Gate

MARKING

DIAGRAMS

1

14

PDIP-14

P SUFFIX

CASE 646

MC140xxBCP

AWLYYWW

SOIC-14

D SUFFIX

CASE 751A

TSSOP-14

DT SUFFIX

CASE 948G

1

14

140xxB

AWLYWW

14

0xxB

ALYW

1

14

xx = Specific Device Code

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

SOEIAJ-14

F SUFFIX

CASE 965

1

14

MC140xxB

AWLYWW

MC14073B Triple 3-Input AND Gate

MC14081B Quad 2-Input AND Gate

MC14082B Dual 4-Input AND Gate

See detailed ordering and shipping information in the package

dimensions section on page 11 of this data sheet.

ORDERING INFORMATION

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MC14001B Series

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2

LOGIC DIAGRAMS

1

2

5

6

8

9

12

13

3

4

10

11

1

2

5

6

8

9

12

13

3

4

10

11

1

2

5

6

8

9

12

13

3

4

10

11

1

2

5

6

8

9

12

13

3

4

10

11

2 INPUT

1

29

3 INPUT

8

3

46

5

11

12 10

13

1

29

8

3

46

5

11

12 10

13

1

29

8

3

46

5

11

12 10

13

1

13

3

4

5

2

10

11

12

9

NC = 6, 8

VDD = PIN 14

VSS = PIN 7

FOR ALL DEVICES

NOR

MC14001B

Quad 2-Input NOR Gate

MC14025B

Triple 3-Input NOR Gate MC14023B

Triple 3-Input NAND Gate

NAND

MC14011B

Quad 2-Input NAND Gate

OR

MC14071B

Quad 2-Input OR Gate

AND

MC14081B

Quad 2-Input AND Gate

MC14073B

Triple 3-Input AND Gate MC14082B

Dual 4-Input AND Gate

PIN ASSIGNMENTS

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

IN 1C

IN 2C

IN 3C

VDD

IN 3A

OUTA

IN 2B

IN 1B

IN 2A

IN 1A

VSS

OUTB

IN 3B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

IN 1C

IN 2C

IN 3C

VDD

IN 3A

OUTA

IN 2B

IN 1B

IN 2A

IN 1A

VSS

OUTB

IN 3B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

IN 1C

IN 2C

IN 3C

VDD

IN 3A

OUTA

IN 2B

IN 1B

IN 2A

IN 1A

VSS

OUTB

IN 3B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

11

12

13

14

8

9

105

4

3

2

1

7

6

IN 2B

IN 3B

IN 4B

OUTB

VDD

NC

IN 1B

IN 3A

IN 2A

IN 1A

OUTA

VSS

NC

IN 4A

NC = NO CONNECTION

MC14023B

Triple 3-Input NAND Gate

MC14001B

Quad 2-Input NOR Gate MC14011B

Quad 2-Input NAND Gate

MC14082B

Dual 4-Input AND Gate

MC14081B

Quad 2-Input AND Gate

MC14025B

Triple 3-Input NOR Gate

MC14071B

Quad 2-Input OR Gate MC14073B

Triple 3-Input AND Gate

MC14001B Series

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3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎ

ÎÎÎ

VDD

ÎÎÎÎÎ

- 55C

ÎÎÎÎÎÎÎÎÎ

25C

ÎÎÎÎÎ

125C

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

V

DD

Vdc

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Typ (3)

ÎÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Output Voltage “0” Level

Vin = VDD or 0

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

VOL

ÎÎÎ

Î

ÎÎÎ

5.0

10

15

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

0.05

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

0

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

0.05

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

0.05

ÎÎÎ

Î

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

“1” Level

Vin = 0 or VDD

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

VOH

ÎÎÎ

Î

ÎÎÎ

5.0

10

15

ÎÎÎ

Î

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎ

Î

ÎÎÎ

5.0

10

15

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Input Voltage “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

VIL

ÎÎÎ

Î

ÎÎÎ

5.0

10

15

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

1.5

3.0

4.0

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

2.25

4.50

6.75

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

1.5

3.0

4.0

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

Î

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

VIH

ÎÎÎ

Î

ÎÎÎ

5.0

10

15

ÎÎÎ

Î

ÎÎÎ

3.5

7.0

11

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

3.5

7.0

11

ÎÎÎ

Î

ÎÎÎ

2.75

5.50

8.25

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

3.5

7.0

11

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

IOH

ÎÎÎ

Î

ÎÎÎ

5.0

10

15

ÎÎÎ

Î

ÎÎÎ

– 3.0

– 0.64

– 1.6

– 4.2

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

– 2.4

– 0.51

– 1.3

– 3.4

ÎÎÎ

Î

ÎÎÎ

– 4.2

– 0.88

– 2.25

– 8.8

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

– 1.7

– 0.36

– 0.9

– 2.4

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

IOL

ÎÎÎ

Î

ÎÎÎ

5.0

10

15

ÎÎÎ

Î

ÎÎÎ

0.64

1.6

4.2

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

0.51

1.3

3.4

ÎÎÎ

Î

ÎÎÎ

0.88

2.25

8.8

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

0.36

0.9

2.4

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Current

ÎÎÎÎ

Iin

ÎÎÎ

15

ÎÎÎ

—

ÎÎÎ

± 0.1

ÎÎÎÎ

—

ÎÎÎ

±0.00001

ÎÎÎÎ

± 0.1

ÎÎÎ

—

ÎÎÎ

± 1.0

ÎÎÎ

µAdc

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Input Capacitance

(Vin = 0)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

Cin

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

5.0

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

7.5

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

pF

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Quiescent Current

(Per Package)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

IDD

ÎÎÎ

Î

ÎÎÎ

5.0

10

15

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

0.25

0.5

1.0

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

0.0005

0.0010

0.0015

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

0.25

0.5

1.0

ÎÎÎ

Î

ÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

7.5

15

30

ÎÎÎ

Î

ÎÎÎ

µAdc

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Total Supply Current (4) (5)

(Dynamic plus Quiescent,

Per Gate, CL = 50 pF)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

IT

ÎÎÎ

Î

ÎÎÎ

5.0

10

15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (0.3 µA/kHz) f + IDD/N

IT = (0.6 µA/kHz) f + IDD/N

IT = (0.9 µA/kHz) f + IDD/N

ÎÎÎ

Î

ÎÎÎ

µAdc

3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

4. The formulas given are for the typical characteristics only at 25C.

5. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL - 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates

per package.

MC14001B Series

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4

B-SERIES GATE SWITCHING TIMES

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS (6) (CL = 50 pF, TA = 25C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

Symbol

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

VDD

Vdc

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

Min

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

Typ (7)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

Max

ÎÎÎ

Î

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Rise Time, All B-Series Gates

tTLH = (1.35 ns/pF) CL + 33 ns

tTLH = (0.60 ns/pF) CL + 20 ns

tTLH = (0.40 ns/PF) CL + 20 ns

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

tTLH

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

100

50

40

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

200

100

80

ÎÎÎ

Î

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Fall Time, All B-Series Gates

tTHL = (1.35 ns/pF) CL + 33 ns

tTHL = (0.60 ns/pF) CL + 20 ns

tTHL = (0.40 ns/pF) CL + 20 ns

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

tTHL

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

100

50

40

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

200

100

80

ÎÎÎ

Î

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time

MC14001B, MC14011B only

tPLH, tPHL = (0.90 ns/pF) CL + 80 ns

tPLH, tPHL = (0.36 ns/pF) CL + 32 ns

tPLH, tPHL = (0.26 ns/pF) CL + 27 ns

All Other 2, 3, and 4 Input Gates

tPLH, tPHL = (0.90 ns/pF) CL + 115 ns

tPLH, tPHL = (0.36 ns/pF) CL + 47 ns

tPLH, tPHL = (0.26 ns/pF) CL + 37 ns

8-Input Gates (MC14068B, MC14078B)

tPLH, tPHL = (0.90 ns/pF) CL + 155 ns

tPLH, tPHL = (0.36 ns/pF) CL + 62 ns

tPLH, tPHL = (0.26 ns/pF) CL + 47 ns

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

tPLH, tPHL

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

5.0

10

15

5.0

10

15

5.0

10

15

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

125

50

40

160

65

50

200

80

60

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

250

100

80

300

130

100

350

150

110

ÎÎÎ

Î

ÎÎÎ

ns

6. The formulas given are for the typical characteristics only at 25C.

7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD

14

CL

VSS

7

PULSE

GENERATOR

INPUT

OUTPUT

90%

50%

10%

50%

90%

20 ns 20 ns

tPHL tPLH

tTLH

tTHL

VOL

VOH

0 V

VDD

INPUT

OUTPUT

INVERTING

*All unused inputs of AND, NAND gates must be connected to VDD.

All unused inputs of OR, NOR gates must be connected to VSS.

90%

50%

10% VOL

VOH

OUTPUT

NON−INVERTING

tTHL

tTLH

tPLH tPHL

*

Figure 1. Switching Time Test Circuit and Waveforms

MC14001B Series

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5

CIRCUIT SCHEMATIC

NOR, OR GATES

14

*

7

VSS

3, 4, 10, 11

VDD

VSS

VDD

*Inverter omitted in MC14001B

1, 6, 8, 13

2, 5, 9, 12

14

*

7

9, 6, 10

VSS

VDD

1, 3, 11

2, 4, 12

VSS

VDD

VSS

VDD

8, 5, 13

MC14001B, MC14071B

One of Four Gates Shown MC14025B

One of Three Gates Shown

*Inverter omitted in MC14025B

CIRCUIT SCHEMATIC

NAND, AND GATES

14

*

7

3, 4, 10, 11

VSS

VDD

*Inverter omitted in MC14011B

14

*

7

9, 6, 10

VSS

VDD

*Inverter omitted in MC14023B

2, 5, 9, 12

1, 6, 8, 13

2, 4, 12

1, 3, 11

VDD

VSS

8, 5, 13

MC14011B, MC14081B

One of Four Gates Shown

MC14023B, MC14073B

One of Three Gates Shown

MC14001B Series

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6

TYPICAL B-SERIES GATE CHARACTERISTICS

N-CHANNEL DRAIN CURRENT (SINK) P-CHANNEL DRAIN CURRENT (SOURCE)

− 40°C

+ 85°C

+ 125°C

Figure 2. VGS = 5.0 Vdc Figure 3. VGS = - 5.0 Vdc

1.0

3.0

5.0

4.0

2.0

01.0 3.0 5.04.02.00

VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc)

− 1.0

00

TA = − 55°C

Figure 4. VGS = 10 Vdc Figure 5. VGS = - 10 Vdc

16

14

12

10

8.0

6.0

4.0

2.0

05.03.01.0 108.06.04.02.00 00

Figure 6. VGS = 15 Vdc Figure 7. VGS = - 15 Vdc

0000

− 40°C

+ 25°C

+ 85°C

+ 125°C

− 1.0 − 3.0 − 5.0− 4.0− 2.0

VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc)

TA = − 55°C

+ 25°C

TA = − 55°C

− 40°C

+ 25°C

+ 85°C

+ 125°C

VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc) VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc)

TA = − 55°C

− 40°C

+ 25°C

+ 85°C

+ 125°C

18

20

9.07.0 − 5.0− 3.0− 1.0 − 10− 8.0− 6.0− 4.0− 2.0 − 9.0− 7.0

− 40

− 35

− 30

− 25

− 20

− 15

− 10

− 5.0

− 45

− 50

106.02.0 2016128.04.0 1814

TA = − 55°C

− 40°C

+ 25°C

+ 85°C

− 10− 6.0− 2.0 − 20− 16− 12− 8.0− 4.0 − 18− 14

− 80

− 70

− 60

− 50

− 40

− 30

− 20

− 10

− 90

− 100

40

35

30

25

20

15

10

5.0

45

50

TA = − 55°C

− 40°C

+ 25°C

+ 85°C

− 2.0

− 3.0

− 4.0

− 5.0

− 6.0

− 7.0

− 8.0

− 9.0

− 10

I ,

DDRAIN CURRENT (mA)

I ,

DDRAIN CURRENT (mA)

I ,

DDRAIN CURRENT (mA)

I ,

DDRAIN CURRENT (mA)

I ,

DDRAIN CURRENT (mA)

I ,

DDRAIN CURRENT (mA)

+ 125°C

These typical curves are not guarantees, but are design aids.

Caution: The maximum rating for output current is 10 mA per pin.

MC14001B Series

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TYPICAL B-SERIES GATE CHARACTERISTICS (cont’d)

VOLTAGE TRANSFER CHARACTERISTICS

Figure 8. VDD = 5.0 Vdc Figure 9. VDD = 10 Vdc

1.0

3.0

5.0

4.0

2.0

01.0 3.0 5.04.02.00 00

Vin, INPUT VOLTAGE (Vdc)

SINGLE INPUT NAND, AND

MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR

MULTIPLE INPUT NAND, AND

SINGLE INPUT NAND, AND

MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR

MULTIPLE INPUT NAND, AND

2.0

6.0

10

8.0

4.0

2.0 6.0 108.04.0

Vin, INPUT VOLTAGE (Vdc)

V ,

out OUTPUT VOLTAGE (Vdc)

V ,

out OUTPUT VOLTAGE (Vdc)

Figure 10. VDD = 15 Vdc

00

SINGLE INPUT NAND, AND

MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR

MULTIPLE INPUT NAND, AND

2.0

6.0

10

8.0

4.0

2.0 6.0 108.04.0

Vin, INPUT VOLTAGE (Vdc)

12

14

16

V ,

out OUTPUT VOLTAGE (Vdc)

DC NOISE MARGIN

The DC noise mar gin is defined as the input voltage range

from an ideal “1” or “0” input level which does not produce

output state change(s). The typical and guaranteed limit

values of the input values VIL and VIH for the output(s) to

be at a fixed voltage VO are given in the Electrical

Characteristics table. VIL and VIH are presented graphically

in Figure 11.

Guaranteed minimum noise margins for both the “1” and

“0” levels =

1.0 V with a 5.0 V supply

2.0 V with a 10.0 V supply

2.5 V with a 15.0 V supply

Figure 11. DC Noise Immunity

Vout

VO

VIL

0

VIH

Vin

VDD

VDD Vout

VO

VIL

0

VIH

Vin

VDD

(a) Inverting Function (b) Non-Inverting Function

VSS = 0 VOLTS DC

MC14001B Series

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8

PACKAGE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 646-06

ISSUE M

17

14 8

B

ADIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 18.80

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

L

M−−− 10 −−− 10

N0.015 0.039 0.38 1.01



NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

F

HG DK

C

SEATING

PLANE

N

-T-

14 PL

M

0.13 (0.005)

L

M

J0.290 0.310 7.37 7.87

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A-03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

-A-

-B-

G

P7 PL

14 8

71 M

0.25 (0.010) B M

S

B

M

0.25 (0.010) A S

T

-T-

F

RX 45

SEATING

PLANE D14 PL K

C

J

M

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A8.55 8.75 0.337 0.344

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.228 0.244

R0.25 0.50 0.010 0.019

 

MC14001B Series

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9

PACKAGE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948G-01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1 DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2 CONTROLLING DIMENSION: MILLIMETER.

3 DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006)

PER SIDE.

4 DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5 DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.

6 TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7 DIMENSION A AND B ARE TO BE DETERMINED AT

DATUM PLANE −W−.

 

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V S

T

L-U-

SEATING

PLANE

0.10 (0.004)

-T-

ÇÇÇ

SECTION N-N

DETAIL E

JJ1

K

K1

ÉÉ

DETAIL E

F

M

-W-

0.25 (0.010)

8

14

7

1

PIN 1

IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

-V-

14X REFK

N

MC14001B Series

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10

PACKAGE DIMENSIONS

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 965-01

ISSUE O

HE

A1

DIM MIN MAX MIN MAX

INCHES

−−− 2.05 −−− 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

−−− 1.42 −−− 0.056

A1

HE

Q1

LE

10 0

10 

LEQ1



NOTES:

1 DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2 CONTROLLING DIMENSION: MILLIMETER.

3 DIMENSIONS D AND E DO NOT INCLUDE MOLD

FLASH OR PROTRUSIONS AND ARE MEASURED

AT THE PARTING LINE. MOLD FLASH OR

PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)

PER SIDE.

4 TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5 THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

0.13 (0.005) M0.10 (0.004)

D

Z

E

1

14 8

7

eA

b

VIEW P

c

L

DETAIL P

M

A

b

c

D

E

e

0.50

M

Z

MC14001B Series

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11

ORDERING & SHIPPING INFORMATION:

Device Package Shipping

MC14001BCP PDIP-14 2000 Units per Box

MC14001BD SOIC-14 2750 Units per Box

MC14001BDR2 SOIC-14 2500 Units / Tape & Reel

MC14001BDT TSSOP-14 96 Units per Rail

MC14001BDTR2 TSSOP-14 2500 Units / Tape & Reel

MC14011BCP PDIP-14 2000 Units per Box

MC14011BD SOIC-14 2750 Units per Box

MC14011BDR2 SOIC-14 2500 Units / Tape & Reel

MC14011BDT TSSOP-14 96 Units per Rail

MC14011BDTEL TSSOP-14 2000 Units / Tape & Reel

MC14011BDTR2 TSSOP-14 2500 Units / Tape & Reel

MC14023BCP PDIP-14 2000 Units per Box

MC14023BD SOIC-14 2750 Units per Box

MC14023BDR2 SOIC-14 2500 Units / Tape & Reel

MC14025BCP PDIP-14 2000 Units per Box

MC14025BD SOIC-14 2750 Units per Box

MC14025BDR2 SOIC-14 2500 Units / Tape & Reel

ORDERING & SHIPPING INFORMATION:

Device Package Shipping

MC14071BCP PDIP-14 2000 Units per Box

MC14071BD SOIC-14 55 Units per Rail

MC14071BDR2 SOIC-14 2500 Units / Tape & Reel

MC14071BDT TSSOP-14 96 Units per Rail

MC14071BDTR2 TSSOP-14 2500 Units / Tape & Reel

MC14073BCP PDIP-14 2000 Units per Box

MC14073BD SOIC-14 55 Units per Rail

MC14073BDR2 SOIC-14 2500 Units / Tape & Reel

MC14081BCP PDIP-14 2000 Units per Box

MC14081BD SOIC-14 55 Units per Rail

MC14081BDR2 SOIC-14 2500 Units / Tape & Reel

MC14081BDT TSSOP-14 96 Units per Rail

MC14081BDTR2 TSSOP-14 2500 Units / Tape & Reel

MC14082BCP PDIP-14 2000 Units per Box

MC14082BD SOIC-14 55 Units per Rail

MC14082BDR2 SOIC-14 2500 Units / Tape & Reel

For ordering information on the EIAJ version of the SOIC pack-

ages, please contact your local ON Semiconductor representa-

tive.

MC14001B Series

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changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

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liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

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PUBLICATION ORDERING INFORMATION

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2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051

Phone: 81-3-5773-3850

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For additional information, please contact your local

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MC14001B/D

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