DS1265Y-100 - Dallas Semiconductor

DS1265Y/AB

8M Nonvolatile SRAM

DS1265Y/AB

060598 1/8

FEATURES

•10 years minimum data retention in the absence of

external power

•Data is automatically protected during power loss

•Unlimited write cycles

•Low–power CMOS operation

•Read and write access times as fast as 70 ns

•Lithium energy source is electrically disconnected to

retain freshness until power is applied for the first time

•Full ±10% VCC operating range (DS1265Y)

•Optional ±5% VCC operating range (DS1265AB)

•Optional industrial temperature range of –40°C to

+85°C, designated IND

PIN ASSIGNMENT

VCC

A19

A15

A17

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

A18

A16

A14

A12

DQ0

DQ1

DQ2

GND

36–PIN ENCAPSULATED PACKAGE

740 MIL EXTENDED

PIN DESCRIPTION

A0 – A19 – Address Inputs

DQ0 – DQ7 – Data In/Data Out

CE – Chip Enable

WE – Write Enable

OE – Output Enable

VCC – Power (+5V)

GND – Ground

NC – No Connect

DESCRIPTION

The DS1265 8M Nonvolatile SRAMs are 8,388,608–bit,

fully static nonvolatile SRAMs organized as 1,048,576

words by 8 bits. Each NV SRAM has a self–contained

lithium energy source and control circuitry which

constantly monitors VCC for an out–of–tolerance condi-

tion. When such a condition occurs, the lithium energy

source is automatically switched on and write protection

is unconditionally enabled to prevent data corruption.

There is no limit on the number of write cycles which can

be executed and no additional support circuitry is

required for microprocessor interfacing.

DS1265Y/AB

060598 2/8

READ MODE

The DS1265 devices execute a read cycle whenever

WE (Write Enable) is inactive (high) and CE (Chip

Enable) and OE (Output Enable) are active (low). The

unique address specified by the 20 address inputs (A0 –

A19) defines which of the 1,048,576 bytes of data is

accessed. V alid data will be available to the eight data

output drivers within tACC (Access Time) after the last

address input signal is stable, providing that CE and OE

(Output Enable) access times are also satisfied. If OE

and CE access times are not satisfied, then data access

must be measured from the later occurring signal (CE or

OE) and the limiting parameter is either tCO for CE or tOE

for OE rather than tACC.

WRITE MODE

The DS1265 devices execute a write cycle whenever

WE and CE signals are active (low) after address inputs

are stable. The later occurring falling edge of CE or WE

will determine the start of the write cycle. The write cycle

is terminated by the earlier rising edge of CE or WE. All

address inputs must be kept valid throughout the write

cycle. WE must return to the high state for a minimum

recovery time (tWR) before another cycle can be initi-

ated. The OE control signal should be kept inactive

(high) during write cycles to avoid bus contention. How-

ever, if the output drivers are enabled (CE and OE

active) then WE will disable the outputs in tODW from its

falling edge.

DATA RETENTION MODE

The DS1265AB provides full functional capability for

VCC greater than 4.75 volts and write protects by

4.5 volts. The DS1265Y provides full functional capabil-

ity for VCC greater than 4.5 volts and write protects by

4.25 volts. Data is maintained in the absence of VCC

without any additional support circuitry . The nonvolatile

static RAMs constantly monitor VCC. Should the supply

voltage decay, the NV SRAMs automatically write pro-

tect themselves, all inputs become don’t care, and all

outputs become high impedance. As VCC falls below

approximately 3.0 volts, a power switching circuit con-

nects the lithium energy source to RAM to retain data.

During power–up, when VCC rises above approximately

3.0 volts, the power switching circuit connects external

VCC to RAM and disconnects the lithium energy source.

Normal RAM operation can resume after VCC exceeds

4.75 volts for the DS1265AB and 4.5 volts for the

DS1265Y.

FRESHNESS SEAL

Each DS1265 device is shipped from Dallas Semicon-

ductor with its lithium energy source disconnected,

guaranteeing full energy capacity. When VCC is first

applied at a level greater than VTP, the lithium energy

source is enabled for battery backup operation.

DS1265Y/AB

060598 3/8

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground –0.3V to +7.0V

Operating Temperature 0°C to 70°C; –40°C to +85°C for IND parts

Storage Temperature –40°C to +70°C; –40°C to +85°C for IND parts

Soldering Temperature 260°C for 10 seconds

* This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

DS1265AB Power Supply Voltage VCC 4.75 5.0 5.25 V

DS1265Y Power Supply Voltage VCC 4.5 5.0 5.5 V

Logic 1 Input Voltage VIH 2.2 VCC V

Logic 0 Input Voltage VIL 0+0.8 V

(VCC=5V±5% for DS1265AB)

DC ELECTRICAL CHARACTERISTICS (tA: See Note 10) (VCC=5V±10% for DS1265Y)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Leakage Current IIL –2.0 +2.0 µA

I/O Leakage Current IIO –2.0 +2.0 µA

Output Current @ 2.4V IOH –1.0 mA

Output Current @ 0.4V IOL 2.0 mA

Standby Current CE=2.2V ICCS1 1.0 1.5 mA

Standby Current CE=VCC–0.5V ICCS2 100 150 µA

Operating Current ICCO1 85 mA

Write Protection Voltage

(DS1265AB) VTP 4.5 4.62 4.75 V

Write Protection Voltage

(DS1265Y) VTP 4.25 4.37 4.5 V

CAPACITANCE (tA = 25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Capacitance CIN 10 20 pF

Output Capacitance CI/O 10 20 pF

DS1265Y/AB

060598 4/8

AC ELECTRICAL CHARACTERISTICS (VCC=5V±5% for DS1265AB)

(tA: See Note 10) (VCC=5V±10% for DS1265Y)

PARAMETER

SYMBOL

DS1265AB–70

DS1265Y–70 DS1265AB–100

DS1265Y–100

UNITS

NOTES

PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

Read Cycle Time tRC 70 100 ns

Access Time tACC 70 100 ns

OE to Output Valid tOE 35 50 ns

CE to Output Valid tCO 70 100 ns

OE or CE to Output Active tCOE 5 5 ns 5

Output High–Z from Deselection tOD 25 35 ns 5

Output Hold from Address Change t OH 5 5 ns

Write Cycle Time tWC 70 100 ns

Write Pulse Width tWP 55 75 ns 3

Address Setup T ime tAW 0 0 ns

Write Recovery Time tWR1

tWR2 5

15 5

15 ns 12

Output High–Z from WE tODW 25 35 ns 5

Output Active from WE tOEW 5 5 ns 5

Data Setup T ime tDS 30 40 ns 4

Data Hold T ime tDH1

tDH2 0

10 0

10 ns

ns 12

TIMING DIAGRAM: READ CYCLE

tRC

tACC

VIH

VIL

VIH

VIL

VIH

VIL

tOH

VIH

tOD

VIH

VOH

VOL

VOH

VOL

tCOE

OUTPUT

DATA VALID

DOUT

ADDRESSES

VIH

VIH tOE

VIL

CE tCO

SEE NOTE 1

DS1265Y/AB

060598 5/8

TIMING DIAGRAM: WRITE CYCLE 1

tWC

VIH

VIL

VIH

VIL

VIH

VIL

ADDRESSES

tAW

DATA IN STABLE

HIGH

IMPEDANCE

VIL VIL

VIH VIH

tWP tWR1

tODW tOEW

tDS tDH1

VIH

VIL

VIH

VIL

DOUT

DIN

SEE NOTES 2, 3, 4, 6, 7, 8 AND 12

TIMING DIAGRAM: WRITE CYCLE 2

tWC

VIL

VIH VIL

VIH

ADDRESSES

DOUT

DIN DATA IN STABLE

tAW tWP tWR2

VIH

VIL VIL VIL

VIH

VIL VIL

tCOE tODW

tDS tDH2

VIL

VIH

VIL

VIH

SEE NOTES 2, 3, 4, 6, 7, 8 AND 13

DS1265Y/AB

060598 6/8

POWER–DOWN/POWER–UP CONDITION

VCC

2.7V

tPD

tRtREC

BACKUP CURRENT-

SUPPLIED FROM

LITHIUM BATTERY

CE,

VTP

SEE NOTE 11

tDR

SLEWS WITH

VCC

tPU

VIH

POWER–DOWN/POWER–UP TIMING (tA: See Note 10)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

VCC Fail Detect to CE and WE

Inactive tPD 1.5 µs11

VCC Slew from VTP to 0V tF150 µs

VCC Slew from 0V to VTP tR150 µs

VCC Valid to CE and WE

Inactive tPU 2ms

VCC Valid to End of Write

Protection tREC 125 ms

(tA = 25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Expected Data Retention Time tDR 10 years 9

WARNING

Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode.

NOTES:

1. WE is high throughout read cycle.

2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state.

3. tWP is specified as the logical AND of CE or WE. tWP is measured from the latter of CE or WE going low to the

earlier of CE or WE going high.

4. tDS is measured from the earlier of CE or WE going high.

5. These parameters are sampled with a 5 pF load and are not 100% tested.

DS1265Y/AB

060598 7/8

6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output buffers remain

in a high impedance state during this period.

7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain

in a high impedance state during this period.

8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers

remain in a high impedance state during this period.

9. Each DS1265 has a built–in switch that disconnects the lithium source until VCC is first applied by the user . The

expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied

by the user.

10.All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial prod-

ucts, this range is 0°C to 70°C. For industrial products (IND), this range is –40°C to +85°C.

11. In a power–down condition the voltage on any pin may not exceed the voltage on VCC.

12.tWR1, tDH1 are measured from WE going high.

13.tWR2, tDH2 are measured from CE going high.

DC TEST CONDITIONS

Outputs Open

All voltages are referenced to ground

AC TEST CONDITIONS

Output Load: 100 pF + 1TTL Gate

Input Pulse Levels: 0V to 3.0V

T iming Measurement Reference Levels

Input: 1.5V

Output: 1.5V

Input pulse Rise and Fall T imes: 5 ns

ORDERING INFORMATION

DS1265TTP– SSS – III Operating Temperature Range

blank: 0°C to 70°C

IND: –40° C to +85°C

Access

70:

100:

Speed

70 ns

100 ns

Package T ype

blank: 36–pin 600 mil DIP

VCC Tolerance

AB: ± 5%

Y: ± 10%

DS1265Y/AB

060598 8/8

DS1265Y/AB NONVOLATILE SRAM 36–PIN 740 MIL EXTENDED MODULE, LONG

DIM MIN MAX

A IN.

B IN.

C IN.

D IN.

E IN.

F IN.

G IN.

H IN.

J IN.

K IN.

2.080

52.83 2.100

53.34

0.720

18.29 0.740

18.80

0.355

9.02 0.405

10.29

0.180

4.57 0.210

5.33

0.015

0.38 0.025

0.63

0.120

3.05 0.150

4.06

0.090

2.29 0.110

2.79

0.590

14.99 0.630

16.00

0.008

0.20 0.012

0.30

0.015

0.38 0.021

0.53

GKD

36–PINPKG