First Release
Features
Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes
Latch-Up Protected up to 4 Amps
High Peak Output Current: 4A Peak
Wide Operating Range: 4.5V to 30V
-55°C to +125°C Extended Operating
Temperature
• High Capacitive Load
Drive Capability: 1800pF in <15ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
Low Output Impedance
Low Supply Current
Two Drivers in Single Chip
Applications
Driving MOSFETs and IGBTs
Motor Controls
Line Drivers
Pulse Generators
Local Power ON/OFF Switch
Switch Mode Power Supplies (SMPS)
DC to DC Converters
Pulse Transformer Driver
Class D Switching Amplifiers
Power Charge Pumps
General Description
The IXDF504, IXDI504 and IXDN504 each consist of two 4-
Amp CMOS high speed MOSFET Gate Drivers for driving
the latest IXYS MOSFETs & IGBTs. Each of the outputs
can source and sink 4 Amps of Peak Current while produc-
ing voltage rise and fall times of less than 15ns. The input
of each driver is TTL or CMOS compatible and is virtually
immune to latch up. Patented* design innovations eliminate
cross conduction and current "shoot-through". Improved
speed and drive capabilities are further enhanced by very
fast, matched rise and fall times.
The IXDF504 is configured with one Gate Driver Inverting +
one Gate Driver Non-Inverting. The IXDI504 is configured as
a Dual Inverting Gate Driver, and the IXDN504 is configured
as a Dual Non-Inverting Gate Driver.
The IXDF504, IXDI504 and IXDN504 are each available in
the 8-Pin P-DIP (PI) package, the 8-Pin SOIC (SIA) pack-
age, and the 6-Lead DFN (D1) package, (which occupies
less than 65% of the board area of the 8-Pin SOIC).
*United States Patent 6,917,227
Ordering Information
Pa rt Num ber Des cription Package
Ty p e Packing Style Pack
Qty Configuration
IXDF504PI 4A Low Side Gate Driver I.C. 8-Pin PDIP Tube 50
IXDF504SIA 4A Low Side Gate Driver I.C. 8-Pin SOIC Tube 94
IXDF504SIAT/R 4A Low Side Gate Driver I.C. 8-Pin SOIC 13” Tape and Reel 2500
IXDF504D1 4A Low Side Gate Driver I.C. 6-Lead DFN 2” x 2” Waffle Pack 56
IXDF504D1T/R 4A Low Side Gate Driver I.C. 6-Lead DFN 13” Tape and Reel 2500
Dual Drivers,
one Inverting
and one Non-
Inverting
IXDI504PI 4A Low Side Gate Driver I.C. 8-Pin PDIP Tube 50
IXDI504SIA 4A Low Side Gate Driver I.C. 8-Pin SOIC Tube 94
IXDI504SIAT/R 4A Low Side Gate Driver I.C. 8-Pin SOIC 13” Tape and Reel 2500
IXDI504D1 4A Low Side Gate Driver I.C. 6-Lead DFN 2” x 2” Waffle Pack 56
IXDI504D1T/R 4A Low Side Gate Driver I.C. 6-Lead DFN 13” Tape and Reel 2500
Dual Inverting
Drivers
IXDN504PI 4A Low Side Gate Driver I.C. 8-Pin PDIP Tube 50
IXDN504SIA 4A Low Side Gate Driver I.C. 8-Pin SOIC Tube 94
IXDN504SIAT/R 4A Low Side Gate Driver I.C. 8-Pin SOIC 13” Tape and Reel 2500
IXDN504D1 4A Low Side Gate Driver I.C. 6-Lead DFN 2” x 2” Waffle Pack 56
IXDN504D1T/R 4A Low Side Gate Driver I.C. 6-Lead DFN 13” Tape and Reel 2500
Dual Non-
Inv e rting
Drivers
DS99567A(10/07)
NOTE: All parts are lead-free and RoHS Compliant
Copyright © 2007 IXYS CORPORATION All rights reserved
IXDF504 / IXDI504 / IXDN504
4 Ampere Dual Low-Side Ultrafast MOSFET Drivers
2
Copyright © 2007 IXYS CORPORATION All rights reserved
IXDF504 / IXDI504 / IXDN504
Figure 3 - IXDN504 Dual 4A Non-Inverting Gate Driver Functional Block Diagram
Figure 2 - IXDI504 Dual Inverting 4A Gate Driver Functional Block Diagram
N
P
N
P
OUT A
Vcc
OUT B
IN A
IN B
GND
ANTI-CROSS
CONDUCTION
CIRCUIT *
ANTI-CROSS
CONDUCTION
CIRCUIT *
Figure 1 - IXDF504 Inverting + Non-Inverting 4A Gate Driver Functional Block Diagram
N
P
N
P
OUT A
Vcc
OUT B
IN A
IN B
GND
ANTI-CROSS
CONDUCTION
CIRCUIT *
ANTI-CROSS
CONDUCTION
CIRCUIT *
*
*
*
*
* United States Patent 6,917,227
N
P
N
P
OUT A
Vcc
OUT B
IN A
IN B
GND
ANTI-CROSS
CONDUCTION
CIRCUIT *
ANTI-CROSS
CONDUCTION
CIRCUIT *
*
*
3
IXDF504 / IXDI504 / IXDN504
Unless otherwise noted, 4.5V VCC 30V .
All voltage measurements with respect to GND. IXD_504 configured as described in Test Conditions. All specifications are for one channel.
Electrical Characteristics @ TA = 25 oC (3)
Absolute Maximum Ratings (1) Operating Ratings (2)
Parameter Value
Supply Voltage 35 V
All Other Pins (Unless specified -0.3 V to VCC + 0.3V
otherwise)
Junction Temperature 150 °C
Storage Temperature -65 °C to 150 °C
Lead Temperature (10 Sec) 300 °C
Parameter Value
Operating Supply Voltage 4.5V to 30V
Operating Temperature Range -55 °C to 125 °C
(4)
IXYS reserves the right to change limits, test conditions, and dimensions.
Package Thermal Resistance *
8-Pin PDIP (PI) θJ-A (typ) 125 °C/W
8-Pin SOIC (SIA) θJ-A(typ) 200 °C/W
6-Lead DFN (D1) θJ-A(typ) 125-200 °C/W
6-Lead DFN (D1) θJ-C(max) 2.1 °C/W
6-Lead DFN (D1) θJ-S(typ) 6.4 °C/W
Symbol Parameter Test Conditions Min Typ Max Units
VIH High input voltage 4.5V VIN 18 V 3 V
VIL Low input voltag e 4.5V VIN 18V 0.8 V
VIN Input voltage range -5 VCC + 0.3 V
IIN Input current 0V VIN VCC -10 10
µA
VOH High output voltage VCC - 0.025 V
VOL Low output voltage 0.025 V
ROH High state output resistance VCC = 18V
IOUT = 10mA 1.5 2.5
ROL Low sta te ou tp ut re si st ance VCC = 18V
IOUT = 10mA 1.2 2
IPEAK Peak output current VCC = 15V 4 A
IDC Continuous output current Limited by package
dissipation 1 A
tR Rise time CLOAD =1000pF
VCC =18V 9 16 ns
tF Fall time CLOAD =1000pF
VCC =18V 8 14 ns
tONDLY On-time propagation delay CLOAD =1000pF
VCC =18V 19 40 ns
tOFFDLY Off-time propagation delay CLOAD =1000pF
VCC =18V 18 35 ns
VCC Power supply voltage 4.5 18 30 V
ICC Pow er supply curren t VCC = 18V, VIN = 0V
VIN = 3.5V
VIN = VCC
0.25 10
3
10
µA
mA
mA
4
Copyright © 2007 IXYS CORPORATION All rights reserved
IXDF504 / IXDI504 / IXDN504
Unless otherwise noted, 4.5V VCC 30V , Tj < 150oC
All voltage measurements with respect to GND. IXD_504 configured as described in Test Conditions. All specifications are for one channel.
Electrical Characteristics @ temperatures over -55 oC to 125 oC (3)
Notes:
1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent
damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
2. The device is not intended to be operated outside of the Operating Ratings.
3. Electrical Characteristics provided are associated with the stated Test Conditions.
4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily
to highlight any specific performance limits within which the device is guaranteed to function.
* The following notes are meant to define the conditions for the θJ-A, θJ-C and θJ-S values:
1) The θJ-A (typ) is defined as junction to ambient. The θJ-A of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated by the
resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with vertical boards
and the values would be lower with forced convection. For the 6-Lead DFN package, the θJ-A value supposes the DFN package is soldered
on a PCB. The θJ-A (typ) is 200 °C/W with no special provisions on the PCB, but because the center pad provides a low thermal resistance
to the die, it is easy to reduce the θJ-A by adding connected copper pads or traces on the PCB. These can reduce the θJ-A (typ) to 125 °C/W
easily, and potentially even lower. The θJ-A for DFN on PCB without heatsink or thermal management will vary significantly with size,
construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no thermal management.
2) θJ-C (max) is defined as juction to case, where case is the large pad on the back of the DFN package. The θJ-C values are generally not
published for the PDIP and SOIC packages. The θJ-C for the DFN packages are important to show the low thermal resistance from junction to
the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.
3) The θJ-S (typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a heatsink.
The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily available IMS in the
U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was assumed. The result was
given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the
DFN package.
S
y
mbol Parameter Test Conditions Min T
y
p Max Units
VIH High input voltage 4.5V VCC 18 V 3 V
VIL Low input voltage 4.5V VCC 18 V 0.8 V
VIN Input voltage range -5 VCC + 0.3 V
IIN Input current 0V VIN VCC -10 10
µA
VOH High output voltage VCC - 0.025 V
VOL Low output voltage 0.025 V
ROH High state output
resistance VCC = 18V, IOUT = 10mA
3
ROL Low state output
resistance VCC = 18V, IOUT = 10mA 2.5
IDC Continuous output current 1 A
tR Rise time CLOAD =1000pF VCC =18V 20 ns
tF Fall time CLOAD =1000pF VCC =18V 15 ns
tONDLY On-time propagation delay CLOAD =1000pF VCC =18V 60 ns
tOFFDLY Off-time propagation delay CLOAD =1000pF VCC =18V 50 ns
VCC Power supply voltage 4.5 18 30 V
ICC Power supply current VCC = 18V, VIN = 0V
V IN = 3.5V
V IN = VCC
150
3
150
µA
mA
mA
5
IXDF504 / IXDI504 / IXDN504
SYMBOL FUNCTION DESCRIPTION
IN A A Channel Input A channel input signal-TTL or CMOS compatible.
GND Ground
The system ground pin. Inter nally conne cted to all cir cui try , this pin prov ide s
ground reference for the entire device. This pin should be connected to a
low noise analog ground plane for optimum performance.
IN B B Channel Input B channel input signal-TTL or CMOS compatible.
OUT B B Channel Output B channel driver output. For application purposes, this pin is connected via a
resistor to the gate of a MOSFET/IGBT.
VCC Supply Voltage
Positive power-supply voltage input. This pin provides power to the entire
device. The range for this voltage is from 4.5V to 30V.
OUT A A Channel Output A chan nel criver output. For application purpose s, this pin is conn ected via a
resistor to the gate of a MOSFET/IGBT.
Pin Description
Figure 4 - Characteristics Test Diagram
CAUTION: Follow proper ESD procedures when handling and assembling this component.
1
2
3
45
6
7
8
NC NC
In A
Gnd
In B Out B
Vcc
Out A
10uF
Vcc
C
LOAD
Agilent 1147A
Current Probe
Agilent 1147A
Current Probe
C
LOAD
0.01uF
IXD_504
1
2
3
4
5
6
7
8
IN A
GND
INB
OUT A
V
S
OUT B
NC
NC
8 Lead PDIP (PI)
8 Pin SOIC (SI)
IXDN402
1
2
3
4
5
6
7
8
IN A
GND
INB
OUT A
V
S
OUT B
NC
NC
8 Lead PDIP (PI)
8 Pin SOIC (SI)
IXDI402
1
2
3
4
5
6
7
8
IN A
GND
INB
OUT A
V
S
OUT B
NC
NC
8 Lead PDIP (PI)
8 Pin SOIC (SI)
IXDF402
IXDN504
IXDI504IXDF504
(SIA) (SIA) (SIA)
1
2
3
4
5
6
GND
IN A
IN B
OUT A
OUT B
Vcc
6 Lead DFN (D1) 6 Lead DFN (D1) 6 Lead DFN (D1)
(Bottom View)
1
2
3
4
5
6IN A
IN B
OUT A
GND
OUT B
Vcc
1
2
3
4
5
6
OUT B
Vcc
IN A
GND
IN B
OUT A
IXYS reserves the right to change limits, test conditions, and dimensions.
Pin Configurations
NOTE: Solder tabs on bottoms of DFN packages are grounded
(Bottom View) (Bottom View)
6
Copyright © 2007 IXYS CORPORATION All rights reserved
IXDF504 / IXDI504 / IXDN504
Ris e / Fall Time vs . Temperatur e
VSUPPLY = 15V CLOAD = 1000pF
0
1
2
3
4
5
6
7
8
9
10
-50 -30 -10 10 30 50 70 90 110 130 150
T emperature (C)
Rise / Fall Time (ns)
Typical Performance Characteristics
Fig. 5 Fig. 6
Fig. 7 Fig. 8
Fig. 9 Fig. 10
Rise Times vs. Supply V oltage
0
10
20
30
40
50
60
70
80
90
0 5 10 15 20 25 30 35
S upply V oltage (V )
Rise Time (ns)
100pF
1000pF
10000pF
5400pF
Fa ll Time s vs. Sup p ly Voltag e
0
10
20
30
40
50
60
70
80
0 5 10 15 20 25 30 35
S u p p ly V oltag e (V)
Fa ll Time (n s)
100pF
1000pF
10000pF
5400pF
Rise Tim e v s. Capacitive Load
0
10
20
30
40
50
60
70
100 1000 10000
Load Capacitance (pF)
Rise Time (ns)
5V
15V
30V
Fall Time vs. Capacitive Load
0
10
20
30
40
50
60
70
100 1000 10000
Load Capacitance (pF)
Fall Time (ns)
30V
15V
5V
Input T hreshold Lev els vs. Supp ly Voltage
0
0.5
1
1.5
2
2.5
0 5 10 15 20 25 30 35
Supp ly V oltage (V )
Threshold Lev el (V)
Positive going input
N egative going input
7
IXDF504 / IXDI504 / IXDN504
Fig. 12
Fig. 14
Fig. 16
Fig. 11
Fig. 13
Fig. 15
Propagation Delay vs. Supply Voltage
R ising In p ut, CLOAD = 10 00pF
0
5
10
15
20
25
30
35
0 5 10 15 20 25 30 35
Supply Voltage (V)
Propagation Delay Time (ns)
Propagation Delay vs. Supply Voltage
Falling Input, CLOAD = 1000pF
0
5
10
15
20
25
30
35
40
45
0 5 10 15 20 25 30 35
Supply Voltage (V)
Propagation Delay Time (ns)
Input Threshold Levels vs. Temperature
VSUPPLY = 15V
0
0.5
1
1.5
2
2.5
3
-50 0 50 100 150
Tem perature (C)
Input Threshold Level (V)
Positive going input
Negative go ing input
Propagation Delay vs. Tem perature
VSUPPLY = 15V C LOAD = 1000pF
0
5
10
15
20
25
30
35
-50 0 50 100 150
Tem e prature (C )
Propagation Delay Time (ns)
Positve going input
Negative going input
Q uiescent Current vs. Supply V oltage
VIN = 0V
0.01
0.1
1
10
0 5 10 15 20 25 30 35
Supply V oltage (V )
Quiesent C urrent (uA)
Q uiescent Current vs. Temperature
VSUPPLY = 15V
0.01
0.1
1
10
100
1000
-50 -30 -10 10 30 50 70 90 110 130 150
T emperature (C)
Quies c ent Cu rrent (uA)
N on-inverting, Input= "0"
Inverting Input = "1"
8
Copyright © 2007 IXYS CORPORATION All rights reserved
IXDF504 / IXDI504 / IXDN504
Fig. 18
Fig. 17
Fig. 19 Fig. 20
Fig. 21 Fig. 22
Supply Current vs. Capacitive Load
VSUPPLY = 5V
0.01
0.1
1
10
100
100 1000 10000
Load Capacitance (pF)
Supply Current (mA)
100kHz
1MHz
2MHz
10kHz
Supply Current vs. Capacitive Load
VSUPPLY = 15V
0.01
0.1
1
10
100
1000
100 1000 10000
Load Capacitance (pF)
Supply C urrent (m A)
100kHz
1MHz
2MHz
10kHz
Supply Current vs. Capacitive Load
VSUPPLY = 30V
0.1
1
10
100
1000
100 1000 10000
Load Capacitance (pF)
Supply C urrent (m A)
2MHz
1MHz
100kHz
10kHz
Supply Current vs. Frequency
VSUPPLY = 30V
0.1
1
10
100
1000
10 100 1000 10000
Frequency (kH z)
Supply C urrent (m A)
100pF
1000pF
5400pF
10000pF
Supply Current vs. Frequency
VSUPPLY = 15V
0.01
0.1
1
10
100
1000
10 100 1000 10000
Frequency (kH z)
Supply C urrent (m A)
100pF
1000pF
10000pF
5400pF
Supply Current vs. Frequency
VSUPPLY = 5V
0.01
0.1
1
10
100
10 100 1000 10000
Frequency (kH z)
Supply C urrent (mA)
100pF
1000pF
10000pF
5400pF
9
IXDF504 / IXDI504 / IXDN504
Low State Output R esistance vs. S upply Voltage
0
0.5
1
1.5
2
2.5
3
0 5 10 15 20 25 30 35
Supply Voltage (V)
Output Resistance (ohms)
Fig. 25 Fig. 26
Fig. 23 Fig. 24
Fig. 27 Fig. 28
Output Source Current vs. Supply Voltage
0
2
4
6
8
10
12
0 5 10 15 20 25 30 35
Supply Voltage (V)
Source Current (A)
Output Sink Current vs. Supply Voltage
-14
-12
-10
-8
-6
-4
-2
0
0 5 10 15 20 25 30 35
Supply Voltage (V )
Sink Current (A)
Output Source Current vs. Tem perature
VSUPPLY = 15V
0
1
2
3
4
5
6
-50 0 50 100 150
Temperature (C)
Output Source Current (A)
Output Sink Current vs. Temperature
VSUPPLY = 15V
-6
-5
-4
-3
-2
-1
0
-50 0 50 100 150
Temperature (C)
Output Sink Current (A)
H igh State Output Resistance vs. Supply Voltage
0
0.5
1
1.5
2
2.5
3
0 5 10 15 20 25 30 35
Supply V oltage (V)
Output Resistance (ohms)
10
Copyright © 2007 IXYS CORPORATION All rights reserved
IXDF504 / IXDI504 / IXDN504
When designing a circuit to drive a high speed MOSFET
utilizing the IXD_504, it is very important to observe certain
design criteria in order to optimize performance of the driver.
Particular attention needs to be paid to Supply Bypassing,
Grounding, and minimizing the Output Lead Inductance.
Say, for example, we are using the IXD_504 to charge a 2500pF
capacitive load from 0 to 25 volts in 25ns.
Using the formula: IC = C (∆V/t), where V=25V C=2500pF &
t=25ns, we can determine that to charge 2500pF to 25 volts
in 25ns will take a constant current of 2.5A. (In reality, the
charging current won’t be constant and will peak somewhere
around 4A).
SUPPLY BYPASSING
In order for our design to turn the load on properly, the IXD_504
must be able to draw this 2.5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the power
supply at the driver with a capacitance value that is an order of
magnitude larger than the load capacitance. Usually, this
would be achieved by placing two different types of bypassing
capacitors, with complementary impedance curves, very close
to the driver itself. (These capacitors should be carefully
selected and should have low inductance, low resistance and
high-pulse current-service ratings). Lead lengths may radiate
at high frequency due to inductance, so care should be taken
to keep the lengths of the leads between these bypass
capacitors and the IXD_504 to an absolute minimum.
GROUNDING
In order for the design to turn the load off properly, the IXD_504
must be able to drain this 2.5A of current into an adequate
grounding system. There are three paths for returning current
that need to be considered: Path #1 is between the IXD_504
and its load. Path #2 is between the IXD_504 and its power
supply. Path #3 is between the IXD_504 and whatever logic is
driving it. All three of these paths should be as low in resistance
and inductance as possible, and thus as short as practical. In
addition, every effort should be made to keep these three
ground paths distinctly separate. Otherwise, the returning
ground current from the load may develop a voltage that would
have a detrimental effect on the logic line driving the IXD_504.
OUTPUT LEAD INDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort
should be made to keep the leads between the driver and its
load as short and wide as possible. If the driver must be placed
farther than 0.2” (5mm) from the load, then the output leads
should be treated as transmission lines. In this case, a twisted-
pair should be considered, and the return line of each twisted
pair should be placed as close as possible to the ground pin
of the driver, and connected directly to the ground terminal of the
load.
Supply Bypassing, Grounding Practices And Output Lead inductance
11
IXDF504 / IXDI504 / IXDN504
IXYS Semiconductor GmbH
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: marcom@ixys.de
IXYS Corporation
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
e-mail: sales@ixys.net
www.ixys.com
HE
e
A
A1
B
D
D
C
L
h X 45
H
h
L
E
e
B
C
M
N
M
N
E1
E
eA
L
eB
e
D
D1
c
b3
b2
b
A2
0.018 [0.47]
0.020 [0.51]
0.019 [0.49]
0.039 [1.00]
0.157±0.005 [3.99±0.13]
0.197±0.005 [5.00±0.13]
0.120 [3.05]
0.100 [2.54]
0.137 [3.48]
S0.002^0.000; o S0.05^0.00;o
[]
0.035 [0.90]