CS53L21-DNZ - Cirrus Logic

http://www.cirrus.com

JUL ‘15

Low-Power, Stereo Analog-to-Digital Converter

FEATURES

98-dB dynamic range (A-weighted)

–88-dB THD+N

Analog gain controls

– +32-dB or +16-dB mic preamps

– Analog programmable gain amplifier (PGA)

+20-dB digital boost

Programmable automatic level control (ALC)

– Noise gate for noise suppression

– Programmable threshold and

attack/release rates

Independent left/right channel control

Digital volume control

High-pass filter disable for DC measurements

Stereo 3:1 analog input MUX

Dual mic inputs

– Programmable, low noise mic bias levels

– Differential mic mix for common mode

noise rejection

Very low 64 Fs oversampling clock reduces

power consumption

SYSTEM FEATURES

24-bit conversion

4–96 kHz sample rate

Multibit delta–sigma architecture

Low power operation

– Stereo record (ADC): 8.72 mW @ 1.8 V

– Stereo record (mic to PGA and ADC): 13.73

mW @ 1.8 V

Variable power supplies

– 1.8–2.5-V digital and analog

– 1.8–3.3-V interface logic

Power down management

– ADC, mic preamplifier, PGA

Software Mode (I²C™ and SPI™ control)

Hardware Mode (standalone control)

Flexible clocking options

– Master or slave operation

Digital routing mixes

– Mono mixes

1.8Vto3.3V

Multibit

Oversampling

ADC

Multibit

Oversampling

ADC

SerialAudio

Output

1.8Vto2.5V

MUX

PGA

PCMSerialInterface

Configuration

LevelTranslator

Reset

HardwareMode

orI2C&SPI

SoftwareMode

ControlData StereoInput1

StereoInput2

StereoInput3/

MicInput1&2

PGA

+32 dB

Volume

Controls

ALC

MIC

Bias

MUX

HighPass

Filters

ALC

Digital

Signal

Processing

Engine

CS53L21

2DS700F1

CS53L21

APPLICATIONS

Portable audio players

Digital microphones

Digital voice recorders

Voice recognition systems

Audio/video capture cards

GENERAL DESCRIPTION

The CS53L21 is a highly integrated, 24-bit, 96-kHz, low

power stereo A/D. Based on multibit, delta–sigma mod-

ulation, it allows infinite sample rate adjustment

between 4 kHz and 96 kHz. The ADC offers many fea-

tures suitable for low power, portable system

applications.

The ADC input path allows independent channel control

of a number of features. An input multiplexer selects be-

tween line-level or microphone-level inputs for each

channel. The microphone input path includes a select-

able programmable-gain preamp stage and a low noise

MIC bias voltage supply. A PGA is available for line or

microphone inputs and provides analog gain with soft

ramp and zero cross transitions. The ADC also features

a digital volume attenuator with soft ramp transitions. A

programmable ALC and Noise Gate monitor the input

signals and adjust the volume levels appropriately.

The Signal Processing Engine (SPE) controls left/right

channel volume mixing, channel swap and channel

mute functions. All volume-level changes may be con-

figured to occur on soft ramp and zero cross transitions.

The CS53L21 is available in a 32-pin QFN package in

both Commercial (-10 to +70° C) and Automotive

grades (-40 to +85° C). The CDB53L21 Customer

Demonstration board is also available for device evalu-

ation and implementation suggestions. Please see

“Ordering Information” on page 56 for complete details.

In addition to its many features, the CS53L21 operates

from a low-voltage analog and digital core, making this

A/D ideal for portable systems that require extremely

low power consumption in a minimal amount of space.

DS700F1 3

CS53L21

TABLE OF CONTENTS

1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 6

1.1 Digital I/O Pin Characteristics ........................................................................................................... 8

2. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 9

3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 11

SPECIFIED OPERATING CONDITIONS ............................................................................................. 11

ABSOLUTE MAXIMUM RATINGS .......................................................................................................11

ANALOG CHARACTERISTICS (COMMERCIAL - CNZ) ..................................................................... 12

ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ) ...................................................................... 13

ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 14

SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 14

SWITCHING SPECIFICATIONS - I²C CONTROL PORT ..................................................................... 16

SWITCHING CHARACTERISTICS - SPI CONTROL PORT ................................................................ 17

DC ELECTRICAL CHARACTERISTICS .............................................................................................. 18

DIGITAL INTERFACE SPECIFICATIONS AND CHARACTERISTICS ................................................ 18

POWER CONSUMPTION .................................................................................................................... 19

4. APPLICATIONS ................................................................................................................................... 20

4.1 Overview ......................................................................................................................................... 20

4.1.1 Architecture ........................................................................................................................... 20

4.1.2 Line and MIC Inputs .............................................................................................................. 20

4.1.3 Signal Processing Engine ..................................................................................................... 20

4.1.4 Device Control (Hardware or Software Mode) ...................................................................... 20

4.1.5 Power Management .............................................................................................................. 20

4.2 Hardware Mode .............................................................................................................................. 21

4.3 Analog Inputs .................................................................................................................................. 22

4.3.1 Digital Code, Offset and DC Measurement ........................................................................... 22

4.3.2 High-Pass Filter and DC Offset Calibration ........................................................................... 23

4.3.3 Digital Routing ....................................................................................................................... 23

4.3.4 Differential Inputs .................................................................................................................. 23

4.3.4.1 External Passive Components ................................................................................... 23

4.3.5 Analog Input Multiplexer ........................................................................................................ 24

4.3.6 MIC and PGA Gain ................................................................................................................ 25

4.3.7 Automatic Level Control (ALC) .............................................................................................. 25

4.3.8 Noise Gate ............................................................................................................................ 26

4.4 Signal Processing Engine ............................................................................................................... 27

4.4.1 Volume Controls .................................................................................................................... 27

4.4.2 Mono Channel Mixer ............................................................................................................. 27

4.5 Serial Port Clocking ........................................................................................................................ 28

4.5.1 Slave ..................................................................................................................................... 28

4.5.2 Master ................................................................................................................................... 29

4.5.3 High-Impedance Digital Output ............................................................................................. 29

4.5.4 Quarter- and Half-Speed Mode .............................................................................................29

4.6 Digital Interface Formats ................................................................................................................ 30

4.7 Initialization ..................................................................................................................................... 30

4.8 Recommended Power-Up Sequence ............................................................................................. 30

4.9 Recommended Power-Down Sequence ........................................................................................ 31

4.10 Software Mode ............................................................................................................................. 31

4.10.1 SPI Control .......................................................................................................................... 32

4.10.2 I²C Control ........................................................................................................................... 32

4.10.3 Memory Address Pointer (MAP) .......................................................................................... 33

4.10.3.1 Map Increment (INCR) ............................................................................................. 33

5. REGISTER QUICK REFERENCE ........................................................................................................ 34

6. REGISTER DESCRIPTION .................................................................................................................. 36

4DS700F1

CS53L21

6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 36

6.2 Power Control 1 (Address 02h) ...................................................................................................... 36

6.3 MIC Power Control and Speed Control (Address 03h) ................................................................... 37

6.4 Interface Control (Address 04h) ..................................................................................................... 39

6.5 MIC Control (Address 05h) ............................................................................................................. 40

6.6 ADC Control (Address 06h) ............................................................................................................ 41

6.7 ADCx Input Select, Invert and Mute (Address 07h) ........................................................................ 42

6.8 SPE Control (Address 09h) ............................................................................................................ 43

6.9 ALCX and PGAX Control: ALCA, PGAA (Address 0Ah) and ALCB, PGAB (Address 0Bh) .......... 45

6.10 ADCx Attenuator: ADCA (Address 0Ch) and ADCB (Address 0Dh) ............................................ 46

6.11 ADCx Mixer Volume Control: ADCA (Address 0Eh) and ADCB (Address 0Fh) ........................... 46

6.12 Channel Mixer (Address 18h) ....................................................................................................... 47

6.13 ALC Enable and Attack Rate (Address 1Ch) ................................................................................ 47

6.14 ALC Release Rate (Address 1Dh) ................................................................................................ 48

6.15 ALC Threshold (Address 1Eh) ...................................................................................................... 48

6.16 Noise Gate Configuration and Misc. (Address 1Fh) ..................................................................... 49

6.17 Status (Address 20h) (Read Only) ............................................................................................... 50

7. ANALOG PERFORMANCE PLOTS ....................................................................................................51

7.1 ADC_FILT+ Capacitor Effects on THD+N ...................................................................................... 51

8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 51

8.1 Auto Detect Enabled ....................................................................................................................... 51

8.2 Auto Detect Disabled ...................................................................................................................... 52

9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 52

9.1 Power Supply, Grounding ............................................................................................................... 52

9.2 QFN Thermal Pad .......................................................................................................................... 53

10. DIGITAL FILTERS .............................................................................................................................. 53

11. PARAMETER DEFINITIONS .............................................................................................................. 54

12. PACKAGE DIMENSIONS ................................................................................................................. 55

THERMAL CHARACTERISTICS .......................................................................................................... 55

13. ORDERING INFORMATION ............................................................................................................. 56

14. REFERENCES .................................................................................................................................... 56

15. REVISION HISTORY ......................................................................................................................... 56

LIST OF FIGURES

Figure 1.Typical Connection Diagram (Software Mode) ............................................................................. 9

Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 10

Figure 3.Serial Audio Interface Slave Mode Timing .................................................................................. 15

Figure 4.Serial Audio Interface Master Mode Timing ................................................................................ 15

Figure 5.Control Port Timing - I²C ............................................................................................................. 16

Figure 6.Control Port Timing - SPI Format ................................................................................................ 17

Figure 7.Analog Input Architecture ............................................................................................................ 22

Figure 8.MIC Input Mix w/Common Mode Rejection .................................................................................24

Figure 9.Differential Input .......................................................................................................................... 24

Figure 10.ALC ........................................................................................................................................... 25

Figure 11.Noise Gate Attenuation ............................................................................................................. 26

Figure 12.Signal Processing Engine ......................................................................................................... 27

Figure 13.Master Mode Timing ................................................................................................................. 29

Figure 14.Tri-State Serial Port .................................................................................................................. 29

Figure 15.I²S Format ................................................................................................................................. 30

Figure 16.Left-Justified Format ................................................................................................................. 30

Figure 17.Initialization Flow Chart ............................................................................................................. 31

Figure 18.Control Port Timing in SPI Mode .............................................................................................. 32

Figure 19.Control Port Timing, I²C Write ................................................................................................... 33

Figure 20.Control Port Timing, I²C Read ................................................................................................... 33

DS700F1 5

CS53L21

Figure 21.AIN and PGA Selection ............................................................................................................. 43

Figure 22.ADC THD+N vs. Frequency w/Capacitor Effects ...................................................................... 51

Figure 23.ADC Passband Ripple .............................................................................................................. 53

Figure 24.ADC Stopband Rejection .......................................................................................................... 53

Figure 25.ADC Transition Band ................................................................................................................ 53

Figure 26.ADC Transition Band Detail ...................................................................................................... 53

LIST OF TABLES

Table 1. I/O Power Rails ............................................................................................................................. 8

Table 2. Hardware Mode Feature Summary ............................................................................................. 21

Table 3. MCLK/LRCK Ratios .................................................................................................................... 28

6DS700F1

CS53L21

1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE

Pin Name # Pin Description

LRCK 1Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

SDA/CDIN

(MCLKDIV2) 2

Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDIN is the input data line for the

control port interface in SPI Mode.

MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry.

SCL/CCLK

(I²S/LJ)3

Serial Control Port Clock (Input) - Serial clock for the serial control port.

Interface Format Selection (Input) - Hardware Mode: Selects between I²S and left-Justified interface

formats for the ADC.

AD0/CS

(TSTN) 4

Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS

is the chip-select signal for SPI format.

Test In (Input) - Hardware Mode: This pin is an input used for test purposes only and should be tied to

DGND for normal operation.

VA_PULLUP 5Reference Pull-up (Input) - This pin is an input used for test purposes only and must be pulled-up to VA

using a 47 k resistor.

TSTO 6Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-

nection external to the pin).

AGND 7Analog Ground (Input) - Ground reference for the internal analog section.

TSTO 8Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-

nection external to the pin).

109

11 12 13 14 15 16

262728

303132

CS53L21

DGND

SDOUT (M/S)

MCLK

TSTN

SCLK

TSTO

NIC

AGND

TSTO

FILT+

SDA/CDIN (MCLKDIV2)

SCL/CCLK (I²S/LJ)

AD0/CS (TSTN)

TSTO

RESET

AGND

TSTO

AFILTA

AIN1A

AIN1B

AIN2A

AIN2B/BIAS

MICIN1/AIN3A

MICIN2/BIAS/AIN3B

AFILTB

VA_PULLUP

LRCK

DS700F1 7

CS53L21

TSTO 9Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-

nection external to the pin).

NIC

.Not Internally Connected - This pin is not connected internal to the device and may be connected to

ground or left “floating”. No other external connection should be made to this pin.

VA 12 Analog Power (Input) - Positive power for the internal analog section.

AGND 13 Analog Ground (Input) - Ground reference for the internal analog section.

TSTO 14 Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-

nection external to the pin).

VQ 15 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.

FILT+ 16 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

MICIN1/

AIN3A 17 Microphone Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics specifi-

cation table.

MICIN2/

BIAS/AIN3B 18

Microphone Input 2 (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics

specification table. This pin can also be configured as an output to provide a low noise bias supply for an

external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table.

AIN2A 19 Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification

table.

AIN2B/BIAS 20

Analog Input (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specifi-

cation table. This pin can also be configured as an output to provide a low noise bias supply for an exter-

nal microphone. Electrical characteristics are specified in the DC Electrical Characteristics table.

AFILTA

AFILTB

22 Filter Connection (Output) - Filter connection for the ADC inputs.

AIN1A

AIN1B

Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification

table.

RESET 25 Reset (Input) - The device enters a low power mode when this pin is driven low.

VL 26 Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and

host control port. Refer to the Recommended Operating Conditions for appropriate voltages.

VD 27 Digital Power (Input) - Positive power for the internal digital section.

DGND 28 Digital Ground (Input) - Ground reference for the internal digital section.

SDOUT

(M/S)29

Serial Audio Data Output (Output) - Output for two’s complement serial audio data.

Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between Master and

Slave Mode for the serial port.

MCLK 30 Master Clock (Input) - Clock source for the delta-sigma modulators.

SCLK 31 Serial Clock (Input/Output) -- Serial clock for the serial audio interface.

TSTN 32 Test In (Input) - This pin is an input used for test purposes only and should be tied to DGND for normal

operation.

Thermal Pad -Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page 53.

8DS700F1

CS53L21

1.1 Digital I/O Pin Characteristics

The logic level for each input should not exceed the maximum ratings for the VL power supply.

Pin Name

SW/(HW)

I/O Driver Receiver

RESET Input - 1.8 V - 3.3 V

SCL/CCLK

(I²S/LJ)Input - 1.8 V - 3.3 V, with Hysteresis

SDA/CDIN

(MCLKDIV2) Input/Output 1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, with Hysteresis

AD0/CS

(DEM) Input - 1.8 V - 3.3 V

MCLK Input - 1.8 V - 3.3 V

LRCK Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V

SCLK Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V

SDOUT

(M/S)Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V

Table 1. I/O Power Rails

DS700F1 9

CS53L21

2. TYPICAL CONNECTION DIAGRAMS

Figure 1. Typical Connection Diagram (Software Mode)

1 µF

+1.8 V or +2.5 V

0.1 µF

1 µF

DGND

0.1 µF

+1.8 V, +2.5 V

or +3.3 V

SCL/CCLK

SDA/CDIN

RESET

2 k 

See Note 1

LRCK

AGND

AD0/CS

MCLK

SCLK

* Capacitors must be C0G or equivalent

150 pF

AFILTA

AFILTB

MICIN1

AIN3A Microphone Input

150 pF

SDOUT

CS53L21

2 k 

1 µF

BIAS2

AIN3B/MICIN2

+1.8 V or +2.5 V

AIN1A Left Analog Input 1

1800 pF

100 k

100 

AIN1B Right Analog Input 1

Note 1:

Resistors are required for I²C

control port operation

RLSee Note 3

Note 3: The value of RL is dictated

by the microphone cartridge.

Digital Audio

Processor

0.1 µF

AIN2A Left Analog Input 2

1800 pF

AIN2B

BIAS1 Right Analog Input 2

10 µF

FILT+

Microphone Bias

1 µF

0.1 µF

100 k

100 

100 k

See Note 4

Note 4:

Series resistance in the path of the power supplies must

be avoided.

TSTN

VA_

PULLUP

47 k

10 DS700F1

CS53L21

+1.8V or +2.5V

0.1 µF

1 µF

DGND

0.1 µF

+1.8V, 2.5 V

or +3.3V

I²S/LJ

MCLKDIV2

RESET

LRCK

AGND

DEM

MCLK

SCLK

* Capacitors must be C0G or equivalent

150 pF

AFILTA

AFILTB

150 pF

SDOUT/

M/S

CS53L21

1 µF

+1.8V or +2.5V

AIN1A Left Analog Input 1

1800 pF

100 k

100 

AIN1B Right Analog Input 1

Digital Audio

Processor

0.1 µF

10 µF

FILT+

1 µF

VL or DGND (1)

See Note 4

Note 4:

Ser ies resistance in the path of the power suppli es

(typi cally used for added filter i ng ) m ust be avoi ded .

(1) Pull-up to VL (47 k



for Master Mode .

Pull -down to DGND for Slave Mode .

TSTN

47 k

VA_

PULLUP

Figure 2. Typical Connection Diagram (Hardware Mode)

DS700F1 11

CS53L21

3. CHARACTERISTIC AND SPECIFICATION TABLES

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per-

formance characteristics and specifications are derived from measurements taken at nominal supply voltages and

TA = 25° C.)

SPECIFIED OPERATING CONDITIONS

(AGND=DGND=0 V, all voltages with respect to ground.)

Note:

1. The device will operate properly over the full range of the analog, digital core and serial/control port in-

terface supplies.

ABSOLUTE MAXIMUM RATINGS

(AGND = DGND = 0 V; all voltages with respect to ground.)

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

Notes:

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause

SCR latch-up.

3. The maximum over/under voltage is limited by the input current.

Parameters Symbol Min Max Units

DC Power Supply (Note 1)

Analog Core VA 1.65 2.63 V

Digital Core VD 1.65 2.63 V

Serial/Control Port Interface VL 1.65 3.47 V

Ambient Temperature Commercial - CNZ

Automotive - DNZ TA

-10

-40

+70

+85

C

Parameters Symbol Min Max Units

DC Power Supply Analog

Digital

Serial/Control Port Interface

-0.3

3.0

4.0

Input Current (Note 2) Iin -±10mA

Analog Input Voltage (Note 3) VIN AGND-0.7 VA+0.7 V

Digital Input Voltage

(Note 3) VIND -0.3 VL+ 0.4 V

Ambient Operating Temperature (power applied) TA-50 +115 °C

Storage Temperature Tstg -65 +150 °C

12 DS700F1

CS53L21

ANALOG CHARACTERISTICS (COMMERCIAL - CNZ)

(Test Conditions (unless otherwise specified): Input sine wave (relative to digital full scale): 1 kHz through passive

input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz)

4. Referred to the typical full-scale voltage. Applies to all THD+N and Dynamic Range values in the table.

5. Measured between AINxx and AGND.

VA = 2.5 V (nominal) VA = 1.8 V (nominal)

Parameter (Note 4) Min Typ Max Min Typ Max Unit

Analog In to ADC (PGA bypassed)

Dynamic Range A-weighted

unweighted

Total Harmonic Distortion + Noise -1 dBFS

-20 dBFS

-60 dBFS

-86

-76

-36

-80

-84

-73

-33

-78

Analog In to PGA to ADC

Dynamic Range

PGA Setting: 0 dB A-weighted

unweighted

PGA Setting: +12 dB A-weighted

unweighted

Total Harmonic Distortion + Noise

PGA Setting: 0 dB -1 dBFS

-60 dBFS

-88

-35

-81

-86

-32

-80

PGA Setting: +12 dB -1 dBFS - -85 -79 - -83 -77 dB

Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC

Dynamic Range

PGA Setting: 0 dB A-weighted

unweighted

Total Harmonic Distortion + Noise

PGA Setting: 0 dB -1 dBFS - -76 - - -74 - dB

Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC

Dynamic Range

PGA Setting: 0 dB A-weighted

unweighted

Total Harmonic Distortion + Noise

PGA Setting: 0 dB -1 dBFS - -74 - - -71 - dB

Other Characteristics

DC Accuracy

Interchannel Gain Mismatch -0.2- -0.2-dB

Gain Drift - ±100 - - ±100 - ppm/°C

Offset Error SDOUT Code with HPF On - 352 - - 352 - LSB

Input

Interchannel Isolation -90- -90-dB

Full-scale Input Voltage ADC

PGA (0 dB)

MIC (+16 dB)

MIC (+32 dB)

0.74•VA

0.75•VA

0.78•VA

0.794•VA

0.129•VA

0.022•VA

0.82•VA

0.83•VA

0.74•VA

0.75•VA

0.78•VA

0.794•VA

0.129•VA

0.022•VA

0.82•VA

0.83•VA

Vpp

Input Impedance (Note 5) ADC

PGA

MIC

k

DS700F1 13

CS53L21

ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ)

(Test Conditions (unless otherwise specified): Input sine wave (relative to full scale): 1 kHz through passive input

filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz)

VA = 2.5 V (nominal) VA = 1.8 V (nominal)

Parameter (Note 4) Min Typ Max Min Typ Max Unit

Analog In to ADC

Dynamic Range A-weighted

unweighted

Total Harmonic Distortion + Noise -1 dBFS

-20 dBFS

-60 dBFS

-86

-76

-36

-78

-84

-73

-33

-76

Analog In to PGA to ADC

Dynamic Range

PGA Setting: 0 dB A-weighted

unweighted

PGA Setting: +12 dB A-weighted

unweighted

Total Harmonic Distortion + Noise

PGA Setting: 0 dB -1 dBFS

-60 dBFS

-88

-35

-80

-86

-32

-78

PGA Setting: +12 dB -1 dBFS - -85 -77 - -83 -75 dB

Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC

Dynamic Range

PGA Setting: 0 dB A-weighted

unweighted

Total Harmonic Distortion + Noise

PGA Setting: 0 dB -1 dBFS - -76 - - -74 - dB

Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC

Dynamic Range

PGA Setting: 0 dB A-weighted

unweighted

Total Harmonic Distortion + Noise

PGA Setting: 0 dB -1 dBFS - -74 - - -71 - dB

Other Characteristics

DC Accuracy

Interchannel Gain Mismatch - 0.1 - - 0.1 - dB

Gain Drift - ±100 - - ±100 - ppm/°C

Offset Error SDOUT Code with HPF On - 352 - - 352 - LSB

Input

Interchannel Isolation -90--90-dB

Full-scale Input Voltage ADC

PGA (0 dB)

MIC (+16 dB)

MIC (+32 dB)

0.74•VA

0.75•VA

0.78•VA

0.794•VA

0.129•VA

0.022•VA

0.82•VA

0.83•VA

0.74•VA

0.75•VA

0.78•VA

0.794•VA

0.129•VA

0.022•VA

0.82•VA

0.83•VA

Vpp

Input Impedance (Note 5) ADC

PGA

MIC

k

14 DS700F1

CS53L21

ADC DIGITAL FILTER CHARACTERISTICS

6. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 23 to 26) have

been normalized to Fs and can be denormalized by multiplying the X-axis scale by Fs. HPF parameters

are for Fs = 48 kHz.

SWITCHING SPECIFICATIONS - SERIAL PORT

(Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT CLOAD = 15 pF.)

Parameter (Note 6) Min Typ Max Unit

Passband (Frequency Response) to -0.1 dB corner 0 - 0.46 Fs

Passband Ripple -0.09 - 0.17 dB

Stopband 0.6 - - Fs

Stopband Attenuation 33 - - dB

Total Group Delay - 7.6/Fs - s

High-Pass Filter Characteristics (48 kHz Fs)

Frequency Response -3.0 dB

-0.13 dB

3.7

24.2

Phase Deviation @ 20 Hz -10-Deg

Passband Ripple - - 0.17 dB

Filter Settling Time -10

5/Fs 0 s

Parameters Symbol Min Max Units

RESET pin Low Pulse Width (Note 7) 1-ms

MCLK Frequency 1.024 38.4 MHz

MCLK Duty Cycle (Note 8) 45 55 %

Slave Mode

Input Sample Rate (LRCK) Quarter-Speed Mode

Half-Speed Mode

Single-Speed Mode

Double-Speed Mode

12.5

100

kHz

LRCK Duty Cycle 45 55 %

SCLK Frequency 1/tP-64•F

sHz

SCLK Duty Cycle 45 55 %

LRCK Setup Time Before SCLK Rising Edge ts(LK-SK) 40 - ns

LRCK Edge to SDOUT MSB Output Delay td(MSB) -52ns

SDOUT Setup Time Before SCLK Rising Edge ts(SDO-SK) 20 - ns

SDOUT Hold Time After SCLK Rising Edge th(SK-SDO) 30 - ns

DS700F1 15

CS53L21

7. After powering up the CS53L21, RESET should be held low after the power supplies and clocks are

settled.

8. See “Example System Clock Frequencies” on page 51 for typical MCLK frequencies.

9. See“Master” on page 29.

10. “MCLK” refers to the external master clock applied.

Master Mode (Note 9)

Output Sample Rate (LRCK) All Speed Modes

(Note 10) Fs-Hz

LRCK Duty Cycle 45 55 %

SCLK Frequency 1/tP- 64•FsHz

SCLK Duty Cycle 45 55 %

LRCK Edge to SDOUT MSB Output Delay td(MSB) -52ns

SDOUT Setup Time Before SCLK Rising Edge ts(SDO-SK) 20 - ns

SDOUT Hold Time After SCLK Rising Edge th(SK-SDO) 30 - ns

Parameters Symbol Min Max Units

MCLK

128

-----------------

th(SK-SDO)

MSB MSB-1

LRCK

SCLK

SDOUT

td(MSB)

ts(LK-SK) tP

ts(SDO-SK)

Figure 3. Serial Audio Interface Slave Mode Timing

th(SK-SDO)

MSB MSB-1

LRCK

SCLK

SDOUT

td(MSB)

ts(SDO-SK)

Figure 4. Serial Audio Interface Master Mode Timing

16 DS700F1

CS53L21

SWITCHING SPECIFICATIONS - I²C CONTROL PORT

(Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL=30pF)

11. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

Parameter Symbol Min Max Unit

SCL Clock Frequency fscl - 100 kHz

RESET Rising Edge to Start tirs 500 - ns

Bus Free Time Between Transmissions tbuf 4.7 - µs

Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs

Clock Low time tlow 4.7 - µs

Clock High Time thigh 4.0 - µs

Setup Time for Repeated Start Condition tsust 4.7 - µs

SDA Hold Time from SCL Falling (Note 11) thdd 0-µs

SDA Setup time to SCL Rising tsud 250 - ns

Rise Time of SCL and SDA trc -1µs

Fall Time SCL and SDA tfc - 300 ns

Setup Time for Stop Condition tsusp 4.7 - µs

Acknowledge Delay from SCL Falling tack 300 3450 ns

tbuf thdst thdst

tlow tr

thdd

thigh

tsud tsust

tsusp

Stop Start Start Stop

Repeated

SDA

SCL

tirs

RST

Figure 5. Control Port Timing - I²C

DS700F1 17

CS53L21

SWITCHING CHARACTERISTICS - SPI CONTROL PORT

(Inputs: Logic 0 = DGND, Logic 1 = VL)

12. Data must be held for sufficient time to bridge the transition time of CCLK.

13. For fsck <1 MHz.

Parameter Symbol Min Max Units

CCLK Clock Frequency fsck 06.0MHz

RESET Rising Edge to CS Falling tsrs 20 - ns

CS Falling to CCLK Edge tcss 20 - ns

CS High Time Between Transmissions tcsh 1.0 - s

CCLK Low Time tscl 66 - ns

CCLK High Time tsch 66 - ns

CDIN to CCLK Rising Setup Time tdsu 40 - ns

CCLK Rising to DATA Hold Time (Note 12) tdh 15 - ns

Rise Time of CCLK and CDIN (Note 13) tr2 -100ns

Fall Time of CCLK and CDIN (Note 13) tf2 -100ns

CCLK

CDIN

RST tsrs

tscl

tsch

tcss

tr2

tf2

tcsh

tdsu tdh

Figure 6. Control Port Timing - SPI Format

18 DS700F1

CS53L21

DC ELECTRICAL CHARACTERISTICS

(AGND = 0 V; all voltages with respect to ground.)

14. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage

through electrolytic de-coupling capacitors.

15. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also

increase the PSRR.

DIGITAL INTERFACE SPECIFICATIONS AND CHARACTERISTICS

16. See “Digital I/O Pin Characteristics” on page 8 for serial and control port power rails.

Parameters Min Typ Max Units

VQ Characteristics

Nominal Voltage

Output Impedance

DC Current Source/Sink (Note 14)

0.5•VA

k

A

FILT+ -VA-V

MIC BIAS Characteristics

Nominal Voltage MICBIAS_LVL[1:0] = 00

MICBIAS_LVL[1:0] = 01

MICBIAS_LVL[1:0] = 10

MICBIAS_LVL[1:0] = 11

DC Current Source

Power Supply Rejection Ratio (PSRR) 1 kHz

0.8•VA

0.7•VA

0.6•VA

0.5•VA

Power Consumption (Normal Operation Worse Case) 1 kHz --30mW

Power Supply Rejection Ratio (PSRR) (Note 15) 1 kHz -60-dB

Parameters (Note 16) Symbol Min Max Units

Input Leakage Current Iin -±10A

Input Capacitance -10pF

1.8 V - 3.3 V Logic

High-Level Output Voltage (IOH = -100 A) VOH VL - 0.2 - V

Low-Level Output Voltage (IOL = 100 A) VOL -0.2V

High-Level Input Voltage VIH 0.68•VL - V

Low-Level Input Voltage VIL - 0.32•VL V

DS700F1 19

CS53L21

POWER CONSUMPTION

See (Note 17)

17. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate =

48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and mas-

ter/slave operation.

18. VL current will slightly increase in master mode.

19. RESET pin 25 held LO, all clocks and data lines are held LO.

20. RESET pin 25 held HI, all clocks and data lines are held HI.

Power Control.

Registers

Typical Current (mA)

Operation

02h 03h

Reserved bit 6

Reserved bit 5

PDN_PGAB

PDN_PGAA

PDN_ADCB

PDN_ADCA

PDN

PDN_MICB

PDN_MICA

PDN_MICBIAS

iVA iVD

iVL

(Note 18) Total

Power

(mWrms)

1Off (Note 19) xxxxxxxxxx 1.8 0 0 0 0

2.5 0 0 0 0

2 Standby (Note 20) xxxxxx1xxx 1.8 0.01 0.02 0 0.05

2.5 0.01 0.03 0 0.10

3 Mono Record ADC1111100111 1.8 1.85 2.03 0.03 7.05

2.5 2.07 3.05 0.05 12.94

PGA to ADC 1110100111 1.8 2.35 2.03 0.03 7.95

2.5 2.58 3.08 0.05 14.29

MIC to PGA to ADC

(with Bias)

1110100100 1.8 3.67 2.05 0.03 10.36

2.5 3.95 3.09 0.05 17.71

MIC to PGA to ADC

(no Bias)

1110100101 1.8 3.27 2.03 0.03 9.61

2.5 3.52 3.08 0.05 16.62

4 Stereo Record ADC1111000111 1.8 2.69 2.12 0.03 8.72

2.5 2.93 3.18 0.04 15.40

PGA to ADC 1100000111 1.8 3.65 2.12 0.03 10.45

2.5 3.91 3.17 0.04 17.84

MIC to PGA to ADC

(no Bias)

1100000001 1.8 5.48 2.11 0.03 13.73

2.5 5.76 3.17 0.04 22.45

20 DS700F1

CS53L21

4. APPLICATIONS

4.1 Overview

4.1.1 Architecture

The CS53L21 is a highly integrated, low power, 24-bit audio A/D. The ADC operates at 64Fs, where Fs

is equal to the system sample rate. The different clock rates maximize power savings while maintaining

high performance. The A/D operates in one of four sample rate speed modes: Quarter, Half, Single and

Double. It accepts and is capable of generating serial port clocks (SCLK, LRCK) derived from an input

Master Clock (MCLK).

4.1.2 Line and MIC Inputs

The analog input portion of the A/D allows selection from and configuration of multiple combinations of

stereo and microphone (MIC) sources. Six line inputs with configuration for two MIC inputs (or one MIC

input with common mode rejection), two MIC bias outputs and independent channel control (including a

high-pass filter disable function) are available. A Programmable Gain Amplifier (PGA), MIC boost, and Au-

tomatic Level Control (ALC), with noise gate settings, provide analog gain and adjustment. Digital volume

controls, including gain, boost, attenuation and inversion are also available.

4.1.3 Signal Processing Engine

The ADC data has independent volume controls and mixing functions such as mono mixes and left/right

channel swaps.

4.1.4 Device Control (Hardware or Software Mode)

In Software Mode, all functions and features may be controlled via a two-wire I²C or three-wire SPI control

port interface. In Hardware Mode, a limited feature set may be controlled via stand-alone control pins.

4.1.5 Power Management

Two Software Mode control registers provide independent power-down control of the ADC, PGA, MIC pre-

amp and MIC bias, allowing operation in select applications with minimal power consumption.

DS700F1 21

CS53L21

4.2 Hardware Mode

A limited feature set is available when the A/D powers up in Hardware Mode (see “Recommended Power-

Up Sequence” on page 30) and may be controlled via stand-alone control pins. Table 2 shows a list of func-

tions/features, the default configuration and the associated stand-alone control available.

Hardware Mode Feature/Function Summary

Feature/Function Default Configuration Stand-Alone Control Note

Power Control Device

PGAx

ADCx

MIC Bias

MICx Preamp

Powered Up

Powered Down

Auto-Detect Enabled - -

Speed Mode Serial Port Slave

Serial Port Master

Auto-Detect Speed Mode

Single-Speed Mode --

MCLK Divide (Selectable) “MCLKDIV2” pin 2 see Section

4.5 on page 28

Serial Port Master / Slave Selection (Selectable) “M/S” pin 29 see Section

4.5 on page 28

Interface Control ADC (Selectable) “I²S/LJ” pin 3 see Section

4.6 on page 30

ADC Volume and Gain Digital Boost

Soft Ramp

Zero Cross

Invert

PGAx

Attenuator

ALC

Noise Gate

Disabled

0 dB

Disabled

ADCx High-Pass Filter

ADCx High-Pass Filter Freeze

Enabled

Continuous DC Subtraction --

Line/MIC Input Select AIN1A to PGAA

AIN1B to PGAB --

ADC mix Volume and Gain Invert

Soft Ramp

Zero Cross

Disabled

Enabled

Signal Processing Engine (SPE) MIX Disabled - -

Data Selection (SPE Enable) ADC Data to SPE - -

Channel Swap ADC ADCA = L; ADCB = R - -

Table 2. Hardware Mode Feature Summary

22 DS700F1

CS53L21

4.3 Analog Inputs

AINxA and AINxB are the analog inputs, internally biased to VQ, that accepts line-level and MIC-level sig-

nals, allowing various gain and signal adjustments for each channel.

4.3.1 Digital Code, Offset and DC Measurement

The ADC output data is in two’s complement binary format. For inputs above positive full scale or below

negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the ADC overflow

bit to be set to a ‘1’.

Given the two’s complement format, low-level signals may cause the MSB of the serial data to periodically

toggle between ‘1’ and ‘0’, possibly introducing noise into the system as the bit switches back and forth.

To prevent this phenomena, a constant DC offset is added to the serial data bringing the low-level signal

just above the point at which the MSB would normally toggle, thus reducing the noise introduced. Note

that this offset is not removed (refer to “Analog Characteristics (Commercial - CNZ)” on page 12 and/or

“Analog Characteristics (Automotive - DNZ)” on page 13 for the specified offset level).

The A/D may be used to measure DC voltages by disabling the high-pass filter for the designated channel.

DC levels are measured relative to VQ and will be decoded as positive two’s complement binary numbers

above VQ and negative two’s complement binary numbers below VQ.

Software

Controls: “Status (Address 20h) (Read Only)” on page 50, “ADC Control (Address 06h)” on page 41.

Multibit

Oversampling

ADC

AIN3A/MICIN1

MICA_BOOST

Attenuator

ALC

PGAA_VOL[5:0]

ADC_SNGVOL

0/-96dB

1dB steps

ADCA_ATT[7:0]

ADCA_HPF ENABLE

ADCA_HPF FREEZE

PDN_ADCA

ADCA_MUTE

SOFTA

ALC_ENA

ALCB_SRDIS

ALCB_ZCDIS

PDN_MICA

MICBIAS

PDN_MICBIAS

MICBIAS_LVL[1:0]

PCMSerialInterface

MICBIAS_SEL

TO SIGNAL PROCESSING

ENGINE (SPE)

INV_ADCA

ALC_ARATE[5:0]

ALC_RRATE[5:0]

MAX[2:0]

MIN[2:0]

ALC_ENB

ALCA_SRDIS

ALCA_ZCDIS

MUX

AIN1A

AIN2A

PGA

+16/

32 dB

AINA_MUX[1:0]

PDN_PGAA

+12/-3dB

0.5dB steps

SOFTA

ZCROSSA

Multibit

Oversampling

ADC AIN3B/MICIN2/

MICBIAS

MICB_BOOST

PGAB_VOL[5:0]

ADC_SNGVOL

0/-96dB

1dB steps

ADCB_ATT[7:0]

ADCB_HPF ENABLE

ADCB_HPF FREEZE

PDN_ADCB

ADCB_MUTE

SOFTB

PDN_MICB

INV_ADCB

MUX

AIN1B

AIN2B/MICBIAS

PGA

+16/

32 dB

AINB_MUX[1:0]

PDN_PGAB

+12/-3dB

0.5dB steps

SOFTB

ZCROSSB

NoiseGate NG_ALL

NG_EN

THRESH[3:0]

NGDELAY[1:0]

Attenuator



MUX

MICMIX

MUX

FROM SIGNAL

PROCESSING ENGINE

(SPE)

DIGMIX

+20dB

Digital

Boost

ADCA_DBOOST

+20dB

Digital

Boost

ADCB_DBOOST

Figure 7. Analog Input Architecture

DS700F1 23

CS53L21

4.3.2 High-Pass Filter and DC Offset Calibration

The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation

filter. If the high-pass filter is “frozen” during normal operation, the current value of the DC offset for the

corresponding channel is held. It is this DC offset that will continue to be subtracted from the conversion

result. This feature makes it possible to perform a system DC offset calibration by:

1. Running the A/D with the high-pass filter enabled and the DC offset not “frozen” until the filter settles.

See the Digital Filter Characteristics for filter settling time.

2. Freezing the DC offset.

The high-pass filters are controlled using the ADCx_HPFRZ and ADCx_HPFEN bits.

If a particular ADC channel is used to measure DC voltages, the high-pass filter may be disabled using

the ADCx_HPFEN bit.

4.3.3 Digital Routing

The digital output of the ADC may be internally routed to the Signal Processing Engine (SPE). ADC output

volume may be controlled using the ADCMIX [6:0] bits, and channel swaps can be done using the

ADCA[1:0] and ADCB[1:0] bits. This “processed” ADC data can be selected for output in place of the ADC

output data using the DIGMIX bit.

4.3.4 Differential Inputs

The stereo pair inputs act as a single differential input when the MICMIX bit is enabled. This provides com-

mon mode rejection of noise in digitally intense PCBs, where the microphone signal traverses long traces,

or across long microphone cables as illustrated in Figure 8.

Since the mixer provides a differential combination of the two signals, the potential input mix may exceed

the maximum full-scale input and result in clipping. The level out of the mixer, therefore, is automatically

attenuated 6 dB. Gain may be applied using either the analog PGA or MIC preamp or the digital ADCMIX

volume control to readjust a small signal to desired levels.

The analog inputs may also be used as a differential input pair as illustrated in Figure 9. The two channels

are differentially combined when the MICMIX bit is enabled.

4.3.4.1 External Passive Components

The microphone input is internally biased to VQ. Input signals must be AC coupled using external capaci-

tors with values consistent with the desired high-pass filter design. The MICINx input resistance of 50 kW

may be combined with an external capacitor of 1 mF to achieve the cutoff frequency defined by the equa-

tion,

An electrolytic capacitor must be placed such that the positive terminal is positioned relative to the side with

the greater bias voltage. The MICBIAS voltage level is controlled by the MICBIAS_LVL[1:0] bits.

Software

Controls: “ADC Control (Address 06h)” on page 41.

Software

Controls:

“ADCx Mixer Volume Control: ADCA (Address 0Eh) and ADCB (Address 0Fh)” on page 46, “Inter-

face Control (Address 04h)” on page 39.

fc 1

250 k1 F

----------------------------------------------- 3 . 1 8 H z==

24 DS700F1

CS53L21

The MICBIAS series resistor must be selected based on the requirements of the particular microphone

used. The MICBIAS output pin is selected using the MICBIAS_SEL bit.

4.3.5 Analog Input Multiplexer

A stereo 4-to-1 analog input multiplexer selects between a line-level input source, or a mic-level input

source, depending on the PDN_PGAx and AINx_MUX[1:0] bit settings. Signals may be routed to or by-

passed around the PGA. To conserve power, the PGAs may be powered down allowing the user to select

from multiple line-level sources and route the stereo signal directly to the ADC. When using the MIC pre-

amp, however, the PGA must be powered up.

Analog input channel B may also be used as an output for the MIC bias voltage. The MICBIAS_SEL bit

routes the bias voltage to either of two pins. The multiplexer must then select from the remainder of the

two input channels.

Each ADC, PGA and MIC preamp has an associated input resistance. When selecting between these

paths, the input resistance to the A/D will change accordingly. Refer to the input resistance characteristics

in the Characteristic and Specification Tables for the input resistance of each path.

Software

Controls: “Interface Control (Address 04h)” on page 39, “MIC Control (Address 05h)” on page 40.

Software

Controls:

“Power Control 1 (Address 02h)” on page 36, “MIC Control (Address 05h)” on page 40 “ADCx

Input Select, Invert and Mute (Address 07h)” on page 42.

MICIN1

MICIN2



MICBIAS

Figure 8. MIC Input Mix w/Common Mode Rejection

Full-Scale Differential Input Level (MICMIX=1)

= (AINxA - AINxB) = 3.6 VPP = 1.27 VRMS

AINxA

AINxB

2.15 V

1.25 V

0.35 V

2.5 V

2.15 V

1.25 V

0.35 V

Figure 9. Differential Input

DS700F1 25

CS53L21

4.3.6 MIC and PGA Gain

The MIC-level input passes through a +16 dB or +32 dB analog gain stage prior to the input multiplexer,

allowing it to be used for microphone level signals without the need for any external gain. The PGA must

be powered up when using the MIC preamp.

The PGA stage provides an additional +12 dB to -3 dB of analog gain in 0.5 dB steps.

4.3.7 Automatic Level Control (ALC)

When enabled, the ALC monitors the analog input signal after the digital attenuator, detects when peak

levels exceed the maximum threshold settings and lowers, first, the PGA gain settings and then increases

the digital attenuation levels at a programmable attack rate and maintains the resulting level below the

maximum threshold.

When input signal levels fall below the minimum threshold, digital attenuation levels are decreased first

and the PGA gain is then increased at a programmable release rate and maintains the resulting level

above the minimum threshold.

Attack and release rates are affected by the ADC soft ramp/zero cross settings and sample rate, Fs. ALC

soft ramp and zero cross dependency may be independently enabled/disabled.

Recommended settings: Best level control may be realized with the fastest attack and slowest release

setting with soft ramp enabled in the control registers. Note: 1.) The maximum realized gain must be set

in the PGAx_VOL register. The ALC will only apply the gain set in the PGAx_VOL. 2.) The ALC maintains

the output signal between the MIN and MAX thresholds. As the input signal level changes, the level-con-

trolled output may not always be the same but will always fall within the thresholds.

Software

Controls:

“Power Control 1 (Address 02h)” on page 36, “ADCx Input Select, Invert and Mute (Address 07h)”

on page 42, “ALCX and PGAX Control: ALCA, PGAA (Address 0Ah) and ALCB, PGAB (Address

0Bh)” on page 45, “MIC Control (Address 05h)” on page 40.

Software

Controls:

“ALC Enable and Attack Rate (Address 1Ch)” on page 47, “ALC Release Rate (Address 1Dh)” on

page 48, “ALC Threshold (Address 1Eh)” on page 48, “ALCX and PGAX Control: ALCA, PGAA

(Address 0Ah) and ALCB, PGAB (Address 0Bh)” on page 45.

Output

(after ALC)

Input

RRATE[5:0]

PGA Gain and/or

Attenuator

ALC

MAX[2:0]

ARATE[5:0]

below full scale

MIN[2:0]

below full scale

MIN[2:0]

below full scale

MAX[2:0]

below full scale

ADCx_ATT[7:0] and

PGAx_VOL[4:0] volume

controls should NOT be

adjusted manually when

ALCx is enabled.

Figure 10. ALC

26 DS700F1

CS53L21

4.3.8 Noise Gate

The noise gate may be used to mute signal levels that fall below a programmable threshold. This prevents

the ALC from applying gain to noise. A programmable delay may be used to set the minimum time before

the noise gate attacks the signal.

Maximum noise gate attenuation levels will depend on the gain applied in either the PGA or MIC preamp.

For example: If both +32 dB preamplification and +12 dB programmable gain is applied, the maximum

attenuation that the noise gate achieves will be 52 dB (-96 + 32 + 12) below full-scale.

Ramp-down time to the maximum setting is affected by the SOFTx bit.

Recommended settings: For best results, enable soft ramp for the digital attenuator. When the analog in-

puts are configured for differential signals (see “Differential Inputs” on page 23“Differential Inputs” on

page 23), enable the NG_ALL bit to trigger the noise gate only when both inputs fall below the threshold.

Software

Controls:

“Noise Gate Configuration and Misc. (Address 1Fh)” on page 49, “ADC Control (Address 06h)” on

page 41.

-96 -40

THRESH[2:0]

Maximum Attenuation*

-52 dB

Output

(dB)

Input (dB)

NGEN=1

NGEN=0

-80 dB

-64 dB

Figure 11. Noise Gate Attenuation

DS700F1 27

CS53L21

4.4 Signal Processing Engine

The SPE provides various signal processing functions that apply to the ADC data.

4.4.1 Volume Controls

The digital volume control functions offer independent control over the ADC signal path into the mixer.

The volume controls are programmable to ramp in increments of 0.125 dB at a rate controlled by the soft

ramp/zero cross settings.

The signal paths may also be muted via mute control bits. When enabled, each bit attenuates the signal

to its maximum value. When the mute bit is disabled, the signal returns to the attenuation level set in the

respective volume control register. The attenuation is ramped up and down at the rate specified by the

SPE_SZC[1:0] bits.

4.4.2 Mono Channel Mixer

A channel mixer may be used to create a mix of the left and right channels for the ADC data. This mix

allows the user to produce a MONO signal from a stereo source. The mixer may also be used to imple-

ment a left/right channel swap.

Software

Controls: “SPE Control (Address 09h)” on page 43

Software

Controls: “ADCx Mixer Volume Control: ADCA (Address 0Eh) and ADCB (Address 0Fh)” on page 46

Software

Controls: “Channel Mixer (Address 18h)” on page 47.

VOL

Channel

Swap

+12dB/-51.5dB

0.5dB steps

ADCMIXA_VOL[6:0]

ADCMIXB_VOL[6:0]

MUTE_ADCMIXA

MUTE_ADCMIXB

SIGNAL PROCESSING ENGINE (SPE)

ADCA[1:0]

ADCB[1:0]

INPUTS FROM ADCA

and ADCB

Digital Mix to ADC

Serial Interface

Figure 12. Signal Processing Engine

28 DS700F1

CS53L21

4.5 Serial Port Clocking

The A/D serial audio interface port operates either as a slave or master. It accepts externally generated

clocks in slave mode and will generate synchronous clocks derived from an input master clock (MCLK) in

master mode.

The frequency of the MCLK must be an integer multiple of, and synchronous with, the system sample rate,

Fs. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked

into or out of the device.

The SPEED and MCLKDIV2 software control bits or the SDOUT/(M/S) and MCLKDIV2 stand-alone control

pins, configure the device to generate the proper clocks in Master Mode and receive the proper clocks in

Slave Mode. The value on the SDOUT pin is latched immediately after powering up in Hardware Mode.

4.5.1 Slave

LRCK and SCLK are inputs in Slave Mode. The speed of the A/D is automatically determined based on

the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will then

require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-alone

control pin.

Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed

mode must be selected using the SPEED[1:0] bits.

Software

Control:

“MIC Power Control and Speed Control (Address 03h)” on page 37, “SPE Control

(Address 09h)” on page 43.

Hardware

Control:

Pin Setting Selection

“SDOUT, M/S” pin 29 47 k Pull-down Slave

47 k Pull-up Master

“MCLKDIV2” pin 2

LO No Divide

HI MCLK is divided by 2 prior

to all internal circuitry.

Auto-Detect QSM HSM SSM DSM

Disabled

(Software

Mode only)

512, 768, 1024, 1536,

2048, 3072

256, 384, 512, 768,

1024, 1536

128, 192, 256, 384,

512, 768 128, 192, 256, 384

Enabled 1024, 1536, 2048*,

3072* 512, 768, 1024*, 1536* 256, 384, 512*, 768* 128, 192, 256*, 384*

*MCLKDIV2 must be enabled.

Table 3. MCLK/LRCK Ratios

DS700F1 29

CS53L21

4.5.2 Master

LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled).

In Hardware Mode the A/D operates in single-speed only. In Software Mode, the A/D operates in either

quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.

4.5.3 High-Impedance Digital Output

The serial port may be placed on a clock/data bus that allows multiple masters for the serial port I/O with-

out the need for external buffers. The 3ST_SP bit places the internal buffers for these I/O in a high-imped-

ance state, allowing another device to transmit serial port data without bus contention.

4.5.4 Quarter- and Half-Speed Mode

Quarter-Speed Mode (QSM) and Half-Speed Mode (HSM) allow lower sample rates while maintaining a

relatively flat noise floor in the typical audio band of 20 Hz - 20 kHz. Single-Speed Mode (SSM) will allow

lower frequency sample rates.

÷ 256

÷ 128

÷ 512

LRCK Output

(Equal to Fs)

Single

Speed

Quarter

Speed

Half

Speed

SCLK Output

÷ 2

÷ 1 0

MCLK

MCLKDIV2

÷ 128 00

÷ 4

÷ 2

÷ 8

Single

Speed

Quarter

Speed

Half

Speed

÷ 2 00

Double

Speed

Double

Speed

SPEED[1:0]

Figure 13. Master Mode Timing

CS53L21

Transmitting Device #1 Transmitting Device #2

Receiving Device

3ST_SP

SDOUT

SCLK/LRCK

Figure 14. Tri-State Serial Port

30 DS700F1

CS53L21

4.6 Digital Interface Formats

The serial port operates in standard I²S or Left-Justified digital interface formats with varying bit depths from

16 to 24. Data is clocked out of the ADC or into the SPE on the rising edge of SCLK. Figures 15-16 illustrate

the general structure of each format. Refer to “Switching Specifications - Serial Port” on page 14 for exact

timing relationship between clocks and data.

4.7 Initialization

Figure 17 shows the initialization and power-down sequence. The A/D enters a Power-Down state on initial

power-up. The interpolation and decimation filters, delta-sigma modulators and control port registers are re-

set. The internal voltage reference, ADC and switched-capacitor low-pass filters are powered down.

The device remains in the Power-Down state until RESET is brought high, at which point, the control port

is accessible and the desired register settings can be loaded per the descriptions in Section 4.10. If a valid

write sequence to the control port is not made within approximately 10 ms, the A/D enters Hardware Mode.

Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage reference, FILT+ will begin powering

up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then ap-

plied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a muted

state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the MC-

LK/LRCK frequency ratio and normal operation begins.

4.8 Recommended Power-Up Sequence

1. Hold RESET low until the power supplies are stable.

2. Bring RESET high. After approximately 10 ms, the device will enter Hardware Mode.

3. For Software Mode operation, set the PDN bit to ‘1’b in under 10 ms. This places the device in “standby”.

4. Load the desired register settings while keeping the PDN bit set to ‘1’b.

5. Start MCLK to the appropriate frequency, as discussed in Section 4.5. SCLK may be applied or set to

master at any time; LRCK may only be applied or set to master while the PDN bit is set to 1.

6. Set the PDN bit to ‘0’b.

7. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to

prevent power glitch related issues.

Software

Control: “Interface Control (Address 04h)” on page 39.

Hardware

Control:

Pin Setting Selection

“I²S/LJ” pin 3 LO Left-Justified Interface

HI I²S Interface

LRCK

SCLK

MSB LSB MSB LSB

AOUTA / AINxA

Left Channel Right Channel

SDIN

AOUTB / AINxB

MSB

Figure 15. I²S Format

LRCK

SCLK

MSB LSB MSB LSB

Left Channel Right Channel

SDIN MSB

AOUTA / AINxA AOUTB / AINxB

Figure 16. Left-Justified Format

DS700F1 31

CS53L21

4.9 Recommended Power-Down Sequence

To minimize audible pops when turning off or placing the A/D in standby,

1. Mute the ADCs.

2. Set the PDN bit in the power control register to ‘1’b. The A/D will not power down until it reaches a fully

muted sate. Do not remove MCLK until after the part has fully muted. Note that it may be necessary to

disable the soft ramp and/or zero cross volume transitions to achieve faster muting/power down.

3. Bring RESET low.

4.10 Software Mode

The control port is used to access the registers allowing the A/D to be configured for the desired operational

modes and formats. The operation of the control port may be completely asynchronous with respect to the

audio sample rates. However, to avoid potential interference problems, the control port pins should remain

static if no operation is required.

ADC Initialization

Software Mode

Registers setup to

desired settings.

RESET = Low?

No Power

1. No audio signal

generated.

Off Mode (Power Applied)

1. No audio signal generated.

2. Control Port Registers reset

to default.

Control Port

Active

Control Port Valid

Write Seq. within

10 ms?

Hardware Mode

Minimal feature

set support.

PDN bit = '1'b?

Sub-Clocks Applied

1. LRCK valid.

2. SCLK valid.

3. Audio samples

processed.

Valid

MCLK/LRCK

Ratio?

Yes

Normal Operation

Audio signal generated per control port or stand-

alone settings. PDN bit set to '1'b

(software mode only)

Standby Mode

1. No audio signal generated.

2. Control Port Registers retain

settings.

Reset Transition

1. Pops suppressed.

Power Off Transition

1. Audible pops.

ERROR: Power removed

Valid

MCLK Applied?

20 ms delay

Charge Caps

1. VQ Charged to

quiescent voltage.

2. Filtx+ Charged.

2048 internal

MCLK cycle delay

RESET = Low

Figure 17. Initialization Flow Chart

32 DS700F1

CS53L21

The device enters software mode only after a successful write command using either SPI or I²C protocol,

with the device acting as a slave. The SPI protocol is permanently selected whenever there is a high-to-low

transition on the AD0/CS pin after reset. If using the I²C protocol, pin AD0/CS should be permanently con-

nected to either VL or GND; this option allows the user to slightly alter the chip address as desired.

4.10.1 SPI Control

In Software Mode, CS is the CS53L21 chip-select signal, CCLK is the control port bit clock (input into the

CS53L21 from the microcontroller), CDIN is the input data line from the microcontroller. Data is clocked

in on the rising edge of CCLK. The A/D will only support write operations. Read request will be ignored.

Figure 18 shows the operation of the control port in Software Mode. To write to a register, bring CS low.

The first seven bits on CDIN form the chip address and must be 1001010. The eighth bit is a read/write

indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),

which is set to the address of the register that is to be updated. The next eight bits are the data which will

be placed into the register designated by the MAP.

There is MAP autoincrement capability, enabled by the INCR bit in the MAP register. If INCR is a zero,

the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will autoincrement

after each byte is read or written, allowing block reads or writes of successive registers.

4.10.2 I²C Control

In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.

There is no CS pin. Pin AD0 forms the least significant bit of the chip address and should be connected

through a resistor to VL or DGND as desired. The pin’s state is sensed while the CS53L21 is being reset.

The signal timings for a read and write cycle are shown in Figure 19 and Figure 20. A Start condition is

defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while

the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the

CS53L21 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low

for a write). The upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a

CS53L21, the chip address field, which is the first byte sent to the CS53L21, should match 100101 fol-

lowed by the setting of the AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write,

the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the

operation is a read, the contents of the register pointed to by the MAP will be output. Setting the autoin-

crement bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by

an acknowledge bit. The ACK bit is output from the CS53L21 after each input byte is read and is input to

the CS53L21 from the microcontroller after each transmitted byte.

4 5 6 7

CCLK

CHIP ADDRESS (WRITE) MAP BYTE DATA

1 0 0 1 0 1 0 0

CDIN INCR 6 5 4 3 2 1 0 7 6 1 0

0 1 2 3 8 9 12 16 1710 11 13 14 15

DATA +n

7 6 1 0

Figure 18. Control Port Timing in SPI Mode

DS700F1 33

CS53L21

Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown

in Figure 20, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-

dition. The following pseudocode illustrates an aborted write operation followed by a read operation.

Send start condition.

Send 100101x0 (chip address and write operation).

Receive acknowledge bit.

Send MAP byte, autoincrement off.

Receive acknowledge bit.

Send stop condition, aborting write.

Send start condition.

Send 100101x1 (chip address and read operation).

Receive acknowledge bit.

Receive byte, contents of selected register.

Send acknowledge bit.

Send stop condition.

Setting the autoincrement bit in the MAP allows successive reads or writes of consecutive registers. Each

byte is separated by an acknowledge bit.

4.10.3 Memory Address Pointer (MAP)

The MAP byte comes after the address byte and selects the register to be read or written. Refer to the

pseudo code above for implementation details.

4.10.3.1 Map Increment (INCR)

The device has MAP autoincrement capability enabled by the INCR bit (the MSB) of the MAP. If INCR is

set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP

will autoincrement after each byte is read or written, allowing block reads or writes of successive registers.

4 5 6 7 24 25

SCL

CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1

START

ACK

STOP

ACKACKACK

1 0 0 1 0 1 AD0 0

SDA INCR 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0

0 1 2 3 8 9 12 16 17 18 1910 11 13 14 15 27 28

DATA +n

Figure 19. Control Port Timing, I²C Write

SCL

CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1

START

ACK

STOP

ACK

1 0 0 1 0 1 AD0 0

SDA 1 0 0 1 0 1 AD0 1

CHIP ADDRESS (READ)

START

INCR 6 5 4 3 2 1 0 7 0 7 0 7 0

168 9 12 13 14 154 5 6 7 0 1 20 21 22 23 24 26 27 28

2 3 10 11 17 18 19 25

ACK

DATA + n

STOP

Figure 20. Control Port Timing, I²C Read

34 DS700F1

CS53L21

5. REGISTER QUICK REFERENCE

Software mode register defaults are as shown. “Reserved” registers must maintain their default state.

AddrFunction7 6543210

01h ID Chip_ID4 Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID2 Rev_ID1 Rev_ID0

p36

default

1 1011001

02h Power Ctl. 1 Reserved Reserved Reserved PDN_PGAB PDN_PGAA PDN_ADCB PDN_ADCA PDN

p36

default

0 1(See Note 2

on page 36)

1(See Note 2

on page 36)

00000

03h Speed Ctl. &

Power Ctl. 2

AUTO SPEED1 SPEED0 3-ST_SP PDN_MICB PDN_MICA PDN_

MICBIAS

MCLKDIV2

p37

default

1 0101110

04h Interface Ctl. Reserved M/S Reserved Reserved Reserved ADC_I²S/LJ DIGMIX MICMIX

p39

default

0 0000000

05h MIC Control

& Misc.

ADC_SNGVOL ADCB_

DBOOST

ADCA_

DBOOST

MICBIAS_

SEL

MICBIAS_

LVL1

MICBIAS_

LVL0

MICB_

BOOST

MICA_

BOOST

p40

default

0 0000000

06h ADC Control ADCB_HPF

ADCB_HP

FRZ

ADCA_HPF

ADCA_HP

FRZ

SOFTB ZCROSSB SOFTA ZCROSSA

p41

default

1 0100000

07h ADC Input

Select, Invert,

Mute

AINB_MUX1 AINB_MUX0 AINA_MUX1 AINA_MUX0 INV_ADCB INV_ADCA ADCB_

MUTE

ADCA_

MUTE

p42

default

0 0000000

08h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

default

0 1100000

09h SPE Control Reserved SPE_

ENABLE

FREEZE Reserved Reserved Reserved SPE_SZC1 SPE_SZC0

p43

default

0 0000110

0Ah ALCA SZC &

PGAA Vol-

ume

ALCA_SR

DIS

ALCA_ZC

DIS

Reserved PGAA

VOL4

PGAA

VOL3

PGAA

VOL2

PGAA

VOL1

PGAA

VOL0

p45

default

0 0000000

0Bh ALCB SZC &

PGAB Vol-

ume

ALCB_SR

DIS

ALCB_ZC

DIS

Reserved PGAB

VOL4

PGAB

VOL3

PGAB

VOL2

PGAB

VOL1

PGAB

VOL0

p45

default

0 0000000

0Ch ADCA Atten-

uator

ADCA_

ATT7

ADCA_

ATT6

ADCA_

ATT5

ADCA_

ATT4

ADCA_

ATT3

ADCA_

ATT2

ADCA_

ATT1

ADCA_

ATT0

p46

default

0 0000000

0Dh ADCB Atten-

uator

ADCB_

ATT7

ADCB_

ATT6

ADCB_

ATT5

ADCB_

ATT4

ADCB_

ATT3

ADCB_

ATT2

ADCB_

ATT1

ADCB_

ATT0

p46

default

0 0000000

0Eh Vol. Control

ADCMIXA

MUTE_ADC

MIXA

ADCMIXA

VOL6

ADCMIXA

VOL5

ADCMIXA

VOL4

ADCMIXA

VOL3

ADCMIXA

VOL2

ADCMIXA

VOL1

ADCMIXA

VOL0

p46

default

1 0000000

0Fh Vol. Control

ADCMIXB

MUTE_ADC

MIXB

ADCMIXB

VOL6

ADCMIXB

VOL5

ADCMIXB

VOL4

ADCMIXB

VOL3

ADCMIXB

VOL2

ADCMIXB

VOL1

ADCMIXB

VOL0

p46

default

1 0000000

DS700F1 35

CS53L21

10h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

default

1 0000000

11h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

default

1 0000000

12h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

default

0 0000000

13h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

default

0 0000000

14h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

default

0 0000000

15h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

default

1 0001000

16h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

default

0 0000000

17h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

default

0 0000000

18h ADC Chan-

nel Mixer

Reserved Reserved Reserved Reserved ADCA1 ADCA0 ADCB1 ADCB0

p47

default

0 0000000

19h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

default

0 0000000

1Ah Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

default 0 1111111

1Bh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

default

0 0000000

1Ch ALC Enable

& Attack Rate

ALC_ENB ALC_ENA ALC_A-

RATE5

AAL-

C_RATE4

ALC_A-

RATE3

ALC_A-

RATE2

ALC_A-

RATE1

ALC_A-

RATE0

p47

default

0 0000000

1Dh ALC Release

Rate

Reserved Reserved ALC_R-

RATE5

ALC_R-

RATE4

ALC_R-

RATE3

ALC_R-

RATE2

ALC_R-

RATE1

ALC_R-

RATE0

p48

default

0 0111111

1Eh ALC Thresh-

old

MAX2 MAX1 MAX0 MIN2 MIN1 MIN0 Reserved Reserved

p48

default

0 0000000

1Fh Noise Gate

Config

NG_ALL NG_EN NG_BOOST THRESH2 THRESH1 THRESH0 NGDELAY1 NGDELAY0

p49

default

0 0000000

20h Status Reserved SP_CLK

ERR

SPEB_OVFL SPEA_OVFL PCMA_OVFL PCMB_OVFL ADCA_OVFL ADCB_OVFL

p50

default

0 0000000

21h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

default

0 1010000

AddrFunction7 6543210

36 DS700F1

CS53L21

6. REGISTER DESCRIPTION

All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are

read only. See the following bit definition tables for bit assignment information. The default state of each bit after a

power-up sequence or reset is listed in each bit description.

All “Reserved” registers must maintain their default state.

6.1 Chip I.D. and Revision Register (Address 01h) (Read Only)

Chip I.D. (Chip_ID[4:0])

Default: 11011

Function:

I.D. code for the CS53L21. Permanently set to 11011.

Chip Revision (Rev_ID[2:0])

Default: 001

Function:

CS53L21 revision level. Revision B is coded as 001. Revision A is coded as 000.

6.2 Power Control 1 (Address 02h)

Notes:

1. To activate the power-down sequence for individual channels (A or B,) both channels must first be pow-

ered down either by enabling the PDN bit or by enabling the power-down bits for both channels. En-

abling the power-down bit on an individual channel basis after the A/D has fully powered up will mute

the selected channel without achieving any power savings.

2. Reserved bits 5 and 6 should always be set “high” by the user to minimize power consumption during

normal operation.

Recommended channel power-down sequence: 1.) Enable the PDN bit, 2.) enable power-down for the se-

lect channels, 3.) disable the PDN bit.

76543210

Chip_ID4 Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID2 Rev_ID1 Rev_ID0

76543210

Reserved Reserved Reserved PDN_PGAB PDN_PGAA PDN_ADCB PDN_ADCA PDN

DS700F1 37

CS53L21

Power Down PGA X (PDN_PGAX)

Default: 0

0 - Disable

1 - Enable

Function:

PGA channel x will either enter a power-down or muted state when this bit is enabled. See Power Control

1 (Address 02h) Note 1 above.

This bit is used in conjunction with AINx_MUX bits to determine the analog input path to the ADC. Refer to

“ADCX Input Select Bits (AINX_MUX[1:0])” on page 42 for the required settings.

Power Down ADC X (PDN_ADCX)

Default: 0

0 - Disable

1 - Enable

Function:

ADC channel x will either enter a power-down or muted state when this bit is enabled. See Note 1 on page

36.

Power Down (PDN)

Default: 0

0 - Disable

1 - Enable

Function:

The entire A/D will enter a low-power state when this function is enabled. The contents of the control port

registers are retained in this mode.

6.3 MIC Power Control and Speed Control (Address 03h)

Auto-Detect Speed Mode (AUTO)

Default: 1

0 - Disable

1 - Enable

Function:

Enables the autodetect circuitry for detecting the speed mode of the A/D when operating as a slave. When

AUTO is enabled, the MCLK/LRCK ratio must be implemented according to Table 3 on page 28. The

SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio.

76543210

AUTO SPEED1 SPEED0 3-ST_SP PDN_MICB PDN_MICA PDN_MICBIAS MCLKDIV2

38 DS700F1

CS53L21

Speed Mode (SPEED[1:0])

Default: 01

11 - Quarter-Speed Mode (QSM) - 4 to 12.5 kHz sample rates

10 - Half-Speed Mode (HSM) - 12.5 to 25 kHz sample rates

01 - Single-Speed Mode (SSM) - 4 to 50 kHz sample rates

00 - Double-Speed Mode (DSM) - 50 to 100 kHz sample rates

Function:

Sets the appropriate speed mode for the A/D in Master or Slave Mode. QSM is optimized for 8 kHz sample

rate and HSM is optimized for 16 kHz sample rate. These bits are ignored when the AUTO bit is enabled

(see Auto-Detect Speed Mode (AUTO) above).

Tri-State Serial Port Interface (3ST_SP)

Default: 0

0 - Disable

1 - Enable

Function:

When enabled and the device is configured as a master, all serial port outputs (clocks and data) are placed

in a high impedance state. If the serial port is configured as a slave, only the SDOUT pin will be placed in a

high-impedance state. The other signals will remain as inputs.

Power Down MIC X (PDN_MICX)

Default: 1

0 - Disable

1 - Enable

Function:

When enabled, the microphone preamp for channel x will be in a power-down state.

Power Down MIC BIAS (PDN_MICBIAS)

Default: 1

0 - Disable

1 - Enable

Function:

When enabled, the microphone bias circuit will be in a power-down state.

MCLK Divide By 2 (MCLKDIV2)

Default: 0

0 - Disabled

1 - Divide by 2

Function:

Divides the input MCLK by 2 prior to all internal circuitry. This bit is ignored when the AUTO bit is disabled

in Slave Mode.

DS700F1 39

CS53L21

6.4 Interface Control (Address 04h)

Master/Slave Mode (M/S)

Default: 0

0 - Slave

1 - Master

Function:

Selects either master or slave operation for the serial port.

ADC I²S or Left-Justified (ADC_I²S/LJ)

Default: 0

0 - Left-Justified

1 - I²S

Function:

Selects either the I²S or Left-Justified digital interface format for the data on SDOUT. The required relation-

ship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and

the options are detailed in this section “Digital Interface Formats” on page 30.

Digital Mix (DIGMIX)

Default: 0

Function:

Routes the ADC outputs to the serial port SDOUT pin. DIGMIX selects either “raw” ADC data or SPE pro-

cessed ADC data to SDOUT. Note: If DIGMIX = 1, SPE_ENABLE must be 1 for the SPE to be functional.

Microphone Mix (MICMIX)

Default: 0

0 - Disabled; No Mix: Left/Right Channel to ADC serial port, SDOUT.

1 - Enabled; Mix: Differential mix ((A-B)/2)to ADC serial port, SDOUT.

Function:

Selects between the ADC stereo mix or a differential mix of analog inputs A and B.

76543210

Reserved M/S Reserved Reserved Reserved ADC_I²S/LJ DIGMIX MICMIX

DIGMIX SPE_ENABLE Mix Selected

0 x ADC data to ADC serial port, SDOUT data.

10 Reserved

1 SPE Processed ADC data to ADC serial port, SDOUT data.

40 DS700F1

CS53L21

6.5 MIC Control (Address 05h)

ADC Single Volume Control (ADC_SNGVOL)

Default: 0

0 - Disabled

1 - Enabled

Function:

The individual PGA Volume (PGAx_VOLx) and ADC channel attenuation (ADCx_ATTx) levels as well as

the ALC A and B enable (ALC_ENx) are independently controlled by their respective control registers when

this function is disabled. When enabled, the volume on both channels is determined by the ADCA Attenuator

Control register, or the PGAA Control register, and the ADCB Attenuator and PGAB Control registers are

ignored. The ALC enable control for channel B is controlled by the ALC A enable when the ADC_SNGVOL

bit is enabled and the ALC_ENB control register is ignored.

ADCx 20 dB Digital Boost (ADCx_DBOOST)

Default: 0

0 - Disabled

1 - Enabled

Function:

Applies a 20 dB digital gain to the input signal on ADC channel x, regardless of the input path.

MIC Bias Select (MICBIAS_SEL)

Default: 0

0 - MICBIAS on AIN3B/MICIN2 pin

1 - MICBIAS on AIN2B pin

Function:

Determines the output pin for the internally generated MICBIAS signal. If set to ‘0’b, the MICBIAS is output

on the AIN3B/MICIN2 pin. If set to ‘1’b, the MICBIAS is output on the AIN2B pin.

MIC Bias Level (MICBIAS_LVL[1:0])

Default: 00

00 - 0.8 x VA

01 - 0.7 x VA

10 - 0.6 x VA

11 - 0.5 x VA

Function:

Determines the output voltage level of the MICBIAS output.

76543210

ADC_SNGVOL ADCB_DBOOST ADCA_DBOOST MICBIAS_SEL MICBIAS_LVL1 MICBIAS_LVL0 MICB_BOOST MICA_BOOST

DS700F1 41

CS53L21

MIC X Preamplifier Boost (MICX_BOOST)

Default: 0

0 - +16 dB Gain

1 - +32 dB Gain

Function:

Determines the amount of gain applied to the microphone preamplifier for channel x.

6.6 ADC Control (Address 06h)

ADCX High-Pass Filter Enable (ADCX_HPFEN)

Default: 1

0 - High-pass filter is disabled

1 - High-pass filter is enabled

Function:

When this bit is set, the internal high-pass filter will be enabled for ADCx. When set to ‘0’, the high-pass filter

will be disabled. For DC measurements, this bit must be cleared to ‘0’. “ADC Digital Filter Characteristics”

on page 14.

ADCX High-Pass Filter Freeze (ADCX_HPFRZ)

Default: 0

0 - Continuous DC Subtraction

1 - Frozen DC Subtraction

Function:

The high-pass filter works by continuously subtracting a measure of the DC offset from the output of the

decimation filter. If the ADCx_HPFRZ bit is taken high during normal operation, the current value of the DC

offset is frozen, and this DC offset will continue to be subtracted from the conversion result. For DC mea-

surements, this bit must be set to ‘1’. See “ADC Digital Filter Characteristics” on page 14.

Soft Ramp CHX Control (SOFTX)

Default: 0

0 - Disabled

1 - Enabled

Function:

Soft Ramp allows level changes to be implemented via an incremental ramp. ADCx_ATT[7:0] digital atten-

uation changes are ramped from the current level to the new level at a rate of 0.125 dB per LRCK period.

PGAx_VOL[4:0] gain changes are ramped in 0.5 dB steps every 16 LRCK periods.

Soft Ramp and Zero Cross Enabled

When used in conjunction with the ZCROSSx bit, the PGAx_VOL[4:0] gain changes will occur in 0.5 dB

steps and be implemented on a signal zero crossing.

76543210

ADCB_HPFEN ADCB_HPFRZ ADCA_HPFEN ADCA_HPFRZ SOFTB ZCROSSB SOFTA ZCROSSA

42 DS700F1

CS53L21

Zero Cross CHX Control (ZCROSSX)

Default: 0

0 - Disabled

1 - Enabled

Function:

Zero Cross Enable dictates that signal level changes will occur on a signal zero crossing to minimize audible

artifacts. The requested level change will occur after a timeout period of 1024 sample periods (approximate-

ly 10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function

is independently monitored and implemented for each channel.

Soft Ramp and Zero Cross Enabled

When used in conjunction with the SOFTx bit, the PGAx_VOL[4:0] gain changes will occur in 0.5 dB steps

and be implemented on a signal zero crossing.

The ADC Attenuator ADCx_ATT[7:0] is not affected by the ZCROSSx bit.

6.7 ADCx Input Select, Invert and Mute (Address 07h)

ADCX Input Select Bits (AINX_MUX[1:0])

Default: 00

Function:

Selects the specified analog input signal into ADCx. The microphone preamp is only available when PD-

N_PGAx is disabled. See Figure 21.

SOFTx ZCROSSx Analog PGA Volume

(PGAx_VOL[4:0])

Digital Attenuator (ADCx_ATT[7:0])

Volume changes immediately. Volume changes immediately.

Volume changes at next zero cross time. Volume changes immediately.

Volume changes in 0.5 dB steps. Change volume in 0.125 dB steps.

Volume changes in 0.5 dB steps at every

signal zero-cross. Change volume in 0.125 dB steps.

76543210

AINB_MUX1 AINB_MUX0 AINA_MUX1 AINA_MUX0 INV_ADCB INV_ADCA ADCB_MUTE ADCA_MUTE

PDN_PGAx AINx_MUX[1:0] Selected Path to ADC

0 00 AIN1x-->PGAx

0 01 AIN2x-->PGAx

0 10 AIN3x/MICINx-->PGAx

0 11 AIN3x/MICINx-->Pre-Amp(+16/+32 dB Gain)-->PGAx

100AIN1x

101AIN2x

1 10 AIN3x/MICINx

1 11 Reserved

DS700F1 43

CS53L21

ADCX Invert Signal Polarity (INV_ADCX)

Default: 0

0 - Disabled

1 - Enabled

Function:

When enabled, this bit will invert the signal polarity of the ADC x channel.

ADCX Channel Mute (ADCX_MUTE)

Default: 0

0 - Disabled

1 - Enabled

Function:

The output of channel x ADC will mute when enabled. The muting function is affected by the ADCx Soft bit

(SOFT).

6.8 SPE Control (Address 09h)

SPE_ENABLE

Default: 0

0 - Reserved

1 - ADC Serial Port to SPE

Function:

Selects the digital signal source for the SPE. Note: If DIGMIX = 1, SPE_ENABLE must be 1 for the SPE to

be functional.

Freeze Controls (FREEZE)

Default: 0

Function:

76543210

Reserved SPE_ENABLE FREEZE Reserved Reserved Reserved SPE_SZC1 SPE_SZC0

MUX

AIN1x

AIN2x

AIN3x/MICINx

PGA

+16/

32 dB

MUX

AINx_MUX[1:0]

PDN_PGAx

AIN1x

AIN2x

AIN3x

Decoder

ADC

Figure 21. AIN and PGA Selection

44 DS700F1

CS53L21

This function will freeze the previous settings of, and allow modifications to be made to all control port reg-

isters without the changes taking effect until the FREEZE is disabled. To have multiple changes in the con-

trol port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then

disable the FREEZE bit.

Note:

1. This bit should only be used to synchronize run-time controls, such as volume and mute, during normal

operation. Using this bit before the relevant circuitry begins normal operation could cause the change

to take effect immediately, ignoring the FREEZE bit.

SPE Soft Ramp and Zero Cross Control (SPE_SZC[1:0])

Default = 10

00 - Immediate Change

01 - Zero Cross

10 - Soft Ramp

11 - Soft Ramp on Zero Crossings

Function:

Note: The SPE_ENABLE bits in reg09h must be set to 1 to enable function control

Immediate Change

When Immediate Change is selected all volume-level changes will take effect immediately in one step.

Zero Cross

This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will

occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a

timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate) if the

signal does not encounter a zero crossing. The zero cross function is independently monitored and imple-

mented for each channel. Note: The LIM_SRDIS bit is ignored.

Soft Ramp

Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implemented

by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 0.5 dB per 4

left/right clock periods.

Soft Ramp on Zero Crossing

This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will

occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur

after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if

the signal does not encounter a zero crossing. The zero cross function is independently monitored and im-

plemented for each channel. Note: The LIM_SRDIS bit is ignored.

DS700F1 45

CS53L21

6.9 ALCX and PGAX Control: ALCA, PGAA (Address 0Ah) and ALCB, PGAB (Address

0Bh)

ALCX Soft Ramp Disable (ALCX_SRDIS)

Default: 0

0 - Off

1 - On

Function:

Overrides the SOFTx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not be

dictated by the soft ramp setting. ALC volume-level changes will take effect in one step.

ALCX Zero Cross Disable (ALCX_ZCDIS)

Default: 0

0 - Off

1 - On

Function:

Overrides the ZCROSSx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not

be dictated by the zero cross setting. ALC volume-level changes will take effect immediately in one step.

PGA X Gain Control (PGAX_VOL[4:0])

Default: 00000

Function:

The PGAx Gain Control register allows independent setting of the signal levels in 0.5 dB increments as dic-

tated by the ADCx Soft and Zero Cross bits (SOFTx and ZCROSSx) from +12 dB to -3 dB. Gain settings

are decoded as shown in the table above. The gain changes are implemented as dictated by the ALCX Soft

and Zero Cross bits (ALCX_SRDIS and ALCX_ZCDIS).

Note: When the ALC is enabled, the PGA is automatically controlled and should not be adjusted manu-

ally.

76543210

ALCX_SRDIS ALCX_ZCDIS Reserved PGAX_VOL4 PGAX_VOL3 PGAX_VOL2 PGAX_VOL1 PGAX_VOL0

Binary Code Volume Setting

11000 +12 dB

··· ···

01010 +5 dB

··· ···

00000 0 dB

11111 -0.5 dB

11110 -1 dB

··· ···

11001 -3 dB

11010 -3 dB

46 DS700F1

CS53L21

6.10 ADCx Attenuator: ADCA (Address 0Ch) and ADCB (Address 0Dh)

ADCX Attenuation Control (ADCX_ATT[7:0])

Default: 00h

Function:

The level of ADCX can be adjusted in 1.0 dB increments as dictated by the ADCx Soft and Zero Cross bits

(SOFTx and ZCROSSx) from 0 to -96 dB. Levels are decoded in two’s complement, as shown in the table

above.

Note: When the ALC is enabled, the Attenuator and PGA volume is automatically controlled and should

not be adjusted manually.

6.11 ADCx Mixer Volume Control: ADCA (Address 0Eh) and ADCB (Address 0Fh)

Note: The SPE_ENABLE bit in reg09h must be set to 1 to enable function control in this register.

ADCX Mixer Channel Mute (MUTE_ADCMIXX)

Default: 1

0 - Disabled

1 - Enabled

Function:

The ADC channel X input to the output mixer will mute when enabled. The muting function is affected by

the SPEX Soft and Zero Cross bits (SPEX_SZC[1:0]).

ADCX Mixer Volume Control (ADCMIXX_VOL[6:0])

Default = 000 0000

76543210

ADCx_ATT7 ADCx_ATT6 ADCx_ATT5 ADCx_ATT4 ADCx_ATT3 ADCx_ATT2 ADCx_ATT1 ADCx_ATT0

Binary Code Volume Setting

0111 1111 0 dB

··· ···

0000 0000 0 dB

1111 1111 -1 dB

1111 1110 -2 dB

··· ···

1010 0000 -96 dB

··· ···

1000 0000 -96 dB

7 6543210

MUTE_ADCMIXx ADCMIXx_VOL6 ADCMIXx_VOL5 ADCMIXx_VOL4 ADCMIXx_VOL3 ADCMIXx_VOL2 ADCMIXx_VOL1 ADCMIXx_VOL0

Binary Code Volume Setting

001 1000 +12.0 dB

··· ···

000 0000 0 dB

111 1111 -0.5 dB

111 1110 -1.0 dB

··· ···

DS700F1 47

CS53L21

Function:

The level of the ADCX input to the output mixer can be adjusted in 0.5 dB increments as dictated by the

SPEX Soft and Zero Cross bits (SPE_SZC[1:0]) from +12 to -51.5 dB. Levels are decoded as shown in the

table above.

6.12 Channel Mixer (Address 18h)

Note: The SPE_ENABLE bits in reg09h must be set to 1 to enable function control in this register.

Channel Mixer (ADCx[1:0])

Default: 00

Function:

Implements mono mixes of the left and right channels as well as a left/right channel swap.

6.13 ALC Enable and Attack Rate (Address 1Ch)

ALC Enable (ALC_ENX)

Default: 0

0 - Disabled

1 - Enabled

Function:

Enables automatic level control for ADC channel x.

Notes:

1. When the ALC is enabled, the Attenuator and PGA volume is automatically controlled and should not

be adjusted manually.

2. The ALC should only be configured while the power down bit is enabled.

001 1001 -51.5 dB

76543210

Reserved Reserved Reserved Reserved ADCA1 ADCA0 ADCB1 ADCB0

ADCA[1:0] SDOUT ADCB[1:0] SDOUT

00 L 00 R

01 01

10 10

11 R 11 L

76543210

ALC_ENB ALC_ENA ALC_ARATE5 ALC_ARATE4 ALC_ARATE3 ALC_ARATE2 ALC_ARATE1 ALC_ARATE0

Binary Code Volume Setting

LR+

------------

LR+

------------

48 DS700F1

CS53L21

ALC Attack Rate (ARATE[5:0])

Default: 000000

Function:

Sets the rate at which the ALC attenuates the analog input from levels above the maximum setting in the

ALC threshold register.

The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the SOFTx

and ZCROSSx bit settings unless the disable bit for each function is enabled.

6.14 ALC Release Rate (Address 1Dh)

ALC Release Rate (RRATE[5:0])

Default: 111111

Function:

Sets the rate at which the ALC releases the PGA and digital attenuation from levels below the minimum

setting in the ALC threshold register, and returns the input level to the PGA_VOL[4:0] and ADCx_ATT[7:0]

setting. The ALC release rate is user selectable, but is also a function of the sampling frequency, Fs, and

the SOFTx and ZCROSS bit settings unless the disable bit for each function is enabled.

6.15 ALC Threshold (Address 1Eh)

Maximum Threshold (MAX[2:0])

Default: 000

Binary Code Attack Time

000000 Fastest Attack

··· ···

111111 Slowest Attack

76543210

Reserved Reserved ALC_RRATE5 ALC_RRATE4 ALC_RRATE3 ALC_RRATE2 ALC_RRATE1 ALC_RRATE0

Binary Code Release Time

000000 Fastest Release

··· ···

111111 Slowest Release

76543210

MAX2 MAX1 MAX0 MIN2 MIN1 MIN0 Reserved Reserved

MAX[2:0] Threshold Setting (dB)

000 0

001 -3

010 -6

011 -9

100 -12

101 -18

110 -24

111 -30

DS700F1 49

CS53L21

Function:

Sets the maximum level, relative to full scale, at which to limit and attenuate the input signal at the attack

rate.

Minimum Threshold (MIN[2:0])

Default: 000

Function:

Sets the minimum level at which to disengage the ALC’s attenuation or amplify the input signal at a rate set

in the release rate register until levels again reach this minimum threshold. The ALC uses this minimum as

a hysteresis point for the input signal as it maintains the signal below the maximum as well as below the

minimum setting. This provides a more natural sound as the ALC attacks and releases.

6.16 Noise Gate Configuration and Misc. (Address 1Fh)

Noise Gate Channel Gang (NG_ALL)

Default: 0

0 - Disabled

1 - Enabled

Function:

Gangs the noise gate function for channel A and B. When enabled, both channels must fall below the thresh-

old setting for the noise gate attenuation to take effect.

Noise Gate Enable (NG_EN)

Default: 0

0 - Disabled

1 - Enabled

Function:

Enables the noise gate. Maximum attenuation is relative to all gain settings applied.

MIN[2:0] Threshold Setting (dB)

000 0

001 -3

010 -6

011 -9

100 -12

101 -18

110 -24

111 -30

76543210

NG_ALL NG_EN NG_BOOST THRESH2 THRESH1 THRESH0 NGDELAY1 NGDELAY0

50 DS700F1

CS53L21

Noise Gate Boost (NG_BOOST) and Threshold (THRESH[3:0])

Default: 000

Function:

Sets the threshold level of the noise gate. Input signals below the threshold level will be attenuated to -96

dB. NG_BOOST = ‘1’b adds 30 dB to the threshold settings.

Noise Gate Delay Timing (NGDELAY[1:0])

Default: 00

00 - 50 ms

01 - 100 ms

10 - 150 ms

11 - 200 ms

Function:

Sets the delay time before the noise gate attacks. Noise gate attenuation is dictated by the SOFTx and

ZCROSS bit settings unless the disable bit for each function is enabled.

6.17 Status (Address 20h) (Read Only)

For all bits in this register, a “1” means the associated error condition has occurred at least once since the

of the register. Reading the register resets all bits to 0.

Serial Port Clock Error (SP_CLK Error)

Default: 0

Function:

Indicates an invalid MCLK to LRCK ratio. See “Serial Port Clocking” on page 28“Serial Port Clocking” on

page 28 for valid clock ratios.

Note: On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes.

ADC Overflow (ADCX_OVFL)

Default = 0

Function:

Indicates that there is an over-range condition anywhere in the CS53L21 ADC signal path of each of the

associated ADCs.

THRESH[2:0] Minimum Setting

(NG_BOOST = ‘0’b)

Minimum Setting

(NG_BOOST = ‘1’b)

000 -64 dB -34 dB

001 -67 dB -37 dB

010 -70 dB -40 dB

011 -73 dB -43 dB

100 -76 dB -46 dB

101 -82 dB -52 dB

110 Reserved -58 dB

111 Reserved -64 dB

76543210

Reserved SP_CLKERR Reserved Reserved Reserved Reserved ADCA_OVFL ADCB_OVFL

DS700F1 51

CS53L21

7. ANALOG PERFORMANCE PLOTS

7.1 ADC_FILT+ Capacitor Effects on THD+N

The value of the capacitor on the ADC_FILT+ pin, 16, affects the low frequency total harmonic distortion +

noise (THD+N) performance of the ADC. Larger capacitor values yield significant improvement in THD+N

at low frequencies. Figure 22 shows the THD+N versus frequency for the ADC analog input. Plots were tak-

en from the CDB53L21 using an Audio Precision analyzer.

8. EXAMPLE SYSTEM CLOCK FREQUENCIES

8.1 Auto Detect Enabled

Sample Rate

LRCK (kHz)

MCLK (MHz)

1024x 1536x 2048x* 3072x*

8 8.1920 12.2880 16.3840 24.5760

11.025 11.2896 16.9344 22.5792 33.8688

12 12.2880 18.4320 24.5760 36.8640

Sample Rate

LRCK (kHz)

MCLK (MHz)

512x 768x 1024x* 1536x*

16 8.1920 12.2880 16.3840 24.5760

22.05 11.2896 16.9344 22.5792 33.8688

24 12.2880 18.4320 24.5760 36.8640

Sample Rate

LRCK (kHz)

MCLK (MHz)

256x 384x 512x* 768x*

32 8.1920 12.2880 16.3840 24.5760

44.1 11.2896 16.9344 22.5792 33.8688

48 12.2880 18.4320 24.5760 36.8640

-100

-60

-96

-92

-88

-84

-80

-76

-72

-68

-64

20 20k50 100 200 500 1k 2k 5k 10k

Figure 22. ADC THD+N vs. Frequency w/Capacitor Effects

1 µF

Legend –

Capacitor Value on ADC_FILT+

10 µF

22 µF

52 DS700F1

CS53L21

*The”MCLKDIV2” pin 4 must be set HI.

8.2 Auto Detect Disabled

9. PCB LAYOUT CONSIDERATIONS

9.1 Power Supply, Grounding

As with any high-resolution converter, the CS53L21 requires careful attention to power supply and ground-

ing arrangements if its potential performance is to be realized. Figure 1 on page 9 shows the recommended

power arrangements, with VA connected to a clean supply. VD, which powers the digital circuitry, may be

run from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite

bead. In this case, no additional devices should be powered from VD.

Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling

capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS53L21 as pos-

sible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same

side of the board as the CS53L21 to minimize inductance effects. All signals, especially clocks, should be

kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+

and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path

from FILT+ and AGND. The CS53L21 evaluation board demonstrates the optimum layout and power supply

arrangements.

Sample Rate

LRCK (kHz)

MCLK (MHz)

128x 192x 256x* 384x*

64 8.1920 12.2880 16.3840 24.5760

88.2 11.2896 16.9344 22.5792 33.8688

96 12.2880 18.4320 24.5760 36.8640

Sample Rate

LRCK (kHz)

MCLK (MHz)

512x 768x 1024x 1536x 2048x 3072x

8 - 6.1440 8.1920 12.2880 16.3840 24.5760

11.025 - 8.4672 11.2896 16.9344 22.5792 33.8688

12 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640

Sample Rate

LRCK (kHz)

MCLK (MHz)

256x 384x 512x 768x 1024x 1536x

16 - 6.1440 8.1920 12.2880 16.3840 24.5760

22.05 - 8.4672 11.2896 16.9344 22.5792 33.8688

24 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640

Sample Rate

LRCK (kHz)

MCLK (MHz)

256x 384x 512x 768x

32 8.1920 12.2880 16.3840 24.5760

44.1 11.2896 16.9344 22.5792 33.8688

48 12.2880 18.4320 24.5760 36.8640

Sample Rate

LRCK (kHz)

MCLK (MHz)

128x 192x 256x 384x

64 8.1920 12.2880 16.3840 24.5760

88.2 11.2896 16.9344 22.5792 33.8688

96 12.2880 18.4320 24.5760 36.8640

DS700F1 53

CS53L21

9.2 QFN Thermal Pad

The CS53L21 is available in a compact QFN package. The under side of the QFN package reveals a large

metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with

an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of

vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers.

In split ground systems, it is recommended that this thermal pad be connected to AGND for best perfor-

mance. The CS53L21 evaluation board demonstrates the optimum thermal pad and via configuration.

10.DIGITAL FILTERS

Figure 23. ADC Passband Ripple Figure 24. ADC Stopband Rejection

Figure 25. ADC Transition Band Figure 26. ADC Transition Band Detail

54 DS700F1

CS53L21

11.PARAMETER DEFINITIONS

Dynamic Range

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified

bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with

a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This

technique ensures that the distortion components are below the noise level and do not affect the measure-

ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,

and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.

Total Harmonic Distortion + Noise

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified

band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured

at -1 and -20 dBFS as suggested in AES17-1991 Annex A.

Frequency Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at

1 kHz. Units in decibels.

Interchannel Isolation

A measure of crosstalk between the left and right channel pairs. Measured for each channel at the convert-

er's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in

decibels.

Interchannel Gain Mismatch

The gain difference between left and right channel pairs. Units in decibels.

Gain Error

The deviation from the nominal full-scale analog output for a full-scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Offset Error

The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.

DS700F1 55

CS53L21

12.PACKAGE DIMENSIONS

1. Controlling dimensions are in millimeters.

2. Dimensioning and tolerancing per ASME Y14.5M.

3. This drawing conforms to JEDEC outline MO-220, variation VHHD-4.

4. Recommended reflow profile is per JEDEC/IPC J-STD-020

THERMAL CHARACTERISTICS

Millimeters Inches

Dimension MIN NOM MAX MIN NOM MAX

A 0.80 0.90 1.00 0.031 0.035 0.039

A1 0.00 0.02 0.05 0.000 0.001 0.002

A3 0.20 REF 0.008 REF

b 0.20 0.25 0.30 0.008 0.010 0.012

D 5.00 BSC 0.197 BSC

D2 3.50 3.65 3.80 0.138 0.144 0.150

e 0.50 BSC 0.020 BSC

E 5.00 BSC 0.197 BSC

E2 3.50 3.65 3.80 0.138 0.144 0.150

L 0.35 0.40 0.45 0.014 0.016 0.018

aaa 0.15 0.006

bbb 0.10 0.004

ddd 0.05 0.002

eee 0.08 0.003

Parameter Symbol Min Typ Max Units

Junction to Ambient Thermal Impedance 2 Layer Board

4 Layer Board JA

-°C/Watt

32L QFN (5 X 5 mm BODY) PACKAGE DRAWING

56 DS700F1

CS53L21

13.ORDERING INFORMATION

14.REFERENCES

1. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000.

http://www.semiconductors.philips.com

15.REVISION HISTORY

Product Description Package Pb-Free Grade Temp Range Container Order #

CS53L21 Low-Power Stereo A/D 32L-QFN Yes

Commercial -10 to +70° C Rail CS53L21-CNZ

Tape and Reel CS53L21-CNZR

Automotive -40 to +85° C Rail CS53L21-DNZ

Tape and Reel CS53L21-DNZR

CDB53L21 CS53L21 Evaluation

Board - No - - - CDB53L21

Revision Changes

JUL ‘15

Updated voltage range in “Specified Operating Conditions” on page 11.

Corrected Max passband frequency in “ADC Digital Filter Characteristics” on page 14.

Updated Section 4.8 “Recommended Power-Up Sequence” on page 30.

Updated Section 4.10 “Software Mode” on page 31.

Added note 1 in the FREEZE control register in “SPE Control (Address 09h)” on page 43.

Added note 2 in the ALC Enable register in “ALC Enable and Attack Rate (Address 1Ch)” on page 47.

Replaced the package drawing, notes, and dimensions table in Section 12. “Package Dimensions” on page 55.

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative.

To find the one nearest to you, go to www.cirrus.com.

IMPORTANT NOTICE

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pertaining to warranty, indemnification, and limitation of liability. Software is provided pursuant to applicable license terms. Cirrus Logic reserves the right

to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest

version of relevant information from Cirrus Logic to verify that the information is current and complete. Testing and other quality control techniques are

utilized to the extent Cirrus Logic deems necessary. Specific testing of all parameters of each device is not necessarily performed. In order to minimize

risks associated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural

hazards. Cirrus Logic is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of

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