HCF4013BEY - STMicroelectronics

1/9Septe mber 2001

■SET - RESET CAPABILITY

■STATIC FLIP-FLOP OPERATION - RETAINS

STATE INDEFINIT ELY WITH CLOCK LEVEL

EITHER "HIGH" OR "LOW"

■MEDIUM SP EED OPERATION 16 MHz (TYP. )

CLOCK TOGGLE RATE AT 10V

■STANDARDIZED SYMMETRICAL O UTPUT

CHARACTERISTICS

■QUIESCENT CURRENT S PECIFIED UP TO

20V

■5V, 10V AND 15V PARAMETRIC RATINGS

■INPUT LEAKAGE CURRENT

II = 100nA (MAX) AT VDD = 18V TA = 25°C

■100% TESTED FOR QUIESCENT CURRENT

■MEETS ALL REQUIREMENT S OF JEDEC

JESD13B " STANDARD SPECIFICATIO NS

FOR DESCRI PTION OF B SERIES CMOS

DEVICES"

DESCRIPTION

The HCF4013B is a monolithic integrated circuit

fabricated in Metal Oxide Semiconductor

technology available in DIP and SOP packages.

The HCF4013B consists of two identical,

independent data type flip-flops. Each flip-flop has

independent data, set, reset, and clock inputs and

Q and Q outputs. This device can be used for shift

to the data input, for counter and toggle

applications. The logic level present at the D input

is transferred to the Q output during the

positive-going transition of t he clock pul se. Setting

or resetting is independent of the clock and is

accomplished by a hi gh level on the set or reset

line, resp ec ti ve l y

HCF4013B

DUAL D-TYP E FLIP FL OP

PIN CONNECTION

ORDER CODES

PACKAGE TUBE T & R

DIP HCF4013BEY

SOP HCF4013BM1 HCF4013M013TR

DIP SOP

HCF4013B

2/9

INPUT EQUIVALE NT CIRCUIT

LOGIC DIAGRAM

PIN DESCRIPTION

TRUTH TABLE

X : Don ’t Ca re

∆ : Low Lev el

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is

not implied .

All vol tage v al ues ar e referr ed t o VSS pin vo l tage .

RECOMMENDE D OPERATING CONDITIONS

PIN No SYMBOL NAME AND FUNCTION

3, 11 CLOCK1

CLOCK2 Clock Inputs

4, 10 RESET1

RESET2 Reset Inputs

6, 8 SET1, SET2 Set Inputs

5, 9 D1, D2 Data Inputs

1, 13 Q1, Q2 Data Outputs

2, 12 Q1, Q2 Data Outputs

7VSS Negative Supply Voltage

14 VDD Positive Supply Voltage

CLOCK∆D RESET SET Q Q

LLLLH

HLLHL

XLLQQ

XXHLLH

XXLHHL

X XHHHH

Symbol Parameter Value Unit

VDD Supply Voltage -0.5 to +22 V

VIDC Input Voltage -0.5 to VDD + 0.5 V

IIDC Input Current ± 10 mA

PDPower Dissipation per Package 200 mW

Power Dissipation per Output Transistor 100 mW

Top Operating Temperature -55 to +125 °C

Tstg Storage Temperature -65 to +150 °C

Symbol Parameter Value Unit

VDD Supply Voltage 3 to 20 V

VIInput Voltage 0 to VDD V

Top Operating Temperature -55 to 125 °C

HCF4013B

3/9

DC SPECIFICATI ONS

Th e Noi se Margin for bot h "1" a nd "0" level is : 1V min. wi th VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V

Symbol Parameter

Test Condition Value

Unit

(V) VO

(V) |IO|

(µA) VDD

(V)

TA = 25°C -40 to 85°C -55 to 125°C

Min. Typ. Max. Min. Max. Min. Max.

ILQuiescent Current 0/5 5 0.02 1 30 30

µA

0/10 10 0.02 2 60 60

0/15 15 0.02 4 120 120

0/20 20 0.04 20 600 600

VOH High Level Output

Voltage 0/5 <1 5 4.95 4.95 4.95 V0/10 <1 10 9.95 9.95 9.95

0/15 <1 15 14.95 14.95 14.95

VOL Low Level Output

Voltage 5/0 <1 5 0.05 0.05 0.05 V10/0 <1 10 0.05 0.05 0.05

15/0 <1 15 0.05 0.05 0.05

VIH High Level Input

Voltage 0.5/4.5 <1 5 3.5 3.5 3.5 V1/9 <1 10 7 7 7

1.5/13.5 <1 15 11 11 11

VIL Low Level Input

Voltage 4.5/0.5 <1 5 1.5 1.5 1.5 V9/1 <1 10 3 3 3

13.5/1.5 <1 15 4 4 4

IOH Output Drive

Current 0/5 2.5 <1 5 -1.36 -3.2 -1.15 -1.1

0/5 4.6 <1 5 -0.44 -1 -0.36 -0.36

0/10 9.5 <1 10 -1.1 -2.6 -0.9 -0.9

0/15 13.5 <1 15 -3.0 -6.8 -2.4 -2.4

IOL Output Sink

Current 0/5 0.4 <1 5 0.44 1 0.36 0.36 mA0/10 0.5 <1 10 1.1 2.6 0.9 0.9

0/15 1.5 <1 15 3.0 6.8 2.4 2.4

IIInput Leakage

Current 0/18 Any Input 18 ±10-5 ±0.1 ±1±1µA

CIInput Capacitance Any Input 5 7.5 pF

HCF4013B

4/9

DYNAMIC ELECTRI CAL CHARACTERISTICS (Tamb = 25° C, C L = 50pF, RL = 200KΩ, tr = tf = 20 ns)

(* ) T ypic al temperature co effici ent for all VDD value is 0.3 %/°C.

(1) Input tr, tf = 5ns

(2) If mo re tha n uni t is ca sc aded in a parall el clock ed appli cati on, tr should be made less than or equal to the sum of t he fixed propa gat i on

del ay time at 1 5pF and th e tran sition time of the ca rry ou tp ut driv i ng sta ge for the esti m at ed capaci tive load.

Symbol Parameter Test Cond ition Valu e (*) Unit

VDD (V) Min. Typ. Max.

tTLH tTHL Propagation Delay Time

(CLOCK to Q or Q outputs) 5 150 300 ns10 65 130

15 45 90

tPLH Propagation Delay Time

(SET to Q or RESET to Q)5 150 300 ns10 65 130

15 45 90

tPHL Propagation Delay

Time(SET to Q or RESET

to Q)

5 200 400 ns10 85 170

15 60 120

tTHL tTLH Trans ition Time 5 10 0 2 00 ns10 50 100

15 40 80

fCL (1) Maximum Clock Input

Frequency 5 3.5 7 MHz10 8 16

15 12 24

tWClock Pulse Width 5 140 70 ns10 60 30

15 40 20

tr , tf (2) Clock Input Rise or Fall

Time 515

µs10 4

15 1

tWSet or Reset Pulse Width 5 180 90 ns10 80 40

15 50 25

tsetup Data Setup Time 5 40 20 ns10 20 10

15 15 7

HCF4013B

5/9

TEST CIRCUIT

CL = 50p F or equi valent (i ncludes jig and p robe ca pacit ance)

RL = 200KΩ

RT = ZOUT of pulse generator (typically 50Ω)

WAV EFORM 1 : CLOCK T O Qn, Q n PROPAGATION DELAY TIMES , Dn TO C LOCK SETUP AND

HOLD TIMES, CL OCK MINIMUM PULSE W ITDH, MAXIMUM CLOCK FREQ UENCY

(f=1MHz; 50% duty cycle)

HCF4013B

6/9

WAVEFORM 2 : PROPAGATION DELAY TIMES (Qn, Qn TO SET, RESET ), M INIM UM PULSE W I DTH

(SET AND RESET) (f=1MHz; 50% duty cycle)

HCF4013B

7/9

DIM. mm. inch

MIN. TYP MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 1.39 1.65 0.055 0.065

b 0.5 0.020

b1 0.25 0.010

D 20 0.787

E 8.5 0.335

e 2.54 0.100

e3 15.24 0.600

F 7.1 0.280

I 5.1 0.201

L 3.3 0.130

Z 1.27 2.54 0.050 0.100

Plastic DIP-14 MECHANICA L DATA

P001A

HCF4013B

8/9

DIM. mm. inch

MIN. TYP MAX. MIN. TYP. MAX.

A 1.75 0.068

a1 0.1 0.2 0.003 0.007

a2 1.65 0.064

b 0.35 0.46 0.013 0.018

b1 0.19 0.25 0.007 0.010

C 0.5 0.019

c1 45° (typ.)

D 8.55 8.75 0.336 0.344

E 5.8 6.2 0.228 0.244

e 1.27 0.050

e3 7.62 0.300

F 3.8 4.0 0.149 0.157

G 4.6 5.3 0.181 0.208

L 0.5 1.27 0.019 0.050

M 0.68 0.026

S8° (max.)

SO-14 MECHANICAL DATA

PO13G

HCF4013B

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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from

its use. No l i cense is gra nte d by imp lication or oth erwise under an y patent or patent rights of STMicroelec tronics. Spec ificat ions

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information

previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or

systems with out expres s written approval of STMicroelec tronics .

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