LM21212MH-2/NOPB - NATIONAL SEMICONDUCTOR

PGOOD

VIN

LM21212-2

VOUT

AGND

COMP

PVIN

FADJ

CIN COUT

LOUT

RC1

CC1

CC2

CC3

RFB1

RFB2

RC2

PGND

AVIN

11-16

8,9,10

5,6,7

SS/

TRK

CSS

optional

HTSSOP-20

optional

RADJ

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM21212-2

SNVS715B –MARCH 2011–REVISED JUNE 2019

LM21212-2 2.95-V to 5.5-V, 12-A, Voltage-Mode Synchronous Buck Regulator

With Adjustable Frequency

1 Features

1• Integrated 7-mΩHigh Side and 4.3-mΩLow-Side

FET Switches

• 300-kHz to 1.55-MHz Resistor-Adjustable

Frequency

• Adjustable Output Voltage from 0.6 V to VIN

(100% Duty Cycle Capable), ±1% Reference

• Input Voltage Range 2.95 V to 5.5 V

• Startup Into Prebiased Loads

• Output Voltage Tracking Capability

• Wide Bandwidth Voltage Loop Error Amplifier

• Adjustable Soft-Start With External Capacitor

• Precision Enable Pin With Hysteresis

• Integrated OVP, OCP, OTP, UVLO, and Power-

Good

• Thermally Enhanced 20-Pin HTSSOP Exposed

Pad Package

• Create a custom design using the LM21212-2 with

the WEBENCH®Power Designer

2 Applications

• Broadband, Networking and Wireless

Communications

• High-Performance FPGAs, ASICs and

Microprocessors

• Simple to Design, High Efficiency Point of Load

Regulation from a 5-V or 3.3-V Bus

3 Description

The LM21212-2 is a monolithic synchronous buck

regulator that is capable of delivering up to 12 A of

continuous output current while producing an output

voltage down to 0.6 V with outstanding efficiency.

The device is optimized to work over an input voltage

range of 2.95 V to 5.5 V, making it suitable for a wide

variety of low voltage systems. The voltage mode

control loop provides high noise immunity and narrow

duty-cycle capability, and it can be compensated to

be stable with any type of output capacitance,

providing maximum flexibility and ease of use.

The LM21212-2 features internal overvoltage

protection (OVP) and overcurrent protection (OCP)

for increased system reliability. A precision enable pin

and integrated UVLO allow turnon of the device to be

tightly controlled and sequenced. Start-up inrush

currents are limited by both an internally fixed and

externally adjustable soft-start circuit. Fault detection

and supply sequencing are possible with the

integrated power good circuit.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LM21212-2 HTSSOP (20) 6.50 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Application Circuit

LM21212-2

SNVS715B –MARCH 2011–REVISED JUNE 2019

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Description, continued.......................................... 3

6 Pin Configuration and Functions......................... 4

7 Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Ratings ........................... 5

7.4 Electrical Characteristics........................................... 5

7.5 Typical Characteristics.............................................. 7

8 Detailed Description............................................ 10

8.1 Overview................................................................. 10

8.2 Functional Block Diagram....................................... 10

8.3 Feature Description................................................. 11

8.4 Device Functional Modes........................................ 14

9 Application and Implementation ........................ 15

9.1 Application Information............................................ 15

9.2 Typical Application ................................................. 15

10 Layout................................................................... 27

10.1 Layout Considerations .......................................... 27

10.2 Layout Example .................................................... 27

10.3 Thermal Considerations........................................ 28

11 Device and Documentation Support................. 30

11.1 Device Support...................................................... 30

11.2 Receiving Notification of Documentation Updates 30

11.3 Community Resources.......................................... 30

11.4 Trademarks........................................................... 30

11.5 Electrostatic Discharge Caution............................ 30

11.6 Glossary................................................................ 31

12 Mechanical, Packaging, and Orderable

Information........................................................... 31

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (March 2013) to Revision B Page

• Editorial changes only, no technical revisions; add links for WEBENCH............................................................................... 1

Changes from Original (March 2013) to Revision A Page

• Changed layout of National Semiconductor data sheet to TI format...................................................................................... 4

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5 Description, continued

The LM21212-2 is designed to work well in multi-rail power supply architectures. The output voltage of the device

can be configured to track an external voltage rail using the SS/TRK pin. The switching frequency can be

programmed between 300 kHz and 1.55 MHz with an external resistor.

If the output is prebiased at start-up, it does not sink current, allowing the output to smoothly rise past the

prebiased voltage. The regulator is offered in a 20-pin HTSSOP package with an exposed pad that can be

soldered to the PCB, eliminating the need for bulky heat sinks.

FADJ

SS/TRK

AVIN

PVIN

PGND SW

AGND

COMP

PGOOD

Top View

PGND

11 SW

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6 Pin Configuration and Functions

PWP Package

20-Pin HTSSOP Package

Top View

Pin Descriptions

NO. NAME Description

1 FADJ Frequency Adjust pin. The switching frequency can be set to a predetermined rate by connecting a resistor

between FADJ and AGND.

2 SS/TRK Soft-start control pin. An internal 2 µA current source charges an external capacitor connected between

this pin and AGND to set the output voltage ramp rate during startup. This pin can also be used to

configure the tracking feature.

3 EN Active high enable input for the device. If not used, the EN pin can be left open, which will go high due to

an internal current source.

4 AVIN Analog input voltage supply that generates the internal bias. It is recommended to connect PVIN to AVIN

through a low pass RC filter to minimize the influence of input rail ripple and noise on the analog control

circuitry.

5,6,7 PVIN Input voltage to the power switches inside the device. These pins should be connected together at the

device. A low ESR input capacitance should be located as close as possible to these pins.

8,9,10 PGND Power ground pins for the internal power switches.

11-16 SW Switch node pins. These pins should be tied together locally and connected to the filter inductor.

17 PGOOD Open-drain power good indicator.

18 COMP Compensation pin is connected to the output of the voltage loop error amplifier.

19 FB Feedback pin is connected to the inverting input of the voltage loop error amplifier.

20 AGND Quiet analog ground for the internal reference and bias circuitry.

EP Exposed Pad Exposed metal pad on the underside of the package with an electrical and thermal connection to PGND. It

is recommended to connect this pad to the PC board ground plane in order to improve thermal dissipation.

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(1) Absolute Maximum Ratings indicate limits beyond witch damage to the device may occur. Recommended operating ratings indicate

conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications

and test conditions, see the Electrical Characteristics.

(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) The PVIN pin can tolerate transient voltages up to 6.5 V for a period of up to 6ns. These transients can occur during the normal

operation of the device.

(4) The SW pin can tolerate transient voltages up to 9 V for a period of up to 6 ns, and -1 V for a duration of 4 ns. These transients can

occur during the normal operation of the device.

7 Specifications

7.1 Absolute Maximum Ratings

See (1)(2)

PVIN(3), AVIN to GND −0.3V to +6V

SW(4), EN, FB, COMP, PGOOD, SS/TRK, FADJ to GND −0.3V to PVIN + 0.3V

Storage Temperature −65°C to 150°C

Soldering Specification for TSSOP Pb-Free Infrared or Convection (30 sec) 260°C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V

(1) Thermal measurements were performed on a 2x2 inch, 4 layer, 2 oz. copper outer layer, 1 oz.copper inner layer board with twelve 8 mil.

vias underneath the EP of the device and an additional sixteen 8 mil. vias under the unexposed package.

7.3 Recommended Operating Ratings

PVIN, AVIN to GND +2.95V to +5.5V

Junction Temperature −40°C to +125°C

θJA(1) 24°C/W

7.4 Electrical Characteristics

Unless otherwise stated, the following conditions apply: VPVIN, AVIN = 5V. Limits in standard type are for TJ= 25°C only, limits

in boldface type apply over the junction temperature (TJ) range of −40°C to +125°C. Minimum and maximum limits are

specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ= 25°C,

and are provided for reference purposes only.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SYSTEM

VFB Feedback pin voltage VIN = 2.95V to 5.5V -1% 0.6 1% V

ΔVOUT/ΔIOUT Load Regulation 0.02 %VOUT/

ΔVOUT/ΔVIN Line Regulation 0.1 %VOUT/

RDSON HS High Side Switch On Resistance ISW = 12A 7.0 9.0 mΩ

RDSON LS Low Side Switch On Resistance ISW = 12A 4.3 6.0 mΩ

ICLR HS Rising Switch Current Limit 15 17 19 A

ICLF LS Falling Switch Current Limit 12 A

VZX Zero Cross Voltage -8 3 12 mV

IQOperating Quiescent Current 1.5 3.0 mA

ISD Shutdown Quiescent Current VEN = 0V 50 70 µA

VUVLO AVIN Undervoltage Lockout AVIN Rising 2.45 2.70 2.95 V

VUVLOHYS AVIN Undervoltage Lockout Hysteresis 140 200 280 mV

VTRACKOS SS/TRACK PIN accuracy (VSS - VFB) 0 < VTRACK < 0.55V -10 620 mV

ISS Soft-Start Pin Source Current 1.3 1.9 2.5 µA

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Electrical Characteristics (continued)

Unless otherwise stated, the following conditions apply: VPVIN, AVIN = 5V. Limits in standard type are for TJ= 25°C only, limits

in boldface type apply over the junction temperature (TJ) range of −40°C to +125°C. Minimum and maximum limits are

specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ= 25°C,

and are provided for reference purposes only.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tINTSS Internal Soft-Start Ramp to Vref CSS = 0 350 500 675 µs

tRESETSS Device Reset to Soft-Start Ramp 50 110 200 µs

OSCILLATOR

fRNG FADJ Frequency Range 300 1550 kHz

fSW Switching Frequency RADJ = 22.6kΩ1400 1550 1700 kHz

RADJ = 95.3kΩ465 500 535

tHSBLANK HS OCP Blanking Time Rising edge of SW to ICLR comparison 55 ns

tLSBLANK LS OCP Blanking Time Falling edge of SW to ICLF comparison 400 ns

tZXBLANK Zero Cross Blanking Time Falling edge of SW to VZX comparison 120 ns

tMINON Minimum HS on-time 140 ns

ΔVramp PWM Ramp p-p Voltage 0.8 V

ERROR AMPLIFIER

VOL Error Amplifier Open Loop Voltage Gain ICOMP = -65µA to 1mA 95 dBV/V

GBW Error Amplifier Gain-Bandwidth Product 11 MHz

IFB Feedback Pin Bias Current VFB = 0.6V 1 nA

ICOMPSRC COMP Output Source Current 1 mA

ICOMPSINK COMP Output Sink Current 65 µA

POWERGOOD

VOVP Overvoltage Protection Rising Threshold VFB Rising 105 112.5 120 %VFB

VOVPHYS Overvoltage Protection Hysteresis VFB Falling 2 %VFB

VUVP Undervoltage Protection Rising Threshold VFB Rising 82 90 97 %VFB

VUVPHYS Undervoltage Protection Hysteresis VFB Falling 2.5 %VFB

tPGDGL PGOOD Deglitch Low (OVP/UVP

Condition Duration to PGOOD Falling) 15 µs

tPGDGH PGOOD Deglitch High (minimum low

pulse) 12 µs

RPGOOD PGOOD Pulldown Resistance 10 20 40 Ω

IPGOODLEAK PGOOD Leakage Current VPGOOD = 5V 1 nA

LOGIC

VIHSYNC SYNC Pin Logic High 2.0 V

VILSYNC SYNC Pin Logic Low 0.8 V

VIHENR EN Pin Rising Threshold VEN Rising 1.20 1.35 1.45 V

VENHYS EN Pin Hysteresis 50 110 180 mV

IEN EN Pin Pullup Current VEN = 0V 2 µA

THERMAL SHUTDOWN

TTHERMSD Thermal Shutdown 165 °C

TTHERMSDHYS Thermal Shutdown Hysteresis 10 °C

-40 -20 0 20 40 60 80 100 120

0.90

0.93

0.96

0.99

1.02

1.05

1.08

1.11

1.14

1.17

1.20

0.100

0.108

0.116

0.124

0.132

0.140

0.148

0.156

0.164

0.172

0.180

IAVIN(mA)

JUNCTION TEMPERATURE (°C)

IPVIN(mA)

IAVIN

IPVIN

-40 -20 0 20 40 60 80 100 120

0.598

0.599

0.600

0.601

0.602

VFB(V)

JUNCTION TEMPERATURE (°C)

3.0 3.5 4.0 4.5 5.0 5.5

1.0

1.1

1.2

1.3

1.4

1.5

IPVIN+ IAVIN(mA)

INPUT VOLTAGE (V)

0 2 4 6 8 10 12

100

EFFICIENCY (%)

OUTPUT CURRENT(A)

VIN= 3.3V

VIN= 4.0V

VIN= 5.0V

VIN= 5.5V

0 2 4 6 8 10 12

EFFICIENCY (%)

OUTPUT CURRENT(A)

FSW= 500kHz

FSW= 1MHz

FSW= 1.5MHz

0 2 4 6 8 10 12

100

EFFICIENCY (%)

OUTPUT CURRENT(A)

VOUT= 3.3

VOUT= 1.2

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7.5 Typical Characteristics

Unless otherwise specified: VVIN = 5 V, VOUT = 1.2 V, L= 0.56 µH (1.8-mΩRDCR), CSS = 33 nF, fSW = 500 kHz (RADJ= 95.3 kΩ),

TA= 25°C for efficiency curves, loop gain plots and waveforms, and TJ= 25°C for all others.

Figure 1. Efficiency Figure 2. Efficiency

VOUT = 2.5 V FSW= 300 KHz Inductor P/N

Ser2010-102MLD

Figure 3. Efficiency Figure 4. Non-Switching IQTOTAL vs VIN

Figure 5. Non-Switching IAVIN and IPVIN vs Temperature Figure 6. VFB vs Temperature

-40 -20 0 20 40 60 80 100 120

RDSON(m)

JUNCTION TEMPERATURE (°C)

LOW SIDE

HIGH SIDE

-40 -20 0 20 40 60 80 100 120

120

124

128

132

136

140

144

148

152

156

160

MINIMUM ON-TIME (nS)

JUNCTION TEMPERATURE(°C)

-40 -20 0 20 40 60 80 100 120

0.50

0.52

0.54

0.57

0.58

0.60

0.62

0.64

0.66

0.68

VOVP,VUVP(V)

JUNCTION TEMPERATURE (°C)

VUVP

VOVP

-40 -20 0 20 40 60 80 100 120

SHUTDOWN CURRENT ISD(μA)

JUNCTION TEMPERATURE(°C)

-40 -20 0 20 40 60 80 100 120

1.28

1.29

1.30

1.31

1.32

1.33

1.34

1.35

1.36

1.37

104

112

120

128

136

144

152

160

VIHENR(V)

JUNCTION TEMPERATURE (°C)

VENHYS(V)

V IHENR

V ENHYS

-40 -20 0 20 40 60 80 100 120

2.60

2.62

2.64

2.66

2.68

2.70

2.72

2.74

2.76

2.78

2.80

150

165

180

195

210

225

240

255

270

285

300

VUVLO(V)

JUNCTION TEMPERATURE (°C)

VUVLOHYS(mV)

V UVLO

V UVLOHYS

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Typical Characteristics (continued)

Unless otherwise specified: VVIN = 5 V, VOUT = 1.2 V, L= 0.56 µH (1.8-mΩRDCR), CSS = 33 nF, fSW = 500 kHz (RADJ= 95.3 kΩ),

TA= 25°C for efficiency curves, loop gain plots and waveforms, and TJ= 25°C for all others.

Figure 7. Enable Threshold and Hysteresis vs Temperature Figure 8. UVLO Threshold and Hysteresis vs Temperature

Figure 9. Enable Low Current vs Temperature Figure 10. OVP/UVP Threshold vs Temperature

Figure 11. Minimum On-Time vs Temperature Figure 12. FET Resistance vs Temperature

VPGOOD (5V/Div)

IL (10A/Div)

VOUT (1V/Div)

VOUT (500 mV/Div)

VPGOOD (5V/Div)

VTRACK (500 mV/Div)

IOUT (10A/Div)

VOUT (500 mV/Div)

VPGOOD (5V/Div)

VENABLE (5V/Div)

IOUT (10A/Div)

-40 -20 0 20 40 60 80 100 120

16.5

16.6

16.7

16.8

16.9

17.0

17.1

17.2

17.3

17.4

17.5

CURRENT LIMIT ICLR(A)

AMBIENT TEMPERATURE (°C)

VOUT (500 mV/Div)

VPGOOD (5V/Div)

VENABLE (5V/Div)

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Typical Characteristics (continued)

Unless otherwise specified: VVIN = 5 V, VOUT = 1.2 V, L= 0.56 µH (1.8-mΩRDCR), CSS = 33 nF, fSW = 500 kHz (RADJ= 95.3 kΩ),

TA= 25°C for efficiency curves, loop gain plots and waveforms, and TJ= 25°C for all others.

Figure 13. Peak Current Limit vs Temperature

2 ms/DIV

Figure 14. Start-up With Prebiased Output

200 µs/DIV

Figure 15. Start-up With SS/TRK Open Circuit 200 ms/DIV

Figure 16. Start-up With Applied Track Signal

10 µs/DIV Figure 17. Output Overcurrent Condition

Control

Logic

Over

temp

OSC RAMP

INT

VREF +

AVIN

FADJ

SS/TRK

COMP

AGND

PGND

PGOOD

PVIN

PWM

comparator

UVLO

Precision

enable

UVP

Ilimit low

Ilimit high

Zero-cross

Driver

OVP

Powerbad

PWM

0.68V

0.54V

AVIN

PVIN

Driver

2.7V

1.35V

0.6V

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SNVS715B –MARCH 2011–REVISED JUNE 2019

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8 Detailed Description

8.1 Overview

The LM21212-2 switching regulator features all of the functions necessary to implement an efficient low voltage

buck regulator using a minimum number of external components. This easy-to-use regulator features two

integrated switches and is capable of supplying up to 12 A of continuous output current. The regulator utilizes

voltage mode control with trailing edge modulation to optimize stability and transient response over the entire

output voltage range. The device can operate at high switching frequency allowing use of a small inductor while

still achieving high efficiency. The precision internal voltage reference allows the output to be set as low as 0.6 V.

Fault protection features include: current limiting, thermal shutdown, overvoltage protection, and shutdown

capability. The device is available in the 20-pin HTSSOP package featuring an exposed pad to aid thermal

dissipation. The LM21212-2 can be used in numerous applications to efficiently step-down from a 5-V or 3.3-V

bus.

8.2 Functional Block Diagram

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8.3 Feature Description

8.3.1 Precision Enable

The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal.

This pin is a precision analog input that enables the device when the voltage exceeds 1.35V (typical). The EN pin

has 110 mV of hysteresis and will disable the output when the enable voltage falls below 1.24 V (typical). If the

EN pin is not used, it can be left open, and will be pulled high by an internal 2-µA current source. Since the

enable pin has a precise turn-on threshold it can be used along with an external resistor divider network from VIN

to configure the device to turn on at a precise input voltage.

8.3.2 UVLO

The LM21212-2 has a built-in undervoltage lockout protection circuit that keeps the device from switching until

the input voltage reaches 2.7V (typical). The UVLO threshold has 200 mV of hysteresis that keeps the device

from responding to power-on glitches during start up. If desired the turnon point of the supply can be changed by

using the precision enable pin and a resistor divider network connected to VIN as shown in Figure 23 in the

design guide.

8.3.3 Current Limit

The LM21212-2 has current limit protection to avoid dangerous current levels on the power FETs and inductor. A

current limit condition is met when the current through the high side FET exceeds the rising current limit level

(ICLR). The control circuitry will respond to this event by turning off the high side FET and turning on the low side

FET. This forces a negative voltage on the inductor, thereby causing the inductor current to decrease. The high-

side FET does not conduct again until the lower current limit level (ICLF) is sensed on the low side FET. At this

point, the device resumes normal switching.

A current limit condition will cause the internal soft-start voltage to ramp downward. After the internal soft-start

ramps below the feedback (FB) pin voltage, (nominally 0.6 V), FB begins to ramp downward, as well. This

voltage foldback limits the power consumption in the device, thereby protecting the device from continuously

supplying power to the load under a condition that does not fall within the device SOA. After the current limit

condition is cleared, the internal soft-start voltage will ramp up again. Figure 18 shows current limit behavior with

VSS, VFB, VOUT and VSW.

8.3.4 Short-Circuit Protection

In the unfortunate event that the output is shorted with a low impedance to ground, the LM21212-2 will limit the

current into the short by resetting the device. A short-circuit condition is sensed by a current-limit condition

coinciding with a voltage on the FB pin that is lower than 100 mV. When this condition occurs, the device will

begin its reset sequence, turning off both power FETs and discharging the soft-start capacitor after tRESETSS

(nominally 110 µs). The device will then attempt to restart. If the short-circuit condition still exists, it will reset

again, and repeat until the short-circuit is cleared. The reset prevents excess current flowing through the FETs in

a highly inefficient manner, potentially causing thermal damage to the device or the bus supply.

SHORT-CIRCUIT

Iclf

Iclr

VSS

VFB

VOUT

VSW

CURRENT LIMIT SHORT-CIRCUIT

REMOVED

100 mV

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Feature Description (continued)

Figure 18. Current Limit Conditions

8.3.5 Thermal Protection

Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum

junction temperature is exceeded. When activated, typically at 165°C, the LM21212-2 tri-states the power FETs

and resets soft start. After the junction cools to approximately 155°C, the device starts up using the normal start

up routine. This feature is provided to prevent catastrophic failures from accidental device overheating. Note that

thermal limit will not stop the die from operating above the specified operating maximum temperature,125°C. The

die should be kept under 125°C to ensure correct operation.

8.3.6 Power-Good Flag

The PGOOD pin provides the user with a way to monitor the status of the LM21212-2. In order to use the

PGOOD pin, the application must provide a pullup resistor to a desired DC voltage (in other words, VIN). PGOOD

responds to a fault condition by pulling the PGOOD pin low with the open-drain output. PGOOD will pull low on

the following conditions – 1) VFB moves above or below the VOVP or VUVP, respectively 2) The enable pin is

brought below the enable threshold 3) The device enters a prebiased output condition (VFB>VSS).

Figure 19 shows the conditions that will cause PGOOD to fall.

IBOUNDARY = (VIN ± VOUT) x D

2 x L x fSW

Vss

VFB

VEN

VPGOOD

VSW

OVP UVP PRE-BIASED

STARTUP

DISABLE

Vovp

Vuvp

tPGDGL

0.6V

tRESETSS

tPGDGH

VOVPHYS

VUVPHYS

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Feature Description (continued)

Figure 19. PGOOD Conditions

8.3.7 Light Load Operation

The LM21212-2 offers increased efficiency when operating at light loads. Whenever the load current is reduced

to a point where the peak-to-peak inductor ripple current is greater than two times the load current, the device

will enter the diode emulation mode preventing significant negative inductor current. The output current at which

this occurs is the critical conduction boundary and can be calculated by Equation 1:

(1)

It can be seen that in diode emulation mode, whenever the inductor current reaches zero the SW node becomes

high impedance. Ringing will occur on this pin as a result of the LC tank circuit formed by the inductor and the

parasitic capacitance at the node. If this ringing is of concern an additional RC snubber circuit can be added from

the switch node to ground.

At very light loads, usually below 500 mA, several pulses may be skipped in between switching cycles, effectively

reducing the switching frequency and further improving light-load efficiency.

Time (s)

Discontinuous Conduction Mode (DCM)

IPeak

Time (s)

Discontinuous Conduction Mode (DCM)

DCM - CCM Boundary

Continuous Conduction Mode (CCM)

Switchnode Voltage Switchnode VoltageInductor CurrentInductor CurrentInductor Current

VIN

IAVERAGE

VIN

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8.4 Device Functional Modes

Several diagrams are shown in Figure 20 illustrating continuous conduction mode (CCM), discontinuous

conduction mode (DCM), and the boundary condition.

Figure 20. Modes Of Operation for LM21212-2

PGOOD

VIN

LM21212-2

VOUT

AGND

COMP

PVIN

FADJ

CIN3

RC1

CC1

CC2

CC3

RFB1

RFB2

RC2

PGND

AVIN

11-16

8,9,10

5,6,7

SS/

TRK

CSS

HTSSOP-20

CIN2

CIN1

VIN

RPGOOD

CO1 CO2 CO3

RADJ

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LM21212-2 switching regulator features all of the functions necessary to implement an efficient low voltage

buck regulator using a minimum number of external components. This easy-to-use regulator features two

integrated switches and is capable of supplying up to 12 A of continuous output current. The regulator utilizes

voltage mode control with trailing edge modulation to optimize stability and transient response over the entire

output voltage range. The device can operate at high switching frequency allowing use of a small inductor while

still achieving high efficiency.

9.2 Typical Application

9.2.1 Typical Application 1

Figure 21. Typical Application Schematic 1

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Typical Application (continued)

9.2.1.1 Design Requirements

Table 1. Bill Of Materials (VIN = 3.3 V - 5.5 V, VOUT = 1.2 V, IOUT = 12 A, FSW = 500 kHz)

ID DESCRIPTION VENDOR PART NUMBER QUANTITY

CFCAP, CERM, 1 uF, 10V, +/-10%,

X7R, 0603 MuRata GRM188R71A105KA61D 1

CIN1, CIN2, CIN3, CO1,

CO2, CO3 CAP, CERM, 100 uF, 6.3V, +/-20%,

X5R, 1206 MuRata GRM31CR60J107ME39L 6

CC1 CAP, CERM, 1800 pF, 50V, +/-5%,

C0G/NP0, 0603 TDK C1608C0G1H182J 1

CC2 CAP, CERM, 68 pF, 50V, +/-5%,

C0G/NP0, 0603 TDK C1608C0G1H680J 1

CC3 CAP, CERM, 820 pF, 50V, +/-5%,

C0G/NP0, 0603 TDK C1608C0G1H821J 1

CSS CAP, CERM, 0.033 uF, 16V, +/-10%,

X7R, 0603 MuRata GRM188R71C333KA01D 1

LOInductor, Shielded Drum Core,

Powdered Iron, 560nH, 27.5A, 0.0018

ohm, SMD

Vishay-Dale IHLP4040DZERR56M01 1

RFRES, 1.0 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW06031R00JNEA 1

RC1 RES, 9.31 kohm, 1%, 0.1W, 0603 Vishay-Dale CRCW06039K31FKEA 1

RC2 RES, 165 ohm, 1%, 0.1W, 0603 Vishay-Dale CRCW0603165RFKEA 1

RFB1, RFB2, RPGOOD RES, 10 kohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060310K0FKEA 3

RADJ RES, 95.3 kohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060395K3FKEA 1

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM21212-2 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.1.2.2 Output Voltage

The first step in designing the LM21212-2 application is setting the output voltage. This is done by using a

voltage divider between VOUT and AGND, with the middle node connected to VFB. When operating under steady-

state conditions, the LM21212-2 will force VOUT such that VFB is driven to 0.6 V.

RA = VPVIN - 1.35V

1.35V - IENRB

AVIN

RALM21212-2

Input Power

Supply VOUT

RFB2

VOUT =RFB1 RFB2

+0.6V

RFB1

RFB2

VOUT

LM21212-2

0.6V

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Figure 22. Setting VOUT

A good starting point for the lower feedback resistor, RFB2, is 10kΩ. RFB1 can then be calculated the following

equation:

(2)

9.2.1.2.3 Precision Enable

The enable (EN) pin of the LM21212-2 allows the output to be toggled on and off. This pin is a precision analog

input. When the voltage exceeds 1.35V, the controller will try to regulate the output voltage as long as the input

voltage has exceeded the UVLO voltage of 2.70V. There is an internal current source connected to EN so if

enable is not used, the device will turn on automatically. If EN is not toggled directly the device can be

preprogrammed to turn on at a certain input voltage higher than the UVLO voltage. This can be done with an

external resistor divider from AVIN to EN and EN to AGND as shown below in Figure 23.

Figure 23. Enable Start-up Through VIN

The resistor values of RAand RBcan be relatively sized to allow EN to reach the enable threshold voltage

depending on the input supply voltage. With the enable current source accounted for, the equation solving for RA

is shown below:

(3)

In the Equation 3 RAis the resistor from VIN to enable, RBis the resistor from enable to ground, IEN is the internal

enable pullup current (2 µA) and 1.35 V is the fixed precision enable threshold voltage. Typical values for RB

range from 10 kΩto 100 kΩ.

9.2.1.2.4 Soft Start

When EN has exceeded 1.35 V, and both PVIN and AVIN have exceeded the UVLO threshold, the LM21212-2

begins charging the output linearly to the voltage level dictated by the feedback resistor network. The LM21212-2

has a user adjustable soft-start circuit to lengthen the charging time of the output set by a capacitor from the soft

start pin to ground. After enable exceeds 1.35 V, an internal 2-µA current source begins to charge the soft start

capacitor. This allows the user to limit inrush currents due to a high output capacitance and not cause an over

current condition. Adding a soft-start capacitor can also reduce the stress on the input rail. Larger capacitor

values will result in longer start-up times. Use the equation below to approximate the size of the soft-start

capacitor:

fSW

RADJ =54680 - 13.15

VOUT

VEN

Voltage

Time

VPGOOD

Soft Start Time (tss)

90% VOUT

(VUVP)

Enable

Delay

(tRESETSS)

tSS x ISS = CSS

0.6V

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where

• ISSis nominally 2 µA

• tSS is the desired start-up time (4)

If VIN is higher than the UVLO level and enable is toggled high the soft start sequence will begin. There is a small

delay between enable transitioning high and the beginning of the soft-start sequence. This delay allows the

LM21212-2 to initialize its internal circuitry. Once the output has charged to 90% of the nominal output voltage

the power-good flag will transition high. This behavior is illustrated in Figure 24.

Figure 24. Soft Start Timing

As shown above, the size of the capacitor is influenced by the nominal feedback voltage level 0.6 V, the soft-start

charging current ISS (2 µA), and the desired soft start time. If no soft-start capacitor is used then the LM21212-2

defaults to a minimum startup time of 500 µs. The LM21212-2 will not start up faster than 500 µs. When enable

is cycled or the device enters UVLO, the charge developed on the soft-start capacitor is discharged to reset the

startup process. This also happens when the device enters short circuit mode from an overcurrent event.

9.2.1.2.5 Resistor-Adjustable Frequency

The frequency adjust (FADJ) pin allows the LM21212-2 to be programmed to a predetermined switching

frequency between 300 kHz to 1.55 MHz by connecting a resistor between FADJ and AGND. To determine the

resistor (RADJ) value for a desired frequency, the following equation can be used:

where

• RADJ is resistance in kΩ

• fSW is frequency in kHz (5)

The desired frequency must fall within the operational frequency range, 300 kHz to 1550 kHz, and a

corresponding resistor must be used for normal operation.

9.2.1.2.6 Inductor Selection

The inductor (L) used in the application will influence the ripple current and the efficiency of the system. The first

selection criteria is to define a ripple current, ΔIL. In a buck converter, it is typically selected to run between 20%

to 30% of the maximum output current. Figure 25 shows the ripple current in a standard buck converter operating

in continuous conduction mode. Larger ripple current results in a smaller inductance value, which will lead to

lower inductor series resistance, and improved efficiency. However, larger ripple current will also cause the

device to operate in discontinuous conduction mode at a higher average output current.

VDROOP = 'IOUTSTEP x RESR + L x 'IOUTSTEP2

COUT x (VIN - VOUT)

'VOUT  'IL x 1

8 x fSW x COUT

RESR +

L =(VIN ± VOUT)D

üILfSW

VIN

IL AVG = IOUT 'IL

Time

VSW

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Figure 25. Switch And Inductor Current Waveforms

Once the ripple current has been determined, the appropriate inductor size can be calculated using the following

equation:

(6)

9.2.1.2.7 Output Capacitor Selection

The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load

conditions. A wide range of output capacitors may be used with the LM21212-2 that provide various advantages.

The best performance is typically obtained using ceramic, SP or OSCON type chemistries. Typical trade-offs are

that the ceramic capacitor provides extremely low ESR to reduce the output ripple voltage and noise spikes,

while the SP and OSCON capacitors provide a large bulk capacitance in a small volume for transient loading

conditions.

When selecting the value for the output capacitor, the two performance characteristics to consider are the output

voltage ripple and transient response. The output voltage ripple can be approximated by using the following

formula:

where

•ΔVOUT (V) is the amount of peak to peak voltage ripple at the power supply output

• RESR (Ω) is the series resistance of the output capacitor

• fSW (Hz) is the switching frequency

• COUT (F) is the output capacitance used in the design (7)

The amount of output ripple that can be tolerated is application specific; however a general recommendation is to

keep the output ripple less than 1% of the rated output voltage. Keep in mind ceramic capacitors are sometimes

preferred because they have very low ESR; however, depending on package and voltage rating of the capacitor

the value of the capacitance can drop significantly with applied voltage. The output capacitor selection will also

affect the output voltage droop during a load transient. The peak droop on the output voltage during a load

transient is dependent on many factors; however, an approximation of the transient droop ignoring loop

bandwidth can be obtained using the following equation:

where

• COUT (F) is the minimum required output capacitance

• L (H) is the value of the inductor

• VDROOP (V) is the output voltage drop ignoring loop bandwidth considerations

IIN-RMS = IOUT D(1 - D)

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•ΔIOUTSTEP (A) is the load step change

• RESR (Ω) is the output capacitor ESR

• VIN (V) is the input voltage

• VOUT (V) is the set regulator output voltage (8)

Both the tolerance and voltage coefficient of the capacitor must be examined when designing for a specific

output ripple or transient droop target.

9.2.1.2.8 Input Capacitor Selection

Quality input capacitors are necessary to limit the ripple voltage at the PVIN pin while supplying most of the

switch current during the on-time. Additionally, they help minimize input voltage droop in an output current

transient condition. In general, it is recommended to use a ceramic capacitor for the input as it provides both a

low impedance and small footprint. Use of a high-grade dielectric for the ceramic capacitor, such as X5R or X7R,

will provide improved performance over temperature and also minimize the DC voltage derating that occurs with

Y5V capacitors. The input capacitors should be placed as close as possible to the PVIN and PGND pins.

Non-ceramic input capacitors should be selected for RMS current rating and minimum ripple voltage. A good

approximation for the required ripple current rating is given by the relationship:

(9)

As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty

cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half the output

current. For best performance, place low ESR ceramic capacitors in parallel with higher capacitance capacitors

to provide the best input filtering for the device.

When operating at low input voltages (3.3 V or lower), additional capacitance may be necessary to protect from

triggering an under-voltage condition on an output current transient. This will depend on the impedance between

the input voltage supply and the LM21212-2, as well as the magnitude and slew rate of the output transient.

The AVIN pin requires a 1-µF ceramic capacitor to AGND and a 1-Ωresistor to PVIN. This RC network filter

inherent noise on PVIN from the sensitive analog circuitry connected to AVIN.

9.2.1.2.9 Control Loop Compensation

The LM21212-2 incorporates a high bandwidth amplifier between the FB and COMP pins to allow the user to

design a compensation network that matches the application. This section will walk through the various steps in

obtaining the open loop transfer function.

There are three main blocks of a voltage mode buck switcher that the power supply designer must consider

when designing the control system; the power train, modulator, and the compensated error amplifier. A closed

loop diagram is shown in Figure 26.

fESR = 2SCOUTRES

RO + RDCR

fLC = 1

2SLOUTCOUT(RO + RESR)

GPWM = Vin

ÂVramp

VIN

LOUT

COUT

RFB1

RFB2

CC2

CC1 RC1

VOUT

CC3

RC2

RDCR

COMP

DRIVER

PWM

Error Amplifier and Compensation

PWM Modulator

SW RESR

Power Train

0.6V

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Figure 26. Loop Diagram

The power train consists of the output inductor (L) with DCR (DC resistance RDCR), output capacitor (C0) with

ESR (effective series resistance RESR), and load resistance (Ro). The error amplifier (EA) constantly forces FB to

0.6 V. The passive compensation components around the error amplifier help maintain system stability. The

modulator creates the duty cycle by comparing the error amplifier signal with an internally generated ramp set at

the switching frequency.

There are three transfer functions that must be taken into consideration when obtaining the total open loop

transfer function; COMP to SW (modulator) , SW to VOUT (power train), and VOUT to COMP (error amplifier). The

COMP to SW transfer function is simply the gain of the PWM modulator.

where

•ΔVRAMP is the oscillator peak-to-peak ramp voltage (nominally 0.8 V) (10)

The SW-to-COMP transfer function includes the output inductor, output capacitor, and output load resistance.

The inductor and capacitor create two complex poles at a frequency described by:

(11)

In addition to two complex poles, a left half plane zero is created by the output capacitor ESR located at a

frequency described by:

(12)

A Bode plot showing the power train response is shown in Figure 27

100 1k 10k 100k 1M 10M

-20

100

-180

-135

-90

-45

GAIN (dB)

FREQUENCY (Hz)

PHASE (°)

GAIN

PHASE

2SfZ1 +1 s

2SfZ2 +1

2SfP1 +1 s

2SfP2 +1

GEA = Km

100 1k 10k 100k 1M 10M

-80

-60

-40

-20

-360

-320

-280

-240

-200

-160

-120

-80

-40

GAIN (dB)

FREQUENCY (HZ)

PHASE (°)

GAIN

PHASE

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Figure 27. Power Train Bode Plot

The complex poles created by the output inductor and capacitor cause a 180° phase shift at the resonant

frequency as seen in Figure 27. The phase is boosted back up to –90° because of the output capacitor ESR

zero. The 180° phase shift must be compensated out and phase boosted through the error amplifier to stabilize

the closed loop response. The compensation network shown around the error amplifier in Figure 26 creates two

poles, two zeros and a pole at the origin. Placing these poles and zeros at the correct frequencies will stabilize

the closed loop response. The Compensated Error Amplifier transfer function is:

(13)

The pole located at the origin gives high open loop gain at DC, translating into improved load regulation

accuracy. This pole occurs at a very low frequency due to the limited gain of the error amplifier; however, it can

be approximated at DC for the purposes of compensation. The other two poles and two zeros can be located

accordingly to stabilize the voltage mode loop depending on the power stage complex poles and Q. Figure 28 is

an illustration of what the Error Amplifier Compensation transfer function will look like.

Figure 28. Type 3 Compensation Network Bode Plot

RC1 = fCROSSOVER

fLC

'VRAMP

VIN RFB1

= 100 kHz

17.4 kHz 10 k:

0.8 V

5.0 V

= 9.2 k:

fZ2 = fLC =

fP1 = fESR =

fP2 = fsw

fZ1 = fLC

2SRC1CC1

2S(RC1 + RFB1)CC3

CC1 + CC2

2SRC1 CC1CC2

2SRC2CC3

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As seen in Figure 28, the two zeros (fLC/2, fLC) in the comensation network give a phase boost. This will cancel

out the effects of the phase loss from the output filter. The compensation network also adds two poles to the

system. One pole should be located at the zero caused by the output capacitor ESR (fESR) and the other pole

should be at half the switching frequency (fSW/2) to roll off the high frequency response. The dependancy of the

pole and zero locations on the compensation components is described below.

(14)

An example of the step-by-step procedure to generate compensation component values using the typical

application setup (see Figure 21) is given. The parameters needed for the compensation values are given in the

table below.

PARAMETER VALUE

VIN 5 V

VOUT 1.2 V

IOUT 12 A

fCROSSOVER 100 kHz

L 0.56 µH

RDCR 1.8 mΩ

CO150 µF

RESR 1 mΩ

ΔVRAMP 0.8 V

fSW 500 kHz

where ΔVRAMP is the oscillator peak-to-peak ramp voltage (nominally 0.8V), and fCROSSOVER is the frequency at

which the open-loop gain is a magnitude of 1. It is recommended that the fcrossover not exceed one-fifth of the

switching frequency. The output capacitance, CO, depends on capacitor chemistry and bias voltage. For Multi-

Layer Ceramic Capacitors (MLCC), the total capacitance will degrade as the DC bias voltage is increased.

Measuring the actual capacitance value for the output capacitors at the output voltage is recommended to

accurately calculate the compensation network. The example given here is the total output capacitance using the

three MLCC output capacitors biased at 1.2V, as seen in the typical application schematic, . Note that it is more

conservative, from a stability standpoint, to err on the side of a smaller output capacitance value in the

compensation calculations rather than a larger, as this will result in a lower bandwidth but increased phase

margin.

First, a the value of RFB1 should be chosen. A typical value is 10 kΩ. From this, the value of RC1 can be

calculated to set the mid-band gain so that the desired crossover frequency is achieved:

(15)

Next, the value of CC1 can be calculated by placing a zero at half of the LC double pole frequency (fLC):

10 100 1k 10k 100k 1M

-50

100

150

200

-40

-20

100

120

140

160

GAIN (dB)

FREQUENCY (Hz)

PHASE MARGIN (°)

GAIN

PHASE

2SfESRRC2

CC3 =

= 898 pF

fLC

fESR - fLC

RC2 =RFB1

= 166:

CC2 = CC1

SfSWRC1 CC1 -1

= 71 pF

CC1 =SfLCRC1

= 1.99 nF

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(16)

Now the value of CC2 can be calculated to place a pole at half of the switching frequency (fSW):

(17)

RC2 can then be calculated to set the second zero at the LC double pole frequency:

(18)

Last, CC3 can be calculated to place a pole at the same frequency as the zero created by the output capacitor

ESR:

(19)

An illustration of the total loop response can be seen in Figure 29.

Figure 29. Loop Response

It is important to verify the stability by either observing the load transient response or by using a network

analyzer. A phase margin between 45° and 70° is usually desired for voltage mode systems. Excessive phase

margin can cause slow system response to load transients and low phase margin may cause an oscillatory load

transient response. If the load step response peak deviation is larger than desired, increasing fCROSSOVER and

recalculating the compensation components may help but usually at the expense of phase margin.

VOUT (50 mV/Div)

IOUT (5A/Div)

VOUT (10 mV/Div)

3.0 3.5 4.0 4.5 5.0 5.5

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06

0.08

0.10

ûOUTPUT VOLTAGE (%)

INPUT VOLTAGE (V)

IOUT = 0A

IOUT = 12A

0 2 4 6 8 10 12

-0.04

-0.03

-0.02

-0.01

0.00

0.01

0.02

0.03

0.04

ûOUTPUT VOLTAGE (%)

OUTPUT CURRENT (A)

VIN = 3.3V

VIN = 5.0V

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9.2.1.3 Application Curves

Figure 30. Load Regulation Figure 31. Line Regulation

100 µs/DIV

Figure 32. Load Transient Response (FSW = 650 kHz) 2 µs/DIV

Figure 33. Output Voltage Ripple

PGOOD

VIN

LM21212-2

VOUT

AGND

COMP

PVIN

FADJ

RC1

CC1

CC2

CC3

RFB1

RFB2

RC2

PGND

AVIN

11-16

8,9,10

5,6,7

SS/

TRK

CSS

HTSSOP-20

CIN1

VIN

RPGOOD

CO1 CO2

REN1

REN2

RADJ

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9.2.2 Typical Application Schematic 2

Figure 34. Typical Application Schematic 2

9.2.2.1 Design Requirements

Table 2. Bill Of Materials (VIN = 4 V- 5.5 V, VOUT = 0.9 V, IOUT =8A,FSW = 1 MHz)

ID DESCRIPTION VENDOR PART NUMBER QUANTITY

CFCAP, CERM, 1 uF, 10V, +/-10%,

X7R, 0603 MuRata GRM188R71A105KA61D 1

CIN1, CO1, CO2 CAP, CERM, 100 uF, 6.3V, +/-20%,

X5R, 1206 MuRata GRM31CR60J107ME39L 3

CC1 CAP, CERM, 1800 pF, 50V, +/-5%,

C0G/NP0, 0603 MuRata GRM1885C1H182JA01D 1

CC2 CAP, CERM, 68 pF, 50V, +/-5%,

C0G/NP0, 0603 TDK C1608C0G1H680J 1

CC3 CAP, CERM, 470 pF, 50V, +/-5%,

C0G/NP0, 0603 TDK C1608C0G1H471J 1

CSS CAP, CERM, 0.033 uF, 16V, +/-10%,

X7R, 0603 MuRata GRM188R71C333KA01D 1

LOInductor, Shielded Drum Core,

Superflux, 240nH, 20A, 0.001 ohm,

SMD

Wurth Elektronik 744314024 1

RFRES, 1.0 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW06031R00JNEA 1

RC1 RES, 4.87 kohm, 1%, 0.1W, 0603 Vishay-Dale CRCW06034K87FKEA 1

RC2 RES, 210 ohm, 1%, 0.1W, 0603 Vishay-Dale CRCW0603210RFKEA 1

REN1, RFB1, RPGOOD RES, 10k ohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060310K0FKEA 3

REN2 RES, 19.6 kohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060319K6FKEA 1

RFB2 RES, 20.0 kohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060320K0FKEA 1

RADJ RES, 41.2 kohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060341K2FKEA 1

9.2.2.2 Detailed Design Procedure

See Detailed Design Procedure

PVIN SW

PGND

LVOUT

LM21212-2

CIN COUT

LOOP1 LOOP2

VIN

LM21212-2

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10 Layout

10.1 Layout Considerations

PC board layout is an important part of DC/DC converter design. Poor board layout can disrupt the performance

of a DC/DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss

in the traces. These can send erroneous signals to the DC/DC converter resulting in poor regulation or instability.

Good layout can be implemented by following a few simple design rules.

1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched

at high slew rates. The first loop starts from the input capacitor, to the regulator PVIN pin, to the regulator

SW pin, to the inductor then out to the output capacitor and load. The second loop starts from the output

capacitor ground, to the regulator GND pins, to the inductor and then out to the load (see Figure 35). To

minimize both loop areas, the input capacitor must be placed as close as possible to the VIN pin. Grounding

for both the input and output capacitor must be close. Ideally, a ground plane must be placed on the top

layer that connects the PGND pins, the exposed pad (EP) of the device, and the ground connections of the

input and output capacitors in a small area near pins 10 and 11 of the device. The inductor must be placed

as close as possible to the SW pin and output capacitor.

2. Minimize the copper area of the switch node. The six SW pins must be routed on a single top plane to the

pad of the inductor. The inductor must be placed as close as possible to the switch pins of the device with a

wide trace to minimize conductive losses. The inductor can be placed on the bottom side of the PCB relative

to the LM21212-2, but care must be taken to not allow any coupling of the magnetic field of the inductor into

the sensitive feedback or compensation traces.

3. Have a solid ground plane between PGND, the EP and the input and output cap. ground connections. The

ground connections for the AGND, compensation, feedback, and soft-start components must be physically

isolated (located near pins 1 and 20) from the power ground plane but a separate ground connection is not

necessary. If not properly handled, poor grounding can result in degraded load regulation or erratic switching

behavior.

4. Carefully route the connection from the VOUT signal to the compensation network. This node is high

impedance and can be susceptible to noise coupling. The trace must be routed away from the SW pin and

inductor to avoid contaminating the feedback signal with switch noise. Additionally,feedback resistors RFB1

and RFB2 must be located near the device to minimize the trace length to FB between these resistors.

5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or

output of the converter and can improve efficiency. Voltage accuracy at the load is important so make sure

feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide

the best output accuracy.

6. Provide adequate device heatsinking. For most 12A designs a four layer board is recommended. Use as

many vias as possible to connect the EP to the power plane heatsink. The vias located underneath the EP

will wick solder into them if they are not filled. Complete solder coverage of the EP to the board is required to

achieve the θJA values described in the previous section. Either an adequate amount of solder must be

applied to the EP pad to fill the vias, or the vias must be filled during manufacturing. See the Thermal

Considerations section to ensure enough copper heatsinking area is used to keep the junction temperature

below 125°C.

10.2 Layout Example

Figure 35. Schematic of LM21212-2 Highlighting Layout Sensitive Nodes

2 3 4 5 6 7 8 9 10

THERMAL RESISTANCE (JA)

BOARD AREA (in2)

PD = PIN (1 - Efficiency) - IOUT2 RDCR

TJ = PD TJA

+ TA

LM21212-2

SNVS715B –MARCH 2011–REVISED JUNE 2019

www.ti.com

Product Folder Links: LM21212-2

10.3 Thermal Considerations

The thermal characteristics of the LM21212-2 are specified using the parameter θJA, which relates the junction

temperature to the ambient temperature. Although the value of θJA is dependant on many variables, it still can be

used to approximate the operating junction temperature of the device.

To obtain an estimate of the device junction temperature, one may use the following relationship:

where

• TJis the junction temperature in °C

•θJA is the junction to ambient thermal resistance for the LM21212-2

• TAis the ambient temperature in °C (20)

and

where

• PIN is the input power in Watts (PIN = VIN x IIN)

• IOUT is the output load current in A (21)

It is important to always keep the operating junction temperature (TJ) below 125°C for reliable operation. If the

junction temperature exceeds 165°C the device will cycle in and out of thermal shutdown. If thermal shutdown

occurs it is a sign of inadequate heatsinking or excessive power dissipation in the device.

Figure 36, shown below, provides a better approximation of the θJA for a given PCB copper area. The PCB used

in this test consisted of 4 layers: 1 oz. copper was used for the internal layers while the external layers were

plated to 2 oz. copper weight. To provide an optimal thermal connection, a 3 × 4 array of 8 mil. vias under the

thermal pad were used, and an additional sixteen 8 mil. vias under the rest of the device were used to connect

the 4 layers.

Figure 36. Thermal Resistance vs PCB Area (4-Layer Board)

0 2 4 6 8 10 12

105

115

125

MAX. AMBIENT TEMPERATURE (°C)

IOUT(A)

LM21212-2

www.ti.com

SNVS715B –MARCH 2011–REVISED JUNE 2019

Product Folder Links: LM21212-2

Thermal Considerations (continued)

Figure 37 shows a plot of the maximum ambient temperature vs output current for the typical application circuit

shown in , assuming a θJA value of 24°C/W.

Figure 37. Maximum Ambient Temperature vs Output Current (0 LFM)

LM21212-2

SNVS715B –MARCH 2011–REVISED JUNE 2019

www.ti.com

Product Folder Links: LM21212-2

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 Development Support

11.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM21212-2 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

LM21212-2

www.ti.com

SNVS715B –MARCH 2011–REVISED JUNE 2019

Product Folder Links: LM21212-2

11.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM21212MH-2/NOPB ACTIVE HTSSOP PWP 20 73 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LM21212

MH-2

LM21212MHE-2/NOPB ACTIVE HTSSOP PWP 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LM21212

MH-2

LM21212MHX-2/NOPB ACTIVE HTSSOP PWP 20 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LM21212

MH-2

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM21212MHE-2/NOPB HTSSOP PWP 20 250 178.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

LM21212MHX-2/NOPB HTSSOP PWP 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Jul-2019

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM21212MHE-2/NOPB HTSSOP PWP 20 250 210.0 185.0 35.0

LM21212MHX-2/NOPB HTSSOP PWP 20 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Jul-2019

Pack Materials-Page 2

MECHANICAL DATA

PWP0020AA

www.ti.com

MYB20XX (REV E)

4214875/A 02/2013

. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

C. Reference JEDEC Registration MO-153, Variation ACT.

NOTES:

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