AVAILABLE
Functional Diagrams
Pin Configurations appear at end of data sheet.
Functional Diagrams continued at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
General Description
The MAX3372E–MAX3379E and MAX3390E–MAX3393E
±15kV ESD-protected level translators provide the level
shifting necessary to allow data transfer in a multivoltage
system. Externally applied voltages, VCC and VL, set the
logic levels on either side of the device. A low-voltage
logic signal present on the VLside of the device appears
as a high-voltage logic signal on the VCC side of the
device, and vice-versa. The MAX3374E/MAX3375E/
MAX3376E/MAX3379E and MAX3390E–MAX3393E unidi-
rectional level translators level shift data in one direction
(VL→VCC or VCC →VL) on any single data line. The
MAX3372E/MAX3373E and MAX3377E/MAX3378E bidi-
rectional level translators utilize a transmission-gate-
based design (Figure 2) to allow data translation in either
direction (VL↔VCC) on any single data line. The
MAX3372E–MAX3379E and MAX3390E–MAX3393E
accept VLfrom +1.2V to +5.5V and VCC from +1.65V to
+5.5V, making them ideal for data transfer between low-
voltage ASICs/PLDs and higher voltage systems.
All devices in the MAX3372E–MAX3379E, MAX3390E–
MAX3393E family feature a three-state output mode that
reduces supply current to less than 1µA, thermal short-
circuit protection, and ±15kV ESD protection on the VCC
side for greater protection in applications that route sig-
nals externally. The MAX3372E/MAX3377E operate at a
guaranteed data rate of 230kbps. Slew-rate limiting
reduces EMI emissions in all 230kbps devices. The
MAX3373E–MAX3376E/MAX3378E/MAX3379E and
MAX3390E–MAX3393E operate at a guaranteed data rate
of 8Mbps over the entire specified operating voltage
range. Within specific voltage domains, higher data rates
are possible. (See the Timing Characteristics table.)
The MAX3372E–MAX3376E are dual level shifters
available in 3 x 3 UCSP™, 8-pin TDFN, and 8-pin
SOT23-8 packages. The MAX3377E/MAX3378E/
MAX3379E and MAX3390E–MAX3393E are quad level
shifters available in 3 x 4 UCSP, 14-pin TDFN, and 14-
pin TSSOP packages.
________________________Applications
SPI™, MICROWIRE™, and I2C Level
Translation
Low-Voltage ASIC Level Translation
Smart Card Readers
Cell-Phone Cradles
Portable POS Systems
Portable Communication Devices
Low-Cost Serial Interfaces
Cell Phones
GPS
Telecommunications Equipment
Features
♦Guaranteed Data Rate Options
230kbps
8Mbps (+1.2V ≤VL≤VCC ≤+5.5V)
10Mbps (+1.2V ≤VL≤VCC ≤+3.3V)
16Mbps (+1.8V ≤VL≤VCC ≤+2.5V and +2.5V
≤VL≤VCC ≤+3.3V)
♦Bidirectional Level Translation
(MAX3372E/MAX3373E and
MAX3377E/MAX3378E)
♦Operation Down to +1.2V on VL
♦±15kV ESD Protection on I/O VCC Lines
♦Ultra-Low 1µA Supply Current in Three-State
Output Mode
♦Low-Quiescent Current (130µA typ)
♦UCSP, TDFN, SOT23, and TSSOP Packages
♦Thermal Short-Circuit Protection
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
I/0 VCC1
I/0 VCC2
N.C.N.C.
I/O VL2
I/O VL1
MAX3377E/
MAX3378E
VL
I/0 VCC3
GND
I/O VL4
I/O VL3
TDFN-14
(3mm x 3mm)
THREE-STATE
I/0 VCC4
TOP VIEW
Pin Configurations
Ordering Information
UCSP is a trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Ordering Information continued at end of data sheet.
Selector Guide appears at end of data sheet.
Pin Configurations continued at end of data sheet.
PART TEMP
RANGE
PIN-
PACKAGE
PKG
CODE
MAX3372EEKA+T
-40°C to +85°C
8 SOT23
K8S-3
+Denotes a lead-free package.
T = Tape and reel.
Pin Configurations
19-2328; Rev 2; 11/07
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = +1.65V to +5.5V, VL= +1.2V to (VCC + 0.3V), GND = 0, I/O VL_ and I/O VCC_ unconnected, TA= TMIN to TMAX, unless other-
wise noted. Typical values are at VCC = +3.3V, VL= +1.8V, TA= +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND.)
VCC ...........................................................................-0.3V to +6V
I/O VCC_......................................................-0.3V to (VCC + 0.3V)
I/O VL_ ...........................................................-0.3V to (VL+ 0.3V)
THREE-STATE...............................................-0.3V to (VL+ 0.3V)
Short-Circuit Duration I/O VL, I/O VCC to GND...........Continuous
Short-Circuit Duration I/O VLor I/O VCC to GND
Driven from 40mA Source
(except MAX3372E and MAX3377E) .....................Continuous
Continuous Power Dissipation (TA= +70°C)
8-Pin SOT23 (derate 8.9mW/°C above +70°C)...........714mW
8-Pin TDFN (derate 18.2mW/°C above +70°C) ........1455mW
3 x 3 UCSP (derate 4.7mW/°C above +70°C) ............379mW
3 x 4 UCSP (derate 6.5mW/°C above +70°C) ............579mW
14-Pin TSSOP (derate 9.1mW/°C above +70°C) ........727mW
14-Pin TDFN (derate 18.2mW/°C above +70°C) ......1454mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS
POWER SUPPLIES
VL Supply Range VL
1.2 5.5
V
VCC Supply Range VCC
1.65 5.50
V
Supply Current from VCC IQVCC
130 300
µA
Supply Current from VLIQVL16
100
µA
VCC Three-State Output Mode
Supply Current
ITHREE-STATE-VCC
TA = +25°C, THREE-STATE = GND
0.03
1µA
VL Three-State Output Mode
Supply Current
ITHREE-STATE-VL
TA = +25°C, THREE-STATE = GND
0.03
1µA
Three-State Output Mode
Leakage Current
I/O VL_ and I/O VCC_
ITHREE-STATE-LKG
TA = +25°C, THREE-STATE = GND
0.02
1µA
THREE-STATE P in Inp ut Leakag eT
A = +25°C
0.02
1µA
ESD PROTECTION
IEC 1000-4-2 Air-Gap Discharge ±8
IEC 1000-4-2 Contact Discharge ±8I/O VCC (Note 3)
Human Body Model
±15
kV
LOGIC-LEVEL THRESHOLDS (MAX3372E/MAX3377E)
I/O VL_ Input-Voltage High VIHL VL - 0.2 V
I/O VL_ Input-Voltage Low VILL
0.15
V
2
Maxim Integrated
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +1.65V to +5.5V, VL= +1.2V to (VCC + 0.3V), GND = 0, I/O VL_ and I/O VCC_ unconnected, TA= TMIN to TMAX, unless other-
wise noted. Typical values are at VCC = +3.3V, VL= +1.8V, TA= +25°C.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS
I/O VCC_ Input-Voltage High VIHC VCC - 0.4 V
I/O VCC_ Input-Voltage Low VILC
0.15
V
I/O VL_ Output-Voltage High VOHL I/O VL_ source current = 20µA,
I/O VCC_
>
VCC - 0.4V 0.67 ✕ VLV
I/O VL_ Output-Voltage Low VOLL I/O VL_ sink current = 20µA,
I/O VCC_
<
0.15V
0.4
V
I/O VCC_ Output-Voltage High VOHC I/O VCC_ source current = 20µA,
I/O VL _
>
VL - 0.2V 0.67 ✕ VCC V
I/O VCC_ Output-Voltage Low VOLC I/O VCC_ sink current = 20µA,
I/O VL_
<
0.15V
0.4
V
THREE-STATE Input-Voltage
High
VIL-THREE-STATE
VL - 0.2 V
THREE-STATE Input-Voltage
Low
VIL-THREE-STATE 0.15
V
LOGIC-LEVEL THRESHOLDS (MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E)
I/O VL_ Input-Voltage High VIHL VL - 0.2 V
I/O VL_ Input-Voltage Low VILL
0.15
V
I/O VCC_ Input-Voltage High VIHC VCC - 0.4 V
I/O VCC_ Input-Voltage Low VILC
0.15
V
I/O VL_ Output-Voltage High VOHL I/O VL_ source current = 20µA,
I/O VCC_ ≥ VCC - 0.4V 0.67 ✕ VLV
I/O VL_ Output-Voltage Low VOLL I/O VL_ sink current = 1mA,
I/O VCC_ ≤ 0.15V
0.4
V
I/O VCC_ Output-Voltage High VOHC I/O VCC_ source current = 20µA,
I/O VL_ ≥ VL - 0.2V 0.67 ✕ VCC V
I/O VCC_ Output-Voltage Low VOLC I/O VCC_ sink current = 1mA,
I/O VL_ ≤ 0.15V
0.4
V
THREE-STATE Input-Voltage
High
VIH-THREE-STATE
VL - 0.2 V
THREE-STATE Input-Voltage
Low
VIL-THREE-STATE 0.15
V
Maxim Integrated
3
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
TIMING CHARACTERISTICS
(VCC = +1.65V to +5.5V, VL= +1.2V to (VCC + 0.3V), GND = 0, RLOAD = 1MΩ, I/O test signal of Figure 1, TA= TMIN to TMAX, unless
otherwise noted. Typical values are at VCC = +3.3V, VL= +1.8V, TA= +25°C, unless otherwise noted.) (Notes 1, 2)
PARAMETER
SYM B O L
CONDITIONS
MIN
TYP
MAX
UNITS
MAX3372E/MAX3377E (CLOAD = 50pF)
I/O VCC_ Rise Time (Note 4) tRVCC
1100
ns
I/O VCC_ Fall Time (Note 5) tFVCC
1000
ns
I/O VL _ Rise Time (Note 4) tRVL
600
ns
I/O VL _ Fall Time (Note 5) tFVL
1100
ns
I/OVL-VCC
Driving I/O VL _
1.6
Propagation Delay
I/OVCC-VL
Driving I/O VCC_
1.6
µs
Channel-to-Channel Skew tSKEW Each translator equally loaded
500
ns
Maximum Data Rate CL = 25pF
230
kbps
M A X3 3 7 3 E– M A X3 3 7 6 E/M A X3 3 7 8 E/ M A X3 3 7 9 E a n d M A X3 3 9 0 E– M A X3 3 9 3 E ( C
LOA D
= 15 p F , Dr iv e r O u t p u t Im p e d a n c e ≤ 5 0 Ω)
+1.2V ≤ VL ≤ VCC ≤ +5.5V
725
I/O VCC_ Rise Time (Note 4) tRVCC Open-drain driving
170 400
ns
637
I/O VCC_ Fall Time (Note 5) tFVCC Open-drain driving 20 50 ns
830
I/O VL _ Rise Time (Note 4) tRVL Open-drain driving
180 400
ns
330
I/O VL _ Fall Time (Note 5) tLFV Open-drain driving 30 60 ns
530
I/OVL-VCC
Driving I/O VL _Open-drain driving
210 1000
430
Propagation Delay
I/OVCC-VL
Driving I/O VCC_Open-drain driving
190 1000
ns
20
Channel-to-Channel Skew tSKEW Each translator
equally loaded Open-drain driving 50 ns
8
Mbps
Maximum Data Rate Open-drain driving
500
kbps
4
Maxim Integrated
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Note 1: All units are 100% production tested at TA= +25°C. Limits over the operating temperature range are guaranteed by design
and not production tested.
Note 2: For normal operation, ensure VL< (VCC + 0.3V). During power-up, VL> (VCC + 0.3V) will not damage the device.
Note 3: To ensure maximum ESD protection, place a 1µF capacitor between VCC and GND. See Applications Circuits.
Note 4: 10% to 90%
Note 5: 90% to 10%
TIMING CHARACTERISTICS (continued)
(VCC = +1.65V to +5.5V, VL= +1.2V to (VCC + 0.3V), GND = 0, RLOAD = 1MΩ, I/O test signal of Figure 1, TA= TMIN to TMAX, unless
otherwise noted. Typical values are at VCC = +3.3V, VL= +1.8V, TA= +25°C, unless otherwise noted.) (Notes 1, 2)
PARAMETER
SYM B O L
CONDITIONS
MIN TYP MAX
UNITS
+1.2V ≤ VL ≤ VCC ≤ +3.3V
I/O VCC_ Rise Time (Note 4) tRVCC 25 ns
I/O VCC_ Fall Time (Note 5) tFVCC 30 ns
I/O VL _ Rise Time (Note 4) tRVL 30 ns
I/O VL _ Fall Time (Note 5) tFVL 30 ns
I/OVL-VCC
Driving I/O VL _20
Propagation Delay
I/OVCC-VL
Driving I/O VCC_20
ns
Channel-to-Channel Skew tSKEW Each translator equally loaded 10 ns
Maximum Data Rate 10
Mbps
+2.5V ≤ VL ≤ VCC ≤ +3.3V
I/O VCC_ Rise Time (Note 4) tRVCC 15 ns
I/O VCC_ Fall Time (Note 5) tFVCC 15 ns
I/O VL _ Rise Time (Note 4) tRVL 15 ns
I/O VL _ Fall Time (Note 5) tFVL 15 ns
I/OVL-VCC
Driving I/O VL _15
Propagation Delay
I/OVCC-VL
Driving I/O VCC_15
ns
Channel-to-Channel Skew tSKEW Each translator equally loaded 10 ns
Maximum Data Rate 16
Mbps
+1.8V ≤ VL ≤ VCC ≤ +2.5V
I/O VCC_ Rise Time (Note 4) tRVCC 15 ns
I/O VCC_ Fall Time (Note 5) tFVCC 15 ns
I/O VL _ Rise Time (Note 4) tRVL 15 ns
I/O VL _ Fall Time (Note 5) tFVL 15 ns
I/OVL-VCC
Driving I/O VL _15
Propagation Delay
I/OVCC-VL
Driving I/O VCC_15
ns
Channel-to-Channel Skew tSKEW Each translator equally loaded 10 ns
Maximum Data Rate 16
Mbps
Maxim Integrated
5
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Typical Operating Characteristics
(RLOAD = 1MΩ, TA = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and
500kbps TOCs apply to MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E only.)
VL SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
MAX3372E toc01
VCC (V)
SUPPLY CURRENT (μA)
4.954.403.853.302.752.20
100
200
300
400
500
600
0
1.65 5.50
8Mbps, CLOAD = 15pF
230kbps, CLOAD = 50pF
500kbps, OPEN-DRAIN, CLOAD = 15pF
VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
MAX3372E toc02
VCC (V)
SUPPLY CURRENT (mA)
4.954.403.853.302.752.20
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
1.65 5.50
8Mbps, CLOAD = 15pF
230kbps, CLOAD = 50pF
500kbps, OPEN-DRAIN, CLOAD = 15pF
VL SUPPLY CURRENT vs. TEMPERATURE
(DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V)
MAX3372E toc03
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
6035-15 10
50
100
150
200
250
300
350
400
0
-40 85
8Mbps, CLOAD = 15pF
230kbps, CLOAD = 50pF
500kbps, OPEN-DRAIN, CLOAD = 15pF
VCC SUPPLY CURRENT vs. TEMPERATURE
(DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V)
MAX3372E toc04
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
6035-15 10
200
400
600
800
1000
1200
1400
1600
0
-40 85
8Mbps, CLOAD = 15pF
230kbps, CLOAD = 50pF
500kbps, OPEN-DRAIN, CLOAD = 15pF
VL SUPPLY CURRENT vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
MAX3372E toc05
CAPACITIVE LOAD (pF)
SUPPLY CURRENT (μA)
8570554025
50
100
150
200
250
300
350
0
10 100
8Mbps
230kbps
500kbps, OPEN-DRAIN
VCC SUPPLY CURRENT vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
MAX3372E toc06
CAPACITIVE LOAD (pF)
SUPPLY CURRENT (μA)
8570554025
500
1000
1500
2000
2500
0
10 100
8Mbps
230kbps
500kbps, OPEN-DRAIN
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
MAX3372E toc07
CAPACITIVE LOAD (pF)
RISE/FALL TIME (ns)
90807060504030
500
1000
1500
2000
2500
0
20 100
DATA RATE = 230kbps
tHL
tLH
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
MAX3372E toc08
CAPACITIVE LOAD (pF)
RISE/FALL TIME (ns)
454030 3520 2515
2
4
6
8
10
12
14
16
18
0
10 50
DATA RATE = 8Mbps
tHL
tLH
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
MAX3372E toc09
CAPACITIVE LOAD (pF)
RISE/FALL TIME (ns)
45403530252015
50
100
150
200
250
0
10 50
tLH
tHL
DATA RATE = 500kbps,
OPEN-DRAIN
6
Maxim Integrated
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
PROPAGATION DELAY vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
MAX3372E toc10
CAPACITIVE LOAD (pF)
PROPAGATION DELAY (ns)
90807060504030
100
200
300
400
500
600
700
0
20 100
DATA RATE = 230kbps
tPHL
tPLH
PROPAGATION DELAY vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
MAX3372E toc11
CAPACITIVE LOAD (pF)
PROPAGATION DELAY (ns)
45403530252015
3
6
9
12
15
0
10 50
DATA RATE = 8Mbps
tPLH
tPHL
PROPAGATION DELAY vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V)
MAX3372E toc12
CAPACITIVE LOAD (pF)
PROPAGATION DELAY (ns)
45403530252015
50
100
150
200
250
300
0
10 50
DATA RATE = 500kbps,
OPEN-DRAIN
tPHL
tPLH
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +2.5V, VL = +1.8V)
MAX3372E toc13
CAPACITIVE LOAD (pF)
RISE/FALL TIME (ns)
90807060504030
500
1000
1500
2000
2500
0
20 100
DATA RATE = 230kbps
tHL
tLH
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VL, VCC = +2.5V, VL = +1.8V)
MAX3372E toc14
CAPACITIVE LOAD (pF)
RISE/FALL TIME (ns)
45403530252015
2
4
6
8
10
12
14
0
10 50
DATA RATE = 8Mbps
tLH
tHL
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +2.5V, VL = +1.8V)
MAX3372E toc15
CAPACITIVE LOAD (pF)
RISE/FALL TIME (ns)
45403530252015
50
100
150
200
250
300
0
10 50
DATA RATE = 500kbps,
OPEN-DRAIN
tHL
tLH
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V)
MAX3372E toc16
CAPACITIVE LOAD (pF)
RISE/FALL TIME (ns)
90807060504030
500
1000
1500
2000
2500
0
20 100
DATA RATE = 230kbps
tLH
tHL
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V)
MAX3372E toc17
CAPACITIVE LOAD (pF)
RISE/FALL TIME (ns)
45403530252015
2
4
6
8
10
12
0
10 50
DATA RATE = 8Mbps
tHL
tLH
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V)
MAX3372E toc18
CAPACITIVE LOAD (pF)
RISE/FALL TIME (ns)
45403530252015
50
100
150
200
250
300
0
10 50
DATA RATE = 500kbps,
OPEN-DRAIN
tHL
tLH
Typical Operating Characteristics (continued)
(RLOAD = 1MΩ, TA = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and
500kbps TOCs apply to MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E only.)
Maxim Integrated
7
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Typical Operating Characteristics (continued)
(RLOAD = 1MΩ, TA = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and
500kbps TOCs apply to MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E only.)
PROPAGATION DELAY vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V)
MAX3372E toc19
CAPACITIVE LOAD (pF)
PROPAGATION DELAY (ns)
90807060504030
100
200
300
400
500
600
700
0
20 100
DATA RATE = 230kbps
tPHL
tPHL
PROPAGATION DELAY vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V)
MAX3372E toc20
CAPACITIVE LOAD (pF)
PROPAGATION DELAY (ns)
45403530252015
1
2
3
4
5
6
0
10 50
DATA RATE = 8Mbps
tPLH
tPHL
PROPAGATION DELAY vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V)
MAX3372E toc21
CAPACITIVE LOAD (pF)
PROPAGATION DELAY (ns)
45403530252015
50
100
150
200
250
300
0
10 50
DATA RATE = 500kbps,
OPEN-DRAIN
tPHL
tPLH
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +2.5V, VL = +1.8V)
MAX3372E toc22
CAPACITIVE LOAD (pF)
RISE/FALL TIME (ns)
90807060504030
500
1000
1500
2000
2500
0
20 100
DATA RATE = 230kbps
tLH
tHL
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +2.5V, VL = +1.8V)
MAX3372E toc23
CAPACITIVE LOAD (pF)
RISE/FALL TIME (ns)
403020
2
4
6
8
10
12
0
10 50
tLH
tHL
DATA RATE = 8Mbps
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O VCC, VCC = +2.5V, VL = +1.8V)
MAX3373E toc24
CAPACITIVE LOAD (pF)
RISE/FALl TIME (ns)
403020
50
100
150
200
250
300
350
0
10 50
DATA RATE = 500kbps,
OPEN-DRAIN
tLH
tHL
RAIL-TO-RAIL DRIVING
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V,
CLOAD = 50pF, DATA RATE = 230kbps)
MAX3372E toc25
I/O VL_
I/O VCC_
1V/div
2V/div
1μs/div
RAIL-TO-RAIL DRIVING
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V,
CLOAD = 15pF, DATA RATE = 8Mbps)
MAX3372E toc26
I/O VL_
I/O VCC_
1V/div
2V/div
200ns/div
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
8
Maxim Integrated
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Typical Operating Characteristics (continued)
(RLOAD = 1MΩ, TA = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and
500kbps TOCs apply to MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E only.)
EXITING THREE-STATE OUTPUT MODE
(VCC = +3.3V, VL = +1.8V, CLOAD = 50pF)
MAX3372E toc28
I/O VL_
I/O VCC_
2μs/div
THREE-STATE
2V/div
1V/div
1V/div
Pin Description
PIN
3 x 4
UCSP
TSSOP SOT23-8
3 x 3
UCSP
TDFN
8
TDFN
14
NAME FUNCTION
A1 2 5 C2 6 1 I/O VL1Input/Output 1. Referenced to VL. (Note 6)
A2 3 4 C3 8 2 I/O VL2Input/Output 2. Referenced to VL. (Note 6)
A3 4 — — — 5 I/O VL3Input/Output 3. Referenced to VL. (Note 6)
A4 5 — — — 6 I/O VL4Input/Output 4. Referenced to VL. (Note 6)
B1 14 7 A1 4 14 VCC VCC Input Voltage +1.65V ≤ VCC ≤ +5.5V.
B2 1 3 C1 7 10 VLLogic Input Voltage +1.2V ≤ VL ≤ (VCC + 0.3V)
B3 8 6 B1 5 3 THREE-
STATE
Thr ee- S tate Outp ut M od e E nab l e. P ul l THREE-STATE l ow
to p l ace d evi ce i n thr ee- state outp ut m od e. I/O V
C C _
and
I/O V
L_ ar e hi g h i m p ed ance i n thr ee- state outp ut m od e.
N o t e : Log i c r efer enced to V
L ( for l og i c thr eshol d s see the
E l ectr i cal C har acter i sti cs tab l e) .
B4 7 2 B3 2 7 GND Ground
C1 13 8 A2 3 13 I/O VCC1Input/Output 1. Referenced to VCC. (Note 6)
C2 12 1 A3 1 12 I/O VCC2Input/Output 2. Referenced to VCC. (Note 6)
C3 11 — — — 9 I/O VCC3Input/Output 3. Referenced to VCC. (Note 6)
C4 10 — — — 8 I/O VCC4Input/Output 4. Referenced to VCC. (Note 6)
—6, 9 — B2 —
4, 11
N.C. No Connection. Not internally connected.
— — — — EP EP EP Exposed Pad. Connect to ground.
Note 6: For unidirectional devices (MAX3374E/MAX3375E/MAX3376E/MAX3379E and MAX3390E–MAX3393E) see the Pin
Configurations for input/output configurations.
OPEN-DRAIN DRIVING
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V,
CLOAD = 15pF, DATA RATE = 500kbps)
MAX3372E toc27
I/O VL_
I/O VCC_
1V/div
2V/div
200ns/div
Maxim Integrated
9
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Detailed Description
The MAX3372E–MAX3379E and MAX3390E–MAX3393E
ESD-protected level translators provide the level shifting
necessary to allow data transfer in a multivoltage system.
Externally applied voltages, VCC and VL, set the logic lev-
els on either side of the device. A low-voltage logic signal
present on the VLside of the device appears as a high-
voltage logic signal on the VCC side of the device, and
vice-versa. The MAX3374E/MAX3375E/MAX3376E/
MAX3379E and MAX3390E–MAX3393E unidirectional
level translators level shift data in one direction (VL→
VCC or VCC →VL) on any single data line. The
MAX3372E/MAX3373E and MAX3377E/MAX3378E bidi-
rectional level translators utilize a transmission-gate-
based design (see Figure 2) to allow data translation in
either direction (VL↔VCC) on any single data line. The
MAX3372E–MAX3379E and MAX3390E–MAX3393E
accept VLfrom +1.2V to +5.5V and VCC from +1.65V to
+5.5V, making them ideal for data transfer between low-
voltage ASICs/PLDs and higher voltage systems.
All devices in the MAX3372E–MAX3379E, MAX3390E–
MAX3393E family feature a three-state output mode that
reduces supply current to less than 1µA, thermal short-
circuit protection, and ±15kV ESD protection on the VCC
side for greater protection in applications that route sig-
nals externally. The MAX3372E/MAX3377E operate at a
guaranteed data rate of 230kbps. Slew-rate limiting
reduces EMI emissions in all 230kbps devices. The
MAX3373E–MAX3376E/MAX3378E/MAX3379E and
MAX3390E–MAX3393E operate at a guaranteed data rate
of 8Mbps over the entire specified operating voltage
range. Within specific voltage domains, higher data rates
are possible. (See the Timing Characteristics table.)
MAX3372E–MAX3379E
AND MAX3390E–MAX3393E
I/O VL_
I/O VL_
(tRISE,
tFALL < 10ns)
DATA
I/O VCC_
RLOAD CLOAD
VCC
VCC
VL
VL
GND
tPD-VCC-LH tPD-VCC-HL
I/O VCC_
tRVCC tFVCC
Figure 1a. Rail-to-Rail Driving I/O VL
MAX3372E–MAX3379E
AND MAX3390E–MAX3393E
I/O VL_
I/O VCC_
(tRISE,
tFALL < 10ns)
DATA
I/O VCC_
VCC
VCC
VL
VL
GND
RLOAD
CLOAD
tPD-VL-LH tPD-VL-HL
I/O VL_
tRVL tFVL
Figure 1b. Rail-to-Rail Driving I/O VCC
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
10
Maxim Integrated
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Level Translation
For proper operation ensure that +1.65V ≤VCC ≤
+5.5V, +1.2V ≤VL≤+5.5V, and VL≤(VCC + 0.3V).
During power-up sequencing, VL≥(VCC + 0.3V) will
not damage the device. During power-supply sequenc-
ing, when VCC is floating and VLis powering up, a cur-
rent may be sourced, yet the device will not latch up.
The speed-up circuitry limits the maximum data rate for
devices in the MAX3372E–MAX3379E, MAX3390E–
MAX3393E family to 16Mbps. The maximum data rate
also depends heavily on the load capacitance (see the
Typical Operating Characteristics), output impedance
of the driver, and the operational voltage range (see the
Timing Characteristics table).
Speed-Up Circuitry
The MAX3373E–MAX3376E/MAX3378E/MAX3379E and
MAX3390E–MAX3393E feature a one-shot generator that
decreases the rise time of the output. When triggered,
MOSFETs PU1 and PU2 turn on for a short time to pull up
I/O VL_ and I/O VCC_ to their respective supplies (see
Figure 2b). This greatly reduces the rise time and propa-
gation delay for the low-to-high transition. The scope
photo of Rail-to-Rail Driving for 8Mbps Operation in the
Typical Operating Characteristics shows the speed-up
circuitry in operation.
Rise-Time Accelerators
The MAX3373E–MAX3376E/MAX3378E/MAX3379E and
the MAX3390E–MAX3393E have internal rise-time
accelerators allowing operation up to 16Mbps. The
rise-time accelerators are present on both sides of the
device and act to speed up the rise time of the input
and output of the device, regardless of the direction of
the data. The triggering mechanism for these accelera-
tors is both level and edge sensitive. To prevent false
triggering of the rise-time accelerators, signal fall times
of less than 20ns/V are recommended for both the
inputs and outputs of the device. Under less noisy con-
ditions, longer signal fall times may be acceptable.
MAX3372E–MAX3379E
AND MAX3390E–MAX3393E
I/O VL_ I/O VCC_
VCC
VCC
VL
VL
GND
I/O VCC_
tPD-VCC-LH
tPD-VCC-HL
I/O VL_
tRVCC tFVCC
DATA
RLOAD
CLOAD
Figure 1c. Open-Drain Driving I/O VCC
MAX3373E–MAX3376E,
MAX3378E/MAX3379E
AND MAX3390E–MAX3393E
I/O VL_
I/O VCC_
DATA
I/O VCC_
VCC
VCC
VL
VL
GND
RLOAD
CLOAD
tPD-VL-LH
tPD-VL-HL
I/O VL_
tRVL tFVL
Figure 1d. Open-Drain Driving I/O VL
Maxim Integrated
11
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC 1MΩRD 1500Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE-
UNDER-
TEST
Figure 3a. Human Body ESD Test Model
IP 100%
90%
36.8%
tRL TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
0
AMPERES
Figure 3b. Human Body Current Waveform
±15kV ESD Protection
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assembly.
The I/O VCC lines have extra protection against static
electricity. Maxim’s engineers have developed state-of-
the-art structures to protect these pins against ESD of
±15kV without damage. The ESD structures withstand
high ESD in all states: normal operation, three-state
output mode, and powered down. After an ESD event,
Maxim’s E versions keep working without latchup,
whereas competing products can latch and must be
powered down to remove latchup.
ESD protection can be tested in various ways. The I/O
VCC lines of this product family are characterized for
protection to the following limits:
1) ±15kV using the Human Body Model
2) ±8kV using the Contact Discharge method specified
in IEC 1000-4-2
3) ±10kV using IEC 1000-4-2’s Air-Gap Discharge
method
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
Human Body Model
Figure 3a shows the Human Body Model and Figure 3b
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
est, which is then discharged into the test device
through a 1.5kΩresistor.
IEC 1000-4-2
The IEC 1000-4-2 standard covers ESD testing and
performance of finished equipment; it does not specifi-
cally refer to integrated circuits. The MAX3372E–
MAX3379E and MAX3390E–MAX3393E help to design
equipment that meets Level 3 of IEC 1000-4-2, without
the need for additional ESD-protection components.
The major difference between tests done using the
Human Body Model and IEC 1000-4-2 is higher peak
current in IEC 1000-4-2, because series resistance is
lower in the IEC 1000-4-2 model. Hence, the ESD with-
stand voltage measured to IEC 1000-4-2 is generally
lower than that measured using the Human Body Model.
Figure 4a shows the IEC 1000-4-2 model, and Figure 4b
shows the current waveform for the ±8kV, IEC 1000-4-2,
Level 4, ESD contact-discharge test.
The air-gap test involves approaching the device with a
charged probe. The contact-discharge method con-
nects the probe to the device before the probe
is energized.
Machine Model
The Machine Model for ESD tests all pins using a
200pF storage capacitor and zero discharge resis-
tance. Its objective is to emulate the stress caused by
contact that occurs with handling and assembly during
manufacturing. Of course, all pins require this protec-
tion during manufacturing, not just inputs and outputs.
Therefore, after PCB assembly, the Machine Model is
less relevant to I/O ports.
12
Maxim Integrated
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Three-State Output Mode
Pull THREE-STATE low to place the MAX3372E–
MAX3379E and MAX3390E–MAX3393E in three-state out-
put mode. Connect THREE-STATE to VL(logic-high) for
normal operation. Activating the three-state output mode
disconnects the internal 10kΩpullup resistors on the I/O
VCC and I/O VLlines. This forces the I/O lines to a high-
impedance state, and decreases the supply current to
less than 1µA. The high-impedance I/O lines in three-
state output mode allow for use in a multidrop network.
When in three-state output mode, do not allow the voltage
at I/O VL_ to exceed (VL+ 0.3V), or the voltage at I/O
VCC_ to exceed (VCC + 0.3V).
Thermal Short-Circuit Protection
Thermal overload detection protects the MAX3372E–
MAX3379E and MAX3390E–MAX3393E from short-circuit
fault conditions. In the event of a short-circuit fault, when
the junction temperature (TJ) reaches +152°C, a thermal
sensor signals the three-state output mode logic to force
the device into three-state output mode. When TJhas
cooled to +142°C, normal operation resumes.
VCC
I/O VLI/O VCC
GATE
BIAS
VL
P P
N
Figure 2a. Functional Diagram, MAX3372E/MAX3377E (1 I/O line)
VCC
I/O VL_ I/O VCC_
GATE
BIAS
VL
PU1 PU2
N
ONE-SHOT
BLOCK
ONE-SHOT
BLOCK
Figure 2b. Functional Diagram, MAX3373E/MAX3378E (1 I/O line)
Maxim Integrated
13
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Level Translation
For proper operation ensure that +1.65V ≤VCC ≤
+5.5V, +1.2V ≤VL≤+5.5V, and VL≤(VCC + 0.3V).
During power-up sequencing, VL≥(VCC + 0.3V) will
not damage the device. During power-supply sequenc-
ing, when VCC is floating and VLis powering up, a cur-
rent may be sourced, yet the device will not latch up.
The speed-up circuitry limits the maximum data rate for
devices in the MAX3372E–MAX3379E, MAX3390E–
MAX3393E family to 16Mbps. The maximum data rate
also depends heavily on the load capacitance (see the
Typical Operating Characteristics), output impedance
of the driver, and the operational voltage range (see the
Timing Characteristics table).
Speed-Up Circuitry
The MAX3373E–MAX3376E/MAX3378E/MAX3379E and
MAX3390E–MAX3393E feature a one-shot generator that
decreases the rise time of the output. When triggered,
MOSFETs PU1 and PU2 turn on for a short time to pull up
I/O VL_ and I/O VCC_ to their respective supplies (see
Figure 2b). This greatly reduces the rise time and propa-
gation delay for the low-to-high transition. The scope
photo of Rail-to-Rail Driving for 8Mbps Operation in the
Typical Operating Characteristics shows the speed-up
circuitry in operation.
Rise-Time Accelerators
The MAX3373E–MAX3376E/MAX3378E/MAX3379E and
the MAX3390E–MAX3393E have internal rise-time
accelerators allowing operation up to 16Mbps. The
rise-time accelerators are present on both sides of the
device and act to speed up the rise time of the input
and output of the device, regardless of the direction of
the data. The triggering mechanism for these accelera-
tors is both level and edge sensitive. To prevent false
triggering of the rise-time accelerators, signal fall times
of less than 20ns/V are recommended for both the
inputs and outputs of the device. Under less noisy con-
ditions, longer signal fall times may be acceptable.
MAX3372E–MAX3379E
AND MAX3390E–MAX3393E
I/O VL_ I/O VCC_
VCC
VCC
VL
VL
GND
I/O VCC_
tPD-VCC-LH
tPD-VCC-HL
I/O VL_
tRVCC tFVCC
DATA
RLOAD
CLOAD
Figure 1c. Open-Drain Driving I/O VCC
MAX3373E–MAX3376E,
MAX3378E/MAX3379E
AND MAX3390E–MAX3393E
I/O VL_
I/O VCC_
DATA
I/O VCC_
VCC
VCC
VL
VL
GND
RLOAD
CLOAD
tPD-VL-LH
tPD-VL-HL
I/O VL_
tRVL tFVL
Figure 1d. Open-Drain Driving I/O VL
14
Maxim Integrated
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Detailed Description
The MAX3372E–MAX3379E and MAX3390E–MAX3393E
ESD-protected level translators provide the level shifting
necessary to allow data transfer in a multivoltage system.
Externally applied voltages, VCC and VL, set the logic lev-
els on either side of the device. A low-voltage logic signal
present on the VLside of the device appears as a high-
voltage logic signal on the VCC side of the device, and
vice-versa. The MAX3374E/MAX3375E/MAX3376E/
MAX3379E and MAX3390E–MAX3393E unidirectional
level translators level shift data in one direction (VL→
VCC or VCC →VL) on any single data line. The
MAX3372E/MAX3373E and MAX3377E/MAX3378E bidi-
rectional level translators utilize a transmission-gate-
based design (see Figure 2) to allow data translation in
either direction (VL↔VCC) on any single data line. The
MAX3372E–MAX3379E and MAX3390E–MAX3393E
accept VLfrom +1.2V to +5.5V and VCC from +1.65V to
+5.5V, making them ideal for data transfer between low-
voltage ASICs/PLDs and higher voltage systems.
All devices in the MAX3372E–MAX3379E, MAX3390E–
MAX3393E family feature a three-state output mode that
reduces supply current to less than 1µA, thermal short-
circuit protection, and ±15kV ESD protection on the VCC
side for greater protection in applications that route sig-
nals externally. The MAX3372E/MAX3377E operate at a
guaranteed data rate of 230kbps. Slew-rate limiting
reduces EMI emissions in all 230kbps devices. The
MAX3373E–MAX3376E/MAX3378E/MAX3379E and
MAX3390E–MAX3393E operate at a guaranteed data rate
of 8Mbps over the entire specified operating voltage
range. Within specific voltage domains, higher data rates
are possible. (See the Timing Characteristics table.)
MAX3372E–MAX3379E
AND MAX3390E–MAX3393E
I/O VL_
I/O VL_
(tRISE,
tFALL < 10ns)
DATA
I/O VCC_
RLOAD CLOAD
VCC
VCC
VL
VL
GND
tPD-VCC-LH tPD-VCC-HL
I/O VCC_
tRVCC tFVCC
Figure 1a. Rail-to-Rail Driving I/O VL
MAX3372E–MAX3379E
AND MAX3390E–MAX3393E
I/O VL_
I/O VCC_
(tRISE,
tFALL < 10ns)
DATA
I/O VCC_
VCC
VCC
VL
VL
GND
RLOAD
CLOAD
tPD-VL-LH tPD-VL-HL
I/O VL_
tRVL tFVL
Figure 1b. Rail-to-Rail Driving I/O VCC
Maxim Integrated
15
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Typical Operating Characteristics (continued)
(RLOAD = 1MΩ, TA = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and
500kbps TOCs apply to MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E only.)
EXITING THREE-STATE OUTPUT MODE
(VCC = +3.3V, VL = +1.8V, CLOAD = 50pF)
MAX3372E toc28
I/O VL_
I/O VCC_
2μs/div
THREE-STATE
2V/div
1V/div
1V/div
Pin Description
PIN
3 x 4
UCSP
TSSOP SOT23-8
3 x 3
UCSP
TDFN
8
TDFN
14
NAME FUNCTION
A1 2 5 C2 6 1 I/O VL1Input/Output 1. Referenced to VL. (Note 6)
A2 3 4 C3 8 2 I/O VL2Input/Output 2. Referenced to VL. (Note 6)
A3 4 — — — 5 I/O VL3Input/Output 3. Referenced to VL. (Note 6)
A4 5 — — — 6 I/O VL4Input/Output 4. Referenced to VL. (Note 6)
B1 14 7 A1 4 14 VCC VCC Input Voltage +1.65V ≤ VCC ≤ +5.5V.
B2 1 3 C1 7 10 VLLogic Input Voltage +1.2V ≤ VL ≤ (VCC + 0.3V)
B3 8 6 B1 5 3 THREE-
STATE
Thr ee- S tate Outp ut M od e E nab l e. P ul l THREE-STATE l ow
to p l ace d evi ce i n thr ee- state outp ut m od e. I/O V
C C _
and
I/O V
L_ ar e hi g h i m p ed ance i n thr ee- state outp ut m od e.
N o t e : Log i c r efer enced to V
L ( for l og i c thr eshol d s see the
E l ectr i cal C har acter i sti cs tab l e) .
B4 7 2 B3 2 7 GND Ground
C1 13 8 A2 3 13 I/O VCC1Input/Output 1. Referenced to VCC. (Note 6)
C2 12 1 A3 1 12 I/O VCC2Input/Output 2. Referenced to VCC. (Note 6)
C3 11 — — — 9 I/O VCC3Input/Output 3. Referenced to VCC. (Note 6)
C4 10 — — — 8 I/O VCC4Input/Output 4. Referenced to VCC. (Note 6)
—6, 9 — B2 —
4, 11
N.C. No Connection. Not internally connected.
— — — — EP EP EP Exposed Pad. Connect to ground.
Note 6: For unidirectional devices (MAX3374E/MAX3375E/MAX3376E/MAX3379E and MAX3390E–MAX3393E) see the Pin
Configurations for input/output configurations.
OPEN-DRAIN DRIVING
(DRIVING I/O VL, VCC = +3.3V, VL = +1.8V,
CLOAD = 15pF, DATA RATE = 500kbps)
MAX3372E toc27
I/O VL_
I/O VCC_
1V/div
2V/div
200ns/div
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
16
Maxim Integrated
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Applications Circuits (continued)
MAX3377E/MAX3378E
THREE-STATE
I/O VL4
I/O VL3
I/O VL1
I/O VL2 DATADATA
I/O VCC1
I/O VCC2
I/O VCC3
I/O VCC4
0.1μF0.1μF 1μF
+3.3V+1.8V
VCC
+3.3V
SYSTEM
+1.8V
SYSTEM
CONTROLLER
VL
MAX3379E
THREE-STATE
DATADATA
0.1μF
0.1μF 1μF
+3.3V+1.8V
VCC
+3.3V
SYSTEM
+1.8V
SYSTEM
CONTROLLER
VL
I VL4
I VL3
I VL1
I VL2
O VCC1
O VCC2
O VCC3
O VCC4
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
Maxim Integrated
17
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Applications Circuits (continued)
MAX3390E
THREE-STATE
DATADATA
0.1μF
0.1μF 1μF
+3.3V+1.8V
VCC
+3.3V
SYSTEM
+1.8V
SYSTEM
CONTROLLER
VL
I VL4
O VL1
I VL2
I VL3
I VL1
O VCC2
O VCC3
O VCC4
MAX3391E
THREE-STATE
DATADATA
0.1μF
0.1μF 1μF
+3.3V+1.8V
VCC
+3.3V
SYSTEM
+1.8V
SYSTEM
CONTROLLER
VL
I VL4
O VL1
O VL2
I VL3
I VCC1
I VCC2
O VCC3
O VCC4
18
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
Maxim Integrated
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Applications Circuits (continued)
MAX3392E
THREE-STATE
DATADATA
0.1μF
0.1μF 1μF
+3.3V+1.8V
VCC
+3.3V
SYSTEM
+1.8V
SYSTEM
CONTROLLER
VL
I VL4
O VL1
O VL2
O VL3
I VCC1
I VCC2
I VCC3
O VCC4
MAX3393E
THREE-STATE
DATADATA
0.1μF
0.1μF 1μF
+3.3V+1.8V
VCC
+3.3V
SYSTEM
+1.8V
SYSTEM
CONTROLLER
VL
I VL4
O VL1
O VL2
O VL3
I VCC1
I VCC2
I VCC3
I VCC4
19
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
Maxim Integrated
MAX3372E/MAX3373E
THREE-STATE
I/O VL2
I/O VL1
DATADATA I/O VCC2
I/O VCC1
0.1μF0.1μF 1μF
+3.3V+1.8V
VCC
+3.3V
SYSTEM
+1.8V
SYSTEM
CONTROLLER
VL
MAX3374E
THREE-STATE
I VL2
I VL1
DATADATA
O VCC1
O VCC2
0.1μF0.1μF 1μF
+3.3V+1.8V
VCC
+3.3V
SYSTEM
+1.8V
SYSTEM
CONTROLLER
VL
Applications Circuits
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
20
Maxim Integrated
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Applications Information
Power-Supply Decoupling
To reduce ripple and the chance of transmitting incor-
rect data, bypass VLand VCC to ground with a 0.1µF
capacitor. See the Typical Operating Circuit. To ensure
full ±15kV ESD protection, bypass VCC to ground with a
1µF capacitor. Place all capacitors as close to the
power-supply inputs as possible.
I2C Level Translation
The MAX3373E–MAX3376E, MAX3378E/MAX3379E
and MAX3390E–MAX3393E level-shift the data present
on the I/O lines between +1.2V and +5.5V, making
them ideal for level translation between a low-voltage
ASIC and an I2C device. A typical application involves
interfacing a low-voltage microprocessor to a 3V or 5V
D/A converter, such as the MAX517.
Push-Pull vs. Open-Drain Driving
All devices in the MAX3372E–MAX3379E and
MAX3390E–MAX3393E family may be driven in a push-
pull configuration. The MAX3373E–MAX3376E/
MAX3378E/MAX3379E and MAX3390E–MAX3393E
include internal 10kΩresistors that pull up I/O VL_ and
I/O VCC_ to their respective power supplies, allowing
operation of the I/O lines with open-drain devices. See
the Timing Characteristics table for maximum data rates
when using open-drain drivers.
tr = 0.7ns to 1ns
30ns
60ns
t
100%
90%
10%
IPEAK
I
Figure 4b. IEC 1000-4-2 ESD Generator Current Waveform
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
150pF
RC 50MΩ to 100MΩRD 330Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE-
UNDER-
TEST
Figure 4a. IEC 1000-4-2 ESD Test Model
MAX3378E–MAX3383E
THREE-STATE
I/O VL_ DATA
DATA I/O VCC_
0.1μF0.1μF1μF
+3.3V+1.8V
VCC
+3.3V
SYSTEM
+1.8V
SYSTEM
CONTROLLER
VL
Typical Operating Circuit
Maxim Integrated
21
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC 1MΩRD 1500Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE-
UNDER-
TEST
Figure 3a. Human Body ESD Test Model
IP 100%
90%
36.8%
tRL TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
0
AMPERES
Figure 3b. Human Body Current Waveform
±15kV ESD Protection
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assembly.
The I/O VCC lines have extra protection against static
electricity. Maxim’s engineers have developed state-of-
the-art structures to protect these pins against ESD of
±15kV without damage. The ESD structures withstand
high ESD in all states: normal operation, three-state
output mode, and powered down. After an ESD event,
Maxim’s E versions keep working without latchup,
whereas competing products can latch and must be
powered down to remove latchup.
ESD protection can be tested in various ways. The I/O
VCC lines of this product family are characterized for
protection to the following limits:
1) ±15kV using the Human Body Model
2) ±8kV using the Contact Discharge method specified
in IEC 1000-4-2
3) ±10kV using IEC 1000-4-2’s Air-Gap Discharge
method
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
Human Body Model
Figure 3a shows the Human Body Model and Figure 3b
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
est, which is then discharged into the test device
through a 1.5kΩresistor.
IEC 1000-4-2
The IEC 1000-4-2 standard covers ESD testing and
performance of finished equipment; it does not specifi-
cally refer to integrated circuits. The MAX3372E–
MAX3379E and MAX3390E–MAX3393E help to design
equipment that meets Level 3 of IEC 1000-4-2, without
the need for additional ESD-protection components.
The major difference between tests done using the
Human Body Model and IEC 1000-4-2 is higher peak
current in IEC 1000-4-2, because series resistance is
lower in the IEC 1000-4-2 model. Hence, the ESD with-
stand voltage measured to IEC 1000-4-2 is generally
lower than that measured using the Human Body Model.
Figure 4a shows the IEC 1000-4-2 model, and Figure 4b
shows the current waveform for the ±8kV, IEC 1000-4-2,
Level 4, ESD contact-discharge test.
The air-gap test involves approaching the device with a
charged probe. The contact-discharge method con-
nects the probe to the device before the probe
is energized.
Machine Model
The Machine Model for ESD tests all pins using a
200pF storage capacitor and zero discharge resis-
tance. Its objective is to emulate the stress caused by
contact that occurs with handling and assembly during
manufacturing. Of course, all pins require this protec-
tion during manufacturing, not just inputs and outputs.
Therefore, after PCB assembly, the Machine Model is
less relevant to I/O ports.
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
22
Maxim Integrated
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Three-State Output Mode
Pull THREE-STATE low to place the MAX3372E–
MAX3379E and MAX3390E–MAX3393E in three-state out-
put mode. Connect THREE-STATE to VL(logic-high) for
normal operation. Activating the three-state output mode
disconnects the internal 10kΩpullup resistors on the I/O
VCC and I/O VLlines. This forces the I/O lines to a high-
impedance state, and decreases the supply current to
less than 1µA. The high-impedance I/O lines in three-
state output mode allow for use in a multidrop network.
When in three-state output mode, do not allow the voltage
at I/O VL_ to exceed (VL+ 0.3V), or the voltage at I/O
VCC_ to exceed (VCC + 0.3V).
Thermal Short-Circuit Protection
Thermal overload detection protects the MAX3372E–
MAX3379E and MAX3390E–MAX3393E from short-circuit
fault conditions. In the event of a short-circuit fault, when
the junction temperature (TJ) reaches +152°C, a thermal
sensor signals the three-state output mode logic to force
the device into three-state output mode. When TJhas
cooled to +142°C, normal operation resumes.
VCC
I/O VLI/O VCC
GATE
BIAS
VL
P P
N
Figure 2a. Functional Diagram, MAX3372E/MAX3377E (1 I/O line)
VCC
I/O VL_ I/O VCC_
GATE
BIAS
VL
PU1 PU2
N
ONE-SHOT
BLOCK
ONE-SHOT
BLOCK
Figure 2b. Functional Diagram, MAX3373E/MAX3378E (1 I/O line)
Maxim Integrated
23
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Pin Configurations (continued)
A
1
2
3
4
BC
12 UCSP (1.5mm x 2.0mm)
BOTTOM VIEW
VCC I VCC1
I VCC2
I VCC3
O VL3
O VL2
O VL1
VL
I VCC4
GND
O VL4
THREE-STATE
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
I VCC1
I VCC2
I VCC3O VL3
O VL2
O VL1
VL
MAX3393E
I VCC4
N.C.
THREE-STATEGND
N.C.
O VL4
TSSOP-14
TOP VIEW
A
1
2
3
4
BC
12 UCSP (1.5mm x 2.0mm)
BOTTOM VIEW
VCC I VCC1
I VCC2
I VCC3
O VL3
O VL2
O VL1
VL
O VCC4
GND
I VL4
THREE-STATE
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
I VCC1
I VCC2
I VCC3O VL3
O VL2
O VL1
VL
MAX3392E
O VCC4
N.C.
THREE-STATEGND
N.C.
I VL4
TSSOP-14
TOP VIEW
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
I VCC1
I VCC2
O VCC3I VL3
O VL2
O VL1
VL
MAX3391E
O VCC4
N.C.
THREE-STATEGND
N.C.
I VL4
TSSOP-14
TOP VIEW
A
1
2
3
4
BC
12 UCSP (1.5mm x 2.0mm)
BOTTOM VIEW
VCC I VCC1
I VCC2
O VCC3
I VL3
O VL2
O VL1
VL
O VCC4
GND
I VL4
THREE-STATE
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
I VCC1
I VCC2
N.C.N.C.
O VL2
O VL1
VL
0 VCC3
GND
I VL4
I VL3
TDFN-14 (3mm x 3mm)
TOP VIEW
THREE-STATE
0 VCC4
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
I VCC1
I VCC2
N.C.N.C.
O VL2
O VL1
VL
I VCC3
GND
I VL4
O VL3
TDFN-14 (3mm x 3mm)
TOP VIEW
THREE-STATE
0 VCC4
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
I VCC1
I VCC2
N.C.N.C.
O VL2
O VL1
VL
I VCC3
GND
O VL4
O VL3
TDFN-14 (3mm x 3mm)
TOP VIEW
THREE-STATE
I VCC4
24
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
Maxim Integrated
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
SOT23, 8L.EPS
0
0
PACKAGE OUTLINE, SOT-23, 8L BODY
21-0078 G 1
1
MARKING
Chip Information
TRANSISTOR COUNT: MAX3372E–MAX3376E: 189
MAX3377E–MAX3379E,
MAX3390E–MAX3393E: 295
PROCESS: BiCMOS
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
25
Maxim Integrated
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
6, 8, &10L, DFN THIN.EPS
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
26
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
Maxim Integrated
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
COMMON DIMENSIONS
SYMBOL MIN. MAX.
A 0.70 0.80
D 2.90 3.10
E 2.90 3.10
A1 0.00 0.05
L 0.20 0.40
PKG. CODE N D2 E2 eJEDEC SPEC b[(N/2)-1] x e
PACKAGE VARIATIONS
0.25 MIN.k
A2 0.20 REF.
2.00 REF0.25±0.050.50 BSC2.30±0.1010T1033-1
2.40 REF0.20±0.05- - - - 0.40 BSC1.70±0.10 2.30±0.1014T1433-1
1.50±0.10 MO229 / WEED-3
0.40 BSC - - - - 0.20±0.05 2.40 REFT1433-2 14 2.30±0.101.70±0.10
T633-2 6 1.50±0.10 2.30±0.10 0.95 BSC MO229 / WEEA 0.40±0.05 1.90 REF
T833-2 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF
T833-3 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF
2.30±0.10 MO229 / WEED-3 2.00 REF0.25±0.050.50 BSC1.50±0.1010T1033-2
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
27
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
Maxim Integrated
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
TSSOP4.40mm.EPS
PACKAGE OUTLINE, TSSOP 4.40mm BODY
21-0066
1
1
I
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
28
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
Maxim Integrated
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
9LUCSP, 3x3.EPS
PACKAGE OUTLINE, 3x3 UCSP
21-0093
1
1
L
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
29
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
Maxim Integrated
12L, UCSP 4x3.EPS
F
1
1
21-0104
PACKAGE OUTLINE, 4x3 UCSP
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
30
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
Maxim Integrated
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 1/02 Initial Release —
1 12/06 Addition of 12-bump ECSP packaging –
2 11/07 Addition of lead-free options 1, 20–31
31
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
© 2007 Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
MAX3372E–MAX3379E/
MAX3390E–MAX3393E
