AUIRLR3915
VDSS 55V
RDS(on) typ. 12m
ID (Silicon Limited) 61A
ID (Package Limited) 30A
max. 14m
Features
Advanced Plannar Technology
Logic-Level Gate Drive
Low On-Resistance
175°C Operating Temperature
Fast Switching
Fully Avalanche Rated
Repetitive Avalanche Allowed up to Tjmax
Lead-Free, RoHS Compliant
Automotive Qualified *
Description
Specifically designed for Automotive applications, this Stripe Planar
design of HEXFET® Power MOSFETs utilizes the latest
processing techniques to achieve low on-resistance per silicon
area. This benefit combined with the fast switching speed and
ruggedized device design that HEXFET power MOSFETs are well
known for, provides the designer with an extremely efficient and
reliable device for use in Automotive and a wide variety of other
applications.
1 2015-12-14
HEXFET® is a registered trademark of Infineon.
*Qualification standards can be found at www.infineon.com
AUTOMOTIVE GRADE
Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 61
A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 43
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited) 30
IDM Pulsed Drain Current 240
PD @TC = 25°C Maximum Power Dissipation 120 W
Linear Derating Factor 0.77 W/°C
VGS Gate-to-Source Voltage ± 16 V
EAS Single Pulse Avalanche Energy (Thermally Limited) 200
mJ
EAS (Tested) Single Pulse Avalanche Energy Tested Value 600
IAR Avalanche Current See Fig.15,16, 12a, 12b A
EAR Repetitive Avalanche Energy mJ
TJ Operating Junction and -55 to + 175
°C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case) 300
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless
otherwise specified.
Thermal Resistance
Symbol Parameter Typ. Max. Units
RJC Junction-to-Case ––– 1.3
°C/W
RJA Junction-to-Ambient ( PCB Mount) ––– 50
RJA Junction-to-Ambient ––– 110
D-Pak
AUIRLR3915
Base part number Package Type Standard Pack Orderable Part Number
Form Quantity
AUIRLR3915 D-Pak Tube 75 AUIRLR3915
Tape and Reel Left 3000 AUIRLR3915TRL
G D S
Gate Drain Source
S
G
D
HEXFET® Power MOSFET
AUIRLR3915
2 2015-12-14
Notes:
Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11)
Limited by TJmax , starting TJ = 25°C, L = 0.45mH, RG = 25, IAS = 30A, VGS =10V. Part not recommended for use above this value.
ISD 30A, di/dt 280A/µs, VDD V(BR)DSS, TJ 175°C.
Pulse width 1.0ms; duty cycle 2%.
Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance.
This value determined from sample failure population, starting TJ = 25°C, L = 0.45mH, RG = 25, IAS = 30A, VGS =10V.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to
application note #AN-994
R is measured at TJ approximately 90°C.
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 55 ––– ––– V VGS = 0V, ID = 250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– 0.057 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 12 14 mVGS = 10V, ID = 30A
––– 14 17 VGS = 5.0V, ID = 26A
VGS(th) Gate Threshold Voltage 1.0 ––– 3.0 V VDS = VGS, ID = 250µA
gfs Forward Trans conductance 42 ––– ––– S VDS = 25V, ID = 30A
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS = 55V, VGS = 0V
––– ––– 250 VDS = 55V,VGS = 0V,TJ =125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA VGS = 16V
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -16V
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Qg Total Gate Charge ––– 61 92
nC
ID = 30A
Qgs Gate-to-Source Charge ––– 9.0 14 VDS = 44V
Qgd Gate-to-Drain Charge ––– 17 25 VGS = 10V
td(on) Turn-On Delay Time ––– 7.4 –––
ns
VDD = 28V
tr Rise Time ––– 51 ––– ID = 30A
td(off) Turn-Off Delay Time ––– 83 ––– RG = 8.5
tf Fall Time ––– 100 ––– VGS = 10V
LD Internal Drain Inductance ––– 4.5 –––
nH
Between lead,
6mm (0.25in.)
LS Internal Source Inductance ––– 7.5 ––– from package
and center of die contact
Ciss Input Capacitance ––– 1870 –––
pF
VGS = 0V
Coss Output Capacitance ––– 390 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 74 ––– ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 2380 ––– VGS = 0V, VDS = 1.0V ƒ = 1.0MHz
Coss Output Capacitance ––– 290 ––– VGS = 0V, VDS = 44V ƒ = 1.0MHz
Coss eff. Effective Output Capacitance ––– 540 ––– VGS = 0V, VDS = 0V to 44V
Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 61
A
MOSFET symbol
(Body Diode) showing the
ISM Pulsed Source Current ––– ––– 240 integral reverse
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C,IS = 30A, VGS = 0V
trr Reverse Recovery Time ––– 62 93 ns TJ = 25°C ,IF = 30A, VDD = 25V
Qrr Reverse Recovery Charge ––– 110 170 nC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
AUIRLR3915
3 2015-12-14
Fig. 2 Typical Output Characteristics
Fig. 3 Typical Transfer Characteristics Fig. 4 Typical Forward Trans conductance
Vs. Drain Current
Fig. 1 Typical Output Characteristics
0.1 110 100 1000
VDS, Drain-to-Source Voltage (V)
0.001
0.01
0.1
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
2.0V
20µs PULSE WIDTH
Tj = 25°C
VGS
TOP 15V
10V
5.0V
3.0V
2.7V
2.5V
2.25V
BOTTOM 2.0V
0.1 110 100 1000
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
2.0V
20µs PULSE WIDTH
Tj = 175°C
VGS
TOP 15V
10V
5.0V
3.0V
2.7V
2.5V
2.25V
BOTTOM 2.0V
1.0 3.0 5.0 7.0 9.0 11.0 13.0 15.0
VGS, Gate-to-Source Voltage (V)
0.10
1.00
10.00
100.00
1000.00
ID, Drain-to-Source Current )
TJ = 25°C
TJ = 175°C
VDS = 25V
20µs PULSE WIDTH
0 102030405060
ID,Drain-to-Source Current (A)
0
10
20
30
40
50
60
70
Gfs, Forward Transconductance (S)
TJ = 25°C
TJ = 175°C
AUIRLR3915
4 2015-12-14
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 8. Maximum Safe Operating Area
Fig. 7 Typical Source-to-Drain Diode
Forward Voltage
110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
100000
C, Capacitance(pF)
VGS
= 0V, f = 1 MHZ
Ciss
= C
gs
+ C
gd, C
ds
SHORTED
Crss
= C
gd
Coss
= C
ds
+ C
gd
Coss
Crss
Ciss
010 20 30 40 50 60 70
0
2
4
6
8
10
12
Q , Total Gate Charge (nC)
V , Gate-to-Source Voltage (V)
G
GS
I=
D30A
V = 11V
DS
V = 27V
DS
V = 44V
DS
0.1
1
10
100
1000
0.0 0.5 1.0 1.5 2.0
V ,Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 175 C
J°
T = 25 C
J°
1 10 100 1000
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
AUIRLR3915
5 2015-12-14
Fig 10. Normalized On-Resistance
Vs. Temperature
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
25 50 75 100 125 150 175
0
10
20
30
40
50
60
70
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
LIMITED BY PACKAGE
-60 -40 -20 020 40 60 80 100 120 140 160 180
0.0
0.5
1.0
1.5
2.0
2.5
T , Junction Temperature ( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
10V
61A
0.01
0.1
1
10
0.00001 0. 0001 0. 001 0. 01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
AUIRLR3915
6 2015-12-14
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12a. Unclamped Inductive Test Circuit
Fig 12b. Unclamped Inductive Waveforms
R
G
I
AS
0.01
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
tp
V
(BR)DSS
I
AS
Fig 13b. Gate Charge Test Circuit
Fig 13a. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
Fig 14. Threshold Voltage Vs. Temperature
25 50 75 100 125 150 175
0
100
200
300
400
500
Starting Tj, Junction Temperature ( C)
E , Single Pulse Avalanche Energy (mJ)
AS
°
ID
TOP
BOTTOM
12A
21A
30A
-75 -50 -25 025 50 75 100 125 150 175 200
TJ , Temperature ( °C )
0.5
1.0
1.5
2.0
VGS(th) Gate threshold Voltage (V)
ID = 250µA
AUIRLR3915
7 2015-12-14
Fig 15. Typical Avalanche Current Vs. Pulse width
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.infineon.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as Tjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
Z
thJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
Iav = 2T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 16. Maximum Avalanche Energy
Vs. Temperature
1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
0.1
1
10
100
1000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming Tj = 25°C due to
avalanche losses
0.01
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
20
40
60
80
100
120
140
160
180
200
220
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 10% Duty Cycle
ID = 30A
AUIRLR3915
8 2015-12-14
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
Fig 18a. Switching Time Test Circuit Fig 18b. Switching Time Waveforms
AUIRLR3915
9 2015-12-14
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
D-Pak (TO-252AA) Package Outline (Dimensions are shown in millimeters (inches))
YWWA
XX XX
Date Code
Y= Year
WW= Work Week
AULR3915
Lot Code
Part Number
IR Logo
D-Pak (TO-252AA) Part Marking Information
AUIRLR3915
10 2015-12-14
D-Pak (TO-252AA) Tape & Reel Information (Dimensions are shown in millimeters (inches))
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
TR
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 ) FEED DIRECTION FEED DIRECTION
16.3 ( .641 )
15.7 ( .619 )
TRR TRL
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
16 mm
13 INCH
AUIRLR3915
11 2015-12-14
Qualification Information
Qualification Level
Automotive
(per AEC-Q101)
Comments: This part number(s) passed Automotive qualification. Infineon’s
Industrial and Consumer qualification level is granted by extension of the higher
Automotive level.
Moisture Sensitivity Level D-Pak MSL1
ESD
Machine Model Class M2 (+/- 200V)†
AEC-Q101-002
Human Body Model Class H1B (+/- 1000V) †
AEC-Q101-001
Charged Device Model Class C5 (+/- 2000V)†
AEC-Q101-005
RoHS Compliant Yes
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2015
All Rights Reserved.
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any
information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and
liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third
party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this
document and any applicable legal requirements, norms and standards concerning customer’s products and any use of
the product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
customer’s technical departments to evaluate the suitability of the product for the intended application and the
completeness of the product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies office (www.infineon.com).
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in question
please contact your nearest Infineon Technologies office.
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized
representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a
failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.
Revision History
Date Comments
12/14/2015 Updated datasheet with corporate template
Corrected ordering table on page 1.
† Highest passing voltage.
