DATA SHEET O K I A S I C P R O D U C T S MSM30R/32R/92R 0.5m Sea Of Gates and Customer Structured Arrays July 2001 ------------------------------------------------------------------------------------------- CONTENTS Description ................................................................................................................................................................1 Features ....................................................................................................................................................................1 MSM30R/32R/92R Family Listing .......................................................................................................................3 Array Architecture ...................................................................................................................................................5 MSM92R000 CSA Layout Methodology ........................................................................................................5 Electrical Characteristics .........................................................................................................................................7 Macro Library .........................................................................................................................................................11 Macrocells for Driving Clock Trees ..............................................................................................................12 Oki Advanced Design Center Cad Tools ...........................................................................................................13 Design Process .................................................................................................................................................14 Automatic Test Pattern Generation ..............................................................................................................15 Floorplanning Design Flow ...........................................................................................................................15 IEEE JTAG Boundary Scan Support .............................................................................................................16 Package Options .....................................................................................................................................................17 0 Oki Semiconductor MSM30R/32R/92R Second-Generation 0.5m Sea of Gates and Customer Structured Arrays DESCRIPTION Oki's second-generation 0.5m ASIC products are available in both Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. The MSM30R Series, MSM32R Series, and MSM92R Series all offer increased density over their first-generation counterparts, as well as 3-V I/O buffers that are 5-V tolerant. Both the SOG-based MSM30R Series and the CSA-based MSM92R Series use a three-layer metal process on 0.5m drawn (0.4m L-effective) CMOS technology. The SOG-based MSM32R Series uses the same SOG base-array architecture as the MSM30R Series, but offers two metal layers instead of three. The semiconductor process is adapted from Oki's production-proven 16-Mbit DRAM manufacturing process. The second-generation 0.5m family retains the high speed and low power of Oki's first-generation 0.5m MSM13R/12R/98R family. The second-generation 0.5m family also shares the same die sizes for arrays with corresponding I/O counts, but the second-generation arrays can contain up to 60% more gates than their first-generation counterparts. The second-generation family is optimized for 3-V core operation, with optimized 3-V I/O buffers and 3-V I/O buffers that are 5-V tolerant, whereas the firstgeneration family offers separate I/O buffers for mixed 3-V and 5-V operation. Oki's first-generation and second-generation 0.5m families together offer an unusually flexible mixed-voltage ASIC capability. The 3-layer-metal MSM30R SOG Series contains 8 array bases, offering up to 448 I/O pads and over 600K raw gates. The 2-layer metal MSM32R SOG Series contains five array bases, offering up to 320 I/O pads and over 300K raw gates. These SOG array sizes are designed to fit the most popular Quad Flat Pack (QFP) and Plastic Ball Grid Array (PBGA) packages. The MSM30R and MSM32R Series' SOG architecture allows rapid prototyping turnaround times, additionally offering the most cost-effective solution for pad-limited circuits (particularly the 2-layer metal MSM32R Series). The 3-layer-metal MSM92R CSA Series contains 36 array bases, offering a wider span of gate and I/O counts than SOG Series. Oki uses the EPOCH memory compiler from Cascade Design Automation to generate optimized single- and dual-port RAM macrocells for CSA designs. As such, the MSM92R Series is suited to memory-intensive ASICs and high-volume designs where fine tuning of package size produces significant cost or real-estate savings. FEATURES * * * * * 0.5m drawn two and three-layer metal CMOS Optimized 3.3-V core Optimized 3-V I/O and 3-V I/O that is 5-V tolerant SOG and CSA architecture availability 120-ps typical gate propagation delay (for a 2-input 4x-drive NAND gate with a fan-out of 2 and 0mm of wire, operating at 3.3 V) * Up to 1.2M raw gates and 624 pads * User-configurable I/O with VSS, VDD, TTL, 3-state, and 1 mA ~ 24 mA options * Slew-rate-controlled outputs for low-radiated noise * Clock tree cells with 0.5-ns clock skew, worst-case (fan-out 9000 at 75 MHz) * User-configurable single and dual-port memories * Specialized macrocells, including phase-locked loop, GTL, PECL, and PCI cells * Floorplanning for front-end simulation, back-end layout controls, and link to synthesis * JTAG boundary scan and scan-path ATPG * Support for popular CAE systems, including Cadence, IKOS, Mentor Graphics, Synopsys, Viewlogic, and Zycad Oki Semiconductor 1 MSM30R/32R/92R ---------------------------------------------------------------------------- MSM30R/32R/92R FAMILY LISTING CSA Part# SOG Part# B92R020X020 -- 80 14,688 72 204 11,750 MSM92RB02 B92R024X024 -- 96 22,784 89 256 18,227 MSM92RB03 B92R026X026 MSM30R0020 104 27,440 98 280 21,952 MSM92RB04 B92R030X030 -- 120 37,720 115 328 30,176 MSM92RB05 B92R032X032 -- 128 43,296 123 352 34,637 -- MSM32R0050 144 56,000 140 400 26,880 MSM92RB06 B92R036X036 MSM30R0050 144 56,000 140 400 42,000 MSM92RB07 B92R038X038 -- 152 63,176 149 424 47,382 MSM92RB08 B92R040X040 -- 160 70,336 157 448 52,752 MSM92RB09 B92R042X042 -- 168 78,352 166 472 58,764 -- MSM32R0080 176 86,304 174 496 38,837 MSM92RB10 B92R044X044 MSM30R0080 176 86,304 174 496 60,413 MSM92RB11 B92R048X048 -- 192 103,904 191 544 72,733 MSM92RB12 B92R050X050 -- 200 114,400 200 572 80,080 -- MSM32R0120 208 123,968 208 596 49,587 MSM92RB13 B92R052X052 MSM30R0120 208 123,968 208 596 86,778 MSM92RB14 B92R056X056 -- 224 144,900 225 644 101,430 MSM92RB15 B92R060X060 -- 240 167,464 242 692 117,225 -- MSM32R0190 256 191,660 259 740 72,831 MSM92RB16 B92R064X064 MSM30R0190 256 191,660 259 740 126,496 MSM92RB17 B92R068X068 -- 272 217,488 276 788 143,542 MSM92RB18 B92R072X072 -- 288 244,948 293 836 161,666 MSM92RB19 B92R076X076 -- 304 274,040 310 884 180,866 -- MSM32R0300 320 306,072 327 936 110,186 MSM92RB20 B92R080X080 MSM30R0300 320 306,072 327 936 195,886 MSM92RB21 B92R084X084 -- 336 338,496 344 984 216,637 MSM92RB22 B92R088X088 -- 352 372,552 361 1032 238,433 MSM92RB23 B92R092X092 -- 368 408,240 378 1080 261,274 MSM92RB24 B92R096X096 MSM30R0440 384 445,560 395 1128 276,247 MSM92RB25 B92R100X100 -- 400 484,512 412 1176 300,397 MSM92RB26 B92R104X104 -- 416 525,096 429 1224 325,560 MSM92RB27 B92R108X108 -- 432 569,096 446 1276 352,840 MSM92RB28 B92R112X112 -- 448 613,012 463 1324 367,807 MSM92RB29 B92R118X118 -- 472 682,644 489 1396 409,586 MSM92RB30 B92R122X122 -- 488 730,664 506 1444 438,398 MSM92RB31 B92R126X126 -- 504 780,316 523 1492 468,190 MSM92RB32 B92R132X132 -- 528 857,072 548 1564 514,243 MSM92RB33 B92R138X138 -- 552 941,360 574 1640 564,816 MSM92RB34 B92R144X144 -- 576 1,025,488 599 1712 615,293 MSM92RB35 B92R150X150 -- 600 1,115,000 625 1784 669,000 MSM92RB36 B92R156X156 -- 624 1,206,400 650 1856 723,840 -- -- -- -- -- I/O Pads Raw Gates Rows [1] CSA Master# MSM92RB01 Columns Usable Gates [2] 1. Row and column numbers are used to evaluate the number and size of mega macrocells that may be included into each array. 2. Usable gate count is design dependent and varies based upon the number of fan-outs per net, internal busses, floor plan, RAM/ROM blocks, etc. 2 Oki Semiconductor --------------------------------------------------------------------------- MSM30R/32R/92R ARRAY ARCHITECTURE The primary components of a 0.5m MSM30R/32R/92R circuit include: * * * * * * * I/O base cells Configurable I/O pads for VDD, VSS, or I/O (optimized 3-V I/O and 3-V I/O that is 5-V tolerant) VDD and VSS pads dedicated to wafer probing Separate power bus for output buffers Separate power bus for internal core logic and input buffers Core base cells containing N-channel and P-channel pairs, arranged in column of gates Isolated gate structure for reduced input capacitance and increased routing flexibility Each array has 24 dedicated corner pads for power and ground use during wafer probing, with four pads per corner. The arrays also have separate power rings for the internal core functions (VDDC and VSSC) and output drive transistors (VDDO and VSSO). I/O base cells Separate power bus (VDDC, VSSC) for internal core logic (2nd metal/3rd metal Configurable I/O pads for VDD, VSS, or I/O 1,2, or 3 layer metal interconnection in core area Core base cell with 4 transistors VDD, VSS pads (4) in each corner for wafer probing only Separate power bus (VDDO, VSSO) over I/O cell for output buffers(2nd metal/3rd metal) Figure 7. MSM30R0000 Array Architecture MSM92R000 CSA Layout Methodology The procedure to design, place, and route a CSA follows. 1. Select suitable base array frame from the available predefined sizes. To select an array size: - Identify the macrocell functions required and the minimum array size to hold the macrocell functions. Oki Semiconductor 3 MSM30R/32R/92R ---------------------------------------------------------------------------- - Add together all the area occupied by the required random logic and macrocells and select the optimum array. 2. Make a floor plan for the design's megacells. - Oki Design Center engineers verify the master slice and review simulation. - Oki Design Center or customer engineers floorplan the array using Oki's proprietary floorplanner or HLD DP3 and customer performance specifications. - Using Oki CAD software, Design Center engineers remove the SOG transistors and replace them with diffused memory macrocells to the customer's specifications. Figure 8 shows an array base after placement of the optimized memory macrocells. Early mask high-density ROM Mega macrocell High-density RAM Multi-port RAM Figure 8. Optimized Memory Macrocell Floor Plan 3. Place and route logic into the array transistors. - Oki Design Center engineers use layout software and customer performance specifications to connect the random logic and optimized memory macrocells. Figure 9 marks the area in which placement and routing is performed with cross hatching. Figure 9. Random Logic Place and Route 4 Oki Semiconductor --------------------------------------------------------------------------- MSM30R/32R/92R ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (VSS = 0 V, Tj = 25 C) [1] Parameter Symbol Power supply voltage Input voltage (normal buffers) Output current per I/O -0.3 ~ VDD+0.3 -0.3 ~ 6.0 (normal buffers) -10 ~ +10 II mA -6 ~ +6 (normal buffers) IO (5-V tolerant) Storage temperature V V -- VO (5-V tolerant) Unit -0.3 ~ +4.6 -0.3 ~ 6.0 (normal buffers) (5-V tolerant) Input current Rated Value -0.3 ~ VDD+0.3 VI (5-V tolerant) Output voltage Conditions VDD Tstg IO = 1, 2, 4, 6, 8, 12, 24 mA -24 ~ +24 IO = 2, 4, 6, 8 mA -8 ~ +8 -- -65 ~ +150 mA C 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions in the other specifications of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions (VSS = 0 V) Parameter Symbol Rated Value Unit Power supply voltage VDD (3 V) +3.0 ~ +3.6 V Junction temperature Tj -40 ~ +70 C Oki Semiconductor 5 MSM30R/32R/92R ---------------------------------------------------------------------------- DC Characteristics (VDD = 3.0 V ~ 3.6 V, VSS = 0 V, Tj = -40 C ~ +70 C) Rated Value Parameter High-level input voltage Low-level input voltage TTL- level Schmitt trigger input threshold voltage (normal buffer) Symbol VIH VIL Conditions Min TTL input (normal) 2.0 2.0 -- 5.5 -- 0.8 TTL input (5-V tolerant) -0.3 -- 0.8 -- 1.5 2.0 0.7 1.0 -- 0.4 0.5 -- -- 1.5 2.0 TTL input Vt+ - VtTTL 5-V tolerant input Vt High-level output voltage (normal buffer) High-level output voltage (5-V tolerant) VOH Low-level output voltage (normal buffer) Low-level output voltage (5-V tolerant) VOL High-level input current (normal buffer) High-level input current (5-V tolerant) IIH Low-level input current (normal buffer) Low-level input current (5-V tolerant) 3-state output leakage current (normal buffer) IIL IOZH IOZL 3-state output leakage current (5-V tolerant) Stand-by current 1. 2. 3. 4. 6 [4] IOZH 0.7 1.0 -- Vt+ - Vt- 0.4 0.5 -- -- IOH = -100 A VDD-0.2 -- IOH = -1, -2, -4, -6, -8, -12 mA 2.4 -- -- IOH = -100 A VDD-0.2 -- -- IOH = -1, -2, -4, -6, -8 mA 2.4 -- -- IOL = 100 A -- -- 0.2 IOL = 1, 2, 4, 6, 8, 12, 24 [3] mA -- -- 0.4 IOL = 100 A -- -- 0.2 IOL = 1, 2, 4, 6, 8 mA -- -- 0.4 VIH = VDD -- 0.01 1 VIH = VDD (50 k pull-down) 15 66 170 VIH = VDD - 0.01 1 VIH = VDD (50 k pull-down) 15 66 170 VIL = VSS -1 -0.01 -- VIL = VSS (50 k pull-up) -170 -66 -15 VIL = VSS (3 k pull-up) -3.3 -1.1 -0.3 VIL = VSS -1 -0.01 -- VIL = VSS (50 k pull-up) -170 -66 -15 VIL = VSS (3 k pull-up) -3.3 -1.1 -0.3 VOH = VDD -- 0.01 1 VOH = VDD (50 k pull-down) 15 66 170 VOL = VSS -1 -0.01 -- VOL = VSS (50 k pull-up) -170 -66 -15 VOL = VSS (3 k pull-up) -3.3 -1.1 -0.3 VOH = VDD -- 0.01 1 VOH = VDD (50 k pull-down) 15 66 170 VOL = VSS -1 -0.01 -- IOZL VOL = VSS (50 k pull-up) -170 -66 -15 VOL = VSS (3 k pull-up) -3.3 -1.1 -0.3 IDDQ Output open, VIH=VDD, VIL=VSS JEDEC Compatible; JESD8-1A LVTTL Typical condition is 3.3 V and Tj = 25 o C on a typical process. 24 mA only available for open-drain outputs. RAM/ROM should be in power-down mode. Oki Semiconductor Max Unit VDD + 0.3 -0.3 Vt- Vt- -- TTL input (normal) Vt+ Vt+ [1] [2] TTL input (5-V tolerant) Vt TTL-level Schmitt trigger input threshold voltage (5-V tolerant) Typ Design Dependent V A mA A mA A A mA A A mA A --------------------------------------------------------------------------- MSM30R/32R/92R AC Characteristics (VDD = 3.3 V, VSS = 0 V, Tj = 25 C) Parameter Internal gate propagation delay Driving Type Inverter 1X 2X 2-input NAND 2-input NOR Conditions [1] [2] F/O=2, L=0mm VDD=3.3V 0.08 0.17 2X 0.14 4X 0.12 1X 0.21 2X 0.17 2X 2-input NAND 2-input NOR Output buffer propagation delay 1X 0.36 2X 0.24 4X 0.17 1X 0.47 2X 0.34 Output buffer transition time 1. 2. 3. 4. [4] 0.30 F/O=1,L=0mm 630 MHz F/O=2,L=1mm 0.40 ns CL=20pF 1.87 TTL-level 5-V tolerant buffer Push-pull (normal buffer) 0.28 0.13 TTL-level normal input buffer 4mA ns 0.20 4X Toggle frequency Unit 0.18 F/O=2, L=1mm VDD=3.3V 4X Input buffer propagation delay 0.12 4X 1X [3] 0.10 1X 4X Inverter Rated Value 0.61 8mA CL=50pF 2.14 12mA CL=100pF 2.71 3-state (5-V tolerant) 4mA CL=20pF 2.29 Push-pull (normal buffer) 12mA CL=75pF 4.09 (r) 3.85 (f) 3-state (5-V tolerant) 4mA CL=20pF 3.18 (r) 4.00 (f) Input transition time in 0.2 ns / 3.3 V. Typical condition is 3.3 V and Tj = 25o C for a typical process. Rated value is calculated as an average of the L-H and H-L delay times of each macro type on a typical process. Output rising and falling times are both specified over a 10%-90% range Oki Semiconductor 7 MSM30R/32R/92R ---------------------------------------------------------------------------- MACRO LIBRARY Oki Semiconductor supports a wide range of macrocells and macrofunctions, ranging from simple hard macrocells for basic Boolean operations to large, user-parameterizable macrofunctions. The following figure illustrates the main classes of macrocells and macrofunctions available. Examples Basic Macrocells NANDs NORs Basic Macrocells with Scan test Flip-Flops EXORs Latches Flip-Flops Combinational Logic Clock Tree Driver Macrocells Macrocells 3V, 5V Tolerant Output Macrocells MSI Macrocells Mega/Special Macrocells [1] 3-State Outputs Push-Pull Outputs PECL Outputs Open Drain Outputs Slew Rate Control Outputs PCI Outputs Counters Shift Registers UART PLL 82C37 82C54 82C59 PCI Controller Ethernet Controller Macro Library 3V, 5V Tolerant Input Macrofunctions Inputs Inputs with Pull-Downs Inputs with Pull-Ups GTL Inputs PECL Inputs 3V, 5V tolerant Bi-Directional Macrofunctions I/O PCI I/O I/O with Pull-Downs I/O with Pull-Ups MSI Macrofunctions 74199 74163 74151 Oscillator Macrofunctions Gated Oscillators Memory Macrocells SOG RAMs: Single-Port RAMs Dual-Port RAMs Macrofunctions Optimized Diffused RAMs: Single-Port RAMs Dual-Port RAMs [1] Under development Figure 10. Oki Macrocell and Macrofunction Library 8 Oki Semiconductor --------------------------------------------------------------------------- MSM30R/32R/92R Macrocells for Driving Clock Trees Oki offers clock-tree drivers that guarantee a skew time of less than 0.5 ns. The advanced layout software uses dynamic driver placement and sub-trunk allocation to optimize the clock-tree implementation for a particular circuit. Features of the clock-tree driver-macrocells include: * * * * * * * * Clock skew 0.5 ns Automatic fan-out balancing Dynamic sub-trunk allocation Single clock tree driver logic symbol Single-level clock drivers Automatic branch length minimization Dynamic driver placement Up to four clock trunks The clock-skew management scheme is described in detail in Oki's 0.5m Technology Clock Skew Management Application Note. Main Trunk Clocked Cell Sub Trunk Branch Clock Drivers Pad Input Buffer Clock Tree Driver Macrocell Figure 11. Clock Tree Structure Oki Semiconductor 9 MSM30R/32R/92R ---------------------------------------------------------------------------- OKI ADVANCED DESIGN CENTER CAD TOOLS Oki's advanced design center CAD tools include support for the following: * * * * Floorplanning for front-end simulation and back-end layout control Clock tree structures improve first-time silicon success by eliminating clock skew problems JTAG Boundary scan support Power calculation which predicts circuit power under simulation conditions to accurately model package requirements Design Kits Vendor Platform (R) [2] Operating System [1] Vendor Software/Revision [1] Description Solaris Ambit Buildgates NC-VerilogTM Verilog XL VerifaultTM Design Synthesis Design Simulation Design Simulation Fault Simulation Cadence Sun Synopsys Sun [2] Solaris Design Compiler Ultra + Tetramax/ATPG Primetime DFT Compiler/Test Compiler RTL Analyzer VCS Design synthesis ATPG Static Timing Analysis (STA) Test synthesis RTL check Design Simulation Model Technology Inc. (MTI) Sun [2] NT Solaris WinNT4.0 MTI-VHDL MTI-Verilog Design Simulation Design Simulation Exemplar Sun [2] NT Solaris WinNT4.0 Leonardo Spectrum Design Synthesis Oki Sun [2] Solaris Floorplanner Floor planning Verplex Sun [2] Solaris Tuxedo Formal verification Zycad Sun [2] Solaris XPLUS Fault Simulation 1. Contact Oki Application Engineering for current software versions. 2. Sun or Sun-compatible. 10 Oki Semiconductor --------------------------------------------------------------------------- MSM30R/32R/92R Design Process The following figure illustrates the overall IC design process, also indicating the three main interface points between external design houses and Oki ASIC Application Engineering. Level 1 [4] VHDL/HDL Description Synopsys Timing Script (optional) Functional Test Vectors Synthesis CAE Front-End Floorplanning Gate-Level Simulation Level 2 Netlist Conversion (EDIF 200) Test Vector Conversion (Oki TPL [3]) Scan Insertion (Optional) TDC [2] CDC [1] Formal Verification Floorplanning Pre-Layout Simulation Level 2.5 [4] Layout / Timing Driven Layout (optional) [6] Static Timing Analysis Fault Simulation [5] Oki Interface Automatic Test Pattern Generation Verification (Design Rule Check/Formal Verification) Post-Layout Simulation Level 3 [4] Manufacturing Prototype Test Program Conversion [1] Oki's Circuit Data Check program (CDC) verifies logic design rules [2] Oki's Test Data Check program (TDC) verifies test vector rules [3] Oki's Test Pattern Language (TPL) [4] Alternate Customer-Oki design interfaces available in addition to standard level 2 [5] Standard design process includes fault simulation [6] Requires Synopsys timing script for Oki timing driven layout Figure 12. Oki's Design Process Oki Semiconductor 11 MSM30R/32R/92R ---------------------------------------------------------------------------- Automatic Test Pattern Generation Oki's 0.5m ASIC technologies support Automatic Test Pattern Generation (ATPG) using full scan-path design techniques, including the following: * * * * * * * * * Increases fault coverage 95% Uses Synopsys Test Compiler Automatically inserts scan structures Connects scan chains Traces and reports scan chains Checks for rule violations Generates complete fault reports Allows multiple scan chains Supports vector compaction ATPG methodology is described in detail in Oki's 0.5m Scan Path Application Note. Combinational Logic A FD1AS Scan Data In D C SD SS B FD1AS Q QN D C SD SS Q Scan Data Out QN Scan Select Figure 13. Full Scan Path Configuration Floorplanning Design Flow Oki's floorplanner can be classified as both a front-end floorplanner and a back-end floorplanner. During front-end floorplanning, logic designers use the floorplanner to generate two files: a capacitance file for pre-layout simulation, and a floorplanner interface file for layout. During back-end floorplanning, the layout engineer transfers the floorplanner interface file to Oki's proprietary layout software, code-named Pegasus. The floorplanner interface file contains information about the placement of blocks and groups of blocks. The back-end floorplanner is automated and is transparent to logic designers. Figure 14 shows a diagram of front-end floorplanning. Figure 15 shows a diagram of back-end floorplanning. 12 Oki Semiconductor --------------------------------------------------------------------------- MSM30R/32R/92R Floorplanner Set Design EDIF rcEst Simulation Interface File EDIF Netlist Pre-Floor Plan Floorplan PLT Pinlist File FPI Floorplanner Interface File Figure 14. Front-End Floorplanning Pegasus Pre-Layout EDIF EDIF Netlist FPI Floorplanner Interface File GCD Layout FIF Layout Interface File Figure 15. Back-End Floorplanning IEEE JTAG Boundary Scan Support Boundary scan offers efficient board-level and chip-level testing capabilities. Benefits resulting from incorporating boundary-scan logic into a design include: * * * * * * Improved chip-level and board-level testing and failure diagnostic capabilities Support for testing of components with limited probe access Easy-to-maintain testability and system self-test capability with on-board software Capability to fully isolate and test components on the scan path Built-in test logic that can be activated and monitored An optional Boundary Scan Identification (ID) Register Oki's boundary scan methodology meets the JTAG Boundary Scan standard, IEEE 1149.1-1990. Oki supports boundary scan on both Sea of Gates (SOG) and Customer Structured Array (CSA) ASIC technologies. Either the customer or Oki can perform boundary-scan insertion. More information is available in Oki's JTAG Boundary Scan Application Note. Contact the Oki Application Engineering Department for interface options. Oki Semiconductor 13 MSM30R/32R/92R ---------------------------------------------------------------------------- PACKAGE OPTIONS MSM30R/32R/92R Package Menu Product SOG QFP TQFP LQFP PBGA FBGA Name I/O MSM92. MSM MSM Pad . 32R 30R s [1] 44 64 80 100 128 160 208 240 304 44 64 80 100 128 144 176 208 256 352 420 560 144 224 0020 104 RB04 120 RB05 RB01 80 RB02 96 RB03 128 RB06 0050 0050 144 RB07 152 RB08 160 RB09 168 RB10 0080 0080 176 RB11 192 RB12 200 RB13 0120 0120 208 RB14 224 RB15 240 RB16 0190 0190 256 RB17 272 RB18 288 RB19 304 RB20 0300 0300 320 RB21 336 RB22 352 368 RB24 0440 384 RB25 400 RB26 416 RB27 432 RB28 448 RB29 472 RB30 488 RB31 504 RB32 528 RB33 552 RB34 576 14 Oki Semiconductor RB23 --------------------------------------------------------------------------- MSM30R/32R/92R MSM30R/32R/92R Package Menu (Continued) Product SOG QFP TQFP LQFP PBGA FBGA Name I/O MSM92. MSM MSM Pad . 32R 30R s [1] 44 64 80 100 128 160 208 240 304 44 64 80 100 128 144 176 208 256 352 420 560 144 224 RB35 600 RB36 624 Body Size (mm) 9x10 14x1414x2014x2028x2828x2828x2832x3240x4010x1010x1012x1214x1414x1420x2024x2428x2827x2735x3535x3535x3513x1315x15 Lead Pitch (mm) 0.8 0.8 0.8 0.65 0.8 0.65 0.5 0.5 0.5 0.8 0.5 0.5 0.5 0.4 0.5 0.5 0.5 1.27 1.27 1.27 1.00 0.8 0.8 Ball Count 256 352 420 560 144 224 Signal I/O 231 304 352 400 144 224 Power Balls 12 16 32 80 - - Ground Balls 13 32 36 80 - - 1. I/O Pads can be used for input, output, bi-directional, power, or ground. = Available now; = In development Oki Semiconductor 15 MSM30R/32R/92R ---------------------------------------------------------------------------- NOTES 16 Oki Semiconductor The information contained herein can change without notice owing to product and/or technical improvements. Please make sure before using the product that the information you are referring to is up-to-date. The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected in the actual circuit and assembly designs. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection with the use of product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges, including but not limited to operating voltage, power dissipation, and operating temperature. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,office automation, communication equipment, measurement equipment, consumer electronics, etc.).These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans. Such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including life support and maintenance. Certain parts in this document may need governmental approval before they can be exported to certain countries. The purchaser assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their own expense, for export to another country. Copyright 2001 Oki Semiconductor Oki Semiconductor reserves the right to make changes in specifications at anytime and without notice. This information furnished by Oki Semiconductor in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Oki Semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Oki. Oki Semiconductor Oki REGIONAL SALES OFFICES Silicon Solutions Northwest Area Southwest Area 785 N. Mary Avenue Sunnyvale, CA 94085 Tel: 408/720-8940 Fax:408/720-8965 2171 Campus Drive, Suite 320 Irvine, CA 92612 Tel: 949/752-1843 Fax:949/752-2423 North Central Area Southeast Area 300 Park Blvd., Suite 365 Itasca, IL 60143 Tel: 630/250-1313 Fax:630/250-1414 1590 Adamson Parkway, Suite 220 Morrow, GA 30260 Tel: 770/960-9660 Fax:770/960-9682 Northeast Area South Central Area 138 River Road Shattuck Office Center Andover, MA 01810 Tel: 978/688-8687 Fax:978/688-8896 Park Creek II 2007 N. Collins Blvd., Suite 305 Richardson, TX 75080 Tel: 972/238-5450 Fax:972/238-0268 Oki Web Site: http://www.okisemi.com Oki Stock No: 010053-002 Corporate Headquarters 785 N. Mary Avenue Sunnyvale, CA 94085-2909 Tel: 408/720-1900 Fax:408/720-1918