D−8 DRB−8DGN−8
TPS2060/TPS2064
DGNPACKAGE
(TOP VIEW)
GND 1
2
3
4
8
7
6
5
IN
EN1
EN2
OC1
OUT1
OUT2
OC2
TPS2068
DGNPACKAGE
(TOP VIEW)
GND 1
2
3
4
8
7
6
5
IN
IN
EN
OUT
OUT
OUT
OC
TPS2069
DGNPACKAGE
(TOP VIEW)
GND 1
2
3
4
8
7
6
5
IN
IN
EN
OUT
OUT
OUT
OC
TPS2068
DPACKAGE
(TOP VIEW)
GND
IN
IN
EN
OUT
OUT
OUT
OC
1
2
3
4
8
7
6
5
GND
IN
EN1
†
EN2
OC1
OUT1
OUT2
OC2
TPS2060/TPS2064
DRBPACKAGES
(TOP VIEW)
† Allenableinputsareactivehighforthe TPS2064devices.
††
†4
3
2
1
5
6
7
8
TPS2060, TPS2064
TPS2068, TPS2069
www.ti.com
SLVS553K –MARCH 2005–REVISED MAY 2011
CURRENT-LIMITED, POWER-DISTRIBUTION SWITCHES
Check for Samples: TPS2060,TPS2064,TPS2068,TPS2069
1FEATURES APPLICATIONS
2•70-mΩHigh-Side MOSFET •Heavy Capacitive Loads
•1.5-A Continuous Current •Short-Circuit Protections
•Thermal and Short-Circuit Protection
•Accurate Current Limit (1.6 A min, 2.6 A max)
•Operating Range: 2.7 V to 5.5 V
•0.6-ms Typical Rise Time
•Undervoltage Lockout
•Deglitched Fault Report (OC)
•No OC Glitch During Power Up
•1-μA Maximum Standby Supply Current
•Reverse Current Blocking
•TPS2060/64 Temperature Range: 0°C to 70°C
•TPS2068/69 DGN Package Temperature
Range: –40°C to 85°C
•TPS2068 D Package Temperature Range:
0°C to 70°C
•UL Listed –File No. E169910
•TPS2068/69: CB Certified
DESCRIPTION
The TPS206x power-distribution switches are intended for applications where heavy capacitive loads and
short-circuits are likely to be encountered. This device incorporates 70-mΩN-channel MOSFET power switches
for power-distribution systems that require single or dual power switches in a single package. Each switch is
controlled by a logic enable input. Gate drive is provided by an internal charge pump designed to control the
power-switch rise times and fall times to minimize current surges during switching. The charge pump requires no
external components and allows operation from supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the device limits the output current
to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low. When
continuous heavy overloads and short-circuits increase the power dissipation in the switch, causing the junction
temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal
shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switch remains
off until valid input voltage is present. Current limit is typically 2.1 A.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPad is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright ©2005–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS2060, TPS2064
TPS2068, TPS2069
SLVS553K –MARCH 2005–REVISED MAY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTION AND ORDERING INFORMATION
RECOMMENDED TYPICAL PACKAGED
MAXIMUM SHORT-CIRCUIT NUMBER OF DEVICES (1) (2)
TAENABLE CONTINUOUS CURRENT LIMIT SWITCHES MSOP (DGN) SON (DRB)
LOAD CURRENT AT 25°C
Active low TPS2060DGN TPS2060DRB
0°C to 70°C Dual
Active high TPS2064DGN TPS2064DRB
Active low 1.5 A 2.1 A TPS2068DGN
–40°C to 85°C Single
Active high TPS2069DGN
0°C to 70°C Active low Single TPS2068D
(1) The package is available taped and reeled. Add an R suffix to device types (e.g., TPS2060DGN).
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
Input voltage range, VI(IN) –0.3 V to 6 V
VIInput voltage range, VI(/ENx), VI(ENx) –0.3 V to 6 V
Voltage range, VI(/OC), VI(/OCx) –0.3 V to 6 V
VOOutput voltage range, VO(OUT), VO(OUTx) –0.3 V to 6 V
IOContinuous output current, IO(OUT), IO(OUTx) Internally limited
Continuous total power dissipation See Dissipation Rating Table
TPS2060/64 0°C to 105°C
Operating virtual junction temperature
TJTPS2068/69 (DGN Package) –40°C to 105°C
range TPS2068 (D Package) 0°C to 105°C
Tstg Storage temperature range –65°C to 150°C
Human body model MIL-STD-883C 2 kV
ESD Electrostatic discharge protection Charge device model (CDM) 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATING RATING TABLE(1)
THERMAL TA<25°C DERATING TA= 70°C TA= 85°C
PACKAGE RESISTANCE POWER RATING FACTOR POWER RATING POWER RATING
θJA ABOVE TA= 25°C
DGN-8(2) 1370 mW 17 mW/°C 600 mW 342 mW
D-8 585.82 mW 5.8582 mW/°C 322.20 mW 234.32 mW
DRB-8 (Low-K)(3) 270 °CW 370 mW 3.71 mW/°C 203 mW 148 mW
DRB-8 (High-K)(4) 60 °CW 1600 mW 16.67 mW/°C 916 mW 866 mW
(1) Heatsink the PowerPad™per the recommendations of SLMA002. PCB used for recommendations per appendix A4.
(2) See Recommended Operating Conditions Table for PowerPad connection guidelines to meet qualifying conditions for CB Certificate.
(3) Soldered PowerPAD on a standard 2-layer PCB without vias for thermal pad. See TI application note SLMA002 for further details.
(4) Soldered PowerPAD on a standard 4-layer PCB with vias for thermal pad. See TI application note SLMA002 for further details.
2Copyright ©2005–2011, Texas Instruments Incorporated
TPS2060, TPS2064
TPS2068, TPS2069
www.ti.com
SLVS553K –MARCH 2005–REVISED MAY 2011
RECOMMENDED OPERATING CONDITIONS(1)
MIN MAX UNIT
Input voltage, VI(IN) 2.7 5.5 V
VIInput voltage, VI(ENx), VI(/ENx) 0 5.5 V
IOContinuous output current, IO(OUTx) 0 1.5 A
TPS2060/64 0 105
TJOperating virtual junction temperature TPS2068/69 (DGN Package) –40 105 °C
TPS2068 (D Package) 0 105
(1) The PowerPad must be connected externally to GND pin to meet qualifying conditions for CB Certificate (DGN package only).
ELECTRICAL CHARACTERISTICS
0°C≤TJ≤105°C for the TPS2060/64 and TPS2068 (D package), plus –40°C≤TJ≤105°for the
TPS2068/69 (DGN package), VI(IN) = 5.5 V, IO= 1 A, VI(/ENx) = 0 V, or VI(ENx) = 5.5 V (unless otherwise noted).
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
POWER SWITCH
Static drain-source on-state resistance,
5-V operation and VI(IN) = 5 V or 3.3 V, IO= 1.5 A 70 115 mΩ
3.3-V operation
rDS(on) Static drain-source on-state resistance, VI(IN) = 2.7 V, IO= 1.5 A 75 125 mΩ
2.7-V operation
VI(IN) = 5.5 V 0.6 1.5
trRise time, output VI(IN) = 2.7 V 0.4 1
CL= 1 μF, TJ= 25°C ms
RL= 5 Ω
VI(IN) = 5.5 V 0.05 0.5
tfFall time, output VI(IN) = 2.7 V 0.05 0.5
ENABLE INPUT EN OR EN
VIH High-level input voltage 2.7 V <VI(IN) <5.5 V 2 V
VIL Low-level input voltage 2.7 V <VI(IN) <5.5 V 0.8
IIInput current VI(/ENx) = 0 V or 5.5 V, VI(ENx) = 0 V or 5.5 V -0.5 0.5 μA
ton Turnon time CL= 100 μF, RL= 5 Ω3ms
toff Turnoff time CL= 100 μF, RL= 5 Ω10
CURRENT LIMIT
VI(IN) = 5 V, OUT connected to GND, device enabled into
IOS Short-circuit output current 1.6 2.1 2.6 A
short-circuit
TPS2060/64 3.2 3.9
VI(IN) = 5 V, Current ramp
IOC_TRIP Overcurrent trip threshold A
(≤100 A/s) on OUT TPS2068/69 2.3 2.85 3.4
VI(IN) = 5 V, OUT1 and OUT2 connected to GND, Device enabled
IOS (2) Short-circuit output current 3.2 4.2 5.2 A
into short-circuit, current measured at VI(IN)
Overcurrent trip threshold VI(IN) = 5 V, Current ramp (≤100 A/s) on OUT1 and OUT2 tied 6.4 7.8 A
IOC_TRIP (2) TPS2060/64 together, current measured at VI(IN) TJ= 25°C 0.5 1
No load on OUT, VI(/ENx) = 5.5 V,
IOL Supply current, low-level output μA
or VI(ENx) = 0 V Over TJrange 0.5 5
TJ= 25°C 50 70
Supply current, high-level output No load on OUT, VI(/ENx) = 0 V,
IOH μA
TPS2060/64 or VI(ENx) = 5.5 V Over TJrange 50 90
TJ= 25°C 43 60
Supply current, high-level output No load on OUT, VI(/ENx) = 0 V,
IOH μA
TPS2068/69 or VI(ENx) = 5.5 V Over TJrange 43 70
OUT connected to ground, VI(/ENx) = 5.5 V,
Ilkg Leakage current 1 μA
or VI(ENx) = 0 V
Reverse leakage current VI(OUTx) = 5.5 V, IN = ground TJ= 25°C 0.2 μA
UNDERVOLTAGE LOCKOUT
Low-level input voltage, IN 2 2.5 V
Hysteresis, IN TJ= 25°C 75 mV
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
(2) This configuration has not been tested for UL certification.
Copyright ©2005–2011, Texas Instruments Incorporated 3
TPS2060, TPS2064
TPS2068, TPS2069
SLVS553K –MARCH 2005–REVISED MAY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
0°C≤TJ≤105°C for the TPS2060/64 and TPS2068 (D package), plus –40°C≤TJ≤105°for the
TPS2068/69 (DGN package), VI(IN) = 5.5 V, IO= 1 A, VI(/ENx) = 0 V, or VI(ENx) = 5.5 V (unless otherwise noted).
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
OVERCURRENT OCx
VOL(/OCx) Output low voltage IO(/OCx) = 5 mA 0.4 V
Off-state current VO(/OCx) = 5 V or 3.3 V 1 μA
OC deglitch OCx assertion or deassertion 4 8 15 ms
THERMAL SHUTDOWN(3)
Thermal shutdown threshold 135 °C
Recovery from thermal shutdown 125 °C
Hysteresis 10 °C
(3) The thermal shutdown only reacts under overcurrent conditions.
DEVICE INFORMATION
Pin Functions
PINS I/O DESCRIPTION
DGN and DRB PACKAGES
NAME TPS2060 TPS2064
EN1 3 —I Enable input, logic low turns on power switch IN-OUT1
EN2 4 —I Enable input, logic low turns on power switch IN-OUT2
EN1 —3 I Enable input, logic high turns on power switch IN-OUT1
EN2 —4 I Enable input, logic high turns on power switch IN-OUT2
GND 1 1 Ground
IN 2 2 I Input voltage
OC1 8 8 O Overcurrent, open-drain output, active low, IN-OUT1
OC2 5 5 O Overcurrent, open-drain output, active low, IN-OUT2
OUT1 7 7 O Power-switch output, IN-OUT1
OUT2 6 6 O Power-switch output, IN-OUT2
PowerPad PowerPad Connect to GND
4Copyright ©2005–2011, Texas Instruments Incorporated
Thermal
Sense
Driver Current
Limit
Charge
Pump
UVLO
CS
Driver Current
Limit
CS
Thermal
Sense
Charge
Pump
GND
EN1
IN
EN2
OC1
OUT1
OUT2
OC2
Deglitch
Deglitch
(SeeNote A)
(SeeNote A)
(SeeNoteB)
(SeeNoteB)
TPS2060, TPS2064
TPS2068, TPS2069
www.ti.com
SLVS553K –MARCH 2005–REVISED MAY 2011
Functional Block Diagram (TPS2060 and TPS2064)
A. Current sense.
B. Active low (ENx) for TPS2060. Active high (ENx) for TPS2064.
Copyright ©2005–2011, Texas Instruments Incorporated 5
OUT
OC
IN
EN
GND
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense
Deglitch
(SeeNote A)
(SeeNoteB)
TPS2060, TPS2064
TPS2068, TPS2069
SLVS553K –MARCH 2005–REVISED MAY 2011
www.ti.com
DEVICE INFORMATION
Pin Functions (TPS2068 and TPS2069)
PINS I/O DESCRIPTION
NAME TPS2068 TPS2069
EN 4 —I Enable input, logic low turns on power switch
EN —4 I Enable input, logic high turns on power switch
GND 1 1 Ground
IN 2, 3 2, 3 I Input voltage
OC 5 5 O Overcurrent, open-drain output, active-low
OUT 6, 7, 8 6, 7, 8 O Power-switch output
PowerPad PowerPad Connect to GND (DGN Package Only)(1)
(1) See the Recommended Operating Conditions Table for PowerPad connection guidelines to meet qualifying conditions for CB Certificate
(DGN package only).
Functional Block Diagram (TPS2068 and TPS2069)
A. Current sense.
B. Active low (EN) for TPS2068. Active high (EN) for TPS2069.
6Copyright ©2005–2011, Texas Instruments Incorporated
RLCL
OUT
trtf
90% 90%
10%
10%
50% 50%
90%
10%
VO(OUT)
VI(EN)
VO(OUT)
VOLTAGE WAVEFORMS
TEST CIRCUIT
ton toff
50% 50%
90%
10%
VI(EN)
VO(OUT)
ton toff
VI(EN)
5V/div
VO(OUT)
2V/div
t-Time-400 sm
R =5
C =1 F,
L
L
W
m
,
=25 CTA°
VI(EN)
5V/div
VO(OUT)
2V/div
t-Time-400 sm
R =5
C =1 F,
L
L
W
m
,
=25 CTA°
TPS2060, TPS2064
TPS2068, TPS2069
www.ti.com
SLVS553K –MARCH 2005–REVISED MAY 2011
PARAMETER MEASUREMENT INFORMATION
Figure 1. Test Circuit and Voltage Waveforms
Figure 2. Turnon Delay and Rise Time With 1-μF Figure 3. Turnoff Delay and Fall Time With 1-μF
Load Load
Copyright ©2005–2011, Texas Instruments Incorporated 7
VI(EN)
5V/div
VO(OUT)
2V/div
t-Time-400 sm
R =5
C =100 F,
L
L
W
m
,
=25 CTA°
VI(EN)
5V/div
VO(OUT)
2V/div
t-Time-400 sm
R =5
C =100 F,
L
L
W
m
,
=25 CTA°
220 mF
470 mF
100 mF
VI(EN)
5 V/div
IO(OUT)
500 mA/div
t − Time − 500 ms/div
VIN = 5 V,
RL = 3 W,
TA = 255C
TPS2060, TPS2064
TPS2068, TPS2069
SLVS553K –MARCH 2005–REVISED MAY 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 4. Turnon Delay and Rise Time With 100-μF Figure 5. Turnoff Delay and Fall Time With 100-μF
Load Load
Figure 6. Short-Circuit Current, Figure 7. Inrush Current With Different
Device Enabled Into Short Load Capacitance
8Copyright ©2005–2011, Texas Instruments Incorporated
VO( )OCx
2V/div
IO(OUT)
1 A/div
t-Time-2ms/div
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
23456
Turnon Time − ms
VI − Input Voltage − V
CL = 100 mF,
RL = 5 W,
TA = 255C
1.5
1.6
1.7
1.8
1.9
2
2 3 4 5 6
CL = 100 mF,
RL = 5 W,
TA = 255C
Turnoff Time − mS
VI − Input Voltage − V
TPS2060, TPS2064
TPS2068, TPS2069
www.ti.com
SLVS553K –MARCH 2005–REVISED MAY 2011
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. 0.6-ΩLoad Connected to Enabled Device
TYPICAL CHARACTERISTICS
TURNON TIME TURNOFF TIME
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 9. Figure 10.
Copyright ©2005–2011, Texas Instruments Incorporated 9
0
0.1
0.2
0.3
0.4
0.5
0.6
2 3 4 5 6
Rise Time − ms
VI − Input Voltage − V
CL = 1 mF,
RL = 5 W,
TA = 255C
0
0.05
0.1
0.15
0.2
0.25
2 3 4 5 6
CL = 1 mF,
RL = 5 W,
TA = 255C
Fall Time − ms
VI − Input Voltage − V
0
10
20
30
40
50
60
70
−50 0 50 100 150
VI = 5.5 V
VI = 5 V
VI = 3.3 V
VI = 2.7 V
TJ − Junction Temperature − 5C
− Supply Current, Output Enabled −
II (IN) Aµ
0
10
20
40
50
60
-50 0 50 100 150
30
T -JunctionTemperature- C
J°
I -SupplyCurrent,OutputEnabled- A
I(IN) m
V =5.5V
I
V =3.3V
I
V =2.7V
I
V =5V
I
TPS2060, TPS2064
TPS2068, TPS2069
SLVS553K –MARCH 2005–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
RISE TIME FALL TIME
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 11. Figure 12.
TPS2060, TPS2064 TPS2068, TPS2069
SUPPLY CURRENT, OUTPUT ENABLED SUPPLY CURRENT, OUTPUT ENABLED
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 13. Figure 14.
10 Copyright ©2005–2011, Texas Instruments Incorporated
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
−50 0 50 100 150
VI = 5.5 V VI = 5 V
VI = 3.3 V
VI = 2.7 V
TJ − Junction Temperature − 5C
− Supply Current, Output Disabled −
II (IN) Aµ
0
20
40
60
80
100
120
−50 0 50 100 150
Out1 = 5 V
Out1 = 3.3 V
Out1 = 2.7 V
IO = 0.5 A
TJ − Junction Temperature − 5C
rDS(on) − Static Drain-Source
On-State Resistance − mΩ
2.1
2.14
2.18
2.22
2.26
2.3
−50 0 50 100 150
UVLO Rising
UVLO Falling
UVOL − Undervoltage Lockout − V
TJ − Junction Temperature − 5C
1.6
1.7
1.8
1.9
2
2.2
2.3
2.4
2.5
2.6
-50 0 50 100 150
2.1
T -JunctionTemperature- C
J°
I -Short-CircuitCurrentLimit- A
OS
V =2.7V
I
V =3.3V
I
V =5V
I
V =5.5V
I
TPS2060, TPS2064
TPS2068, TPS2069
www.ti.com
SLVS553K –MARCH 2005–REVISED MAY 2011
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT, OUTPUT DISABLED STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 15. Figure 16.
SHORT-CIRCUIT OUTPUT CURRENT UNDERVOLTAGE LOCKOUT
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 17. Figure 18.
Copyright ©2005–2011, Texas Instruments Incorporated 11
0
50
100
150
200
0 2.5 5 7.5 10
Current-LimitResponse- sm
PeakCurrent- A
VI=5V,
TA°=25 C
TPS2060, TPS2064
TPS2068, TPS2069
SLVS553K –MARCH 2005–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
CURRENT-LIMIT RESPONSE
vs
PEAK CURRENT
Figure 19.
12 Copyright ©2005–2011, Texas Instruments Incorporated
IN
OC1
EN1
OC2
2
8
5
7
0.1 µF22 µF
0.1 µF22 µF
Load
Load
OUT1
OUT2
Power Supply
2.7 V to 5.5 V
6
EN2
3
4
GND
0.1 µF
TPS2060
1
TPS2060, TPS2064
TPS2068, TPS2069
www.ti.com
SLVS553K –MARCH 2005–REVISED MAY 2011
APPLICATION INFORMATION
POWER-SUPPLY CONSIDERATIONS
Figure 20. Typical Application
A 0.01-μF to 0.1-μF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the
output with a 0.01-μF to 0.1-μF ceramic capacitor improves the immunity of the device to short-circuit transients.
OVERCURRENT
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not
increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only
if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 6). The TPS206x senses the short and
immediately switches into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, high currents may flow for a short period of time before the current-limit circuit can react (see Figure 8).
After the current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into
constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded. The TPS206x is capable of delivering current up to the current-limit threshold without damaging the
device. Once the threshold has been reached, the device switches into its constant-current mode.
OC RESPONSE
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition
is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or
overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a
momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit.
The TPS206x is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch eliminates
the need for external components to remove unwanted pulses. OCx is not deglitched when the switch is turned
off due to an overtemperature shutdown.
Copyright ©2005–2011, Texas Instruments Incorporated 13
GND
IN
EN1
EN2
OC1
OC2
OUT1
OUT2
TPS2060 Rpullup
V+
TPS2060, TPS2064
TPS2068, TPS2069
SLVS553K –MARCH 2005–REVISED MAY 2011
www.ti.com
Figure 21. Typical Circuit for the OC Pin
POWER DISSIPATION AND JUNCTION TEMPERATURE
The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large
currents. The thermal resistance of these packages are high compared to those of power packages; it is good
design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of the
N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the
highest operating ambient temperature of interest and read rDS(on) from Figure 16. Using this value, the power
dissipation per switch can be calculated by:
PD= rDS(on) ×I2
Multiply this number by the number of switches being used. This step renders the total power dissipation from
the N-channel MOSFETs.
Finally, calculate the junction temperature:
TJ= PD×RθJA + TA
Where:
TA= Ambient temperature °C
RθJA = Thermal resistance
PD= Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
THERMAL PROTECTION
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The TPS206x implements a thermal sensing to monitor the operating junction
temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperature
rises due to excessive power dissipation. Once the die temperature rises to approximately 140°C due to
overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the power
switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled
approximately 10°C, the switch turns back on. The switch continues to cycle in this manner until the load fault or
input power is removed. The OCx open-drain output is asserted (active low) when an overtemperature shutdown
or overcurrent occurs.
UNDERVOLTAGE LOCKOUT (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input
voltage falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if the
switch is enabled. On reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and
voltage overshoots.
14 Copyright ©2005–2011, Texas Instruments Incorporated
TPS2060, TPS2064
TPS2068, TPS2069
www.ti.com
SLVS553K –MARCH 2005–REVISED MAY 2011
UNIVERSAL SERIAL BUS (USB) APPLICATIONS
The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for low-
to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
•Hosts/self-powered hubs (SPH)
•Bus-powered hubs (BPH)
•Low-power, bus-powered functions
•High-power, bus-powered functions
•Self-powered functions
SPHs and BPHs distribute data and power to downstream functions. The TPS206x has higher current capability
than required by one USB port; so, it can be used on the host side and supplies power to multiple downstream
ports or functions.
HOST/SELF-POWERED AND BUS-POWERED HUBS
Hosts and SPHs have a local power supply that powers the embedded functions and the downstream ports (see
Figure 22). This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream
connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection
and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers,
and stand-alone hubs.
Copyright ©2005–2011, Texas Instruments Incorporated 15
IN
OC1
EN1
OC2
EN2
GND
0.1 µF
2
8
3
5
4
7
22 µF
22 µF
GND
1
OUT1
TPS2060
Power Supply
D+
D−
VBUS
GND
D+
D−
VBUS
Downstream
USB Ports
USB
Controller
3.3 V 5 V
2 µFGND
OUT2
D+
D−
VBUS
22 µFGND
D+
D−
VBUS
6
0.1 µF
0.1 µF
0.1 µF
0.1 µF
22 µFGND
D+
D−
VBUS
0.1 µF
22 µFGND
D+
D−
VBUS
0.1 µF
TPS2060, TPS2064
TPS2068, TPS2069
SLVS553K –MARCH 2005–REVISED MAY 2011
www.ti.com
Figure 22. Typical Six-Port USB Host/Self-Powered Hub
BPHs obtain all power from upstream ports and often contain an embedded function. The hubs are required to
power up with less than one unit load. The BPH usually has one embedded function, and power is always
available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up,
the power to the embedded function may need to be kept off until enumeration is completed. This can be
accomplished by removing power or by shutting off the clock to the embedded function. Power switching the
embedded function is not necessary if the aggregate power draw for the function and controller is less than one
unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
16 Copyright ©2005–2011, Texas Instruments Incorporated
IN
OC1
OC2
2
8
3
5
4
7
0.1 µF10 µFInternal
Function
OUT1
Power Supply
3.3 V
EN1
6
0.1 µF10 µF
OUT2 Internal
Function
0.1 µF
10 µF
USB
Control
GND
VBUS
D−
D+ TPS2060
EN2 GND
1
TPS2060, TPS2064
TPS2068, TPS2069
www.ti.com
SLVS553K –MARCH 2005–REVISED MAY 2011
LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS
Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can
draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω
and 10 μF at power up, the device must implement inrush current limiting (see Figure 23). With TPS206x, the
internal functions could draw more than 500 mA, which fits the needs of some applications such as motor driving
circuits.
Figure 23. High-Power Bus-Powered Function
USB POWER-DISTRIBUTION REQUIREMENTS
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
•Hosts/SPHs must:
–Current-limit downstream ports
–Report overcurrent conditions on USB VBUS
•BPHs must:
–Enable/disable power to downstream ports
–Power up at <100 mA
–Limit inrush current (<44 Ωand 10 μF)
•Functions must:
–Limit inrush currents
–Power up at <100 mA
The feature set of the TPS206x allows them to meet each of these requirements. The integrated current-limiting
and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and controlled rise
times meet the need of both input and output ports on bus-powered hubs, as well as the input ports for
bus-powered functions (see Figure 24).
Copyright ©2005–2011, Texas Instruments Incorporated 17
DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
DM4
DP0
DM0
VCC
XTAL1
XTAL2
OCSOFF
SN75240
D +
D −
5 V
GND
D +
D −
5 V
D +
D −
5 V
D +
D −
5 V
48-MHz
Crystal
Downstream
Ports
TUSB2040
Hub Controller
Tuning
Circuit
A
BC
D
33 µF†
SN75240
A
BC
D
GND
GND
GND
33 µF†
33 µF†
33 µF†
D +
D −
Upstream
Port
TPS2041B
SN75240
A
B
5 V
GND
C
D
1 µF
IN
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR
GANGED
Tie to TPS2041 EN Input
OC EN
OUT
5-V Power
Supply
IN
GND
3.3 V
4.7 µF
0.1 µF
4.7 µF
EN1
IN
OC1
OUT1
TPS2060
EN2
OC2
OUT2
0.1 µF
GND
†USB rev 1.1 requires 120 µF per hub.
TPS76333
TPS2060, TPS2064
TPS2068, TPS2069
SLVS553K –MARCH 2005–REVISED MAY 2011
www.ti.com
Figure 24. Hybrid Self / Bus-Powered Hub Implementation
GENERIC HOT-PLUG APPLICATIONS
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen by
the main power supply and the card being inserted. The most effective way to control these surges is to limit and
slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS206x, these devices can be used to
provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS206x
also ensures that the switch is off after the card has been removed, and that the switch is off during the next
insertion. The UVLO feature insures a soft start with a controlled rise time for every insertion of the card or
module.
18 Copyright ©2005–2011, Texas Instruments Incorporated
Power
Supply
0.1 µF
1000 µF
Optimum
2.7 V to 5.5 V
PC Board
Overcurrent Response
TPS2060
OC1
GND
EN1
IN
EN2
OUT1
OUT2
OC2 Block of
Circuitry
Block of
Circuitry
TPS2060, TPS2064
TPS2068, TPS2069
www.ti.com
SLVS553K –MARCH 2005–REVISED MAY 2011
Figure 25. Typical Hot-Plug Implementation
By placing the TPS206x between the VCC input and the rest of the circuitry, the input power reaches these
devices first after insertion. The typical rise time of the switch is approximately 1 ms, providing a slow voltage
ramp at the output of the device. This implementation controls system surge currents and provides a
hot-plugging mechanism for any device.
DETAILED DESCRIPTION
Power Switch
The power switch is an N-channel MOSFET with a low on-state resistance. Configured as a high-side switch, the
power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies a
minimum current of 1.5 A.
Charge Pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
little supply current.
Driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall
times of the output voltage.
Enable (ENx)
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current. The supply current is reduced to less than 1 μA when a logic high is present on ENx, or when
a logic low is present on ENx. A logic zero input on ENx, or a logic high input on ENx restores bias to the drive
and control circuits and turns the switch on. The enable input is compatible with both TTL and CMOS logic
levels.
Overcurrent (OCx)
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A
10-ms deglitch circuit prevents the OCx signal from oscillation or false triggering. If an overtemperature shutdown
occurs, the OCx is asserted instantaneously.
Copyright ©2005–2011, Texas Instruments Incorporated 19
TPS2060, TPS2064
TPS2068, TPS2069
SLVS553K –MARCH 2005–REVISED MAY 2011
www.ti.com
Current Sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its
saturation region, which switches the output into a constant-current mode and holds the current constant while
varying the voltage on the load.
Thermal Sense
The TPS206x implements a thermal sensing to monitor the operating temperature of the power distribution
switch. In an overcurrent or short-circuit condition the junction temperature rises. When the die temperature rises
to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns off the switch,
thus preventing the device from damage. Hysteresis is built into the thermal sense, and after the device has
cooled approximately 10 degrees, the switch turns back on. The switch continues to cycle off and on until the
fault is removed. The open-drain false reporting output (OCx) is asserted (active low) when an overtemperature
shutdown or overcurrent occurs.
Undervoltage Lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
20 Copyright ©2005–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 7-May-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2060DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2060DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2060DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2060DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2060DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2060DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2064DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2064DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2064DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2064DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2064DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2064DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2068D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2068DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2068DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2068DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2068DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 7-May-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2068DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2068DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2068DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2069DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2069DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2069DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2069DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 7-May-2011
Addendum-Page 3
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS2068 :
•Automotive: TPS2068-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2060DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TPS2060DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS2060DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS2060DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS2064DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TPS2064DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS2064DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS2064DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS2068DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TPS2068DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jun-2012
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2068DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2069DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2060DGNR MSOP-PowerPAD DGN 8 2500 346.0 346.0 35.0
TPS2060DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0
TPS2060DRBR SON DRB 8 3000 346.0 346.0 35.0
TPS2060DRBT SON DRB 8 250 203.0 203.0 35.0
TPS2064DGNR MSOP-PowerPAD DGN 8 2500 346.0 346.0 35.0
TPS2064DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0
TPS2064DRBR SON DRB 8 3000 346.0 346.0 35.0
TPS2064DRBT SON DRB 8 250 203.0 203.0 35.0
TPS2068DGNR MSOP-PowerPAD DGN 8 2500 346.0 346.0 35.0
TPS2068DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0
TPS2068DR SOIC D 8 2500 533.4 186.0 36.0
TPS2069DGNR MSOP-PowerPAD DGN 8 2500 346.0 346.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jun-2012
Pack Materials-Page 2
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