Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
3851 Group
(Built-in 24 KB or more ROM)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
DESCRIPTION
The 3851 group (built-in 24 KB or more ROM) is the 8-bit micro-
computer based on the 740 family core technology.
The 3851 group (built-in 24 KB or more ROM) is designed for the
household products and office automation equipment and includes
serial I/O functions, 8-bit timer, I2C-bus interface, and A-D con-
verter.
FEATURES
●Basic machine-language instructions ...................................... 71
●Minimum instruction execution time .................................. 0.5 µs
(at 8 MHz oscillation frequency)
●Memory size
ROM ................................................................. 24K to 32K bytes
RAM .....................................................................640 to 1K bytes
●Programmable input/output ports ............................................ 34
●Interrupts ................................................. 17 sources, 16 vectors
●Timers ............................................................................. 8-bit ✕ 4
●Serial I/O1 .................... 8-bit ✕ 1(UART or Clock-synchronized)
●Serial I/O2 ................................... 8-bit ✕ 1(Clock-synchronized)
●Multi-master I2C-bus interface (option) ....................... 1 channel
●PWM ............................................................................... 8-bit ✕ 1
●A-D converter ............................................... 10-bit ✕ 5 channels
●Watchdog timer ............................................................ 16-bit ✕ 1
PIN CONFIGURATION (TOP VIEW)
Fig. 1 M38517M8-XXXFP/SP pin configuration
●Clock generating circuit..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power source voltage
In high-speed mode .................................................. 4.0 to 5.5 V
(at 8 MHz oscillation frequency)
In middle-speed mode............................................... 2.7 to 5.5 V
(at 8 MHz oscillation frequency)
In low-speed mode .................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency)
●Power dissipation
In high-speed mode ..........................................................34 mW
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode
Except M38517F8FP/SP................................................... 60 µW
M38517F8FP/SP ............................................................. 450 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
●Operating temperature range....................................–20 to 85°C
APPLICATION
Office automation equipment, FA equipment, Household products,
Consumer electronics, etc.
Package type : FP ........................... 42P2R-A/E (42-pin plastic-molded SSOP)
Package type : SP ........................... 42P4B (42-pin plastic-molded SDIP)
P
40/
C
N
T
R1
P41/INT0
P
42/
I
N
T1
P
43/
I
N
T2/
SC
M
P
2
P44/INT3/PWM
VR
E
F
VC
CP31/AN1
P32/AN2
P0
0
/SIN2
P04
P05
P06
P07
P11/(LED1)
P12/(LED2)
P13/(LED3)
P14/(LED4)
P15/(LED5)
P10/(LED0)
P01/SOUT2
P02/SCLK2
P30/AN0
P33/AN3
P34/AN4
P03/SRDY2
4
0
4
1
42
2
2
2
3
24
2
5
2
6
27
2
8
2
9
30
3
1
3
2
3
4
35
36
3
7
3
8
3
9
3
3
3
2
1
2
1
2
0
19
1
8
1
7
16
1
5
1
4
13
1
2
1
1
9
8
7
6
5
4
1
0
M
3
8
5
1
7
M
8
-
X
X
X
F
P
/
S
P
P16/(LED6)
P17/(LED7)
P
27/
C
N
T
R0/
SR
D
Y
1
P
26/
SC
L
K
1
P
25/
S
C
L2/
T
x
D
P
24/
S
D
A2/
R
x
D
P
23/
S
C
L1
P22/SDA1
C
N
VS
S
P
21/
XC
I
N
P20/XCOUT
RESET
XI
N
XOUT
VS
S
AVSS
✽This data sheet explains the products which have
24 KB or more ROM.
1
2
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
FUNCTIONAL BLOCK DIAGRAM
Fig.2 Functional block diagram
FUNCTIONAL BLOCK
I
N
T
0
–
V
R
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F
A
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6
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(
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3
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
I/O port P2
I/O port P3
I/O port P4
VCC, VSS
CNVSS
VREF
AVSS
RESET
XIN
XOUT
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04–P07
P10–P17
Functions
NamePin
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
•This pin controls the operation mode of the chip.
•Normally connected to VSS.
•Reference voltage input pin for A-D converter.
•Analog power source input pin for A-D converter.
•Connect to Vss.
•Reset input pin for active “L.”
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
•CMOS 3-state output structure.
•P10 to P17 (8 bits) are enabled to output large current
for LED drive.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
•P22 to P25 can be switched between CMOS compatible
input level or SMBUS input level in the I2C-BUS inter-
face function.
•P20, P21, P24 to P27: CMOS3-state output structure.
•P24, P25: N-channel open-drain structure in the I2C-
BUS interface function.
•P22, P23: N-channel open-drain structure.
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
Power source
CNVSS input
Reference
voltage input
Analog power
source input
Table 1 Pin description
Function except a port function
• Serial I/O2 function pin
• Sub-clock generating circuit I/O
pins (connect a resonator)
Reset input
Clock input
Clock output
I/O port P0
I/O port P1
P20/XCOUT
P21/XCIN
P22/SDA1
P23/SCL1
P24/SDA2/RxD
P25/SCL2/TxD
P26/SCLK1
P27/CNTR0/
SRDY1
P30/AN0–
P34/AN4
P40/CNTR1
P41/INT0
P42/INT1
P43/INT2/SCMP2
P44/INT3/PWM
•I2C-BUS interface function pins
•I2C-BUS interface function pin/
Serial I/O1 function pins
•Serial I/O1 function pin
• Serial I/O1 function pin/Timer X
function pin
• A-D converter input pin
• Timer Y function pin
• Interrupt input pins
• Interrupt input pin
• SCMP2 output pin
• Interrupt input pin
• PWM output pin
4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
PART NUMBERING
Fig. 3 Part numbering
M
3
8
5
14 M 6 –X
X
XS
P
Product name
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1
2
3
4
5
6
7
8
: 4096 bytes
: 8192 bytes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 bytes
: 32768 bytes
T
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f
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s
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Me mory type
M: Mask ROM version
E : EPROM or One T ime PROM ve rsion
F : Flash memory version
R
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1
2
3
4
: 192 bytes
: 256 bytes
: 384 bytes
: 512 bytes
: 640 bytes
–
:
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: 36864 bytes
: 40960 bytes
: 45056 bytes
: 49152 bytes
: 53248 bytes
: 57344 bytes
: 61440 bytes
9
A
B
C
D
E
F
5
6
7
8
9
: 768 bytes
: 896 bytes
: 1024 bytes
: 1536 bytes
: 2048 bytes
5
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
GROUP EXPANSION
Mitsubishi plans to expand the 3851 group (built-in 24 KB or more
ROM) as follows.
Memory Type
Support for mask ROM, One Time PROM, and flash memory ver-
sions.
Memory Size
Flash memory size .........................................................32 K bytes
Mask ROM size ................................................. 24 K t o 32 K bytes
One Time PROM size.....................................................24 K bytes
RAM size ...............................................................640 to 1 K bytes
Packages
42P4B ......................................... 42-pin shrink plastic-molded DIP
42P2R-A/E......................................... 42-pin plastic-molded SSOP
42S1B-A .................. 42-pin shrink ceramic DIP (EPROM version)
Fig. 4 Memory expansion plan
Memory Expansion Plan
32K
28K
2
4
K
2
0
K
16K
12K
8
K
384 512 640 768 896 1024 1152 1280 1408 1536 2048
R
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(
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R
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(
b
y
t
e
s
)
M38517M8/F8
M38514M6/E6
Products under development or planning: the development schedule and specification may be revised without notice.
The development of planning products may be stopped.
M
a
s
s
p
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o
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n
t
6
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Currently planning products are listed below.
RAM size (bytes) Remarks
Package
Table 2 Support products
Product name
24576
(24446)
ROM size (bytes)
ROM size for User in ( )
M38514M6-XXXSP
M38514E6-XXXSP
M38514E6SP
M38514E6SS
M38514M6-XXXFP
M38514E6-XXXFP
M38514E6FP
42P4B Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
640
Table 4 Differences between 3851 group (built-in 16 KB ROM) and 3851 group (built-in 24 KB or more ROM)
Serial I/O
A-D converter
Large current port
3851 group (built-in 16 KB ROM)
1: Serial I/O
(UART or Clock-synchronized)
Unserviceable in low-speed mode
5: P13–P17
3851 group (built-in 24 KB or more ROM)
2: Serial I/O1 (UART or Clock-synchronized)
Serial I/O2 (Clock-synchronized)
Serviceable in low-speed mode
8: P10–P17
Notes on differences between 3851 group
(built-in 16 KB ROM), 3851 group (built-in 24
KB or more ROM)
(1) The absolute maximum ratings of 3851 group (built-in 24 KB or
more ROM) is smaller than that of 3851 group (built-in 16 KB
ROM).
•Power source voltage Vcc = –0.3 to 6.5 V
•CNVss input voltage
VI = –0.3 to Vcc +0.3 V (M38514M6, M38517M8)
VI = –0.3 to 6.5 V (M38517F8)
(2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may
be some differences between 3851 group (built-in 16 KB
ROM) and 3851 group (built-in 24 KB or more ROM).
(3) Do not write any data to the reserved area and the reserved
bit. (Do not change the contents after reset.)
(4) Fix bit 3 of the CPU mode register to “1”.
(5) Be sure to perform the termination of unused pins.
42S1B-A
42P2R-A/E
Table 3 3851 group (built-in 16 KB ROM) and 3851 group (built-in 24 KB or
more ROM) corresponding products
3851 group (built-in 16 KB ROM)
M38513M4-XXXFP/SP
M38513E4-XXXFP/SP
M38513E4FP/SP
M38513E4SS
3851 group (built-in 24 KB or more ROM)
M38514M6-XXXFP/SP
M38514E6-XXXFP/SP
M38514E6FP/SP
M38514E6SS
M38517M8-XXXFP/SP
M38517F8FP/SP
7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 3851 group uses the standard 740 Family instruction set. Re-
fer to the table of 740 Family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack ad-
dress are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with pro-
gram when the user needs them during interrupts or subroutine
calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
Fig. 5 740 Family CPU register structure
A Accumulator
b7
b7
b7
b7 b0
b7b15 b0
b7 b0
b0
b0
b0
X Index register X
Y Index register Y
S Stack pointer
PC
L
Program counterPC
H
N V T B D I Z C Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
8
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Table 5 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Fig. 6 Register push and pop at interrupt generation and subroutine call
Note: Condition for acceptance of an interrupt Interrupt enable flag is “1”
E
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s
s
f
r
o
m
s
t
a
c
k
P
u
s
h
r
e
t
u
r
n
a
d
d
r
e
s
s
o
n
s
t
a
c
kM
(
S
)(
P
S
)
E
x
e
c
u
t
e
R
T
I
(
P
S
)M
(
S
)
(
S
)
(
S
)
–
1
(
S
)
(
S
)
+
1
I
n
t
e
r
r
u
p
t
S
e
r
v
i
c
e
R
o
u
t
i
n
e
P
O
P
c
o
n
t
e
n
t
s
o
f
p
r
o
c
e
s
s
o
r
s
t
a
t
u
s
r
e
g
i
s
t
e
r
f
r
o
m
s
t
a
c
k
M
(
S
)(
P
CH)
(
S
)
(
S
)
–
1
M
(
S
)(
P
CL)
(
S
)
(
S
)
–
1
(
P
CL)M
(
S
)
(
S
)
(
S
)
+
1
(
S
)
(
S
)
+
1
(
P
CH)M
(
S
)
P
O
P
r
e
t
u
r
n
a
d
d
r
e
s
s
f
r
o
m
s
t
a
c
k
I
F
l
a
g
i
s
s
e
t
f
r
o
m
“
0
”
t
o
“
1
”
F
e
t
c
h
t
h
e
j
u
m
p
v
e
c
t
o
r
P
u
s
h
r
e
t
u
r
n
a
d
d
r
e
s
s
o
n
s
t
a
c
k
P
u
s
h
c
o
n
t
e
n
t
s
o
f
p
r
o
c
e
s
s
o
r
s
t
a
t
u
s
r
e
g
i
s
t
e
r
o
n
s
t
a
c
k
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
(Note)
Interrupt disable flag is “0”
9
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 6 Set and clear instructions of each bit of processor status register
Set instruction
Clear instruction
C flag Z flag I flag D flag B flag T flag V flag N flag
SEC
CLC
_
_SEI
CLI SED
CLD
_
_SET
CLT CLV
__
_
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
10
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B16.
Fig. 7 Structure of CPU mode register
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
(
C
P
U
M
:
a
d
d
r
e
s
s
0
0
3
B1
6)
b
7b
0
Stack page selection bit
0 : 0 page
1 : 1 page
F
i
x
t
h
i
s
b
i
t
t
o
“
1
”
.
P
r
o
c
e
s
s
o
r
m
o
d
e
b
i
t
s
b
1
b
0
0
0
:
S
i
n
g
l
e
-
c
h
i
p
m
o
d
e
0
1
:
1
0
:
N
o
t
a
v
a
i
l
a
b
l
e
1
1
:
P
o
r
t
XC
s
w
i
t
c
h
b
i
t
0
:
I
/
O
p
o
r
t
f
u
n
c
t
i
o
n
(
s
t
o
p
o
s
c
i
l
l
a
t
i
n
g
)
1
:
XC
I
N–
XC
O
U
T
o
s
c
i
l
l
a
t
i
n
g
f
u
n
c
t
i
o
n
M
a
i
n
c
l
o
c
k
(
XI
N–
XO
U
T)
s
t
o
p
b
i
t
0
:
O
s
c
i
l
l
a
t
i
n
g
1
:
S
t
o
p
p
e
d
M
a
i
n
c
l
o
c
k
d
i
v
i
s
i
o
n
r
a
t
i
o
s
e
l
e
c
t
i
o
n
b
i
t
s
b
7
b
6
0
0
:
φ
=
f
(
XI
N)
/
2
(
h
i
g
h
-
s
p
e
e
d
m
o
d
e
)
0
1
:
φ
=
f
(
XI
N)
/
8
(
m
i
d
d
l
e
-
s
p
e
e
d
m
o
d
e
)
1
0
:
φ
=
f
(
XC
I
N)
/
2
(
l
o
w
-
s
p
e
e
d
m
o
d
e
)
1
1
:
N
o
t
a
v
a
i
l
a
b
l
e
1
11
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains
control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
Access to this area with only 2 bytes is possible in the special
page addressing mode.
Fig. 8 Memory map diagram
0100
1
6
0
0
0
0
1
6
0
0
4
0
1
6
F
F
0
0
1
6
FFDC
1
6
F
F
F
E
1
6
FFFF
1
6
1
9
2
2
5
6
3
8
4
5
1
2
6
4
0
7
6
8
8
9
6
1
0
2
4
1
5
3
6
2
0
4
8
XXXX
1
6
0
0
F
F
1
6
0
1
3
F
1
6
0
1
B
F
1
6
0
2
3
F
1
6
0
2
B
F
1
6
0
3
3
F
1
6
0
3
B
F
1
6
0
4
3
F
1
6
0
6
3
F
1
6
0
8
3
F
1
6
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F000
16
E000
16
D000
16
C000
16
B000
16
A000
16
9000
16
8000
16
7000
16
6000
16
5000
16
4000
16
3000
16
2000
16
1000
16
F080
16
E080
16
D080
16
C080
16
B080
16
A080
16
9080
16
8080
16
7080
16
6080
16
5080
16
4080
16
3080
16
2080
16
1080
16
Y
Y
Y
Y
1
6
ZZZZ
1
6
RAM
ROM
0FF0
16
0
F
F
F
1
6
SFR area
N
o
t
u
s
e
d
I
n
t
e
r
r
u
p
t
v
e
c
t
o
r
a
r
e
a
ROM area R
e
s
e
r
v
e
d
R
O
M
a
r
e
a
(
1
2
8
b
y
t
e
s
)
Zero page
Special page
R
A
M
a
r
e
a
R
A
M
s
i
z
e
(
b
y
t
e
s
)A
d
d
r
e
s
s
X
X
X
X
1
6
R
O
M
s
i
z
e
(
b
y
t
e
s
)A
d
d
r
e
s
s
Y
Y
Y
Y
1
6
Reserved ROM are
a
A
d
d
r
e
s
s
Z
Z
Z
Z
1
6
N
o
t
u
s
e
d
S
F
R
a
r
e
a
(
N
o
t
e
)
N
o
t
e
:
F
l
a
s
h
m
e
m
o
r
y
v
e
r
s
i
o
n
o
n
l
y
12
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 9 Memory map of special function register (SFR)
0
0
2
0
1
6
0
0
2
1
1
6
0
0
2
2
1
6
0
0
2
3
1
6
0
0
2
4
1
6
0
0
2
5
1
6
0
0
2
6
1
6
0
0
2
7
1
6
0
0
2
8
1
6
0
0
2
9
1
6
0
0
2
A
1
6
0
0
2
B
1
6
0
0
2
C
1
6
0
0
2
D
1
6
002E
16
002F
16
0
0
3
0
1
6
0
0
3
1
1
6
0032
16
0
0
3
3
1
6
0034
16
0
0
3
5
1
6
0
0
3
6
1
6
0037
16
0
0
3
8
1
6
0039
16
0
0
3
A
1
6
0
0
3
B
1
6
003C
16
0
0
3
D
1
6
003E
16
0
0
3
F
1
6
0
0
0
0
1
6
0
0
0
1
1
6
0
0
0
2
1
6
0
0
0
3
1
6
0
0
0
4
1
6
0
0
0
5
1
6
0
0
0
6
1
6
0
0
0
7
1
6
0
0
0
8
1
6
0
0
0
9
1
6
0
0
0
A
1
6
0
0
0
B
1
6
0
0
0
C
1
6
0
0
0
D
1
6
000E
16
000F
16
0
0
1
0
1
6
0
0
1
1
1
6
0012
16
0
0
1
3
1
6
0014
16
0
0
1
5
1
6
0
0
1
6
1
6
0017
16
0
0
1
8
1
6
0019
16
0
0
1
A
1
6
0
0
1
B
1
6
001C
16
0
0
1
D
1
6
001E
16
0
0
1
F
1
6
P
o
r
t
P
0
(
P
0
)
P
o
r
t
P
0
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
0
D
)
P
o
r
t
P
1
(
P
1
)
P
o
r
t
P
1
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
1
D
)
P
o
r
t
P
2
(
P
2
)
P
o
r
t
P
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
2
D
)
Port P3 (P3)
P
o
r
t
P
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
3
D
)
P
o
r
t
P
4
(
P
4
)
P
o
r
t
P
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
4
D
)
T
r
a
n
s
m
i
t
/
R
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
(
T
B
/
R
B
)
S
e
r
i
a
l
I
/
O
1
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
S
I
O
S
T
S
)
Serial I/O1 control register (SIOCON)
UART control register (UARTCON)
B
a
u
d
r
a
t
e
g
e
n
e
r
a
t
o
r
(
B
R
G
)
Inter rupt control register 2 ( ICON2)
A-D con v er s ion low-or der r egister ( A DL)
Prescaler Y (PREY)
Timer Y (TY)
A-D control register (ADCON)
A-D con v er s ion high-or der regist er (A DH)
Interr upt edge selection reg is ter (INTEDGE)
CPU mode register (CPUM)
Interr upt request register 1 ( I RE Q1)
Interr upt request register 2 ( I RE Q2)
Inter rupt control register 1 ( ICON1)
Prescaler 12 (PR E 12)
Timer 2 (T2)
Prescaler X (PREX)
Timer X (TX)
Timer 1 (T1)
Timer XY mode register (TM)
I
2
C data shift register ( S 0)
MISRG
Watchdog timer c ontrol register (WDTCON)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
P
W
M
r
e
g
i
s
t
e
r
(
P
W
M
)
Timer count source selection register (TCSS)
Serial I/O2 control register 1 (SIO2CON1)
Serial I/O2 control register 2 (SIO2CON2)
Serial I/O2 register (SIO2)
✽ Reserved : Do not write any data to this addresses, because these areas are reserved.
I
2
C addres s r egister (S0D )
I
2
C statu s re gis ter (S1)
I
2
C control register ( S 1D)
I
2
C clock control register (S2)
I
2
C start/stop condition control reg ister (S2D)
Reserved ✽
Reserved ✽
R
e
s
e
r
v
e
d
✽
R
e
s
e
r
v
e
d
✽
Reserved ✽
0FFD
16
Flash memory control register 1 (FMCR)
0
F
F
E
1
6
0
F
F
F
1
6
R
e
s
e
r
v
e
d
R
e
s
e
r
v
e
d
13
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be
input port or output port.
When “0” is written to the bit corresponding to a pin, that pin
becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Pin Name Input/Output I/O Structure Non-Port Function
Table 7 I/O port function Related SFRs
Port P0
Port P1
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04–P07
P10–P17
P20/XCOUT
P21/XCIN
P22/SDA1
P23/SCL1
P24/SDA2/RxD
P25/SCL2/TxD
P26/SCLK1
P27/CNTR0/SRDY1
P30/AN0–P34/AN4
P40/CNTR1
P41/INT0
P42/INT1
P43/INT2/SCMP2
P44/INT3/PWM
CMOS compatible
input level
CMOS 3-state output
Serial I/O2 control register
Serial I/O2 function I/O
CPU mode register
CMOS compatible
input level
CMOS/SMBUS input
level (when selecting I
2
C-
BUS interface function)
CMOS 3-state output
N-channel open-drain
output (when selecting I
2
C-
BUS interface function)
Input/output,
individual
bits
Ref.No.
(5)
(1)
(2)
(3)
(4)
(6)
(7)
(8)
(9)
(10)
(11)
(17)
CMOS compatible
input level
CMOS/SMBUS input
level (when selecting I
2
C-
BUS interface function)
N-channel open-drain
output
(12)
(13)
(14)
Sub-clock generating
circuit
I2C-BUS interface
function I/O
I2C-BUS interface
function I/O
Serial I/O1 function I/O
Serial I/O1 function I/O
Serial I/O1 function I/O
Timer X function I/O
A-D conversion input
Timer Y function I/O
External interrupt input
External interrupt input
SCMP2 output
External interrupt input
PWM output
Port P2
Port P3
Port P4
CMOS compatible
input level
CMOS 3-state
output
I2C control register
I2C control register
Serial I/O1 control register
Serial I/O1 control register
Serial I/O1 control register
Timer XY mode register
A-D control register
Timer XY mode register
Interrupt edge selection
register
Interrupt edge selection register
Serial I/O2 control register
Interrupt edge selection register
PWM control register
(15)
(16)
(18)
Note: When reading bit 5, 6, or 7 of ports P3 and P4, the contents are undefined.
14
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 10 Port block diagram (1)
P
o
r
t
l
a
t
c
h
(
1
)
P
o
r
t
P
00(2) Port P01
P01/SOUT2 P-channel output disable bit
P
02/
SC
L
K
2
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
Direction
register
P
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Port latch
Direction
register
Direction
register
Port latch
Direction
register
Port latch
Direction
register
P
o
r
t
l
a
t
c
h
D
a
t
a
b
u
s
Data bus
D
a
t
a
b
u
sData bus
D
a
t
a
b
u
s
Data bus
S
e
r
i
a
l
I
/
O
2
i
n
p
u
t
Serial I/O2 output
Serial I/O2 Transmit completion signal
S
e
r
i
a
l
I
/
O
2
p
o
r
t
s
e
l
e
c
t
i
o
n
b
i
t
(
3
)
P
o
r
t
P
02
S
e
r
i
a
l
I
/
O
2
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
S
e
r
i
a
l
I
/
O
2
p
o
r
t
s
e
l
e
c
t
i
o
n
b
i
t
S
e
r
i
a
l
I
/
O
2
c
l
o
c
k
o
u
t
p
u
t
S
e
r
i
a
l
I
/
O
2
e
x
t
e
r
n
a
l
c
l
o
c
k
i
n
p
u
t
(4) Port P03
S
e
r
i
a
l
I
/
O
2
r
e
a
d
y
o
u
t
p
u
t
SRDY2 output enable bit
(5) Ports P04-P07,P1 (6) Port P20
P
o
r
t
XC
s
w
i
t
c
h
b
i
t
O
s
c
i
l
l
a
t
o
r
Port XC switch bi
t
P
o
r
t
P
21
(
7
)
P
o
r
t
P
21
Port XC switch bit
Data bus
S
u
b
-
c
l
o
c
k
g
e
n
e
r
a
t
i
n
g
c
i
r
c
u
i
t
i
n
p
u
t
(8) Port P22
I2C-BUS interface enable bit
SDA/SCL pin selection bit
SDA output S
D
A
i
n
p
u
t
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Port latch
D
a
t
a
b
u
s
15
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 11 Port block diagram (2)
(
9
)
P
o
r
t
P
2
3
P
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
D
a
t
a
b
u
s
Port latch
Direction
register
Data bus
Port latch
Direction
register
D
a
t
a
b
u
s
Port latch
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Data bus
P
o
r
t
l
a
t
c
h
Direction
register
D
a
t
a
b
u
s
(12) Port P2
6
Serial I/O1 synchronous
clock selection bit
Serial I/O1 enable bit
S
e
r
i
a
l
I
/
O
1
e
n
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
1
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
Serial I/O1 clock output E
x
t
e
r
n
a
l
c
l
o
c
k
i
n
p
u
t
(14) Ports P3
0
-P3
4
A
-
D
c
o
n
v
e
r
t
e
r
i
n
p
u
t
A
n
a
l
o
g
i
n
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
(16) Ports P4
1
,P4
2
Interrupt input
(
1
1
)
P
o
r
t
P
2
5
(13) Port P2
7
Serial I/O1 enable bit
S
e
r
i
a
l
I
/
O
1
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
SR
D
Y
1
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
o
u
t
p
u
tC
N
T
R0
i
n
t
e
r
r
u
p
t
i
n
p
u
t
S
e
r
i
a
l
r
e
a
d
y
o
u
t
p
u
t
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
(
1
5
)
P
o
r
t
P
4
0
Timer out p u
t
C
N
T
R1
i
n
t
e
r
r
u
p
t
i
n
p
u
t
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
(10) Port P2
4
S
C
L
i
n
p
u
t
I
2
C-BUS interface enable bit
SDA/SCL pin selection bit
Serial I/O1 enable bit
R
e
c
e
i
v
e
e
n
a
b
l
e
b
i
t
S
D
A
i
n
p
u
t
SDA output
Serial I/O1 output SCL input
S
C
L
o
u
t
p
u
t
P-channel output disable bit
S
e
r
i
a
l
I
/
O
1
e
n
a
b
l
e
b
i
t
T
r
a
n
s
m
i
t
e
n
a
b
l
e
b
i
t
Direction
register
P
o
r
t
l
a
t
c
h
D
a
t
a
b
u
s
P
o
r
t
l
a
t
c
h
P
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
D
a
t
a
b
u
s
D
a
t
a
b
u
s
S
C
L
o
u
t
p
u
tS
e
r
i
a
l
I
/
O
1
i
n
p
u
t
I
2
C
-
B
U
S
i
n
t
e
r
f
a
c
e
e
n
a
b
l
e
b
i
t
S
D
A
/
S
C
L
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
I
2
C
-
B
U
S
i
n
t
e
r
f
a
c
e
e
n
a
b
l
e
b
i
t
S
D
A
/
S
C
L
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
16
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 12 Port block diagram (3)
(
1
8
)
P
o
r
t
P
4
4
P
W
M
o
u
t
p
u
t
Data bus
PWM output enable bit
P
o
r
t
l
a
t
c
h
Direction
register
P
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
D
a
t
a
b
u
s
(17) Port P43
I
n
t
e
r
r
u
p
t
i
n
p
u
t
S
e
r
i
a
l
I
/
O
2
I
/
O
c
o
m
p
a
r
i
s
o
n
s
i
g
n
a
l
c
o
n
t
r
o
l
b
i
t
S
e
r
i
a
l
I
/
O
2
I
/
O
c
o
m
p
a
r
i
s
o
n
s
i
g
n
a
l
o
u
t
p
u
tI
n
t
e
r
r
u
p
t
i
n
p
u
t
17
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
INTERRUPTS
Interrupts occur by 17 sources among 17 sources: seven external,
nine internal, and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in-
struction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
■Notes
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer XY mode register (address 2316)
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt edge selection register (address 3A16)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
➀Set the corresponding interrupt enable bit to “0” (disabled).
➁Set the interrupt edge select bit or the interrupt source select bit.
➂Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃Set the corresponding interrupt enable bit to “1” (enabled).
18
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Interrupt Request
Generating Conditions Remarks
Interrupt Source Low
FFFC16
High
FFFD16
Priority
1
Table 8 Interrupt vector addresses and priority
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
V ector Addresses (Note 1)
Reset (Note 2)
INT0
SCL, SDA
INT1
INT2
INT3
Serial I/O2
I2C
Timer X
Timer Y
Timer 1
Timer 2
Serial I/O1
reception
Serial I/O1
transmission
CNTR0
CNTR1
A-D converter
BRK instruction
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
At detection of either rising or
falling edge of INT2 input
At detection of either rising or
falling edge of INT3 input
At completion of serial I/O2 data
reception/transmission
At completion of data transfer
At completion of serial I/O1 data
reception
At completion of serial I/O1
transfer shift or when transmis-
sion buffer is empty
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
STP release timer underflow
At detection of either rising or
falling edge of SCL or SDA input
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At completion of A-D conversion
At BRK instruction execution
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Switch by Serial I/O2/INT3
interrupt source bit
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16 FFDC16FFDD16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Non-maskable software interrupt
19
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 13 Interrupt control
Fig. 14 Structure of interrupt-related registers
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
f
l
a
g
(
I
)
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
B
R
K
i
n
s
t
r
u
c
t
i
o
n
R
e
s
e
t
b
7
b
0
b7 b0 b7 b0
b
7
b
0 b
7
b
0
I
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
INT
0
active edge selection bit
INT1 active edge selection bit
INT2 active edge selection bit
INT3 active edge selection bit
Serial I/O2 / INT3 interrupt source bit
0 : INT3 interrupt selected
1 : Serial I/O2 interrupt selected
Not used (returns “0” when read)
(
I
N
T
E
D
G
E
:
a
d
d
r
e
s
s
0
0
3
A
1
6
)
0 : Falling edge active
1 : Rising edge active
Interrupt request register 1
I
N
T
0
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
S
C
L
/
S
D
A
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
N
T1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
N
T2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
N
T3 /
S
e
r
i
a
l
I
/
O
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I2C
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
X
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
Y
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
0 : No interrupt request issued
1 : Interrupt request issued
(
I
R
E
Q
1
:
a
d
d
r
e
s
s
0
0
3
C
1
6
)I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
2
T
i
m
e
r
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
S
e
r
i
a
l
I
/
O
1
r
e
c
e
p
t
i
o
n
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
S
e
r
i
a
l
I
/
O
1
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
C
N
T
R0
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
C
N
T
R1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
A
D
c
o
n
v
e
r
t
e
r
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
(IREQ2 : address 003D
16
)
0 : No interrupt request issued
1 : Interrupt request issued
Interrupt control register 1
I
N
T0
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
S
C
L
/
S
D
A
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
I
N
T1
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
I
N
T2
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
I
N
T3 /
S
e
r
i
a
l
I
/
O
2 i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
I2C
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
X
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
Y
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
(
I
C
O
N
1
:
a
d
d
r
e
s
s
0
0
3
E
1
6
)Interrupt control register 2
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Serial I/O1 reception interrupt enable bit
Serial I/O1 transmit interrupt enable bit
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
0 : Interrupts disabled
1 : Interrupts enabled
(ICON2 : address 003F
16
)
0
:
I
n
t
e
r
r
u
p
t
s
d
i
s
a
b
l
e
d
1
:
I
n
t
e
r
r
u
p
t
s
e
n
a
b
l
e
d
20
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
TIMERS
The 3851 group (built-in 24 KB or more ROM) has four timers:
timer X, timer Y, timer 1, and timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down. When the timer reaches “0016”, an un-
derflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating
modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts the count source selected by Timer count source
selection bit.
(2) Pulse Output Mode
The timer counts the count source selected by Timer count source
selection bit. Whenever the contents of the timer reach “0016”, the
signal output from the CNTR0 (or CNTR1) pin is inverted. If the
CNTR0 (or CNTR1) active edge selection bit is “0”, output begins
at “ H”.
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P27 ( or port P40) direction register to out-
put mode.
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR0 or
CNTR1 pin.
When the CNTR0 (or CNTR1) active edge selection bit is “0”, the
rising edge of the CNTR0 (or CNTR1) pin is counted.
When the CNTR0 (or CNTR1) active edge selection bit is “1”, the
falling edge of the CNTR0 (or CNTR1) pin is counted.
(4) Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer
counts the selected signals by the count source selection bit while
the CNTR0 (or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) ac-
tive edge selection bit is “1”, the timer counts it while the CNTR0
(or CNTR1) pin is at “L”.
The count can be stopped by setting “1” to the timer X (or timer Y)
count stop bit in any mode. The corresponding interrupt request
bit is set each time a timer underflows.
Fig. 15 Structure of timer XY mode register
■Note
When switching the count source by the timer 12, X and Y count
source bits, the value of timer count is altered in unconsiderable
amount owing to generating of a thin pulses in the count input
signals.
Therefore, select the timer count source before set the value to
the prescaler and the timer.
When timer X/timer Y underflow while executing the instruction
which sets “1” to the timer X/timer Y count stop bits, the timer X/
timer Y interrupt request bits are set to “1”. Timer X/Timer Y in-
terrupts are received if these interrupts are enabled at this time.
The timing which interrupt is accepted has a case after the in-
struction which sets “1” to the count stop bit, and a case after
the next instruction according to the timing of the timer under-
flow. When this interrupt is unnecessary, set “0” (disabled) to the
interrupt enable bit and then set “1” to the count stop bit.
Fig. 16 Structure of timer count source selection register
Timer 1 and Timer 2
The count source of prescaler 12 is the oscillation frequency
which is selected by timer 12 count source selection bit. The out-
put of prescaler 12 is counted by timer 1 and timer 2, and a timer
underflow sets the interrupt request bit.
T
i
m
e
r
X
c
o
u
n
t
s
t
o
p
b
i
t
0
:
C
o
u
n
t
s
t
a
r
t
1
:
C
o
u
n
t
s
t
o
p
T
i
m
e
r
X
Y
m
o
d
e
r
e
g
i
s
t
e
r
(
T
M
:
a
d
d
r
e
s
s
0
0
2
3
1
6
)
T
i
m
e
r
Y
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
0
0
:
T
i
m
e
r
m
o
d
e
0
1
:
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
1
0
:
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
1
1
:
P
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
CNTR
1
active edge selection bit
0: Inte rr upt at falling edge
Count at rising edge in event
counter mode
1: Inter r upt at rising edge
Count at falling edge in event
counter mode
b
7
C
N
T
R
0
a
c
t
i
v
e
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
I
n
t
e
r
r
u
p
t
a
t
f
a
l
l
i
n
g
e
d
g
e
C
o
u
n
t
a
t
r
i
s
i
n
g
e
d
g
e
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
1
:
I
n
t
e
r
r
u
p
t
a
t
r
i
s
i
n
g
e
d
g
e
C
o
u
n
t
a
t
f
a
l
l
i
n
g
e
d
g
e
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
b
0
T
i
m
e
r
X
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
0
0
:
T
i
m
e
r
m
o
d
e
0
1
:
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
1
0
:
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
1
1
:
P
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
b
1
b
0
b5b4
T
i
m
e
r
Y
c
o
u
n
t
s
t
o
p
b
i
t
0
:
C
o
u
n
t
s
t
a
r
t
1
:
C
o
u
n
t
s
t
o
p
T
i
m
e
r
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
T
C
S
S
:
a
d
d
r
e
s
s
0
0
2
8
1
6
)
b
7b
0
T
i
m
e
r
X
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
f
(
X
I
N
)
/
1
6
(
f
(
X
C
I
N
)
/
1
6
a
t
l
o
w
-
s
p
e
e
d
m
o
d
e
)
1
:
f
(
X
I
N
)
/
2
(
f
(
X
C
I
N
)
/
2
a
t
l
o
w
-
s
p
e
e
d
m
o
d
e
)
T
i
m
e
r
Y
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
f
(
X
I
N
)
/
1
6
(
f
(
X
C
I
N
)
/
1
6
a
t
l
o
w
-
s
p
e
e
d
m
o
d
e
)
1
:
f
(
X
I
N
)
/
2
(
f
(
X
C
I
N
)
/
2
a
t
l
o
w
-
s
p
e
e
d
m
o
d
e
)
T
i
m
e
r
1
2
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
f
(
X
I
N
)
/
1
6
(
f
(
X
C
I
N
)
/
1
6
a
t
l
o
w
-
s
p
e
e
d
m
o
d
e
)
1
:
f
(
X
C
I
N
)
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
21
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 17 Block diagram of timer X, timer Y, timer 1, and timer 2
Q
Q
“1”
“
0
”
P
2
7
/
C
N
T
R
0
/
S
R
D
Y
1
Q
Q
P4
0
/CNTR
1
“
0
”
“
1
”
R
R
“1”
“0”
“0”
“
1
”
T
T
P
r
e
s
c
a
l
e
r
X
l
a
t
c
h
(
8
)
Prescaler X (8)
T
i
m
e
r
X
l
a
t
c
h
(
8
)
Timer X (8) T
o
t
i
m
e
r
X
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
Toggle flip-flop
T
i
m
e
r
X
c
o
u
n
t
s
t
o
p
b
i
t
P
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
eT
o
C
N
T
R
0
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
Pulse out put mode
P
o
r
t
P
2
7
l
a
t
c
h
Port P2
7
directi on r egister
CNTR
0
active
edge sel ec tion
bit
Timer X lat c h wr ite pulse
Pulse out put mode
T
i
m
e
r
m
o
d
e
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
Prescaler Y latch (8)
Prescaler Y (8)
T
i
m
e
r
Y
l
a
t
c
h
(
8
)
Timer Y (8) T
o
t
i
m
e
r
Y
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
o
g
g
l
e
f
l
i
p
-
f
l
o
p
T
i
m
e
r
Y
c
o
u
n
t
s
t
o
p
b
i
t
To CNTR
1
interrupt
request bit
Pulse out put mode
P
o
r
t
P
4
0
l
a
t
c
h
Port P4
0
directi on r egister
C
N
T
R
1
a
c
t
i
v
e
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
Timer Y lat c h wr ite pulse
Pulse out put mode
Timer mode
Pulse out put mode
Data bus
D
a
t
a
b
u
s
Prescaler 12 latch (8)
P
r
e
s
c
a
l
e
r
1
2
(
8
)
Timer 1 latch (8)
Timer 1 (8)
Data bus
Timer 2 latch (8)
Timer 2 (8) To timer 2 interrupt
request bit
T
o
t
i
m
e
r
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
C
N
T
R
0
a
c
t
i
v
e
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
C
N
T
R
1
a
c
t
i
v
e
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
P
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
-
m
e
n
t
m
o
d
e
Event
counter
mode
f(X
CIN
)
T
i
m
e
r
1
2
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
f
(
X
I
N
)
/
1
6
f(X
IN
)/2
Timer Y count source selection bit
f(X
IN
)/16
f
(
X
I
N
)
/
2
T
i
m
e
r
X
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
f
(
X
I
N
)
/
1
6
(
f
(
X
C
I
N
)
/
1
6
a
t
l
o
w
-
s
p
e
e
d
m
o
d
e
)
(
f
(
X
C
I
N
)
/
2
a
t
l
o
w
-
s
p
e
e
d
m
o
d
e
)
(f(X
CIN
)/16 at low-s peed mode)
(f(X
CIN
)/2 at low-s peed mode)
(
f
(
X
C
I
N
)
/
1
6
a
t
l
o
w
-
s
p
e
e
d
m
o
d
e
)
22
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
SERIAL I/O
●SERIAL I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O1 mode selection bit of the serial I/O1 control register (bit
6 of address 001A16) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Fig. 18 Block diagram of clock synchronous serial I/O1
Fig. 19 Operation of clock synchronous serial I/O1 function
1/4
1/4
F/F
P2
6
/S
CLK
Serial I/O1 status register
Serial I/O1 control register
P2
7
/S
RDY1
P2
4
/R
X
D
P2
5
/T
X
D
X
IN
Receive buffer register
Address 0018
16
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C
16
BRG count source selection bit
Clock control circuit
Falling-edge detector
Transmit buffer register
Data bus Address 0018
16
Shift clock Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 0019
16
Data bus
Address 001A
16
Transmit shift register
D
7
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
RBF = 1
TSC = 1
TBE = 0 TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
Write pulse to receive/transmit
buffer register (address 0018
16
)
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has
ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Receive enable signal
S
RDY1
23
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit (b6) of the serial I/O1
control register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Fig. 20 Block diagram of UART serial I/O1
X
I
N
1
/
4
O
E
P
EFE
1/16
1/16
D
a
t
a
b
u
s
R
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
A
d
d
r
e
s
s
0
0
1
8
1
6
R
e
c
e
i
v
e
s
h
i
f
t
r
e
g
i
s
t
e
r
Receive buffer full flag (RBF)
Receive interrupt request (RI)
B
a
u
d
r
a
t
e
g
e
n
e
r
a
t
o
r
F
r
e
q
u
e
n
c
y
d
i
v
i
s
i
o
n
r
a
t
i
o
1
/
(
n
+
1
)
Address 001C
16
ST/SP/PA gener at or
T
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
D
a
t
a
b
u
s
Transmit shift register
Address
0018
16
Transmit shift complet ion flag (T SC)
Transmit buffer empty flag (TBE)
T
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
(
T
I
)
Address
0019
16
S
T
d
e
t
e
c
t
o
r
SP detector U
A
R
T
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
A
d
d
r
e
s
s
0
0
1
B
1
6
Character length selection bit
A
d
d
r
e
s
s
0
0
1
A
1
6
BRG count source selection bit
Transmit interrupt source selecti on bit
Serial I/O1 synchronous clock selection bit
C
l
o
c
k
c
o
n
t
r
o
l
c
i
r
c
u
i
t
C
h
a
r
a
c
t
e
r
l
e
n
g
t
h
s
e
l
e
c
t
i
o
n
b
i
t
7
b
i
t
s
8
b
i
t
s
S
e
r
i
a
l
I
/
O
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
P2
6
/S
CL
K
Serial I/O1 status register
P
2
4
/
R
X
D
P
2
5
/
T
X
D
24
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 21 Operation of UART serial I/O1 function
[Transmit Buffer Register/Receive Buffer
Register (TB/RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[Serial I/O1 Status Register (SIOSTS)] 001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the serial I/O1 control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O1 Control Register (SIOCON)] 001A16
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer and one bit (bit 4) which is al-
ways valid and sets the output structure of the P25/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
TSC=0
TBE=1
RBF=0
TBE=0 TBE=0
RBF=1 RBF=1
STD0D1SP D0D1
ST SP
TBE=1 TSC=1
STD0D1SP D0D1
ST SP
Transmit or receive clock
Transmit buffer write
signal
Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Notes
Serial output TXD
Serial input RXD
Receive buffer read
signal
25
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
■Notes on serial I/O1
1. When using the serial I/O1, clear the I2C-BUS interface enable
bit to “0” or the SDA/SCL interrupt pin selection bit to “0”.
2. When setting the transmit enable bit of serial I/O1 to “1”, the
serial I/O1 transmit interrupt request bit is automatically set to
“1”. When not requiring the interrupt occurrence synchronized
with the transmission enalbed, take the following sequence.
➀Set the serial I/O1 transmit interrupt enable bit to “0” (dis-
abled).
➁Set the transmit enable bit to “1”.
➂Set the serial I/O1 transmit interrupt request bit to “0” after 1
or more instructions have been executed.
➃Set the serial I/O1 transmit interrupt enable bit to “1” (en-
abled).
Fig. 22 Structure of serial I/O1 control registers
b
7
T
r
a
n
s
m
i
t
b
u
f
f
e
r
e
m
p
t
y
f
l
a
g
(
T
B
E
)
0
:
B
u
f
f
e
r
f
u
l
l
1
:
B
u
f
f
e
r
e
m
p
t
y
R
e
c
e
i
v
e
b
u
f
f
e
r
f
u
l
l
f
l
a
g
(
R
B
F
)
0
:
B
u
f
f
e
r
e
m
p
t
y
1
:
B
u
f
f
e
r
f
u
l
l
T
r
a
n
s
m
i
t
s
h
i
f
t
c
o
m
p
l
e
t
i
o
n
f
l
a
g
(
T
S
C
)
0
:
T
r
a
n
s
m
i
t
s
h
i
f
t
i
n
p
r
o
g
r
e
s
s
1
:
T
r
a
n
s
m
i
t
s
h
i
f
t
c
o
m
p
l
e
t
e
d
O
v
e
r
r
u
n
e
r
r
o
r
f
l
a
g
(
O
E
)
0
:
N
o
e
r
r
o
r
1
:
O
v
e
r
r
u
n
e
r
r
o
r
P
a
r
i
t
y
e
r
r
o
r
f
l
a
g
(
P
E
)
0
:
N
o
e
r
r
o
r
1
:
P
a
r
i
t
y
e
r
r
o
r
F
r
a
m
i
n
g
e
r
r
o
r
f
l
a
g
(
F
E
)
0
:
N
o
e
r
r
o
r
1
:
F
r
a
m
i
n
g
e
r
r
o
r
S
u
m
m
i
n
g
e
r
r
o
r
f
l
a
g
(
S
E
)
0
:
(
O
E
)
U
(
P
E
)
U
(
F
E
)
=
0
1
:
(
O
E
)
U
(
P
E
)
U
(
F
E
)
=
1
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
1
”
w
h
e
n
r
e
a
d
)
S
e
r
i
a
l
I
/
O
1
s
t
a
t
u
s
r
e
g
i
s
t
e
r
Serial I/O1 control register
b
7b
0b
0
BRG count source selection bit (CSS)
0: f(XIN)
1: f(XIN)/4
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O1 is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O1 is selected, external clock input divided by 16
when UART is selected.
SRDY1 output enable bit (SRDY)
0: P27 pin operates as ordinary I/O pin
1: P27 pin operates as SRDY1 output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (R E)
0: Receive disabled
1: Receive enabled
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchro nous seri al I/O
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P24 to P27 operate as ordinary I/O pins)
1: Serial I/O1 enabled
(pins P24 to P27 operate as serial I/O1 pins)
b
7U
A
R
T
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
C
h
a
r
a
c
t
e
r
l
e
n
g
t
h
s
e
l
e
c
t
i
o
n
b
i
t
(
C
H
A
S
)
0
:
8
b
i
t
s
1
:
7
b
i
t
s
P
a
r
i
t
y
e
n
a
b
l
e
b
i
t
(
P
A
R
E
)
0
:
P
a
r
i
t
y
c
h
e
c
k
i
n
g
d
i
s
a
b
l
e
d
1
:
P
a
r
i
t
y
c
h
e
c
k
i
n
g
e
n
a
b
l
e
d
P
a
r
i
t
y
s
e
l
e
c
t
i
o
n
b
i
t
(
P
A
R
S
)
0
:
E
v
e
n
p
a
r
i
t
y
1
:
O
d
d
p
a
r
i
t
y
S
t
o
p
b
i
t
l
e
n
g
t
h
s
e
l
e
c
t
i
o
n
b
i
t
(
S
T
P
S
)
0
:
1
s
t
o
p
b
i
t
1
:
2
s
t
o
p
b
i
t
s
P
25/
TXD
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
(
P
O
F
F
)
0
:
C
M
O
S
o
u
t
p
u
t
(
i
n
o
u
t
p
u
t
m
o
d
e
)
1
:
N
-
c
h
a
n
n
e
l
o
p
e
n
d
r
a
i
n
o
u
t
p
u
t
(
i
n
o
u
t
p
u
t
m
o
d
e
)
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
1
”
w
h
e
n
r
e
a
d
)
b
0
(SIOSTS : address 001916) (SIOCON : address 001A16)
(
U
A
R
T
C
O
N
:
a
d
d
r
e
s
s
0
0
1
B1
6)
26
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
●SERIAL I/O2
The serial I/O2 can be operated only as the clock synchronous type.
As a synchronous clock for serial transfer, either internal clock or
external clock can be selected by the serial I/O2 synchronous clock
selection bit (b6) of serial I/O2 control register 1.
The internal clock incorporates a dedicated divider and permits se-
lecting 6 types of clock by the internal synchronous clock selection
bits (b2, b1, b0) of serial I/O2 control register 1.
Regarding SOUT2 and SCLK2 being output pins, either CMOS output
format or N-channel open-drain output format can be selected by the
P01/SOUT2, P02/SCLK2 P-channel output disable bit (b7) of
serial I/O2 control register 1.
When the internal clock has been selected, a transfer starts by a
write signal to the serial I/O2 register (address 001716). After comple-
tion of data transfer, the level of the SOUT2 pin goes to high imped-
ance automatically but bit 7 of the serial I/O2 control register 2 is not
set to “1” automatically.
When the external clock has been selected, the contents of the serial
I/O2 register is continuously sifted while transfer clocks are input.
Accordingly, control the clock externally. Note that the SOUT2 pin does
not go to high impedance after completion of data transfer.
To cause the SOUT2 pin to go to high impedance in the case where
the external clock is selected, set bit 7 of the serial I/O2 control reg-
ister 2 to “1” when SCLK2 is “H” after completion of data transfer. After
the next data transfer is started (the transfer clock falls), bit 7 of the
serial I/O2 control register 2 is set to “0” and the SOUT2 pin is put into
the active state.
Regardless of the internal clock to external clock, the interrupt re-
quest bit is set after the number of bits (1 to 8 bits) selected by the
optional transfer bit is transferred. In case of a fractional number of
bits less than 8 bits as the last data, the received data to be stored in
the serial I/O2 register becomes a fractional number of bits close to
MSB if the transfer direction selection bit of serial I/O2 control regis-
ter 1 is LSB first, or a fractional number of bits close to LSB if the
transfer direction selection bit is MSB first. For the remaining bits, the
previously received data is shifted.
At transmit operation using the clock synchronous serial I/O, the SCMP2
signal can be output by comparing the state of the transmit pin SOUT2
with the state of the receive pin SIN2 in synchronization with a rise of
the transfer clock. If the output level of the SOUT2 pin is equal to the
input level to the SIN2 pin, “L” is output from the SCMP2 pin. If not, “H”
is output. At this time, an INT2 interrupt request can also be gener-
ated. Select a valid edge by bit 2 of the interrupt edge selection reg-
ister (address 003A16).
[Serial I/O2 Control Registers 1, 2 (SIO2CON1 /
SIO2CON2)] 001516, 001616
The serial I/O2 control registers 1 and 2 are containing various se-
lection bits for serial I/O2 control as shown in Figure 23.
Fig. 23 Structure of Serial I/O2 control registers 1, 2
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
S
I
O
2
C
O
N
1
:
a
d
d
r
e
s
s
0
0
1
5
1
6
)
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
S
I
O
2
C
O
N
2
:
a
d
d
r
e
s
s
0
0
1
6
1
6
)
b7 b0
Optional transfer bi ts
b2 b1 b0
0 0 0: 1 bit
0 0 1: 2 bit
0 1 0: 3 bit
0 1 1: 4 bit
1 0 0: 5 bit
1 0 1: 6 bit
1 1 0: 7 bit
1 1 1: 8 bit
Not used ( returns "0" when read)
Serial I/O2 I/O compariso n signal control bit
0: P4
3
I/O
1: S
CMP2
output
S
OUT2
pin control bit (P0
1
)
0: Output act i ve
1: Output high-impedance
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
s
b
2
b
1
b
0
0
0
0
:
f
(
X
I
N
)
/
8
(
f
(
X
C
I
N
)
/
8
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
0
0
1
:
f
(
X
I
N
)
/
1
6
(
f
(
X
C
I
N
)
/
1
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
0
1
0
:
f
(
X
I
N
)
/
3
2
(
f
(
X
C
I
N
)
/
3
2
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
0
1
1
:
f
(
X
I
N
)
/
6
4
(
f
(
X
C
I
N
)
/
6
4
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
1
1
0
:
f
(
X
I
N
)
/
1
2
8
f
(
X
C
I
N
)
/
1
2
8
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
1
1
1
:
f
(
X
I
N
)
/
2
5
6
(
f
(
X
C
I
N
)
/
2
5
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
S
e
r
i
a
l
I
/
O
2
p
o
r
t
s
e
l
e
c
t
i
o
n
b
i
t
0
:
I
/
O
p
o
r
t
1
:
S
O
U
T
2
,
S
C
L
K
2
o
u
t
p
u
t
p
i
n
S
R
D
Y
2
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
0
:
P
0
3
p
i
n
i
s
n
o
r
m
al
I
/
O
p
i
n
1
:
P
0
3
p
i
n
i
s
S
R
D
Y
2
o
u
t
p
u
t
p
i
n
T
r
a
n
s
f
e
r
d
i
r
e
c
t
i
o
n
s
e
l
e
c
t
i
o
n
b
i
t
0
:
L
S
B
f
i
r
s
t
1
:
M
S
B
f
i
r
s
t
S
e
r
i
a
l
I
/
O
2
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
0
:
E
x
t
e
r
n
a
l
c
l
o
c
k
1
:
I
n
t
e
r
n
a
l
c
l
o
c
k
P
0
1
/
S
O
U
T
2
,
P
0
2
/
S
C
L
K
2
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
0
:
C
M
O
S
o
u
t
p
u
t
(
i
n
o
u
t
p
u
t
m
o
d
e
)
1
:
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
(
i
n
o
u
t
p
u
t
m
o
d
e
)
b
7b
0
27
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 24 Block diagram of Serial I/O2
Fig. 25 Timing chart of Serial I/O2
D7D0D1D2D3D4D5D6
T
r
a
n
s
f
e
r
c
l
o
c
k
(
N
o
t
e
1
)
S
e
r
i
a
l
I
/
O
2
o
u
t
p
u
t
S
O
U
T
2
S
e
r
i
a
l
I
/
O
2
i
n
p
u
t
S
I
N
2
R
e
c
e
i
v
e
e
n
a
b
l
e
s
i
g
n
a
l
S
R
D
Y
2
W
r
i
t
e
-
i
n
s
i
g
n
a
l
t
o
s
e
r
i
a
l
I
/
O
2
r
e
g
i
s
t
e
r
(
N
o
t
e
2
)
S
e
r
i
a
l
I
/
O
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
s
e
t
.
1
:
W
h
e
n
t
h
e
i
n
t
e
r
n
a
l
c
l
o
c
k
i
s
s
e
l
e
c
t
e
d
a
s
a
t
r
a
n
s
f
e
r
c
l
o
c
k
,
t
h
e
f
(
X
I
N
)
c
l
o
c
k
d
i
v
i
s
i
o
n
(
f
(
X
C
I
N
)
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
c
a
n
b
e
s
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l
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c
t
e
d
b
y
s
e
t
t
i
n
g
b
i
t
s
0
t
o
2
o
f
s
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
.
2
:
W
h
e
n
t
h
e
i
n
t
e
r
n
a
l
c
l
o
c
k
i
s
s
e
l
e
c
t
e
d
a
s
a
t
r
a
n
s
f
e
r
c
l
o
c
k
,
t
h
e
S
O
U
T
2
p
i
n
h
a
s
h
i
g
h
i
m
p
e
d
a
n
c
e
a
f
t
e
r
t
r
a
n
s
f
e
r
c
o
m
p
l
e
t
i
o
n
.
N
o
t
e
s
X
IN
“1”
“0
”
“0
”
“1”
“0
”
“1”
S
R
D
Y
2
S
C
L
K
2
“0”
“1
”
1/8
1/16
1
/
3
2
1
/
6
4
1
/
1
2
8
1
/
2
5
6
“1
”
“0
”
X
CIN
“1
0
”
“0
0
”
“
0
1
”
Data bus
Serial I/O2
interrupt request
S
e
r
i
a
l
I
/
O
2
p
o
r
t
s
e
l
e
c
t
i
o
n
b
i
t
S
e
r
i
a
l
I
/
O
c
o
u
n
t
e
r
2
(
3
)
S
e
r
i
a
l
I
/
O
2
r
e
g
i
s
t
e
r
(
8
)
S
y
n
c
h
r
o
n
o
u
s
c
i
r
c
u
i
t
S
e
r
i
a
l
I
/
O
2
p
o
r
t
s
e
l
e
c
t
i
o
n
b
i
t
Serial I/O2 synch r onous
clock selection bit
S
R
D
Y
2
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
E
x
t
e
r
n
a
l
c
l
o
c
k
Internal synchronous
clock selection bits
D
i
v
i
d
e
r
Optional transfer bits (3)
P0
2
/S
CLK2
P
0
1
/
S
O
U
T
2
P0
0
/S
IN2
P
0
2
l
a
t
c
h
P
0
1
l
a
t
c
h
P
0
3
l
a
t
c
h
P
0
3
/
S
R
D
Y
2
P4
3
/S
CMP2
/INT
2
Serial I/O2 I/O comparison
signal control bit
P4
3
latch
QD
Main clock division ratio
selection bits (Note)
Note: Either high - s peed, middle - s peed or low-s peed mode is selected by bi ts 6 and 7 of CPU mode register.
28
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 26 SCMP2 output operation
SC
L
K
2
SI
N
2
SO
U
T
2
SC
M
P
2
J
u
d
g
e
m
e
n
t
o
f
I
/
O
d
a
t
a
c
o
m
p
a
r
i
s
o
n
29
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Function
In conformity with Philips I2C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I2C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at φ= 4 MHz)
Table 9 Multi-master I2C-BUS interface functions
Item
Format
Communication mode
System clock φ = f(XIN)/2 (high-speed mode)
φ = f(XIN)/8 (middle-speed mode)
MULTI-MASTER I2C-BUS INTERFACE
The multi-master I2C-BUS interface is a serial communications cir-
cuit, conforming to the Philips I2C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchro-
nous functions, is useful for the multi-master serial
communications.
Figure 27 shows a block diagram of the multi-master I2C-BUS in-
terface and Table 9 lists the multi-master I2C-BUS interface
functions.
This multi-master I2C-BUS interface consists of the I2C address
register, the I 2C data shift register, the I2C clock control register,
the I2C control register, the I2C status register, the I2C start/stop
condition control register and other control circuits.
When using the multi-master I2C-BUS interface, set 1 MHz or
more to φ.
Note: Mitsubishi Electric Corporation assumes no responsibility for in-
fringement of any third-party’s rights or originating in the use of the
connection control function between the I2C-BUS interface and the
ports SCL1, SCL2, SDA1 and SDA2 with the bit 6 of I2C control regis-
ter (002E16).
Fig. 27 Block diagram of multi-master I2C-BUS interface
✽ : Purchase of MITSUBISHI ELECTRIC CORPORATIONS I2C components conveys a license under the Philips I2C Patent Rights to use these components
an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
SCL clock frequency
I
2
C address regi sterb
7b0
S
A
D
6S
A
D
5SAD
4
SAD
3
SAD2 SAD1 S
A
D
0R
W
B
Noise
elimination
circuit
A
d
d
r
e
s
s
c
o
m
p
a
r
a
t
o
r
b7
I
2
C data shift register
b0
D
a
t
a
c
o
n
t
r
o
l
c
i
r
c
u
i
t
System clock (φ)
Interrupt
generating
circuit
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
s
i
g
n
a
l
(
I
I
C
I
R
Q
)
b7
MST
TRX
BB
PIN
A
L
A
A
S
A
D
0
LRB
b
0
S1
b
7b
0
TIS
S
10BIT
SAD A
L
S
B
C
2B
C
1B
C
0
S1D
Bi
t counte
r
BB
circuit
Clock
control
circuit
N
o
i
s
e
e
l
i
m
i
n
a
t
i
o
n
c
i
r
c
u
i
tb
7b0
AC
K
A
C
K
B
I
TFAST
MODE C
C
R
4C
C
R
3
C
C
R
2
CCR1 CCR
0
I
nterna
l
d
ata
b
us
Cl
oc
k
di
v
i
s
i
on
S
0
S2
S0D
A
L
c
i
r
c
u
i
t
E
S
0
SIS
I2C
s
t
a
r
t
/
s
t
o
p
c
o
n
d
i
t
i
o
n
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
SIP
SSC
4
S
S
C
3
S
S
C
2
SSC1 S
S
C
0
I
2
C
c
l
o
c
k
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
I2C status register
S
2
D
CLK
STP
I
2
C
c
l
o
c
k
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
S1D I C control register
2
Serial data
(S
DA
)
Serial
clock
(S
CL
)
30
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
[I2C Data Shift Register (S0)] 002B16
The I2C data shift register (S0 : address 002B16) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to
the outside from bit 7 in synchronization with the SCL clock, and
each time one-bit data is output, the data of this register are
shifted by one bit to the left. When data is received, it is input to
this register from bit 0 in synchronization with the SCL clock, and
each time one-bit data is input, the data of this register are shifted
by one bit to the left. The minimum 2 machine cycles are required
from the rising of the SCL clock until input to this register.
The I2C data shift register is in a write enable status only when the
I2C-BUS interface enable bit (ES0 bit : bit 3 of address 002E16) of
the I2C control register is “1”. The bit counter is reset by a write in-
struction to the I2C data shift register. When both the ES0 bit and
the MST bit of the I2C status register (address 002D16) are “1,” the
SCL is output by a write instruction to the I2C data shift register.
Reading data from the I2C data shift register is always enabled re-
gardless of the ES0 bit value.
[I2C Address Register (S0D)] 002C16
The I2C address register (address 002C16) consists of a 7-bit
slave address and a read/write bit. In the addressing mode, the
slave address written in this register is compared with the address
data to be received immediately after the START condition is de-
tected.
•Bit 0: Read/write bit (RWB)
This is not used in the 7-bit addressing mode. In the 10-bit ad-
dressing mode, the first address data to be received is compared
with the contents (SAD6 to SAD0 + RWB) of the I2C address reg-
ister.
The RWB bit is cleared to “0” automatically when the stop condi-
tion is detected.
•Bits 1 to 7: Slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address-
ing mode and the 10-bit addressing mode, the address data
transmitted from the master is compared with the contents of
these bits.
Fig. 28 Structure of I2C address register
S
A
D
6 SAD5 S
A
D
4S
A
D
3S
A
D
2 SAD1 SAD
0
RWB
S
l
a
v
e
a
d
d
r
e
s
s
I
2
C
a
d
d
r
e
s
s
r
e
g
i
s
t
e
r
(
S
0
D
:
a
d
d
r
e
s
s
0
0
2
C
1
6
)
R
e
a
d
/
w
r
i
t
e
b
i
t
b7 b
0
31
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Table 10 Set values of I2C clock control register and SCL
frequency
Fig. 29 Structure of I2C clock control register
SCL frequency (Note 1)
(at φ = 4 MHz, unit : kHz)
Setting value of
CCR4–CCR0 Standard clock
mode
Setting disabled
Setting disabled
Setting disabled
High-speed clock
mode
CCR4
0
0
0
0
0
0
0
1
1
1
CCR3
0
0
0
0
0
0
0
1
1
1
CCR2
0
0
0
0
1
1
1
1
1
1
CCR1
0
0
1
1
0
0
1
0
1
1
CCR0
0
1
0
1
0
1
0
1
0
1
…
…
…
…
…
Setting disabled
Setting disabled
Setting disabled
34.5
33.3
32.3
100
83.3
333
250
400 (Note 3)
166
– (Note 2)
– (Note 2)
[I2C Clock Control Register (S2)] 002F16
The I2C clock control register (address 002F16) is used to set ACK
control, SCL mode and SCL frequency.
•Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency. Refer to Table 10.
•Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the
standard clock mode is selected. When the bit is set to “1,” the
high-speed clock mode is selected.
When connecting the bus of the high-speed mode I2C bus stan-
dard (maximum 400 kbits/s), use 8 MHz or more oscillation
frequency f(XIN) and 2 division clock.
•Bit 6: ACK bit (ACK BIT)
This bit sets the SDA status when an ACK clock✽ is generated.
When this bit is set to “0,” the ACK return mode is selected and
SDA goes to “L” at the occurrence of an ACK clock. When the bit
is set to “1,” the ACK non-return mode is selected. The SDA is
held in the “H” status at the occurrence of an ACK clock.
However, when the slave address agree with the address data in
the reception of address data at ACK BIT = “0,” the SDA is auto-
matically made “L” (ACK is returned). If there is a disagreement
between the slave address and the address data, the SDA is auto-
matically made “H” (ACK is not returned).
✽ACK clock: Clock for acknowledgment
•Bit 7: ACK clock bit (ACK)
This bit specifies the mode of acknowledgment which is an ac-
knowledgment response of data transfer. When this bit is set to
“0,” the no ACK clock mode is selected. In this case, no ACK clock
occurs after data transmission. When the bit is set to “1,” the ACK
clock mode is selected and the master generates an ACK clock
each completion of each 1-byte data transfer. The device for
transmitting address data and control data releases the SDA at
the occurrence of an ACK clock (makes SDA “H”) and receives the
ACK bit generated by the data receiving device.
Note: Do not write data into the I2C clock control register during transfer. If
data is written during transfer, the I2C clock generator is reset, so
that data cannot be transferred normally.
A
C
K
A
C
K
B
I
TFAST
MODE C
C
R
4C
C
R
3
C
C
R
2CCR1C
C
R
0
I
2
C
c
l
o
c
k
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
2
:
a
d
d
r
e
s
s
0
0
2
F
1
6
)
b7 b0
S
C
L
f
r
e
q
u
e
n
c
y
c
o
n
t
r
o
l
b
i
t
s
R
e
f
e
r
t
o
T
a
b
l
e
1
0
.
S
C
L
m
o
d
e
s
p
e
c
i
f
i
c
a
t
i
o
n
b
i
t
0
:
S
t
a
n
d
a
r
d
c
l
o
c
k
m
o
d
e
1
:
H
i
g
h
-
s
p
e
e
d
c
l
o
c
k
d
A
C
K
b
i
t
0
:
A
C
K
i
s
r
e
t
u
r
n
e
d
.
1
:
A
C
K
i
s
n
o
t
t
d
A
C
K
c
l
o
c
k
b
i
t
0
:
N
o
A
C
K
c
l
o
c
k
1
:
A
C
K
c
l
o
c
k
500/CCR value
(Note 3) 1000/CCR value
(Note 3)
17.2
16.6
16.1
Notes 1: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 %
only when the high-speed clock mode is selected and CCR value
= 5 (400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuates
from –4 to +2 machine cycles in the standard clock mode, and
fluctuates from –2 to +2 machine cycles in the high-speed clock
mode. In the case of negative fluctuation, the frequency does not
increase because “L” duration is extended instead of “H” duration
reduction.
These are value when SCL clock synchronization by the synchro-
nous function is not performed. CCR value is the decimal
notation value of the SCL frequency control bits CCR4 to CCR0.
2: Each value of SCL frequency exceeds the limit at φ = 4 MHz or
more. When using these setting value, use φ of 4 MHz or less.
3: The data formula of SCL frequency is described below:
φ/(8 ✕ CCR value) Standard clock mode
φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5)
φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5)
Do not set 0 to 2 as CCR value regardless of φ frequency.
Set 100 kHz (max.) in the standard clock mode and 400 kHz
(max.) in the high-speed clock mode to the SCL frequency by set-
ting the SCL frequency control bits CCR4 to CCR0.
32
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 31 Structure of I2C control register
[I2C Control Register (S1D)] 002E16
The I2C control register (address 002E16) controls data communi-
cation format.
•Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. The I2C interrupt request signal occurs immediately
after the number of count specified with these bits (ACK clock is
added to the number of count when ACK clock is selected by ACK
clock bit (bit 7 of address 002F16)) have been transferred, and
BC0 to BC2 are returned to “0002”.
Also when a START condition is received, these bits become
“0002” and the address data is always transmitted and received in
8 bits.
•Bit 3: I2C interface enable bit (ES0)
This bit enables to use the multi-master I2C-BUS interface. When
this bit is set to “0,” the use disable status is provided, so that the
SDA and the SCL become high-impedance. When the bit is set to
“1,” use of the interface is enabled.
When ES0 = “0,” the following is performed.
•PIN = “1,” BB = “0” and AL = “0” are set (which are bits of the I2C
status register at address 002D16 ).
•Writing data to the I2C data shift register (address 002B16) is dis-
abled.
•Bit 4: Data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses.
When this bit is set to “0,” the addressing format is selected, so
that address data is recognized. When a match is found between a
slave address and address data as a result of comparison or when
a general call (refer to “I2C Status Register,” bit 1) is received,
transfer processing can be performed. When this bit is set to “1,”
the free data format is selected, so that slave addresses are not
recognized.
•Bit 5: Addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit
is set to “0,” the 7-bit addressing format is selected. In this case,
only the high-order 7 bits (slave address) of the I2C address regis-
ter (address 002C16) are compared with address data. When this
bit is set to “1,” the 10-bit addressing format is selected, and all
the bits of the I2C address register are compared with address
data.
•Bit 6: SDA/SCL pin selection bit
This bit selects the input/output pins of SCL and SDA of the multi-
master I2C-BUS interface.
•Bit 7: I2C-BUS interface pin input level selection bit
This bit selects the input level of the SCL and SDA pins of the
multi-master I2C-BUS interface.
Fig. 30 SDA/SCL pin selection bit
S
C
L
S
D
A
Multi-master
I C-BUS interface
2
T
S
E
LS
C
L
1
/
P
2
3
S
C
L
2
/
T
x
D
/
P
2
5
S
D
A
1
/
P
2
2
S
D
A
2
/
R
x
D
/
P
2
4
T
S
E
L
T
S
E
L
T
S
E
L
b7
TISS TSEL
10 BIT
SAD ALS ES0 BC2 BC1 BC0
b0
SDA/SCL pin selection bit
0 : Connect to ports P2
2
, P2
3
1 : Connect to ports P2
4
, P2
5
I
2
C control register
(S1D : address 002E
16
)
Bit counter (Number of
transmit/receive bits)
b2 b1 b0
0 0 0 : 8
0 0 1 : 7
0 1 0 : 6
0 1 1 : 5
1 0 0 : 4
1 0 1 : 3
1 1 0 : 2
1 1 1 : 1
I
2
C-BUS interface
enable bit
0 : Disabled
1 : Enabled
Data format selection bit
0 : Addressing format
1 : Free data format
Addressing format
selection bit
0 : 7-bit addressing
format
1 : 10-bit addressing
format
I
2
C-BUS interface pin input
level selection bit
0 : CMOS input
1 : SMBUS input
33
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
•Bit 4: SCL pin low hold bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte
data is transmitted, the PIN bit changes from “1” to “0.” At the
same time, an interrupt request signal occurs to the CPU. The PIN
bit is set to “0” in synchronization with a falling of the last clock (in-
cluding the ACK clock) of an internal clock and an interrupt
request signal occurs in synchronization with a falling of the PIN
bit. When the PIN bit is “0,” the SCL is kept in the “0” state and
clock generation is disabled. Figure 33 shows an interrupt request
signal generating timing chart.
The PIN bit is set to “1” in one of the following conditions:
•Executing a write instruction to the I2C data shift register (ad-
dress 002B16). (This is the only condition which the prohibition of
the internal clock is released and data can be communicated ex-
cept for the start condition detection.)
•When the ES0 bit is “0”
•At reset
•When writing “1” to the PIN bit by software
The conditions in which the PIN bit is set to “0” are shown below:
•Immediately after completion of 1-byte data transmission (includ-
ing when arbitration lost is detected)
•Immediately after completion of 1-byte data reception
•In the slave reception mode, with ALS = “0” and immediately af-
ter completion of slave address agreement or general call
address reception
•In the slave reception mode, with ALS = “1” and immediately af-
ter completion of address data reception
•Bit 5: Bus busy flag (BB)
This bit indicates the status of use of the bus system. When this
bit is set to “0,” this bus system is not busy and a START condition
can be generated. The BB flag is set/reset by the SCL, SDA pins
input signal regardless of master/slave. This flag is set to “1” by
detecting the start condition, and is set to “0” by detecting the stop
condition. The condition of these detecting is set by the start/stop
condition setting bits (SSC4–SSC0) of the I2C start/stop condition
control register (address 003016). When the ES0 bit of the I2C
control register (address 002E16) is “0” or reset, the BB flag is set
to “0.”
For the writing function to the BB flag, refer to the sections
“START Condition Generating Method” and “STOP Condition Gen-
erating Method” described later.
[I2C Status Register (S1)] 002D16
The I2C status register (address 002D16) controls the I2C-BUS in-
terface status. The low-order 4 bits are read-only bits and the
high-order 4 bits can be read out and written to.
Set “00002” to the low-order 4 bits, because these bits become the
reserved bits at writing.
•Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an
ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned,
this bit is set to “1.” Except in the ACK mode, the last bit value of
received data is input. The state of this bit is changed from “1” to
“0” by executing a write instruction to the I2C data shift register
(address 002B16).
•Bit 1: General call detecting flag (AD0)
When the ALS bit is “0”, this bit is set to “1” when a general call✽
whose address data is all “0” is received in the slave mode. By a
general call of the master device, every slave device receives con-
trol data after the general call. The AD0 bit is set to “0” by
detecting the STOP condition or START condition, or reset.
✽General call:The master transmits the general call address “0016” to all
slaves.
•Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of address data when the
ALS bit is “0”.
➀In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions:
• The address data immediately after occurrence of a START
condition agrees with the slave address stored in the high-or-
der 7 bits of the I2C address register (address 002C16).
•A general call is received.
➁In the slave receive mode, when the 10-bit addressing format is
selected, this bit is set to “1” with the following condition:
•When the address data is compared with the I2C address reg-
ister (8 bits consisting of slave address and RWB bit), the first
bytes agree.
➂ This bit is set to “0” by executing a write instruction to the I2C
data shift register (address 002B16) when ES0 is set to “1” or
reset.
•Bit 3: Arbitration lost✽ detecting flag (AL)
In the master transmission mode, when the SDA is made “L” by
any other device, arbitration is judged to have been lost, so that
this bit is set to “1.” At the same time, the TRX bit is set to “0,” so
that immediately after transmission of the byte whose arbitration
was lost is completed, the MST bit is set to “0.” The arbitration lost
can be detected only in the master transmission mode. When ar-
bitration is lost during slave address transmission, the TRX bit is
set to “0” and the reception mode is set. Consequently, it becomes
possible to detect the agreement of its own slave address and ad-
dress data transmitted by another master device.
✽Arbitration lost :The status in which communication as a master is dis-
abled.
34
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 33 Interrupt request signal generating timing
Fig. 32 Structure of I2C status register
•Bit 6: Communication mode specification bit (transfer direc-
tion specification bit: TRX)
This bit decides a direction of transfer for data communication.
When this bit is “0,” the reception mode is selected and the data of
a transmitting device is received. When the bit is “1,” the transmis-
sion mode is selected and address data and control data are
output onto the SDA in synchronization with the clock generated
on the SCL.
This bit is set/reset by software and hardware. About set/reset by
hardware is described below. This bit is set to “1” by hardware
when all the following conditions are satisfied:
• When ALS is “0”
•In the slave reception mode or the slave transmission mode
•When the R/W bit reception is “1”
This bit is set to “0” in one of the following conditions:
•When arbitration lost is detected.
•When a STOP condition is detected.
•When writing “1” to this bit by software is invalid by the START
condition duplication preventing function (Note).
•With MST = “0” and when a START condition is detected.
•With MST = “0” and when ACK non-return is detected.
•At reset
•Bit 7: Communication mode specification bit (master/slave
specification bit: MST)
This bit is used for master/slave specification for data communica-
tion. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are re-
ceived, and data communication is performed in synchronization
with the clock generated by the master. When this bit is “1,” the
master is specified and a START condition and a STOP condition
are generated. Additionally, the clocks required for data communi-
cation are generated on the SCL.
This bit is set to “0” in one of the following conditions.
•Immediately after completion of 1-byte data transfer when arbi-
tration lost is detected
•When a STOP condition is detected.
•Writing “1” to this bit by software is invalid by the START condi-
tion duplication preventing function (Note).
•At reset
Note: START condition duplication preventing function
The MST, TRX, and BB bits is set to “1” at the same time after con-
firming that the BB flag is “0” in the procedure of a START condition
occurrence. However, when a START condition by another master
device occurs and the BB flag is set to “1” immediately after the con-
tents of the BB flag is confirmed, the START condition duplication
preventing function makes the writing to the MST and TRX bits in-
valid. The duplication preventing function becomes valid from the
rising of the BB flag to reception completion of slave address.
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1 : Last bit = “1”
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35
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 36 START condition detecting timing diagram
START/STOP Condition Detecting Operation
The START/STOP condition detection operations are shown in
Figures 36, 37, and Table 13. The START/STOP condition is set
by the START/STOP condition set bit.
The START/STOP condition can be detected only when the input
signal of the SCL and SDA pins satisfy three conditions: SCL re-
lease time, setup time, and hold time (see Table 13).
The BB flag is set to “1” by detecting the START condition and is
reset to “0” by detecting the STOP condition.
The BB flag set/reset timing is different in the standard clock mode
and the high-speed clock mode. Refer to Table 13, the BB flag set/
reset time.
Note: When a STOP condition is detected in the slave mode (MST = 0), an
interrupt request signal “IICIRQ” occurs to the CPU.
START Condition Generating Method
When writing “1” to the MST, TRX, and BB bits of the I2C status
register (address 002D16) at the same time after writing the slave
address to the I2C data shift register (address 002B16) with the
condition in which the ES0 bit of the I2C control register (address
002E16) and the BB flag are “0”, a START condition occurs. After
that, the bit counter becomes “0002” and an SCL for 1 byte is out-
put. The START condition generating timing is different in the
standard clock mode and the high-speed clock mode. Refer to
Figure 34, the START condition generating timing diagram, and
Table 11, the START condition generating timing table.
STOP Condition Generating Method
When the ES0 bit of the I2C control register (address 002E16) is
“1,” write “1” to the MST and TRX bits, and write “0” to the BB bit
of the I2C status register (address 002D16) simultaneously. Then a
STOP condition occurs. The STOP condition generating timing is
different in the standard clock mode and the high-speed clock
mode. Refer to Figure 35, the STOP condition generating timing
diagram, and Table 12, the STOP condition generating timing
table.
Fig. 34 START condition generating timing diagram
Fig. 35 STOP condition generating timing diagram
Table 12 STOP condition generating timing table
Item
Setup time
Hold time
Standard clock mode
5.0 µs (20 cycles)
4.5 µs (18 cycles)
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ
cycles.
High-speed clock mode
3.0 µs (12 cycles)
2.5 µs (10 cycles)
Table 11 START condition generating timing table
Item
Setup time
Hold time
Standard clock mode
5.0 µs (20 cycles)
5.0 µs (20 cycles)
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ
cycles.
High-speed clock mode
2.5 µs (10 cycles)
2.5 µs (10 cycles)
Table 13 START condition/ST OP condition detecting conditions
Note: Unit : Cycle number of system clock φ
SSC value is the decimal notation value of the START/STOP condi-
tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC
value. The value in parentheses is an example when the I2C START/
STOP condition control register is set to “1816” at φ = 4 MHz.
Fig. 37 STOP condition detecting timing diagram
S
CL
release time
Standard clock mode
High-speed clock mode
4 cycles (1.0 µs)
2 cycles (1.0 µs)
2 cycles (0.5 µs)
3.5 cycles (0.875 µs)
SSC value + 1
2
SSC value + 1
2
SSC value –1
2
Setup time
Hold time
BB flag set/
reset time
SSC value + 1 cycle (6.25 µs)
cycle
< 4.0 µs (3.125 µs)
cycle
< 4.0 µs (3.125 µs)
+ 2 cycles (3.375 µs)
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36
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
[I2C START/STOP Condition Control Register
(S2D)] 003016
The I2C START/STOP condition control register (address 003016)
controls START/STOP condition detection.
•Bits 0 to 4: START/STOP condition set bit (SSC4–SSC0)
SCL release time, setup time, and hold time change the detection
condition by value of the main clock divide ratio selection bit and
the oscillation frequency f(XIN) because these time are measured
by the internal system clock. Accordingly, set the proper value to
the START/STOP condition set bits (SSC4 to SSC0) in considered
of the system clock frequency. Refer to Table 13.
Do not set “000002” or an odd number to the START/STOP condi-
tion set bit (SSC4 to SSC0).
Refer to Table 14, the recommended set value to START/STOP
condition set bits (SSC4–SSC0) for each oscillation frequency.
•Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP)
An interrupt can occur when detecting the falling or rising edge of
the SCL or SDA pin. This bit selects the polarity of the SCL or
SDA pin interrupt pin.
•Bit 6: SCL/SDA interrupt pin selection bit (SIS)
This bit selects the pin of which interrupt becomes valid between
the SCL pin and the SDA pin.
Note: When changing the setting of the SCL/SDA interrupt pin polarity se-
lection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS
interface enable bit ES0, the SCL/SDA interrupt request bit may be
set. When selecting the SCL/SDA interrupt source, disable the inter-
rupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/
SDA interrupt pin selection bit, or the I2C-BUS interface enable bit
ES0 is set. Reset the request bit to “0” after setting these bits, and
enable the interrupt.
Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective
address communication formats are described below.
➀ 7-bit addressing format
To adapt the 7-bit addressing format, set the 10BIT SAD bit of
the I2C control register (address 002E16) to “0.” The first 7-bit
address data transmitted from the master is compared with the
high-order 7-bit slave address stored in the I2C address register
(address 002C16). At the time of this comparison, address com-
parison of the RWB bit of the I2C address register (address
002C16) is not performed. For the data transmission format
when the 7-bit addressing format is selected, refer to Figure 39,
(1) and (2).
➁ 10-bit addressing format
To adapt the 10-bit addressing format, set the 10BIT SAD bit of
the I2C control register (address 002E16) to “1.” An address
comparison is performed between the first-byte address data
transmitted from the master and the 8-bit slave address stored
in the I2C address register (address 002C16). At the time of this
comparison, an address comparison between the RWB bit of
the I2C address register (address 002C16) and the R/W bit
which is the last bit of the address data transmitted from the
master is made. In the 10-bit addressing mode, the RWB bit
which is the last bit of the address data not only specifies the
direction of communication for control data, but also is pro-
cessed as an address data bit.
When the first-byte address data agree with the slave address,
the AAS bit of the I2C status register (address 002D16) is set to
“1.” After the second-byte address data is stored into the I2C
data shift register (address 002B16), perform an address com-
parison between the second-byte data and the slave address
by software. When the address data of the 2 bytes agree with
the slave address, set the RWB bit of the I2C address register
(address 002C16) to “1” by software. This processing can make
the 7-bit slave address and R/W data agree, which are re-
ceived after a RESTART condition is detected, with the value of
the I2C address register (address 002C16). For the data trans-
mission format when the 10-bit addressing format is selected,
refer to Figure 39, (3) and (4).
37
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
START/STOP
condition
control register
Oscillation
frequency
f(XIN) (MHz)
Fig. 39 Address data communication format
Fig. 38 Structure of I2C START/STOP condition control register
Note: Do not set an odd number to the START/STOP condition set bit (SSC4 to SSC0).
Table 14 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency
Main clock
divide ratio System
clock φ
(MHz)
SCL release time
(µs) Setup time
(µs) Hold time
(µs)
8
8
4
2
2
8
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2
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XXX11000
XXX00100
XXX01100
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XXX00100
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3.125 µs (12.5 cycles)
2.5 µs (2.5 cycles)
3.25 µs (6.5 cycles)
2.75 µs (5.5 cycles)
2.5 µs (2.5 cycles)
6.75 µs (27 cycles)
6.25 µs (25 cycles)
5.0 µs (5 cycles)
6.5 µs (13 cycles)
5.5 µs (11 cycles)
5.0 µs (5 cycles)
3.375 µs (13.5 cycles)
3.125 µs (12.5 cycles)
2.5 µs (2.5 cycles)
3.25 µs (6.5 cycles)
2.75 µs (5.5 cycles)
2.5 µs (2.5 cycles)
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r
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l
a
v
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d
d
r
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d
b
y
t
e
sAS
rSlave address
1st 7 bits R
/
W A
D
a
t
aD
a
t
a P
A
: Master to slave
: Slave to master
A
38
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is
shown below.
➀ Set a slave address in the high-order 7 bits of the I2C address
register (address 002C16) and “0” into the RWB bit.
➁ Set the ACK return mode and SCL = 100 kHz by setting “8516”
in the I2C clock control register (address 002F16).
➂ Set “0016” in the I2C status register (address 002D16) so that
transmission/reception mode can become initializing condition.
➃ Set a communication enable status by setting “0816” in the I2C
control register (address 002E16).
➄ Confirm the bus free condition by the BB flag of the I2C status
register (address 002D16).
➅ Set the address data of the destination of transmission in the
high-order 7 bits of the I2C data shift register (address 002B16)
and set “0” in the least significant bit.
➆ Set “F016” in the I2C status register (address 002D16) to gener-
ate a START condition. At this time, an SCL for 1 byte and an
ACK clock automatically occur.
➇ Set transmit data in the I2C data shift register (address 002B16).
At this time, an SCL and an ACK clock automatically occur.
➈ When transmitting control data of more than 1 byte, repeat step
➇.
➉ Set “D016” in the I2C status register (address 002D16) to gener-
ate a STOP condition if ACK is not returned from slave
reception side or transmission ends.
Example of Slave Reception
An example of slave reception in the high-speed clock mode, at
the SCL frequency of 400 kHz, in the ACK non-return mode and
using the addressing format is shown below.
➀ Set a slave address in the high-order 7 bits of the I2C address
register (address 002C16) and “0” in the RWB bit.
➁ Set the no ACK clock mode and SCL = 400 kHz by setting
“2516” in the I2C clock control register (address 002F16).
➂ Set “0016” in the I2C status register (address 002D16) so that
transmission/reception mode can become initializing condition.
➃ Set a communication enable status by setting “0816” in the I2C
control register (address 002E16).
➄ When a START condition is received, an address comparison is
performed.
➅ •When all transmitted addresses are “0” (general call):
AD0 of the I2C status register (address 002D16) is set to “1”
and an interrupt request signal occurs.
• When the transmitted addresses agree with the address set
in ➀:
ASS of the I2C status register (address 002D16) is set to “1”
and an interrupt request signal occurs.
• In the cases other than the above AD0 and AAS of the I2C sta-
tus register (address 002D16) are set to “0” and no interrupt
request signal occurs.
➆ Set dummy data in the I2C data shift register (address 002B16).
➇ When receiving control data of more than 1 byte, repeat step ➆.
➈ When a STOP condition is detected, the communication ends.
39
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
■Precautions when using multi-master I2C-
BUS interface
(1) Read-modify-write instruction
The precautions when the read-modify-write instruction such as
SEB, CLB etc. is executed for each register of the multi-master
I2C-BUS interface are described below.
•I2C data shift register (S0: address 002B16)
When executing the read-modify-write instruction for this regis-
ter during transfer, data may become a value not intended.
•I2C address register (S0D: address 002C16)
When the read-modify-write instruction is executed for this regis-
ter at detecting the STOP condition, data may become a value
not intended. It is because H/W changes the read/write bit
(RWB) at the above timing.
•I2C status register (S1: address 002D16)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by H/W.
•I2C control register (S1D: address 002E16)
When the read-modify-write instruction is executed for this regis-
ter at detecting the START condition or at completing the byte
transfer, data may become a value not intended. Because H/W
changes the bit counter (BC0-BC2) at the above timing.
•I2C clock control register (S2: address 002F16)
The read-modify-write instruction can be executed for this regis-
ter.
•I2C START/STOP condition control register (S2D: address
003016)
The read-modify-write instruction can be executed for this regis-
ter.
(2) START condition generating procedure using multi-master
1. Procedure example (The necessary conditions of the generat-
ing procedure are described in Items 2 to 5 below.
LDA —(Taking out of slave address value)
SEI (Interrupt disabled)
BBS 5, S1, BUSBUSY (BB flag confirming and branch process)
BUSFREE:
STA S0 (Writing of slave address value)
LDM #$F0, S1 (T rigger of START condition generating)
CLI (Interrupt enabled)
BUSBUSY:
CLI (Interrupt enabled)
2. Use “Branch on Bit Set” of “BBS 5, $002D, –” for the BB flag
confirming and branch process.
3. Use “STA $2B, STX $2B” or “STY $2B” of the zero page ad-
dressing instruction for writing the slave address value to the
I2C data shift register.
4. Execute the branch instruction of Item 2 and the store instruc-
tion of Item 3 continuously, as shown in the procedure example
above.
5. Disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
(3) RESTART condition generating procedure
1. Procedure example (The necessary conditions for the proce-
dure are described in items 2 to 4 below.)
Execute the following procedure when the PIN bit is “0.”
LDM #$00, S1 (Select slave receive mode)
LDA —(Take out of slave address value)
SEI (Disable interrupt)
STA S0 (Write slave address value)
LDM #$F0, S1 (
T rigger RESTART condition generation
)
CLI (Enable interrupt)
2. Select the slave receive mode when the PIN bit is “0.” Do not
write “1” to the PIN bit. Neither “0” nor “1” is specified as input to
the BB bit.
The TRX bit becomes “0” and the SDA pin is released.
3. The SCL pin is released by writing the slave address value to
the I2C data shift register.
4. Disable interrupts during the following two process steps:
• Write slave address value
• Trigger RESTART condition generation
(4) Writing to I2C status register
Do not execute an instruction to set the PIN bit to “1” from “0” and
an instruction to set the MST and TRX bits to “0” from “1” simulta-
neously. Because it may enter the state that the SCL pin is
released and the SDA pin is released after about one machine
cycle. Do not execute an instruction to set the MST and TRX bits
to “0” from “1” simultaneously when the PIN bit is “1.” Because it
may become the same as above.
(5) Process of after STOP condition generating
Do not write data in the I2C data shift register S0 and the I2C sta-
tus register S1 until the bus busy flag BB becomes “0” after
generating the STOP condition in the master mode. Because the
STOP condition waveform might not be normally generated.
Reading to the above registers do not have the problem.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
40
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
PULSE WIDTH MODULATION (PWM)
The 3851 group (built-in 24 KB or more ROM) has a PWM func-
tion with an 8-bit resolution, based on a signal that is the clock
input XIN or that clock input divided by 2.
Data Setting
The PWM output pin also functions as port P44. Set the PWM
period by the PWM prescaler, and set the “H” term of output pulse
by the PWM register.
If the value in the PWM prescaler is n and the value in the PWM
register is m (where n = 0 to 255 and m = 0 to 255) :
PWM period = 255 ✕ (n+1) / f(XIN)
= 31.875 ✕ (n+1) µs
(when f(XIN) = 8 MHz,count source selection bit = “0”)
Output pulse “H” term = PWM period ✕ m / 255
= 0.125 ✕ (n+1) ✕ m µs
(when f(XIN) = 8 MHz,count source selection bit = “0”)
Fig. 40 Timing of PWM period
Fig. 41 Block diagram of PWM function
PWM Operation
When bit 0 (PWM enable bit) of the PWM control register is set to
“1”, operation starts by initializing the PWM output circuit, and
pulses are output starting at an “H”.
If the PWM register or PWM prescaler is updated during PWM
output, the pulses will change in the cycle after the one in which
the change was made.
3
1
.
8
7
5
✕
m
✕
(
n
+
1
)
2
5
5µs
T = [31. 875 ✕ (n+1)] µs
P
W
M
o
u
t
p
u
t
m: Contents of PWM register
n : Contents of PWM prescaler
T : PWM period (when f(X
IN
) = 8 MHz, count
source selection bit = “0”)
D
a
t
a
b
u
s
Count source
selection bit
“
0
”
“
1
”
PWM
prescaler pre-latch P
W
M
r
e
g
i
s
t
e
r
p
r
e
-
l
a
t
c
h
PWM
prescaler la tch P
W
M
r
e
g
i
s
t
e
r
l
a
t
c
h
T
r
a
n
s
f
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r
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t
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r
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i
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r
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IN
P
o
r
t
P
4
4
l
a
t
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h
P
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e
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a
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t
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r
t
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4
4
P
W
M
p
r
e
s
c
a
l
e
r
(X
CIN
at low-speed mode)
41
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 42 Structure of PWM control register
Fig. 43 PWM output timing when PWM register or PWM prescaler is changed
■Note
The PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin.
The length of this “L” level output is as follows:
sec (Count source selection bit = 0, where n is the value set in the prescaler)
sec (Count source selection bit = 1, where n is the value set in the prescaler)
n+1
2 • f(XIN)
n+1
f(XIN)
P
W
M
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
W
M
C
O
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:
a
d
d
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s
s
0
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1
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6
)
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(
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0
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:
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a
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:
P
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a
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(
XI
N)
(
f
(
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I
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d
m
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/
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(
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(
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/
2
a
t
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o
w
-
s
p
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e
d
m
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)
ABC
B
TC
T
2
=
P
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o
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p
u
t
P
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r
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g
i
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w
r
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P
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p
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c
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r
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r
i
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s
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n
a
l
(
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h
a
n
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e
s
“
H
”
t
e
r
m
f
r
o
m
“
A
”
t
o
“
B
”
.
)
(
C
h
a
n
g
e
s
P
W
M
p
e
r
i
o
d
f
r
o
m
“
T
”
t
o
“
T
2
”
.
)
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h
e
n
t
h
e
c
o
n
t
e
n
t
s
o
f
t
h
e
P
W
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r
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i
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r
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P
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p
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d
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n
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f
r
o
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t
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t
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c
h
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e
.
TTT
2
42
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
A-D CONVERTER
[A-D Conversion Registers (ADL, ADH)]
003516, 003616
The A-D conversion registers are read-only registers that store the
result of an A-D conversion. Do not read these registers during an
A-D conversion.
[A-D Control Register (ADCON)] 003416
The AD control register controls the A-D conversion process. Bits
0 to 2 select a specific analog input pin. Bit 4 indicates the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AVSS and VREF into 1024 and outputs the divided voltages.
Channel Selector
The channel selector selects one of ports P30/AN0 to P34/AN4 and
inputs the voltage to the comparator.
Comparator and Control Circuit
The comparator and control circuit compare an analog input volt-
age with the comparison voltage, and the result is stored in the
A-D conversion registers. When an A-D conversion is completed,
the control circuit sets the A-D conversion completion bit and the
A-D interrupt request bit to “1”.
Note that because the comparator consists of a capacitor cou-
pling, set f(XIN) to 500 kHz or more during an A-D conversion.
When the A-D converter is operated at low-speed mode, f(XIN)
and f(XCIN) do not have the lower limit of frequency, because of
the A-D converter has a built-in self-oscillation circuit.
Fig. 44 Structure of A-D control register
Fig. 45 Structure of A-D conversion registers
Fig. 46 Block diagram of A-D converter
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
A
D
C
O
N
:
a
d
d
r
e
s
s
0
0
3
41
6)
Analog input pin selection bits
0 0 0: P30/AN0
0 0 1: P31/AN1
0 1 0: P32/AN2
0 1 1: P33/AN3
1 0 0: P34/AN4
Not used (returns “0” when read)
A-D conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
b7 b
0
b
2
b
1
b
0
1
0
-
b
i
t
r
e
a
d
i
n
g
(
R
e
a
d
a
d
d
r
e
s
s
0
0
3
6
1
6
b
e
f
o
r
e
0
0
3
5
1
6
)
(
A
d
d
r
e
s
s
0
0
3
6
1
6
)
(
A
d
d
r
e
s
s
0
0
3
5
1
6
)
8
-
b
i
t
r
e
a
d
i
n
g
(
R
e
a
d
o
n
l
y
a
d
d
r
e
s
s
0
0
3
5
1
6
)
(
A
d
d
r
e
s
s
0
0
3
5
1
6
)
b
8
b
7b
6b
5b
4
b
3b
2b
1b
0
b
7b
0
b
9
b7 b
0
N
o
t
e
:
T
h
e
h
i
g
h
-
o
r
d
e
r
6
b
i
t
s
o
f
a
d
d
r
e
s
s
0
0
3
61
6
b
e
c
o
m
e
“
0
”
a
t
r
e
a
d
i
n
g
.
b9 b8 b7 b
6
b5 b4 b
3
b
2
b
7b0
C
h
a
n
n
e
l
s
e
l
e
c
t
o
r
A
-
D
c
o
n
t
r
o
l
c
i
r
c
u
i
t
A
-
D
c
o
n
v
e
r
s
i
o
n
l
o
w
-
o
r
d
e
r
r
e
g
i
s
t
e
r
R
e
s
i
s
t
o
r
l
a
d
d
e
r
V
R
E
F
A
V
S
S
Comparator
A
-
D
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
7b
0
3
10
P
3
0
/
A
N
0
P
3
1
/
A
N
1
P3
2
/AN
2
P
3
3
/
A
N
3
P
3
4
/
A
N
4
Data bus
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
A-D conversion high-order register
(
A
d
d
r
e
s
s
0
0
3
4
1
6
)
(
A
d
d
r
e
s
s
0
0
3
6
1
6
)
(
A
d
d
r
e
s
s
0
0
3
5
1
6
)
43
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control reg-
ister (address 003916) after reset, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
003916) and an internal reset occurs at an underflow of the watch-
dog timer H.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 003916) may be
started before an underflow. When the watchdog timer control reg-
ister (address 003916) is read, the values of the high-order 6 bits
of the watchdog timer H, STP instruction disable bit, and watch-
dog timer H count source selection bit are read.
●Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address
003916), each watchdog timer H and L are set to “FF16.”
Fig. 48 Structure of Watchdog timer control register
●Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 003916) per-
mits selecting a watchdog timer H count source. When this bit is
set to “0”, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to 131.072 ms at f(XIN)
= 8 MHz frequency and 32.768 s at f(XCIN) = 32 kHz frequency.
When this bit is set to “1”, the count source becomes the signal
divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case
is set to 512 µs at f(XIN) = 8 MHz frequency and 128 ms at f(XCIN)
= 32 kHz frequency. This bit is cleared to “0” after reset.
●Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 003916) per-
mits disabling the STP instruction when the watchdog timer is in
operation.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, once the STP
instruction is executed, an internal reset occurs. When this bit is
set to “1”, it cannot be rewritten to “0” by program. This bit is
cleared to “0” after reset.
Fig. 47 Block diagram of Watchdog timer
X
IN
Data bus
X
CIN
“
1
0
”
“
0
0
”
“
0
1
”
Main clock division
ratio selection bits
(Note)
“
0
”
“
1
”
1
/
1
6
Watchdog timer H c ount
source selection bit
R
e
s
e
t
c
i
r
c
u
i
t
STP instruction disable bit
W
a
t
c
h
d
o
g
t
i
m
e
r
H
(
8
)
“
F
F
1
6
”
i
s
s
e
t
w
h
e
n
w
a
t
c
h
d
o
g
t
i
m
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
i
s
w
r
i
t
t
e
n
t
o
.
I
n
t
e
r
n
a
l
r
e
s
e
t
R
E
S
E
T
W
a
t
c
h
d
o
g
t
i
m
e
r
L
(
8
)
N
o
t
e
:
A
n
y
o
n
e
o
f
h
i
g
h
-
s
p
e
e
d
,
m
i
d
d
l
e
-
s
p
e
e
d
o
r
l
o
w
-
s
p
e
e
d
m
o
d
e
i
s
s
e
l
e
c
t
e
d
b
y
b
i
t
s
7
a
n
d
6
o
f
t
h
e
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
.
STP instruction
“FF
16
” is set when
watchdog timer
control register is
writ te n to.
b
0
STP instruction disable bit
0: STP instruction enable d
1: STP instruction disabled
Watc hdog timer H c ount s our c e selection bit
0: Watchdog timer L underflow
1: f(X
IN
)/16 or f(X
CIN
)/16
W
a
t
c
h
d
o
g
t
i
m
e
r
H
(
f
o
r
r
e
a
d
-
o
u
t
o
f
h
i
g
h
-
o
r
d
e
r
6
b
i
t
)
Watchdog timer control register
(WDTCON : address 0039
16
)
b
7
44
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
RESET CIRCUIT
To reset the microcomputer, RESET pin must be held at an “L”
level for 20 cycles or more of XIN. Then the RESET pin is returned
to an “H” level (the power source voltage must be between 2.7 V
and 5.5 V, and the oscillation must be stable), reset is released.
After the reset is completed, the program starts from the address
contained in address FFFD16 (high-order byte) and address
FFFC16 (low-order byte). Make sure that the reset input voltage is
less than 0.54 V for VCC of 2.7 V.
Fig. 50 Reset sequence
Fig. 49 Reset circuit example
(Note)
0
.
2
V
C
C
0V
0V
P
o
w
e
r
o
n
V
C
C
R
E
S
E
T
V
C
C
R
E
S
E
T
P
o
w
e
r
s
o
u
r
c
e
v
o
l
t
a
g
e
d
e
t
e
c
t
i
o
n
c
i
r
c
u
i
t
P
o
w
e
r
s
o
u
r
c
e
v
o
l
t
a
g
e
R
e
s
e
t
i
n
p
u
t
v
o
l
t
a
g
e
N
o
t
e :
R
e
s
e
t
r
e
l
e
a
s
e
v
o
l
t
a
g
e
;
V
c
c
=
2
.
7
V
R
E
S
E
T
D
a
t
a
φ
A
d
d
r
e
s
s
S
Y
N
C
X
I
N
:
8
t
o
1
3
c
l
o
c
k
c
y
c
l
e
s
X
I
N
???? ?F
F
F
CF
F
F
DA
D
H
,
L
??? ??AD
L
A
D
H
1: The frequency relation of f(X
IN
) and f(φ) is f(X
IN
) = 8 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous stat e.
3: All signals except X
IN
and RESET are internals.
R
e
s
e
t
a
d
d
r
e
s
s
f
r
o
m
t
h
e
v
e
c
t
o
r
t
a
b
l
e
.
N
o
t
e
s
R
E
S
E
T
O
U
T
45
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 51 Internal status at reset
000
X
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
F
F1
6
0
11
6
0
01
6
0
01
6
F
F1
6
F
F1
6
F
F1
6
F
F1
6
0
01
6
0
01
6
0
01
6
0
01
6
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
A
D
C
O
N
)
A
-
D
c
o
n
v
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r
s
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o
n
l
o
w
-
o
r
d
e
r
r
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g
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s
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e
r
(
A
D
L
)
A
-
D
c
o
n
v
e
r
s
i
o
n
h
i
g
h
-
o
r
d
e
r
r
e
g
i
s
t
e
r
(
A
D
H
)
M
I
S
R
G
W
a
t
c
h
d
o
g
t
i
m
e
r
c
o
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t
r
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l
r
e
g
i
s
t
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r
(
W
D
T
C
O
N
)
I
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
r
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g
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r
(
I
N
T
E
D
G
E
)
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
(
C
P
U
M
)
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
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g
i
s
t
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r
1
(
I
R
E
Q
1
)
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
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g
i
s
t
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r
2
(
I
R
E
Q
2
)
I
n
t
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r
r
u
p
t
c
o
n
t
r
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r
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g
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1
(
I
C
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N
1
)
I
n
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r
r
u
p
t
c
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t
r
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r
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g
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2
(
I
C
O
N
2
)
P
r
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:
N
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t
f
i
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S
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t
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v
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n
a
b
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v
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R
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M
c
o
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t
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f
i
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a
t
r
e
s
e
t
,
t
h
e
y
m
u
s
t
b
e
s
e
t
.
(
1
)
(
2
)
(
3
)
(
4
)
(
5
)
(
6
)
(
7
)
(
8
)
(
9
)
(
1
0
)
(
1
1
)
(
1
2
)
(
1
3
)
(
1
4
)
(
1
5
)
(
1
6
)
(
1
7
)
(
1
8
)
(
1
9
)
(
2
0
)
(
2
1
)
(
2
2
)
(
2
3
)
(
2
4
)
(
2
5
)
(
2
6
)
(
2
7
)
(
2
8
)
(
2
9
)
(
3
0
)
(
3
1
)
(
3
2
)
(
3
3
)
(
3
4
)
(
3
5
)
A
d
d
r
e
s
sR
e
g
i
s
t
e
r
c
o
n
t
e
n
t
s
P
o
r
t
P
0
(
P
0
)
P
o
r
t
P
0
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
0
D
)
P
o
r
t
P
1
(
P
1
)
P
o
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t
P
1
d
i
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c
t
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o
n
r
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g
i
s
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r
(
P
1
D
)
P
o
r
t
P
2
(
P
2
)
P
o
r
t
P
2
d
i
r
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c
t
i
o
n
r
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g
i
s
t
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r
(
P
2
D
)
P
o
r
t
P
3
(
P
3
)
P
o
r
t
P
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
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r
(
P
3
D
)
P
o
r
t
P
4
(
P
4
)
P
o
r
t
P
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
4
D
)
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
S
I
O
2
C
O
N
1
)
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
S
I
O
2
C
O
N
2
)
S
e
r
i
a
l
I
/
O
2
r
e
g
i
s
t
e
r
(
S
I
O
2
)
T
r
a
n
s
m
i
t
/
R
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
(
T
B
/
R
B
)
S
e
r
i
a
l
I
/
O
1
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
S
I
O
S
T
S
)
S
e
r
i
a
l
I
/
O
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
I
O
C
O
N
)
U
A
R
T
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
U
A
R
T
C
O
N
)
B
a
u
d
r
a
t
e
g
e
n
e
r
a
t
o
r
(
B
R
G
)
P
W
M
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
W
M
C
O
N
)
P
W
M
p
r
e
s
c
a
l
e
r
(
P
R
E
P
W
M
)
P
W
M
r
e
g
i
s
t
e
r
(
P
W
M
)
P
r
e
s
c
a
l
e
r
1
2
(
P
R
E
1
2
)
T
i
m
e
r
1
(
T
1
)
T
i
m
e
r
2
(
T
2
)
T
i
m
e
r
X
Y
m
o
d
e
r
e
g
i
s
t
e
r
(
T
M
)
P
r
e
s
c
a
l
e
r
X
(
P
R
E
X
)
T
i
m
e
r
X
(
T
X
)
P
r
e
s
c
a
l
e
r
Y
(
P
R
E
Y
)
T
i
m
e
r
Y
(
T
Y
)
T
i
m
e
r
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
T
C
S
S
)
I2C
a
d
d
r
e
s
s
r
e
g
i
t
e
r
(
S
0
D
)
I2C
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
S
1
)
I2C
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
1
D
)
I2C
c
l
o
c
k
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
2
)
I2C
s
t
a
r
t
/
s
t
o
p
c
o
n
d
i
t
i
o
n
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
2
D
)
00000111
10000000
X
X
X
X
X
X
X
X
0
0
0
01
6
0
0
0
11
6
0
0
0
21
6
0
0
0
31
6
0
0
0
41
6
0
0
0
51
6
0
0
0
61
6
0
0
0
71
6
0
0
0
81
6
0
0
0
91
6
0
0
1
51
6
0
0
1
61
6
0
0
1
71
6
0
0
1
81
6
0
0
1
91
6
0
0
1
A1
6
0
0
1
B1
6
0
0
1
C1
6
0
0
1
D1
6
0
0
1
E1
6
0
0
1
F1
6
0
0
2
01
6
0
0
2
11
6
0
0
2
21
6
0
0
2
31
6
0
0
2
41
6
0
0
2
51
6
0
0
2
61
6
0
0
2
71
6
0
0
2
81
6
0
0
2
C1
6
0
0
2
D1
6
0
0
2
E1
6
0
0
2
F1
6
0
0
3
01
6
11100000
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
(48)
Register contents
0
0
3
41
6
0
0
3
51
6
0
0
3
61
6
0
0
3
81
6
0
0
3
91
6
0
0
3
A1
6
0
0
3
B1
6
0
0
3
C1
6
0
0
3
D1
6
0
0
3
E1
6
0
0
3
F1
6
(
P
S
)
(
P
CH)
(
P
CL)
A
d
d
r
e
s
s
0016
0016
0016
0016
0016
0016
XX
X
X
X1
X
X
F
F
F
D1
6
c
o
n
t
e
n
t
s
F
F
F
C1
6
c
o
n
t
e
n
t
s
00111111
01001000
00010000
X
X
X
X
X
X
X
X
X
X
000000
000 0100
X
X
X
XX
46
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
CLOCK GENERATING CIRCUIT
The 3851 group (built-in 24 KB or more ROM) has two built-in os-
cillation circuits: main clock XIN-XOUT oscillation circuit and sub
clock XCIN-XCOUT oscillation circuit. An oscillation circuit can be
formed by connecting a resonator between XIN and XOUT (XCIN
and XCOUT). Use the circuit constants in accordance with the reso-
nator manufacturer’s recommended values. No external resistor is
needed between XIN and XOUT since a feed-back resistor exists
on-chip. However, an external feed-back resistor is needed be-
tween XCIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After re-
set is released, this mode is selected.
(2) High-speed mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed mode
The internal clock φ is half the frequency of XCIN.
■Note
If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The sufficient time
is required for the sub-clock to stabilize, especially immediately af-
ter power on and at returning from the stop mode. When switching
the mode between middle/high-speed and low-speed, set the fre-
quency on condition that f(XIN) > 3•f(XCIN).
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to “1.” When the main clock XIN is
restarted (by setting the main clock stop bit to “0”), set sufficient
time for oscillation to stabilize.
The sub-clock XCIN-XCOUT oscillation circuit can not directly input
clocks that are generated externally. Accordingly, make sure to
cause an external resonator to oscillate.
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillation stops. When the oscillation
stabilizing time set after STP instruction released bit is “0,” the
prescaler 12 is set to “FF16” and timer 1 is set to “0116.” When the
oscillation stabilizing time set after STP instruction released bit is
“1,” set the sufficient time for oscillation of used oscillator to stabi-
lize since nothing is set to the prescaler 12 and timer 1.
Either XIN or XCIN divided by 16 is input to the prescaler 12 as
count source. Oscillator restarts when an external interrupt is re-
ceived, but the internal clock φ is not supplied to the CPU (remains
at “H”) until timer 1 underflows. The internal clock φ is supplied for
the first time, when timer 1 underflows. This ensures time for the
clock oscillation using the ceramic resonators to be stabilized.
Fig. 52 Ceramic resonator circuit
Fig. 53 External clock input circuit
When the oscillator is restarted by reset, apply “L” level to the
RESET pin until the oscillation is stable since a wait time will not
be generated.
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ re-
starts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
To ensure that the interrupts will be received to release the STP or
WIT state, their interrupt enable bits must be set to “1” before ex-
ecuting of the STP or WIT instruction.
When releasing the STP state, the prescaler 12 and timer 1 will
start counting the clock XIN divided by 16. Accordingly, set the
timer 1 interrupt enable bit to “0” before executing the STP instruc-
tion.
■Note
When using the oscillation stabilizing time set after STP instruction
released bit set to “1”, evaluate time to stabilize oscillation of the
used oscillator and set the value to the timer 1 and prescaler 12.
XC
I
N
XC
O
U
T
XI
N
XO
U
T
CI
NCO
U
T
CC
I
NCC
O
U
T
R
fR
d
X
C
I
N
X
C
O
U
T
X
I
N
X
O
U
T
C
C
I
N
C
C
O
U
T
R
fR
dO
p
e
n
E
x
t
e
r
n
a
l
o
s
c
i
l
l
a
t
i
o
n
c
i
r
c
u
i
t
V
c
c
V
s
s
47
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 54 Structure of MISRG
■Notes on middle-speed mode automatic
switch set bit
When the middle-speed mode automatic switch set bit is set to “1”
while operating in the low-speed mode, by detecting the rising/fall-
ing edge of the SCL or SDA pin, XIN oscillation automatically starts
and the mode is automatically switched to the middle-speed
mode. The timing which changes from the low-speed mode to the
middle-speed mode can be set as 4.5 to 5.5 cycle, or 6.5 to 7.5
cycle in the low-speed mode by the middle-speed mode automatic
switch waiting time set bit. Select according to the oscillation start
characteristic of the XIN oscillator to be used.
Fig. 55 System clock generating circuit block diagram (Single-chip mode)
M
I
S
R
G
(
M
I
S
R
G
:
a
d
d
r
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s
s
0
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81
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b
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:
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t
“0
11
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t
o
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r
1
,
“
F
F1
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t
o
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r
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s
c
a
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r
1
2
1
:
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u
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r
(
a
d
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0
0
3
B1
6)
c
h
a
n
g
e
s
.
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
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r
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a
d
)
M
i
d
d
l
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-
s
p
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d
m
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a
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m
a
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c
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w
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h
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(
D
e
p
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d
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o
n
p
r
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r
a
m
)
0
:
I
n
v
a
l
i
d
1
:
A
u
t
o
m
a
t
i
c
s
w
i
t
c
h
s
t
a
r
t
M
i
d
d
l
e
-
s
p
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d
m
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a
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m
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t
b
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0
:
4
.
5
t
o
5
.
5
m
a
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h
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y
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1
:
6
.
5
t
o
7
.
5
m
a
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h
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s
M
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:
N
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a
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1
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n
a
b
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W
I
T
i
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s
t
r
u
c
t
i
o
nSTP instruction
T
i
m
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g
φ
(
i
n
t
e
r
n
a
l
c
l
o
c
k
)
S
R
Q
S
T
P
i
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s
t
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c
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S
R
Q
M
a
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n
c
l
o
c
k
s
t
o
p
b
i
t
S
R
Q
1
/
21/4
X
IN
X
OUT
X
C
O
U
T
X
C
I
N
I
n
t
e
r
r
u
p
t
r
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q
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t
R
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I
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r
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p
t
d
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a
b
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f
l
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l
1
/
2
P
o
r
t
X
C
s
w
i
t
c
h
b
i
t
“
1
”“
0
”
Low-speed mode
H
i
g
h
-
s
p
e
e
d
o
r
m
i
d
d
l
e
-
s
p
e
e
d
m
o
d
e
Middle-speed mode
High-speed or
low-speed mode
M
a
i
n
c
l
o
c
k
d
i
v
i
s
i
o
n
r
a
t
i
o
s
e
l
e
c
t
i
o
n
b
i
t
s
(
N
o
t
e
1
)
N
o
t
e
s
1
:
A
n
y
o
n
e
o
f
h
i
g
h
-
s
p
e
e
d
,
m
i
d
d
l
e
-
s
p
e
e
d
o
r
l
o
w
-
s
p
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d
m
o
d
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i
s
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l
e
c
t
e
d
b
y
b
i
t
s
7
a
n
d
6
o
f
t
h
e
C
P
U
m
o
d
e
r
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g
i
s
t
e
r
.
W
h
e
n
l
o
w
-
s
p
e
e
d
m
o
d
e
i
s
s
e
l
e
c
t
e
d
,
s
e
t
p
o
r
t
X
c
s
w
i
t
c
h
b
i
t
(
b
4
)
t
o
“
1
”
.
2
:
W
h
e
n
b
i
t
0
o
f
M
I
S
R
G
=
“
0
”
M
a
i
n
c
l
o
c
k
d
i
v
i
s
i
o
n
r
a
t
i
o
s
e
l
e
c
t
i
o
n
b
i
t
s
(
N
o
t
e
1
)
FF
16
01
16
P
r
e
s
c
a
l
e
r
1
2Timer 1
Reset or
STP instruction
(Note 2)
R
e
s
e
t
Timer 12 count source
select ion bi t
48
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 56 State transitions of system clock
C
M
4
:
P
o
r
t
X
c
s
w
i
t
c
h
b
i
t
0
:
I
/
O
p
o
r
t
f
u
n
c
t
i
o
n
(
s
t
o
p
o
s
c
i
l
l
a
t
i
n
g
)
1
:
X
C
I
N
-
X
C
O
U
T
o
s
c
i
l
l
a
t
i
n
g
f
u
n
c
t
i
o
n
C
M
5
:
M
a
i
n
c
l
o
c
k
(
X
I
N
-
X
O
U
T
)
s
t
o
p
b
i
t
0
:
O
p
e
r
a
t
i
n
g
1
:
S
t
o
p
p
e
d
C
M
7
,
C
M
6
:
M
a
i
n
c
l
o
c
k
d
i
v
i
s
i
o
n
r
a
t
i
o
s
e
l
e
c
t
i
o
n
b
i
t
s
b
7
b
6
0
0
:
φ
=
f
(
X
I
N
)
/
2
(
H
i
g
h
-
s
p
e
e
d
m
o
d
e
)
0
1
:
φ
=
f
(
X
I
N
)
/
8
(
M
i
d
d
l
e
-
s
p
e
e
d
m
o
d
e
)
1
0
:
φ
=
f
(
X
C
I
N
)
/
2
(
L
o
w
-
s
p
e
e
d
m
o
d
e
)
1
1
:
N
o
t
a
v
a
i
l
a
b
l
e
N
o
t
e
s
R
e
s
e
t
C
M
4
“
1
”
←→
“
0
”
C
M
4
“
0
”
←→
“
1
”
C
M
6
“
1
”
←→
“
0
”
C
M
4
“
1
”
←→
“
0
”
C
M
6
“
1
”
←→
“
0
”
C
M
7
“
1
”
←→
“
0
”C
M
4
“
1
”
←→
“
0
”
C
M
5
“
1
”
←→
“
0
”
CM
6
“1” ←→ “0”
CM
6
“1” ←→ “0”
CPU mode regist er
b7 b
4
C
M
7
“
0
”
←→
“
1
”
C
M
6
“
1
”
←→
“
0
”
(
C
P
U
M
:
a
d
d
r
e
s
s
0
0
3
B
1
6
)
C
M
7
=
0
C
M
6
=
1
C
M
5
=
0
(
8
M
H
z
o
s
c
i
l
l
a
t
i
n
g
)
C
M
4
=
0
(
3
2
k
H
z
s
t
o
p
p
e
d
)
M
i
d
d
l
e
-
s
p
e
e
d
m
o
d
e
(
f
(
φ
)
=
1
M
H
z
)
C
M
7
=
0
C
M
6
=
1
C
M
5
=
0
(
8
M
H
z
o
s
c
i
l
l
a
t
i
n
g
)
C
M
4
=
1
(
3
2
k
H
z
o
s
c
i
l
l
a
t
i
n
g
)
M
i
d
d
l
e
-
s
p
e
e
d
m
o
d
e
(
f
(
φ
)
=
1
M
H
z
)
C
M
7
=
0
C
M
6
=
0
C
M
5
=
0
(
8
M
H
z
o
s
c
i
l
l
a
t
i
n
g
)
C
M
4
=
0
(
3
2
k
H
z
s
t
o
p
p
e
d
)
High-speed mode
(f(
φ
) = 4 MHz)
C
M
7
=
1
C
M
6
=
0
C
M
5
=
0
(
8
M
H
z
o
s
c
i
l
l
a
t
i
n
g
)
C
M
4
=
1
(
3
2
k
H
z
o
s
c
i
l
l
a
t
i
n
g
)
Low-speed mode
(f(
φ
)=16 kHz)
CM
7
= 1
CM
6
= 0
CM
5
= 1 (8 MHz stopped)
CM
4
= 1 (32 kHz oscillating)
L
o
w
-
s
p
e
e
d
m
o
d
e
(
f
(
φ
)
=
1
6
k
H
z
)
CM
7
= 0
CM
6
= 0
CM
5
= 0 (8 MHz oscillating)
CM
4
= 1 (32 kHz oscillating)
High-speed mode
(f(
φ
) = 4 MHz)
1
:
S
w
i
t
c
h
t
h
e
m
o
d
e
b
y
t
h
e
a
l
l
o
w
s
s
h
o
w
n
b
e
t
w
e
e
n
t
h
e
m
o
d
e
b
l
o
c
k
s
.
(
D
o
n
o
t
s
w
i
t
c
h
b
e
t
w
e
e
n
t
h
e
m
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d
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s
d
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c
t
l
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w
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t
h
o
u
t
a
n
a
l
l
o
w
.
)
2
:
T
h
e
a
l
l
m
o
d
e
s
c
a
n
b
e
s
w
i
t
c
h
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d
t
o
t
h
e
s
t
o
p
m
o
d
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o
r
t
h
e
w
a
i
t
m
o
d
e
a
n
d
r
e
t
u
r
n
t
o
t
h
e
s
o
u
r
c
e
m
o
d
e
w
h
e
n
t
h
e
s
t
o
p
m
o
d
e
o
r
t
h
e
w
a
i
t
m
o
d
e
i
s
e
n
d
e
d
.
3
:
T
i
m
e
r
o
p
e
r
a
t
e
s
i
n
t
h
e
w
a
i
t
m
o
d
e
.
4
:
W
h
e
n
b
i
t
0
o
f
M
I
S
R
G
i
s
“
0
”
a
n
d
t
h
e
s
t
o
p
m
o
d
e
i
s
e
n
d
e
d
,
a
d
e
l
a
y
o
f
a
p
p
r
o
x
i
m
a
t
e
l
y
1
m
s
o
c
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49
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Table 15 Summary of M38517F8 (flash memory version)
FLASH MEMORY MODE
The M38517F8 (flash memory version) has an internal new
DINOR (DIvided bit line NOR) flash memory that can be rewritten
with a single power source when VCC is 5 V, and 2 power sources
when VPP is 5 V and VCC is 3.0-5.5 V in the CPU rewrite and stan-
dard serial I/O modes.
For this flash memory, three flash memory modes are available in
which to read, program, and erase: the parallel I/O and standard
serial I/O modes in which the flash memory can be manipulated
using a programmer and the CPU rewrite mode in which the flash
memory can be manipulated by the Central Processing Unit
(CPU).
Summary
Table 15 lists the summary of the M38517F8 (flash memory ver-
sion).
The flash memory of the M38517F8 is divided into User ROM area
and Boot ROM area as shown in Figure 57.
In addition to the ordinary User ROM area to store the MCU op-
eration control program, the flash memory has a Boot ROM area
that is used to store a program to control rewriting in CPU rewrite
and standard serial I/O modes. This Boot ROM area has had a
standard serial I/O mode control program stored in it when
shipped from the factory. However, the user can write a rewrite
control program in this area that suits the user ’s application sys-
tem. This Boot ROM area can be rewritten in only parallel I/O
mode.
Item
Power source voltage
VPP voltage (For Program/Erase)
Flash memory mode
Erase block division User ROM area
Boot ROM area
Program method
Erase method
Program/Erase control method
Number of commands
Number of program/Erase times
ROM code protection
Specifications
Vcc = 2.7– 5.5 V (Note 1)
Vcc = 2.7–3.6 V (Note 2)
4.5-5.5 V
3 modes (Parallel I/O mode, Standard serial I/O mode, CPU rewrite mode)
1 block (32 Kbytes)
1 block (4 Kbytes) (Note 3)
Byte program
Batch erasing
Program/Erase control by software command
6 commands
100 times
Available in parallel I/O mode and standard serial I/O mode
Notes 1: The power source voltage must be Vcc = 4.5–5.5 V at program and erase operation.
2: The power source voltage can be Vcc = 3.0–3.6 V also at program and erase operation.
3: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be
rewritten in only parallel I/O mode.
50
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 57 Block diagram of built-in flash memory
(1) CPU Rewrite Mode
In CPU rewrite mode, the internal flash memory can be operated
on (read, program, or erase) under control of the Central Process-
ing Unit (CPU).
In CPU rewrite mode, only the User ROM area shown in Figure 57
can be rewritten; the Boot ROM area cannot be rewritten. Make
sure the program and block erase commands are issued for only
the User ROM area and each block area.
The control program for CPU rewrite mode can be stored in either
User ROM or Boot ROM area. In the CPU rewrite mode, because
the flash memory cannot be read from the CPU, the rewrite con-
trol program must be transferred to internal RAM area to be
executed before it can be executed.
Microcomputer Mode and Boot Mode
The control program for CPU rewrite mode must be written into
the User ROM or Boot ROM area in parallel I/O mode beforehand.
(If the control program is written into the Boot ROM area, the stan-
dard serial I/O mode becomes unusable.)
See Figure 57 for details about the Boot ROM area.
Normal microcomputer mode is entered when the microcomputer
is reset with pulling CNVSS pin low. In this case, the CPU starts
operating using the control program in the User ROM area.
When the microcomputer is reset by pulling the P41/INT0 pin high,
the CNVss pin high, the CPU starts operating using the control
program in the Boot ROM area (program start address is FFFC16,
FFFD16 fixation). This mode is called the “Boot” mode.
Block Address
Block addresses refer to the maximum address of each block.
These addresses are used in the block erase command. In case
of the M38517F8, it has only one block.
8
0
0
0
1
6
Block 1 : 32 kbyte
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BSEL = 0 BSEL = 1
User ar ea / Boot ar ea sele c tion bit = 0 User ar ea / Boot ar ea sele c tion bit = 1
51
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Outline Performance (CPU Rewrite Mode)
CPU rewrite mode is usable in the single-chip or Boot mode. The
only User ROM area can be rewritten in CPU rewrite mode.
In CPU rewrite mode, the CPU erases, programs and reads the in-
ternal flash memory by executing software commands. This
rewrite control program must be transferred to the RAM before it
can be executed.
The MCU enters CPU rewrite mode by applying 5 V ± 0.5 V to the
CNVSS pin and setting “1” to the CPU Rewrite Mode Select Bit (bit
1 of address 0FFE16). Software commands are accepted once the
mode is entered.
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or
in error can be verified by reading the status register.
Figure 58 shows the flash memory control register.
Bit 0 is the RY/BY status flag used exclusively to read the operat-
ing status of the flash memory. During programming and erase
operations, it is “0” (busy). Otherwise, it is “1” (ready).
Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to
“1”, the MCU enters CPU rewrite mode. Software commands are
accepted once the mode is entered. In CPU rewrite mode, the
CPU becomes unable to access the internal flash memory directly.
Therefore, use the control program in the RAM for write to bit 1. To
set this bit to “1”, it is necessary to write “0” and then write “1” in
succession. The bit can be set to “0” by only writing “0”.
Bit 2 is the CPU Rewrite Mode Entry Flag. This flag indicates “1” in
CPU rewrite mode, so that reading this flag can check whether
CPU rewrite mode has been entered or not.
Bit 3 is the flash memory reset bit used to reset the control circuit
of internal flash memory. This bit is used when exiting CPU rewrite
mode and when flash memory access has failed. When the CPU
Rewrite Mode Select Bit is “1”, setting “1” for this bit resets the
control circuit. To set this bit to “1”, it is necessary to write “0” and
then write “1” in succession. To release the reset, it is necessary
to set this bit to “0”.
Bit 4 is the User Area/Boot Area Select Bit. When this bit is set to
“1”, Boot ROM area is accessed, and CPU rewrite mode in Boot
ROM area is available. In Boot mode, this bit is set to “1” auto-
matically. Reprogramming of this bit must be in the RAM.
Figure 59 shows a flowchart for setting/releasing CPU rewrite
mode.
Fig. 58 Structure of flash memory control register
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RY/BY status flag
0: Busy (being programmed or erased)
1: Ready
CPU rewrite mode select bit (Note 2)
0: Normal mode (Software commands invalid)
1: CPU rewrite mode (Software commands acceptable)
CPU rewrite mode entry flag
0: Normal mode
1: CPU rewrite mode
Flash memory reset bit (Note 3)
0: Normal operation
1: Reset
User ROM area / Boot ROM area select bit
(Note 4)
0: User ROM area accessed
1: Boot ROM area accessed
Reserved bits (Indefinite at read/ “0” at write)
b0b7
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52
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 59 CPU rewrite mode set/release flowchart
End
S
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Using software command execute erase,
program, or other operation
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t
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
(
0
0
3
B1
6)
.
3:
B
e
f
o
r
e
e
x
i
t
i
n
g
t
h
e
C
P
U
r
e
w
r
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t
e
m
o
d
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a
f
t
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r
c
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p
l
e
t
i
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g
e
r
a
s
e
o
r
p
r
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g
r
a
m
o
p
e
r
a
t
i
o
n
,
a
l
w
a
y
s
b
e
s
u
r
e
t
o
e
x
e
c
u
t
e
t
h
e
r
e
a
d
a
r
r
a
y
c
o
m
m
a
n
d
o
r
r
e
s
e
t
t
h
e
f
l
a
s
h
m
e
m
o
r
y
.
W
r
i
t
e
“
0
”
t
o
C
P
U
r
e
w
r
i
t
e
m
o
d
e
s
e
l
e
c
t
b
i
t
S
e
t
C
P
U
r
e
w
r
i
t
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m
o
d
e
s
e
l
e
c
t
b
i
t
t
o
“
1
”
(
b
y
w
r
i
t
i
n
g
“
0
”
a
n
d
t
h
e
n
“
1
”
i
n
s
u
c
c
e
s
s
i
o
n
)
C
h
e
c
k
C
P
U
r
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w
r
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m
o
d
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n
t
r
y
f
l
a
g
S
e
t
t
i
n
g
R
e
l
e
a
s
e
d
53
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting
the flash memory in CPU rewrite mode.
(1) Operation speed
During CPU rewrite mode, set the internal clock frequency 4.0
MHz or less using the main clock division ratio selection bits (bit
6, 7 at 003B16).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode .
(3) Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode be-
cause they refer to the internal data of the flash memory.
(4) Watchdog timer
In case of the watchdog timer has been running already, the in-
ternal reset generated by watchdog timer underflow does not
happen, because of watchdog timer is always clearing during
program or erase operation.
(5) Reset
Reset is always valid. In case of CNVSS = H when reset is re-
leased, boot mode is active. So the program starts from the ad-
dress contained in address FFFC16 and FFFD16 in boot ROM
area.
54
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Software Commands (CPU Rewrite Mode)
Table 16 lists the software commands.
After setting the CPU Rewrite Mode Select Bit of the flash memory
control register to “1”, execute a software command to specify an
erase or program operation.
Each software command is explained below.
●Read Array Command (FF16)
The read array mode is entered by writing the command code
“FF16” in the first bus cycle. When an address to be read is input in
one of the bus cycles that follow, the contents of the specified ad-
dress are read out at the data bus (D0 to D7).
The read array mode is retained intact until another command is
written.
●Read Status Register Command (7016)
The read status register mode is entered by writing the command
code “7016” in the first bus cycle. The contents of the status regis-
ter are read out at the data bus (D0 to D7) by a read in the second
bus cycle.
The status register is explained in the next section.
●Clear Status Register Command (5016)
This command is used to clear the bits SR1, SR4, and SR5 of the
status register after they have been set. These bits indicate that
operation has ended in an error. To use this command, write the
command code “5016” in the first bus cycle.
●Program Command (4016)
Program operation starts when the command code “4016” is writ-
ten in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, program operation (data program-
ming and verification) will start.
Whether the write operation is completed can be confirmed by
_____
reading the status register or the RY/BY Status Flag of the flash
memory control register. When the program starts, the read status
Table 16 List of software commands (CPU rewrite mode)
register mode is entered automatically and the contents of the sta-
tus register is read at the data bus (D0 to D7). The status register
bit 7 (SR7) is set to “0” at the same time the write operation starts
and is returned to “1” upon completion of the write operation. In
this case, the read status register mode remains active until the
next command is written.
____
The RY/BY Status Flag is “0” (busy) during write operation and “1”
(ready) when the write operation is completed as is the status reg-
ister bit 7.
At program end, program results can be checked by reading bit 4
(SR4) of the status register.
Fig. 60 Program flowchart
S
t
a
r
t
Write 40
16
S
t
a
t
u
s
r
e
g
i
s
t
e
r
r
e
a
d
Program completed
(Read array command
“FF
16
” write)
NO
Y
E
S
W
r
i
t
e
a
d
d
r
e
s
s
W
r
i
t
e
d
a
t
a
S
R
4
=
0
?P
r
o
g
r
a
m
e
r
r
o
r
NO
Y
E
S
S
R
7
=
1
?
o
r
R
Y
/
B
Y
=
1
?
Write
Command
P
r
o
g
r
a
m
C
l
e
a
r
s
t
a
t
u
s
r
e
g
i
s
t
e
r
R
e
a
d
a
r
r
a
y
R
e
a
d
s
t
a
t
u
s
r
e
g
i
s
t
e
r
X
X
First bus cycle S
e
c
o
n
d
b
u
s
c
y
c
l
e
F
F
1
6
7
0
1
6
5
0
1
6
4
0
1
6
W
r
i
t
e
W
r
i
t
e
W
r
i
t
e
W
r
i
t
e
XS
R
DR
e
a
d
W
r
i
t
e
E
r
a
s
e
a
l
l
b
l
o
c
k
s2
0
1
6
W
r
i
t
eX2
0
1
6
W
r
i
t
e
(Note 2)
W
A
(Note 3)
W
D
(
N
o
t
e
3
)
B
l
o
c
k
e
r
a
s
e2
0
1
6
W
r
i
t
eD
0
1
6
W
r
i
t
eB
A
(Note 4)
Mode Address Mode A
d
d
r
e
s
sData
(D
0
to D
7
)
(
D
0
t
o
D
7
)
(Note 1)
Notes 1: X denotes a given address in the User ROM area .
2: SRD = Status Register Data
3: WA = Write Address, WD = Write Data
4: BA = Block Address to be erased (Input the maximum address of each block.)
C
y
c
l
e
n
u
m
b
e
r
1
2
1
2
2
2
X
X
X
X
D
a
t
a
55
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
●Erase All Blocks Command (2016/2016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “2016” in the second bus cycle that
follows, the operation of erase all blocks (erase and erase verify)
starts.
Whether the erase all blocks command is terminated can be con-
____
firmed by reading the status register or the RY/BY Status Flag of
flash memory control register. When the erase all blocks operation
starts, the read status register mode is entered automatically and
the contents of the status register can be read out at the data bus
(D0 to D7). The status register bit 7 (SR7) is set to “0” at the same
time the erase operation starts and is returned to “1” upon comple-
tion of the erase operation. In this case, the read status register
mode remains active until another command is written.
____
The RY/BY Status Flag is “0” during erase operation and “1” when
the erase operation is completed as is the status register bit 7
(SR7).
After the erase all blocks end, erase results can be checked by
reading bit 5 (SRS) of the status register. For details, refer to the
section where the status register is detailed.
●Block Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “D016” and the blobk address in the
second bus cycle that follows, the block erase (erase and erase
verify) operation starts for the block address of the flash memory
to be specified.
Whether the block erase operation is completed can be confirmed
____
by reading the status register or the RY/BY Status Flag of flash
memory control register. At the same time the block erase opera-
tion starts, the read status register mode is automatically entered,
so that the contents of the status register can be read out. The
status register bit 7 (SR7) is set to “0” at the same time the block
erase operation starts and is returned to “1” upon completion of
the block erase operation. In this case, the read status register
mode remains active until the read array command (FF16) is writ-
ten. ____
The RY/BY Status Flag is “0” during block erase operation and “1”
when the block erase operation is completed as is the status reg-
ister bit 7.
After the block erase ends, erase results can be checked by read-
ing bit 5 (SRS) of the status register. For details, refer to the
section where the status register is detailed.
Fig. 61 Erase flowchart
W
r
i
t
e
2
0
1
6
20
16
/D0
16
Block address
Erase compl et ed
(Read comand “FF
16
”
write)
N
O
Y
E
S
S
t
a
r
t
Write
S
R
5
=
0
?
E
r
a
s
e
e
r
r
o
r
YES
N
O
2
0
1
6
:
E
r
a
s
e
a
l
l
b
l
o
c
k
s
c
o
m
m
a
n
d
D
0
1
6
:
B
l
o
c
k
e
r
a
s
e
c
o
m
m
a
n
d
SR
7 = 1
?
or
RY/BY = 1 ?
S
t
a
t
u
s
r
e
g
i
s
t
e
r
r
e
a
d
56
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Symbol
Table 17 Definition of each bit in status register (SRD)
Status Register (SRD)
The status register shows the operating status of the flash
memory and whether erase operations and programs ended suc-
cessfully or in error. It can be read in the following ways:
(1) By reading an arbitrary address from the User ROM area after
writing the read status register command (7016)
(2) By reading an arbitrary address from the User ROM area in the
period from when the program starts or erase operation starts
to when the read array command (FF16) is input.
Also, the status register can be cleared by writing the clear status
register command (5016).
After reset, the status register is set to “8016”.
Table 17 shows the status register. Each bit in this register is ex-
plained below.
•Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. This bit is set to “0” (busy) during write or erase operation
and is set to “1” when these operations ends.
After power-on, the sequencer status is set to “1” (ready).
•Erase status (SR5)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
•Program status (SR4)
The program status indicates the operating status of write opera-
tion. When a write error occurs, it is set to “1”.
The program status is set to “0” when it is cleared.
If “1” is written for any of the SR5 and SR4 bits, the program,
erase all blocks, and block erase commands are not accepted.
Before executing these commands, execute the clear status regis-
ter command (5016) and clear the status register.
Also, if any commands are not correct, both SR5 and SR4 are set
to “1”.
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Definition
“1” “0”
Status name
Sequencer status
Reserved
Erase status
Program status
Reserved
Reserved
Reserved
Reserved
Ready
-
Terminated in error
Terminated in error
-
-
-
-
Busy
-
Terminated normally
Terminated normally
-
-
-
-
57
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Full Status Check
By performing full status check, it is possible to know the execu-
tion results of erase and program operations. Figure 62 shows a
Fig. 62 Full status check flowchart and remedial procedure for errors
full status check flowchart and the action to be taken when each
error occurs.
Read status register
SR4 = 1 and
SR5 = 1 ?
N
O
YES
S
R
5
=
0
?
Y
E
S
Er
a
s
e
e
r
r
o
r
N
O
S
R
4
=
0
?
Y
E
S
N
O
Command
sequence error
Program error
E
n
d
(
e
r
a
s
e
,
p
r
o
g
r
a
m
)
E
x
e
c
u
t
e
t
h
e
c
l
e
a
r
s
t
a
t
u
s
r
e
g
i
s
t
e
r
c
o
m
m
a
n
d
(
5
01
6)
t
o
c
l
e
a
r
t
h
e
s
t
a
t
u
s
r
e
g
i
s
t
e
r
.
T
r
y
p
e
r
f
o
r
m
i
n
g
t
h
e
o
p
e
r
a
t
i
o
n
o
n
e
m
o
r
e
t
i
m
e
a
f
t
e
r
c
o
n
f
i
r
m
i
n
g
t
h
a
t
t
h
e
c
o
m
m
a
n
d
i
s
e
n
t
e
r
e
d
c
o
r
r
e
c
t
l
y
.
S
h
o
u
l
d
a
n
e
r
a
s
e
e
r
r
o
r
o
c
c
u
r
,
t
h
e
b
l
o
c
k
i
n
e
r
r
o
r
c
a
n
n
o
t
b
e
u
s
e
d
.
N
o
t
e:
W
h
e
n
o
n
e
o
f
S
R
5
a
n
d
S
R
4
i
s
s
e
t
t
o
“
1
”
,
n
o
n
e
o
f
t
h
e
r
e
a
d
a
r
r
a
y
,
t
h
e
p
r
o
g
r
a
m
,
e
r
a
s
e
a
l
l
b
l
o
c
k
s
,
a
n
d
b
l
o
c
k
e
r
a
s
e
c
o
m
m
a
n
d
s
i
s
a
c
c
e
p
t
e
d
.
E
x
e
c
u
t
e
t
h
e
c
l
e
a
r
s
t
a
t
u
s
r
e
g
i
s
t
e
r
c
o
m
m
a
n
d
(
5
0
1
6
)
b
e
f
o
r
e
e
x
e
c
u
t
i
n
g
t
h
e
s
e
c
o
m
m
a
n
d
s
.
S
h
o
u
l
d
a
p
r
o
g
r
a
m
e
r
r
o
r
o
c
c
u
r
,
t
h
e
b
l
o
c
k
i
n
e
r
r
o
r
c
a
n
n
o
t
b
e
u
s
e
d
.
58
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Functions To Inhibit Rewriting Flash Memory
Version
To prevent the contents of internal flash memory from being read
out or rewritten easily, this MCU incorporates a ROM code protect
function for use in parallel I/O mode and an ID code check func-
tion for use in standard serial I/O mode.
●ROM Code Protect Function (in Parallel I/O Mode)
The ROM code protect function is the function to inhibit reading
out or modifying the contents of internal flash memory by using
the ROM code protect control (address FFDB16) in parallel I/O
mode. Figure 63 shows the ROM code protect control (address
FFDB16). (This address exists in the User ROM area.)
If one or both of the pair of ROM Code Protect Bits is set to “0”,
the ROM code protect is turned on, so that the contents of internal
flash memory are protected against readout and modification. The
ROM code protect is implemented in two levels. If level 2 is se-
lected, the flash memory is protected even against readout by a
shipment inspection LSI tester, etc. When an attempt is made to
select both level 1 and level 2, level 2 is selected by default.
If both of the two ROM Code Protect Reset Bits are set to “00”, the
ROM code protect is turned off, so that the contents of internal
flash memory can be read out or modified. Once the ROM code
protect is turned on, the contents of the ROM Code Protect Reset
Bits cannot be modified in parallel I/O mode. Use the serial I/O or
CPU rewrite mode to rewrite the contents of the ROM Code Pro-
tect Reset Bits.
Fig. 63 Structure of ROM code protect control
R
O
M
c
o
d
e
p
r
o
t
e
c
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
a
d
d
r
e
s
s
F
F
D
B
1
6
)
(N
o
t
e
1)
R
O
M
C
P
Reserved bits (“1” at read/write)
ROM code protect level 2 set bits (ROMCP2) (Notes 2, 3)
b3b2
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
ROM code protect reset bits (Note 4)
b5b4
0 0: Protect removed
0 1: Protect set bits effective
1 0: Protect set bits effective
1 1: Protect set bits effective
ROM code protect level 1 set bits (ROMCP1) (Note 2)
b7b6
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
b
0b
7
Notes 1: This area is on the ROM in the mask ROM version.
2: When ROM code protect is turned on, the internal flash memory is protected
against readout or modification in parallel I/O mode.
3: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
4: The ROM code protect reset bits can be used to turn off ROM code protect level 1
and ROM code protect level 2. However, since these bits cannot be modified in
parallel I/O mode, they need to be rewritten in standard serial I/O mode or CPU
rewrite mode.
11
59
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
ID Code Check Function (in Standard serial
I/O mode)
Use this function in standard serial I/O mode. When the contents
of the flash memory are not blank, the ID code sent from the pro-
grammer is compared with the ID code written in the flash memory
to see if they match. If the ID codes do not match, the commands
sent from the programmer are not accepted. The ID code consists
of 8-bit data, and its areas are FFD416 to FFDA16. Write a pro-
gram which has had the ID code preset at these addresses to the
flash memory.
Fig. 64 ID code store addresses
ROM code protect control
ID7
ID6
I
D
5
I
D
4
ID3
ID2
I
D
1
FFDB16
FFDA16
FFD916
F
F
D
81
6
F
F
D
71
6
F
F
D
61
6
F
F
D
51
6
F
F
D
41
6
A
d
d
r
e
s
s
I
n
t
e
r
r
u
p
t
v
e
c
t
o
r
a
r
e
a
60
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
(2) Parallel I/O Mode
Parallel I/O mode is the mode which parallel output and input soft-
ware command, address, and data required for the operations
(read, program, erase, etc.) to a built-in flash memory. Use the ex-
clusive external equipment flash programmer which supports the
3851 Group (flash memory version). Refer to each programmer
maker’s handling manual for the details of the usage.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in
Figure 57 can be rewritten. Both areas of flash memory can be oper-
ated on in the same way.
Program and block erase operations can be performed in the user ROM
area. The user ROM area and its block is shown in Figure 57.
The boot ROM area is 4 Kbytes in size. It is located at addresses
F00016 through FFFF16. Make sure program and block erase opera-
tions are always performed within this address range. (Access to any
location outside this address range is prohibited.)
In the Boot ROM area, an erase block operation is applied to only
one 4 Kbyte block. The boot ROM area has had a standard serial I/O
mode control program stored in it when shipped from the Mitsubishi
factory. Therefore, using the device in standard serial I/O mode, you
do not need to write to the boot ROM area.
61
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
(3) Standard serial I/O Mode
The standard serial I/O mode inputs and outputs the software
commands, addresses and data needed to operate (read, pro-
gram, erase, etc.) the internal flash memory. This I/O is clock
synchronized serial. This mode requires the exclusive external
equipment (serial programmer).
The standard serial I/O mode is different from the parallel I/O
mode in that the CPU controls flash memory rewrite (uses the
CPU rewrite mode), rewrite data input and so forth. The standard
serial I/O mode is started by connecting “H” to the P26 (SCLK) pin
and “H” to the P41 (INT0) pin and “H” to the CNVSS pin (apply 4.5
V to 5.5 V to Vpp from an external source), and releasing the re-
set operation. (In the ordinary microcomputer mode, set CNVss
pin to “L” level.)
This control program is written in the Boot ROM area when the
product is shipped from Mitsubishi. Accordingly, make note of the
fact that the standard serial I/O mode cannot be used if the Boot
ROM area is rewritten in parallel I/O mode. Figure 65 shows the
pin connection for the standard serial I/O mode.
In standard serial I/O mode, serial data I/O uses the four serial I/O
pins SCLK1, RxD, TxD and SRDY1 (BUSY). The SCLK1 pin is the
transfer clock input pin through which an external transfer clock is
input. The TxD pin is for CMOS output. The SRDY1 (BUSY) pin
outputs “L” level when ready for reception and “H” level when re-
ception starts.
Serial data I/O is transferred serially in 8-bit units.
In standard serial I/O mode, only the User ROM area shown in
Figure 44 can be rewritten. The Boot ROM area cannot.
In standard serial I/O mode, a 7-byte ID code is used. When there
is data in the flash memory, commands sent from the peripheral
unit (programmer) are not accepted unless the ID code matches.
Outline Performance (Standard Serial I/O
Mode)
In standard serial I/O mode, software commands, addresses and
data are input and output between the MCU and peripheral units
(serial programmer, etc.) using 4-wire clock-synchronized serial
I/O (serial I/O1).
In reception, software commands, addresses and program data
are synchronized with the rise of the transfer clock that is input to
the SCLK pin, and are then input to the MCU via the RxD pin. In
transmission, the read data and status are synchronized with the
fall of the transfer clock, and output from the TxD pin.
The TxD pin is for CMOS output. Transfer is in 8-bit units with LSB
first.
When busy, such as during transmission, reception, erasing or
program execution, the SRDY1 (BUSY) pin is “H” level. Accord-
ingly, always start the next transfer after the SRDY1 (BUSY) pin is
“L” level.
Also, data and status registers in a memory can be read after in-
putting software commands. Status, such as the operating state of
the flash memory or whether a program or erase operation ended
successfully or not, can be checked by reading the status register.
Here following explains software commands, status registers, etc.
62
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Table 18 Description of pin function (Standard Serial I/O Mode)
Pin D
e
s
c
r
i
p
t
i
o
n
VC
C,
VS
SA
p
p
l
y
p
r
o
g
r
a
m
/
e
r
a
s
e
p
r
o
t
e
c
t
i
o
n
v
o
l
t
a
g
e
t
o
V
c
c
p
i
n
a
n
d
0
V
t
o
V
s
s
p
i
n
.
C
N
VS
SC
o
n
n
e
c
t
t
o
VC
C
w
h
e
n
VC
C
=
4
.
5
V
t
o
5
.
5
V
.
C
o
n
n
e
c
t
t
o
V
p
p
(
=
4
.
5
V
t
o
5
.
5
V
)
w
h
e
n
VC
C
=
2
.
7
V
t
o
4
.
5
V
.
R
E
S
E
TR
e
s
e
t
i
n
p
u
t
p
i
n
.
W
h
i
l
e
r
e
s
e
t
i
s
“
L
”
l
e
v
e
l
,
a
2
0
c
y
c
l
e
o
r
l
o
n
g
e
r
c
l
o
c
k
m
u
s
t
b
e
i
n
p
u
t
t
o
XI
N
p
i
n
.
XI
NC
o
n
n
e
c
t
a
c
e
r
a
m
i
c
r
e
s
o
n
a
t
o
r
o
r
c
r
y
s
t
a
l
o
s
c
i
l
l
a
t
o
r
b
e
t
w
e
e
n
XI
N
a
n
d
XO
U
T
p
i
n
s
.
T
o
i
n
p
u
t
a
n
e
x
t
e
r
n
a
l
l
y
g
e
n
e
r
a
t
e
d
c
l
o
c
k
,
i
n
p
u
t
i
t
t
o
XI
N
p
i
n
a
n
d
o
p
e
n
XO
U
T
p
i
n
.
XO
U
T
N
a
m
e
P
o
w
e
r
i
n
p
u
t
C
N
VS
S
R
e
s
e
t
i
n
p
u
t
C
l
o
c
k
i
n
p
u
t
C
l
o
c
k
o
u
t
p
u
t
I
/
O
I
I
I
O
A
VS
S
VR
E
F
Connect AVSS to VSS .
Enter the reference voltage for AD from this pin, or open.
P00 to P07Input “H” or “L”, or open.
P10 to P17Input “H” or “L”, or open.
P20 to P23
This pin is for serial data input.
A
n
a
l
o
g
p
o
w
e
r
s
u
p
p
l
y
i
n
p
u
t
R
e
f
e
r
e
n
c
e
v
o
l
t
a
g
e
i
n
p
u
t
Input port P0
Input port P1
Input port P2
I
I
I
I
P
41Input “H” when RESET is released only.
P40, P42 to P44
P
24
This pin is for serial data output.
P25
P26This pin is for serial clock input.
P27
I
n
p
u
t
p
o
r
t
P
4
I
n
p
u
t
p
o
r
t
P
4
R
x
D
i
n
p
u
t
T xD output
S
CLK
input
BUSY output
I
I
I
I
P
30
t
o
P
34In
p
u
t
p
o
r
t
P
3I
O
O
Input “H” or “L”, or open.
This pin is for BUSY signal output.
Input “H” or “L”, or open.
Input “H” or “L”, or open.
63
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 65 Pin connection diagram in standard serial I/O mode
P4
0
/CNTR
1
P
4
1
/
I
N
T
0
P
4
2
/
I
N
T
1
P
4
3
/
I
N
T
2
/
S
C
M
P
2
A
V
S
S
P
4
4
/
I
N
T
3
/
P
W
M
V
R
E
F
P
3
1
/
A
N
1
P
3
2
/
A
N
2
P
00/
S
I
N
2
P
0
4
P
0
5
P
0
6
P0
7
P
1
1
/
(
L
E
D
1
)
P
1
2
/
(
L
E
D
2
)
P
1
3
/
(
L
E
D
3
)
P
1
4
/
(
L
E
D
4
)
P1
5
/(LED
5
)
P
1
0
/
(
L
E
D
0
)
P
0
1
/
S
O
U
T
2
P
0
2
/
S
C
L
K
2
P
3
0
/
A
N
0
P
3
3
/
A
N
3
P
3
4
/
A
N
4
40
41
42
22
23
24
25
26
27
28
29
30
31
32
34
35
36
37
38
39
33
3
2
1
2
1
20
1
9
1
8
1
7
1
6
1
5
14
1
3
1
2
1
1
9
8
7
6
5
4
1
0
M
3
8
5
1
7
F
8
S
P
/
F
P
P
1
6
/
(
L
E
D
6
)
P
1
7
/
(
L
E
D
7
)
P
2
7
/
C
N
T
R
0
/
S
R
D
Y
1
P
2
6
/
S
C
L
K
P
2
5
/
T
x
D
P
2
4
/
R
x
D
C
N
V
S
S
P
2
1
/
X
C
I
N
P
2
0
/
X
C
O
U
T
RESET
X
IN
X
OUT
V
S
S
P
0
3
/
S
R
D
Y
2
P4
1
S
C
L
K
✽ 1
P2
3
/SCL
1
P
2
2
/
S
D
A
1
V
CC
V
SS
V
CC
RESET
V
P
P
✽ 2
R
X
D
T
x
D
R
x
D
B
U
S
Y
Not es 1: Connect oscillator circuit
2: Connect to Vcc when Vcc = 4.5 V to 5. 5 V .
Connect to V
PP
(=4.5 V to 5.5 V) when Vcc = 2.7 V to 4.5 V.
3: It is necessary to apply Vcc only when reset is released.
Signal Value
C
N
V
S
S
R
E
S
E
T
M
o
d
e
s
e
t
u
p
m
e
t
h
o
d
4.5 to 5. 5 V
V
SS
→ V
CC
S
C
L
K
V
C
C
✽ 3
P
4
1
V
C
C
✽ 3
64
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Software Commands (Standard Serial I/O
Mode)
Table 19 lists software commands. In standard serial I/O mode,
erase, program and read are controlled by transferring software
2nd byte
Address
(middle)
3rd byte
Address
(high)
4th byte
Data
output
5th byte
Data
output
6th byte
Data
output
.....
Data
output to
259th byte
Data input
to 259th
byte
FF16
When ID is
not verified
1st byte
transfer
Notes1: Shading indicates transfer from the internal flash memory microcomputer to a programmer. All other data is transferred from an external equipment
(programmer) to the internal flash memory microcomputer.
2: SRD refers to status register data. SRD1 refers to status register 1 data.
3: All commands can be accepted when the flash memory is totally blank.
4: Address high must be “0016”.
commands via the RxD pin. Software commands are explained
here below.
Table 19 Software commands (Standard serial I/O mode)
1 Page read
4116 Address
(middle) Address
(high) Data
input Data
input Data
input Not
acceptable
Not
acceptable
A716 D016
7016 SRD
output SRD1
output Acceptable
5016 Not
acceptable
F516 Address
(low) Address
(middle) Address
(high) ID size ID1 To ID7 Acceptable
FA16 Data
input
To
required
number
of times
Not
acceptable
FB16 Version
data
output
Version
data
output
Version
data
output
Version
data
output
Version
data
output
Version
data output
to 9th byte
Control command
2 Page program
3 Erase all blocks
4 Read status register
5 Clear status register
6 ID code check
7 Download function
8 Version data output function
Size
(low) Size
(high) Check-
sum
Acceptable
Not
acceptable
65
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
●Read Status Register Command
This command reads status information. When the “7016” com-
mand code is transferred with the 1st byte, the contents of the
status register (SRD) with the 2nd byte and the contents of status
register 1 (SRD1) with the 3rd byte are read.
●Page Read Command
This command reads the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page read
command as explained here following.
(1) T ransfer the “FF16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and
3rd bytes respectively.
(3) From the 4th byte onward, data (D0 to D7) for the page (256
bytes) specified with addresses A8 to A23 will be output se-
quentially from the smallest address first synchronized with the
fall of the clock.
Fig. 66 Timing for page read
Fig. 67 Timing for reading status register
data0 data255
A8
t
o
A1
5A1
6
t
o
A2
3
F
F1
6
SC
L
K
R
x
D
T
x
D
SR
D
Y
1(
B
U
S
Y
)
S
R
D
o
u
t
p
u
tS
R
D
1
o
u
t
p
u
t
S
C
L
K
R
x
D
T
x
D
S
R
D
Y
1
(
B
U
S
Y
)
7
0
1
6
66
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 68 Timing for clear status register
●Clear Status Register Command
This command clears the bits (SR4, SR5) which are set when the
status register operation ends in error. When the “5016” command
code is sent with the 1st byte, the aforementioned bits are
cleared. When the clear status register operation ends, the SRDY1
(BUSY) signal changes from “H” to “L” level.
●Page Program Command
This command writes the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page pro-
gram command as explained here following.
(1) T ransfer the “4116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 (“0016”) with the
2nd and 3rd bytes respectively.
(3) From the 4th byte onward, as write data (D0 to D7) for the
page (256 bytes) specified with addresses A8 to A23 is input
sequentially from the smallest address first, that page is auto-
matically written.
When reception setup for the next 256 bytes ends, the SRDY1
(BUSY) signal changes from “H” to “L” level. The result of the
page program can be known by reading the status register. For
more information, see the section on the status register.
Fig. 69 Timing for page program
SC
L
K
R
x
D
T
x
D
SR
D
Y
1(
B
U
S
Y
)
5016
A
8
t
o
A
1
5
A
1
6
t
o
A
2
3
4
1
1
6
d
a
t
a
0d
a
t
a
2
5
5
S
C
L
K
R
x
D
T
x
D
S
R
D
Y
1
(
B
U
S
Y
)
67
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
●Erase All Blocks Command
This command erases the contents of all blocks. Execute the
erase all blocks command as explained here following.
(1) T ransfer the “A716” command code with the 1st byte.
(2) Transfer the verify command code “D016” with the 2nd byte.
With the verify command code, the erase operation will start
and continue for all blocks in the flash memory.
When erase all blocks end, the SRDY1 (BUSY) signal changes
from “H” to “L” level. The result of the erase operation can be
known by reading the status register.
Fig. 70 Timing for erase all blocks
A7
16
D
0
1
6
S
C
L
K
R
x
D
T
x
D
S
R
D
Y
1
(
B
U
S
Y
)
68
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
●Download Command
This command downloads a program to the RAM for execution.
Execute the download command as explained here following.
(1) Transfer the “FA16” command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is
added to all data sent with the 5th byte onward.
(4) The program to execute is sent with the 5th byte onward.
When all data has been transmitted, if the check sum matches,
the downloaded program is executed. The size of the program will
vary according to the internal RAM.
Fig. 71 Timing for download
FA
16
Program
data
P
r
o
g
r
a
m
d
a
t
a
D
a
t
a
s
i
z
e
(
l
o
w
)C
h
e
c
k
s
u
m
S
C
L
K
R
x
D
T
x
D
S
R
D
Y
1
(
B
U
S
Y
)
D
a
t
a
s
i
z
e
(
h
i
g
h
)
69
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
●Version Information Output Command
This command outputs the version information of the control pro-
gram stored in the Boot ROM area. Execute the version
information output command as explained here following.
(1) T ransfer the “FB16” command code with the 1st byte.
(2) The version information will be output from the 2nd byte on-
ward. This data is composed of 8 ASCII code characters.
Fig. 72 Timing for version information output
F
B1
6
‘
X
’
‘V
’‘E’‘
R
’
SC
L
K
R
x
D
T
x
D
SR
D
Y
1(
B
U
S
Y
)
70
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
●ID Check
This command checks the ID code. Execute the boot ID check
command as explained here following.
●ID Code
When the flash memory is not blank, the ID code sent from the se-
rial programmer and the ID code written in the flash memory are
compared to see if they match. If the codes do not match, the
command sent from the serial programmer is not accepted. An ID
code contains 8 bits of data. Area is, from the 1st byte, addresses
FFD416 to FFDA16. Write a program into the flash memory, which
already has the ID code set for these addresses.
Fig. 73 Timing for ID check
Fig. 74 ID code storage addresses
(1) Transfer the “F516” command code with the 1st byte.
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 (“0016”)
of the 1st byte of the ID code with the 2nd, 3rd, and 4th bytes
respectively.
(3) Transfer the number of data sets of the ID code with the 5th
byte.
(4) Transfer the ID code with the 6th byte onward, starting with the
1st byte of the code.
I
D
s
i
z
e I
D
1 I
D
7
F
5
1
6
D
4
1
6
F
F
1
6
0
0
1
6
S
C
L
K
R
x
D
T
x
D
S
R
D
Y
1
(
B
U
S
Y
)
R
O
M
c
o
d
e
p
r
o
t
e
c
t
c
o
n
t
r
o
l
ID7
I
D
6
I
D
5
I
D
4
ID3
ID2
I
D
1
FFDB
16
FFDA
16
FFD9
16
F
F
D
8
1
6
F
F
D
7
1
6
F
F
D
6
1
6
F
F
D
5
1
6
F
F
D
4
1
6
Address
I
n
t
e
r
r
u
p
t
v
e
c
t
o
r
a
r
e
a
71
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
●Status Register (SRD)
The status register indicates operating status of the flash memory
and status such as whether an erase operation or a program
ended successfully or in error. It can be read by writing the read
status register command (7016). Also, the status register is
cleared by writing the clear status register command (5016).
Table 20 lists the definition of each status register bit. After releas-
ing the reset, the status register becomes “8016”.
•Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory.
After power-on and recover from deep power down mode, the se-
quencer status is set to “1” (ready).
This status bit is set to “0” (busy) during write or erase operation
and is set to “1” upon completion of these operations.
•Erase status (SR5)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
•Program status (SR4)
The program status indicates the operating status of write opera-
tion. If a program error occurs, it is set to “1”. When the program
status is cleared, it is set to “0”.
SRD0 bits
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Definition
“1”“0”
Table 20 Definition of each bit of status register (SRD)
Status name
Sequencer status
Reserved
Erase status
Program status
Reserved
Reserved
Reserved
Reserved
Ready
-
Terminated in error
Terminated in error
-
-
-
-
Busy
-
Terminated normally
Terminated normally
-
-
-
-
72
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
●Status Register 1 (SRD1)
The status register 1 indicates the status of serial communica-
tions, results from ID checks and results from check sum
comparisons. It can be read after the status register (SRD) by writ-
ing the read status register command (7016). Also, status register
1 is cleared by writing the clear status register command (5016).
Table 21 lists the definition of each status register 1 bit. This regis-
ter becomes “0016” when power is turned on and the flag status is
maintained even after the reset.
Table 21 Definition of each bit of status register 1 (SRD1)
00 Not verified
01 Verification mismatch
10 Reserved
11 Verified
SR15 (bit7)
SR14 (bit6)
SR13 (bit5)
SR12 (bit4)
SR11 (bit3)
SR10 (bit2)
SR9 (bit1)
SR8 (bit0)
Boot update completed bit
Reserved
Reserved
Checksum match bit
ID check completed bits
Data reception time out
Reserved
“1”
Update completed
-
-
Match
Time out
-
“0”
Not Update
-
-
Mismatch
Normal operation
-
Definition
SRD1 bits Status name
•Boot update completed bit (SR15)
This flag indicates whether the control program was downloaded
to the RAM or not, using the download function.
•Check sum consistency bit (SR12)
This flag indicates whether the check sum matches or not when a
program, is downloaded for execution using the download func-
tion.
•ID check completed bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands
cannot be accepted without an ID code check.
•Data reception time out (SR9)
This flag indicates when a time out error is generated during data
reception. If this flag is attached during data reception, the re-
ceived data is discarded and the MCU returns to the command
wait state.
73
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Full Status Check
Results from executed erase and program operations can be
known by running a full status check. Figure 75 shows a flowchart
of the full status check and explains how to remedy errors which
occur.
Fig. 75 Full status check flowchart and remedial procedure for errors
Read status register
S
R
4
=
1
a
n
d
S
R5
=
1
?
NO
Y
E
S
SR5 = 0 ?
Y
E
S
Er
a
s
e
e
r
r
o
r
NO
SR4 = 0 ?
Y
E
S
N
O
Command
sequence error
Program error
End (Erase, program)
E
x
e
c
u
t
e
t
h
e
c
l
e
a
r
s
t
a
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e
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m
a
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d
(
5
0
1
6
)
t
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.
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.
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k
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r
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n
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t
b
e
u
s
e
d
.
Note: When one of SR5 to SR4 is set to “1” , none of the program, erase all blocks
commands is accepted. Execute the clear status register command (5016) before
executing these commands.
S
h
o
u
l
d
a
p
r
o
g
r
a
m
e
r
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o
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a
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t
b
e
u
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e
d
.
74
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Example Circuit Application for Standard
Serial I/O Mode
Figure 76 shows a circuit application for the standard serial I/O
mode. Control pins will vary according to a programmer, therefore
see a programmer manual for more information.
Fig. 76 Example circuit application for standard serial I/O mode
S
RDY1
(BUSY)
S
C
L
K
R
X
D
T
X
D
CNVss
C
l
o
c
k
i
n
p
u
t
B
U
S
Y
o
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t
p
u
t
D
a
t
a
i
n
p
u
t
D
a
t
a
o
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t
p
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t
M
3
8
5
1
7
F
8
Notes 1: Control pins and exter nal circuit r y will vary ac c or ding to peripheral unit. For m or e
info r m ation, see t he peripher al unit manual.
2: In th is ex am ple, the Vp p power supply is supplied from an external source (wr iter) . T o use
the user’s pow er sour c e, connec t to 4.5 V to 5.5 V.
3: It is necessary to apply Vcc t o S CLK pin only when reset is released.
V
P
P
p
o
w
e
r
s
o
u
r
c
e
i
n
p
u
t
P
4
1
75
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Table 23 Flash memory mode Electrical characteristics
(Ta = 25oC, VCC = 4.5 to 5.5V unless otherwise noted)
Flash memory Electrical characteristics
Limits
Parameter Min. Typ. Max.
Symbol Unit
Conditions
IPP1
IPP2
IPP3
VPP
VCC
4.5
Table 22 Absolute maximum ratings
Power source voltage
Input voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
VREF
Input voltage P22, P23
Input voltage RESET, XIN
Input voltage CNVSS
Output voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
XOUT
Output voltage P22, P23
Power dissipation
Operating temperature
Storage temperature
VCC
VI
VI
VI
VI
VO
VO
Pd
Topr
Tstg
Symbol Parameter Conditions Ratings
–0.3 to 6.5
–0.3 to VCC +0.3
–0.3 to 5.8
–0.3 to VCC +0.3
–0.3 to 6.5
–0.3 to VCC +0.3
–0.3 to 5.8
1000 (Note)
25±5
–40 to 125
V
V
V
V
V
V
V
mW
°C
°C
Unit
Ta = 25 °C
All voltages are based on VSS.
Output transistors are cut off.
Note: The rating becomes 300 mW at the 42P2R-A/E package.
4.5
3.0
5.5
3.6
V
V
VPP power source current (read)
VPP power source current (program)
VPP power source current (erase)
VPP power source voltage
VCC power source voltage
100
60
30
5.5
µA
mA
mA
V
VPP = VCC
VPP = VCC
VPP = VCC
Microcomputer mode operation at
VCC = 2.7 to 5.5V
Microcomputer mode operation at
VCC = 2.7 to 3.6V
76
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” Af-
ter a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before perform-
ing a BBC or BBS instruction.
Decimal Calculations
•To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
•In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Multiplication and Division Instructions
•The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
•The execution of these instructions does not change the con-
tents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
•The data transfer instruction (LDA, etc.)
•The operation instruction when the index X mode flag (T) is “1”
•The addressing mode which uses the value of a direction regis-
ter as an index
•The bit-test instruction (BBC or BBS, etc.) to a direction register
•The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial I/O
In serial I/O1 (clock synchronous mode), if the receive side is us-
ing an external clock and it is to output the SRDY1 signal, set the
transmit enable bit, the receive enable bit, and the SRDY1 output
enable bit to “1.”
Serial I/O1 continues to output the final bit from the TXD pin after
transmission is completed.
SOUT2 pin for serial I/O2 goes to high impedance after transmis-
sion is completed.
When an external clock is used as synchronous clock in serial
I/O1 or serial I/O2, write transmission data to the transmit buffer
register or serial I/O2 register while the transfer clock is “H.”
A-D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) in the middle/high-speed mode is
at least on 500 kHz during an A-D conversion.
Do not execute the STP instruction during an A-D conversion.
Instruction Execution Time
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency of the internal clock φ is half of the XIN frequency in
high-speed mode.
NOTES ON USAGE
Differences between 3851 group (built-in 16
KB ROM) and 3851 group (built-in 24 KB or
more ROM)
(1) The absolute maximum ratings of 3851 group (built-in 24 KB or
more ROM) is smaller than that of 3851 group (built-in 16 KB
ROM).
•Power source voltage Vcc = –0.3 to 6.5 V
•CNVss input voltage
VI = –0.3 to Vcc +0.3 V (M38514M6, M38517M8)
VI = –0.3 to 6.5 V (M38517F8)
(2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may
be some differences between 3851 group (built-in 16 KB
ROM) and 3851 group (built-in 24 KB or more ROM).
(3) Do not write any data to the reserved area and the reserved
bit. (Do not change the contents after rest.)
(4) Fix bit 3 of the CPU mode register to “1”.
(5) Be sure to perform the termination of unused pins.
Handling of Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suit-
able for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (VSS pin) and between power
source pin (VCC pin) and analog power source input pin (AVSS
pin). Besides, connect the capacitor to as close as possible. For
bypass capacitor which should not be located too far from the pins
to be connected, a ceramic capacitor of 0.01 µF–0.1µF is recom-
mended.
EPROM Version/One Time PROM Version/
Flash Memory Version
The CNVss pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss
pin and Vss pin or Vcc pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVss pin has no operational in-
terference even if it is connected to Vss pin or Vcc pin via a
resistor.
77
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Electric Characteristic Differences Among
Mask ROM, Flash Memory, and One Time
PROM Version MCUs
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation among mask ROM, flash
memory, and One Time PROM version MCUs due to the differ-
ences in the manufacturing processes.
When manufacturing an application system with the flash memory,
One Time PROM version and then switching to use of the mask
ROM version, perform sufficient evaluations for the commercial
samples of the mask ROM version.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
1. Mask ROM Order Confirmation Form✽
2. Mark Specification Form✽
3. Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk.
DATA REQUIRED FOR One Time PROM
PROGRAMMING ORDERS
The following are necessary when ordering a PROM programming
service:
1. ROM Programming Confirmation Form✽
2. Mark Specification Form✽ (only special mark with customer ’s
trade mark logo)
3. Data to be programmed to PROM, in EPROM form (three iden-
tical copies) or one floppy disk.
✽For the mask ROM confirmation and the mark specifications, re-
fer to the “Mitsubishi MCU Technical Information” Homepage
(http://www.infomicom.maec.co.jp/indexe.htm).
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and buit-
in EPROM version can be read or programmed with a
general-purpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
Table 20 Programming adapter
Package
42P4B, 42S1B
42P2R-A/E
Name of Programming Adapter
PCA4738S-42A
PCA4738F-42A
The PROM of the blank One Ti me PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 77 is recommended to verify programming.
Fig. 77 Programming and testing of One Time PROM version
Programming wit h PROM
programmer
S
c
r
e
e
n
i
n
g
(
C
a
u
t
i
o
n
)
(
1
5
0
°
C
f
o
r
4
0
h
o
u
r
s
)
Verification with
PROM programmer
F
u
n
c
t
i
o
n
a
l
c
h
e
c
k
i
n
t
a
r
g
e
t
d
e
v
i
c
e
T
h
e
s
c
r
e
e
n
i
n
g
t
e
m
p
e
r
a
t
u
r
e
i
s
f
a
r
h
i
g
h
e
r
t
h
a
n
t
h
e
s
t
o
r
a
g
e
t
e
m
p
e
r
a
t
u
r
e
.
N
e
v
e
r
e
x
p
o
s
e
t
o
1
5
0
°
C
e
x
c
e
e
d
i
n
g
1
0
0
h
o
u
r
s
.
Caution :
78
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Electrical characteristics
Absolute maximum ratings
Table 25 Absolute maximum ratings
Power source voltage
Input voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
VREF
Input voltage P22, P23
Input voltage RESET, XIN
Input voltage CNVSS
M38514M6, M38514M8
M38514E6
M38517F8
Output voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
XOUT
Output voltage P22, P23
Power dissipation
Operating temperature
Storage temperature
VCC
VI
VI
VI
VI
VO
VO
Pd
Topr
Tstg
Symbol Parameter Conditions Ratings
–0.3 to 6.5
–0.3 to VCC +0.3
–0.3 to 5.8
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to 13
–0.3 to 6.5
–0.3 to VCC +0.3
–0.3 to 5.8
1000 (Note)
–20 to 85
–40 to 125
V
V
V
V
V
V
V
V
V
mW
°C
°C
Unit
Ta = 25 °C
All voltages are based on VSS.
Output transistors are cut off.
Note : The rating becomes 300mW at the 42P2R-A/E package.
79
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Table 26 Recommended operating conditions (1)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Recommended operating conditions
VCC
VSS
VREF
AVSS
VIA
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
5.5
5.5
VCC
VCC
VCC
VCC
5.8
VCC
5.8
VCC
0.2VCC
0.3VCC
0.6
0.2VCC
0.16VCC
–80
–80
80
120
80
–40
–40
40
60
40
Power source voltage
Power source voltage
A-D convert reference voltage
Analog power source voltage
Analog input voltage AN0–AN4
“H” input voltage P00–P07, P10–P17, P20–P27, P30–P34, P40–P44
“H” input voltage (when I2C-BUS input level is selected)
SDA2, SCL2
“H” input voltage (when SMBUS input level is selected)
SDA2, SCL2
“H” input voltage RESET, XIN, CNVSS
“L” input voltage P00–P07, P10–P17, P20–P27, P30–P34, P40–P44
“L” input voltage (when I2C-BUS input level is selected) SDA1, SDA2, SCL1, SCL2
“L” input voltage (when SMBUS input level is selected) SDA1, SDA2, SCL1, SCL2
“L” input voltage RESET, CNVSS
“L” input voltage XIN
“H” total peak output current (Note) P00–P07, P10–P17, P30–P34
“H” total peak output current (Note) P20, P21, P24–P27, P40–P44
“L” total peak output current (Note) P00–P07, P30–P34
“L” total peak output current (Note) P10–P17
“L” total peak output current (Note) P20–P27,P40–P44
“H” total average output current (Note) P00–P07, P10–P17, P30–P34
“H” total average output current (Note) P20, P21, P24–P27, P40–P44
“L” total average output current (Note) P00–P07, P30–P34
“L” total average output current (Note) P10–P17
“L” total average output current (Note) P20–P27,P40–P44
Symbol Parameter Limits
Min. Unit
4.0
2.7
2.0
AVSS
0.8VCC
0.7VCC
0.7VCC
1.4
1.4
0.8VCC
0
0
0
0
0
5.0
5.0
0
0
Typ. Max.
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
8 MHz (high-speed mode)
8 MHz (middle-speed mode), 4 MHz (high-speed mode)
SDA1, SCL1
SDA1, SCL1
80
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Table 27 Recommended operating conditions (2)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
–10
10
20
–5
5
15
8
4
“H” peak output current P00–P07, P10–P17, P20, P21, P24–P27, P30–P34,
P40–P44 (Note 1)
“L” peak output current (Note 1) P00–P07, P20–P27, P30–P34, P40–P44
P10–P17
“H” average output current P00–P07, P10–P17, P20, P21, P24–P27, P30–P34,
P40–P44 (Note 2)
“L” average output current
(Note 2)
P00–P07, P20–P27, P30–P34, P40–P44
P10–P17
Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 3)
Internal clock oscillation frequency (VCC = 2.7 to 5.5V) (Note 3)
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
f(XIN)
f(XIN)
Symbol Parameter Limits
Min.
mA
mA
mA
mA
mA
mA
MHz
MHz
Unit
Typ. Max.
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50%.
Table 28 Electrical characteristics (1)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Electrical characteristics
“H” output voltage
P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44
(Note)
“L” output voltage
P00–P07, P20–P27,P30–P34,
P40–P44
“L” output voltage
P10–P17
Limits
V
V
V
V
V
V
Parameter Min. Typ. Max.
Symbol Unit
Note: P25 is measured when the P25/SCL2/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
IOH = –10 mA
VCC = 4.0–5.5 V
IOH = –1.0 mA
VCC = 2.7–5.5 V
IOL = 10 mA
VCC = 4.0–5.5 V
IOL = 1.0 mA
VCC = 2.7–5.5 V
IOL = 20 mA
VCC = 4.0–5.5 V
IOL = 10 mA
VCC = 2.7–5.5 V
VCC–2.0
VCC–1.0
Test conditions
2.0
1.0
2.0
1.0
VOH
VOL
VOL
81
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
VT+–VT–
VT+–VT–
VT+–VT–
IIH
IIH
IIH
IIL
IIL
IIL
VRAM
Hysteresis
CNTR0, CNTR1, INT0–INT3
Hysteresis
RxD, S
CLK
Hysteresis ____________
RESET
“H” input current
P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44
“H” input current ____________
RESET, CNVSS
“H” input current XIN
“L” input current
P00–P07, P10–P17, P20–P27
P30–P34, P40–P44
“L” input current ____________
RESET,CNVSS
“L” input current XIN
RAM hold voltage
VI = VCC
VI = VCC
VI = VCC
VI = VSS
VI = VSS
VI = VSS
When clock stopped
0.4
0.5
0.5
4
–4
2.0
5.0
5.0
–5.0
–5.0
5.5
V
V
V
µA
µA
µA
µA
µA
µA
V
Table 29 Electrical characteristics (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits
Parameter Min. Typ. Max.
Symbol Unit
Test conditions
82
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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Table 30 Electrical characteristics (3)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Power source current
Limits
Parameter Min. Typ. Max.
Symbol Unit
High-speed mode
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
High-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(X
CIN
) = 32.768 kHz (in WIT state)
Output transistors “off”
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(X
CIN
) = 32.768 kHz (in WIT state)
Output transistors “off”
Middle-speed mode
f(XIN) = 8 MHz
f(XCIN) = stopped
Output transistors “off”
Middle-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = stopped
Output transistors “off”
Increment when A-D conversion is executed
f(XIN) = 8 MHz
Test conditions
13
ICC
Ta = 25 °C
Ta = 85 °C
6.8 mA
All oscillation stopped
(in STP state)
Output transistors “off”
1.6
60
250
20
70
150
5.0
20
4.0
200
mA
µA
Except
M38517F8FP/SP
M38517F8FP/SP
Except
M38517F8FP/SP
M38517F8FP/SP
20
1.5
800
0.1
40
55
10.0
7.0
1.0
10
µA
µA
µA
µA
µA
µA
µA
mA
mA
µA
µA
µA
Except
M38517F8FP/SP
M38517F8FP/SP
Except
M38517F8FP/SP
M38517F8FP/SP
83
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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A-D converter characteristics
Table 31 A-D converter characteristics
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, T a = –20 to 85 °C, f(XIN) = 8 MHz, unless otherwise noted)
bit
LSB
tc(
φ
)
µs
kΩ
µA
µA
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Ladder resistor
Reference power source input current
A-D port input current
Min.
50
Typ.
40
35
150
0.5
Max.
10
±4
61
200
5.0
5.0
High-speed mode,
Middle-speed mode
Low-speed mode
VREF = 5.0 V
Unit
Limits
Parameter
–
–
tCONV
RLADDER
IVREF
II(AD)
Test conditionsSymbol
VREF “on”
VREF “off”
84
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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(Built-in 24 KB or more ROM)
Timing requirements
Table 32 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Limits
XIN cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
20
125
50
50
200
80
80
80
80
800
370
370
220
100
1000
400
400
200
200
Typ. Max.
Symbol Unit
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
Table 33 Timing requirements (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Limits
XIN cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
20
250
100
100
500
230
230
230
230
2000
950
950
400
200
2000
950
950
400
300
Typ. Max.
Symbol Unit
Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 4 MHz and bit 6 of address 001A16 is “0” (UART).
85
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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3851 Group
(Built-in 24 KB or more ROM)
Table 34 Switching characteristics (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Table 35 Switching characteristics (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tv (SCLK1-TXD)
tr (SCLK1)
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tv (SCLK2-SOUT2)
tf (SCLK2)
tr (CMOS)
tf (CMOS)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
tC(SCLK1)/2–30
tC(SCLK1)/2–30
–30
tC(SCLK2)/2–160
tC(SCLK2)/2–160
0
Typ.
10
10
Max.
140
30
30
200
30
30
30
Symbol Unit
Notes 1: When the P2 5/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”.
3: The XOUT pin is excluded.
Test conditions
Fig. 79
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tv (SCLK1-TXD)
tr (SCLK1)
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tv (SCLK2-SOUT2)
tf (SCLK2)
tr (CMOS)
tf (CMOS)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
tC(SCLK1)/2–50
tC(SCLK1)/2–50
–30
tC(SCLK2)/2–240
tC(SCLK2)/2–240
0
Typ.
20
20
Max.
350
50
50
400
50
50
50
Symbol Unit
Notes 1: When the P2 5/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”.
3: The XOUT pin is excluded.
Test conditions
Fig. 79
Switching characteristics
86
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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3851 Group
(Built-in 24 KB or more ROM)
Fig. 79
Circuit for measuring output switching characteristics (1)
Symbol Parameter Unit
MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS
Table 36 Multi-master I2C-BUS bus line characteristics
Bus free time
Hold time for START condition
Hold time for SCL clock = “0”
Rising time of both SCL and SDA signals
Data hold time
Hold time for SCL clock = “1”
Falling time of both SCL and SDA signals
Data setup time
Setup time for repeated START condition
Setup time for STOP condition
tBUF
tHD;STA
tLOW
tR
tHD;DAT
tHIGH
tF
tSU;DAT
tSU;STA
tSU;STO
Min. Max. Min. Max. µs
µs
µs
ns
µs
µs
ns
ns
µs
µs
Standard clock mode
High-speed clock mode
Note: Cb = total capacitance of 1 bus line
4.7
4.0
4.7
0
4.0
250
4.7
4.0
1000
300
1.3
0.6
1.3
20+0.1Cb
0
0.6
20+0.1Cb
100
0.6
0.6
300
0.9
300
Test conditions
Fig. 80
Fig. 78 Timing diagram of multi-master I2C-BUS
Fig. 80
Circuit for measuring output switching characteristics (2)
t
BUF
t
H
D
:
S
T
A
t
H
D
:
D
T
A
t
LOW
t
R
t
F
t
H
I
G
H
t
s
u
:
D
A
T
tsu
:STA
t
HD:STA
tsu
:STO
SCL pSSr p
SDA
M
e
a
s
u
r
e
m
e
n
t
o
u
t
p
u
t
p
i
n
1
0
0
p
F
C
M
O
S
o
u
t
p
u
t
N
-
c
h
a
n
n
n
e
l
o
p
e
n
-
d
r
a
i
n
1
kΩ
M
e
a
s
u
r
e
m
e
n
t
o
u
t
p
u
t
p
i
n
1
0
0
p
F
87
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
Fig. 81 Timing diagram
t
C
(
C
N
T
R
)
0
.
2
V
C
C
t
WL(INT)
0.8V
CC
t
WH(INT)
0.2V
CC
0.8V
CC
t
W
(
R
E
S
E
T
)
R
E
S
E
T
0
.
2
V
C
C
t
WL(CNTR)
0.8V
CC
t
WH(CNTR)
0
.
2
V
C
C
0.2V
CC
0
.
8
V
C
C
0
.
8
V
C
C
0.2V
CC
t
WL(XIN)
0
.
8
V
C
C
t
WH(XIN
)
t
C
(
XI
N)
XI
N
t
f
t
r
t
d
(
SC
L
K
1-
TXD
)
,
t
d
(
SC
L
K
2-
SO
U
T
2)
t
v
(
SC
L
K
1-
TXD
)
,
t
v
(
SC
L
K
2-
SO
U
T
2)
t
C
(
SC
L
K
1)
,
t
C
(
SC
L
K
2)
t
W
L
(
SC
L
K
1)
,
t
W
L
(
SC
L
K
2)
t
WH(SCLK1),
t
WH(SCLK2)
t
h(SCLK1
-
R
x
D),
t
h(SCLK2
-
SIN2)
t
s
u
(
R
x
D
-
SC
L
K
1)
,
t
s
u
(
SI
N
2
-
SC
L
K
2)
TXD
SOUT2
RXD
SI
N
2
SC
L
K
1
SC
L
K
2
I
N
T0
t
o
I
N
T3
C
N
T
R0
C
N
T
R1
88
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
PACKAGE OUTLINE
SDIP42-P-600-1.78 Weight(g)
–
JEDEC Code 4.1
EIAJ Package Code Lead Material
Alloy 42/Cu Alloy
42P4B Plastic 42pin 600mil SDIP
Symbol Min Nom Max
A
A2
b
b1
b2
c
E
D
L
Dimension in Millimeters
A10.51 – –
–3.8–
0.35 0.45 0.55
0.9 1.0 1.3
0.63 0.73 1.03
0.22 0.27 0.34
36.5 36.7 36.9
12.85 13.0 13.15
– 1.778 –
– 15.24 –
3.0 – –
0°–15°
– – 5.5
e
e1
42 22
21
1
E
c
e1
A2A1
b
b1b2
e
LA
SEATING PLANE
D
MMP
SSOP42-P-450-0.80 Weight(g)
–
JEDEC Code 0.63
EIAJ Package Code Lead Material
Alloy 42
42P2R-A/E Plastic 42pin 450mil SSOP
Symbol Min Nom Max
A
A
2
b
c
D
E
L
L
1
y
Dimension in Millimeters
H
E
A
1
I
2
–
–
.250
.050
.130.317.28–
.6311.30–
–
–
.271
–
–
.02.30.150.517.48.80.9311.50.7651
–
.4311–
–
.42
–
.40.20.717.68–
.2312.70–
.150
–
b
2
–.50–
–
0°–10°
e
e
1
42 22
21
1
H
E
E
D
ey
F
A
A
2
A
1
L
1
L
c
eb
2
e
1
I
2
Recommended Mount Pad
Detail F
z
Z
1
Detail G
–
–
Z
10.75
––
0.9
z
b
G
89
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
WDIP42-C-600-1.78 Weight(g)
JEDEC Code
EIAJ Package Code
42S1B-A Metal seal 42pin 600mil DIP
–– ––
–– 0.46
0.25
––
3.44
15.8 –
–
–
––
–
3.05
–– ––
–
Symbol Min Nom Max
A
A2
b
b1
c
D
E
L
Z
Dimension in Millimeters
A1
3.05 15.24
1.778
41.1
0.33 0.17 0.9 0.8 0.7 0.540.38
1.0 5.0
e
e1
e
E
D
1
42 22
21
bZ
SEATING PLANE
AL
A2A1
b1
e1
c
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
© 2002 MITSUBISHI ELECTRIC CORP.
New publication, effective July 2002.
Specifications subject to change without notice.
Notes regarding these materials
•These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
•Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
contained in these materials.
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Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
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•Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
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REVISION HISTORY
3851 GROUP (built-in 24 KB or more ROM) DATA SHEET
Rev. Date Description
Page Summary
(1/1)
1.0 07/26/02 First Edition