1. General description
The 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use
as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device
and is pin and function compatible with the 74HC4053 and 74HCT4053. Each switch has
a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common
input/output (nZ). All three switches share an enable input (E). A HIGH on E causes all
switches into the high-impedance OFF-state, independent of Sn.
VCC and GND are the supp ly vo ltage connections for the dig ital control inpu ts (Sn and E).
The VCC to GND range is 1 V to 6 V. The analog inputs/outputs (nY0, nY1 and nZ) can
swing between VCC as a positive limit and VEE as a negative limit. VCC VEE may not
exceed 6 V. For op eration as a digit al m ultiplexer/de multiplexe r, VEE is connected to GND
(typically ground). VEE and VSS are the supply voltage connections for the switches.
2. Features and benefits
Optimized for low-voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Low ON resistance:
180 (typical) at VCC VEE = 2.0 V
100 (typical) at VCC VEE = 3.0 V
75 (typical) at VCC VEE = 4.5 V
Logic level translation:
To enable 3 V logic to communicate with 3 V analog signals
Typical ‘break before make’ built in
ESD protection:
HBM JESD22-A114-C exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 Cto+85C and from 40 Cto+125C
74LV4053
Triple single-pole double-throw analog switch
Rev. 5 — 18 September 2014 Product data sheet
74LV4053 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 18 September 2014 2 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LV4053N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74LV4053D 40 C to +125 C SO16 plastic small outline package; 16 leads; body
width 3.9 mm SOT109-1
74LV4053DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body
width 5.3 mm SOT338-1
74LV4053PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body wid th 4.4 mm SOT403-1
74LV4053BQ 40 C to +125 C DHVQFN16 plastic dual-in line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
SOT763-1
Fig 1. Functional diag ram
001aak341
LOGIC
LEVEL
CONVERSION
11
16
VCC
13 1Y1
S1
LOGIC
LEVEL
CONVERSION
DECODER
LOGIC
LEVEL
CONVERSION
12 1Y0
14 1Z
1 2Y1
2 2Y0
15 2Z
3 3Y1
5 3Y0
43Z
10
S2
9
87
VEE
GND
S3
6
E
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Product data sheet Rev. 5 — 18 September 2014 3 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
Fig 2. Logic symbol Fig 3. IEC logic symbol
DDH
< 
<
6


6
6
(
<
<
<
<
=
= 
= 
DDH
(1

08;'08;


î




Fig 4. Schematic diagram (one switc h)
DDG
IURP
ORJLF
9
&&
9
((
9
((
9
&&
9
&&
9
((
<
=
9
&&
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Product data sheet Rev. 5 — 18 September 2014 4 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The
substrate is attached to this pad
using conductive die attach
material. There is no electrical or
mechanical requirement to
solder this pad. However, if it is
soldered, the solder land should
remain floating or be connected
to VCC.
Fig 5. Pin configuration SOT38-4
and SOT109-1 Fig 6. Pin configuration
SOT338-1 and SOT403-1 Fig 7. Pin configuration for
SOT763-1
74LV4053
2Y1 VCC
2Y0 2Z
3Y1 1Z
3Z 1Y1
3Y0 1Y0
ES1
VEE S2
GND S3
001aak424
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
74LV4053
2Y1 VCC
2Y0 2Z
3Y1 1Z
3Z 1Y1
3Y0 1Y0
ES1
VEE S2
GND S3
001aak342
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
001aak343
VEE S2
ES1
3Y0 1Y0
3Z 1Y1
3Y1 1Z
2Y0 2Z
GND
S3
2Y1
VCC
Transparent top view
7 10
6 11
5 12
413
3 14
2 15
8
9
1
16
terminal 1
index area
VCC(1)
74LV4053
Table 2. Pin description
Symbol Pin Description
E6 enable input (active LOW)
VEE 7 supply voltage
GND 8 ground supply voltage
S1, S2, S3 11, 10, 9 select input
1Y0, 2Y0, 3Y0 12, 2, 5 independent input or output
1Y1, 2Y1, 3Y1 13, 1, 3 independent input or output
1Z, 2Z, 3Z 14, 15, 4 common output or input
VCC 16 supply voltage
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Product data sheet Rev. 5 — 18 September 2014 5 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
[1] To avoid drawing VCC current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current will flow out of terminals nYn, and in this case
there is no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed VCC or VEE.
[2] The minimum input voltage rating may be exceeded if the input current rating is observed.
[3] For DIP16 packages: above 70 C the value of Ptot derates linearly with 12 mW/K.
For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
Table 3. Function table [1]
Inputs Channel on
ESn
LLnY0 to nZ
L H nY1 to nZ
H X switches off
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage [1] 0.5 +7.0 V
IIK input clamping current VI<0.5 V or VI> V CC + 0.5 V [2] -20 mA
ISK switch clamping current VSW < 0.5 V or VSW > VCC + 0.5 V [2] -20 mA
ISW switch current VSW >0.5 V or VSW < VCC + 0.5 V ;
source or sink current [2] -25 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C[3]
DIP16 package - 750 mW
SO16 package - 500 mW
TSSOP16 package - 500 mW
DHVQFN16 package - 500 mW
74LV4053 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 18 September 2014 6 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
8. Recommended operating conditions
[1] The static characteristics are guaranteed from VCC = 1.2 V to 6.0 V, but L V devices are guaranteed to function down to VCC =1.0V (with
input levels GND or VCC).
Table 5. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage see Figure 8 13.36V
VIinput voltage 0 - VCC V
VSW switch voltage 0 - VCC V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V
VCC = 2.0 V to 2.7 V - - 200 ns/V
VCC = 2.7 V to 3.6 V - - 100 ns/V
Fig 8. Guaranteed operating area as a function of the supply voltages
VCC - VEE (V)
0 8.06.02.0 4.0
001aak344
4.0
2.0
6.0
8.0
VCC - GND
(V)
0
operating area
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Product data sheet Rev. 5 — 18 September 2014 7 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
9. Static characteristics
[1] Typical values are measured at Tamb = 25 C.
Table 6. Static characteristics
At recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VIH HIGH-level input voltage VCC = 1.2 V 0.9 - - 0.9 - V
VCC = 2.0 V 1.4 - - 1.4 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VCC = 4.5 V 3.15 - - 3.15 - V
VCC = 6.0 V 4.20 - - 4.20 - V
VIL LOW-level input voltage VCC = 1.2 V - - 0.3 - 0.3 V
VCC = 2.0 V - - 0.6 - 0.6 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VCC = 4.5 V - - 1.35 - 1.35 V
VCC = 6.0 V - - 1.80 - 1.80 V
IIinput leakage current VI=V
CC or GND
VCC = 3.6 V - - 1.0 - 1.0 A
VCC = 6.0 V - - 2.0 - 2.0 A
IS(OFF) OFF-state leakage current VI = VIH or VIL; see Figure 9
VCC = 3.6 V - - 1.0 - 1.0 A
VCC = 6.0 V - - 2.0 - 2.0 A
IS(ON) ON-state leakage current VI = VIH or VIL; see Figure 10
VCC = 3.6 V - - 1.0 - 1.0 A
VCC = 6.0 V - - 2.0 - 2.0 A
ICC supply current VI = VCC or GND; IO = 0 A
VCC = 3.6 V - - 20 - 40 A
VCC = 6.0 V - - 40 - 80 A
ICC additional supply current per input; VI = VCC 0.6 V;
VCC = 2.7 V to 3.6 V --500-850A
CIinput capacitance - 3.5 - - - pF
Csw switch capacitance independent pins nYn - 5 - - - pF
common pins nZ - 8 - - - pF
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Product data sheet Rev. 5 — 18 September 2014 8 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
9.1 Test circuits
9.2 O N resistance
VI = VCC or VEE and VO = VEE or VCC.V
I = VCC or VEE and VO = open circuit.
Fig 9. Test circuit for measuring OFF-state leakage
current Fig 10. Test circuit for measuring ON-state leakage
current
IS
001aak346
GND
VO
switch
GND = VEE
S1 to S3
E
nZ
nY0
VIH or VIL
VCC
nY1
1
2
VI
Table 7. ON resistance
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 11 and
Figure 12.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
RON(peak) ON resistance (peak) VI = 0 V to VCC VEE
VCC =1.2V; I
SW = 100 A[2] --- - -
VCC =2.0V; I
SW = 1000 A - 180 365 - 435
VCC =2.7V; I
SW = 1000 A - 115 225 - 270
VCC = 3.0 V to 3.6 V;
ISW = 1000 A- 100 200 - 245
VCC =4.5V; I
SW = 1000 A - 75 150 - 180
VCC =6.0V; I
SW = 1000 A - 70 140 - 165
RON ON resistance mismatch
between channels VI = 0 V to VCC VEE
VCC =1.2V; I
SW = 100 A[2] --- - -
VCC =2.0V; I
SW = 1000 A-5- - -
VCC =2.7V; I
SW = 1000 A-4- - -
VCC = 3.0 V to 3.6 V;
ISW = 1000 A-4- - -
VCC =4.5V; I
SW = 1000 A-3- - -
VCC =6.0V; I
SW = 1000 A-2- - -
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Product data sheet Rev. 5 — 18 September 2014 9 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
[1] Typical values are measured at Tamb = 25 C.
[2] When supply voltages (VCC VEE) near 1.2 V the analog switch ON resistance becomes extremely non-linear. When using a supply of
1.2 V, it is recommended to use these devices only for transmitting digital signals.
RON(rail) ON resistance (rail) VI = GND
VCC =1.2V; I
SW = 100 A[2] - 250 - - -
VCC =2.0V; I
SW = 1000 A - 120 280 - 325
VCC =2.7V; I
SW = 1000 A - 75 170 - 195
VCC = 3.0 V to 3.6 V;
ISW = 1000 A- 70 155 - 180
VCC =4.5V; I
SW = 1000 A - 50 120 - 135
VCC =6.0V; I
SW = 1000 A - 45 105 - 120
RON(rail) ON resistance (rail) VI = VCC VEE
VCC =1.2V; I
SW = 100 A[2] - 350 - - -
VCC =2.0V; I
SW = 1000 A - 170 340 - 400
VCC =2.7V; I
SW = 1000 A - 105 210 - 250
VCC = 3.0 V to 3.6 V;
ISW = 1000 A- 95 190 - 225
VCC =4.5V; I
SW = 1000 A - 70 140 - 165
VCC =6.0V; I
SW = 1000 A - 65 125 - 150
Table 7. ON resistance …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 11 and
Figure 12.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
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Product data sheet Rev. 5 — 18 September 2014 10 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
9.3 On resistance waveform and test circuit
RON =V
SW /I
SW.
Fig 11. Test circuit for measuring RON
V
001aak347
GND
VI
VSW
ISW
switch
GND = V
EE
S1 to S3
E
nZ
nY0
V
IH
or V
IL
V
CC
nY1
1
2
Vi = 0 V to VCC VEE
Fig 12. Typical RON as a function of input voltage
VI (V)
0 4.81.2 2.4 3.6
001aak348
100
150
50
200
RON
(Ω)
0
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
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Product data sheet Rev. 5 — 18 September 2014 11 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
10. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 15.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation delay nYn, nZ to nZ, nYn; see Figure 13 [2]
VCC =1.2V - 25 - - - ns
VCC =2.0V - 9 17 - 20 ns
VCC =2.7V - 6 13 - 15 ns
VCC = 3.0 V to 3.6 V [3] -510- 12ns
VCC =4.5V - 4 9 - 10 ns
VCC =6.0V - 3 7 - 8 ns
ten enable time E to nYn, nZ; see Figure 14 [2]
VCC = 1.2 V - 100 - - - ns
VCC =2.0V - 34 65 - 77 ns
VCC =2.7V - 25 48 - 56 ns
VCC = 3.0 V to 3.6 V ; CL=15pF [3] -16- - -ns
VCC = 3.0 V to 3.6 V [3] -1938- 45ns
VCC =4.5V - 17 32 - 38 ns
VCC =6.0V - 13 25 - 29 ns
Sn to nYn, nZ; see Figure 14 [2]
VCC = 1.2 V - 125 - - - ns
VCC =2.0V - 43 82 - 97 ns
VCC =2.7V - 31 60 - 71 ns
VCC = 3.0 V to 3.6 V ; CL=15pF [3] -20- - -ns
VCC = 3.0 V to 3.6 V [3] -2448- 57ns
VCC =4.5V - 21 41 - 48 ns
VCC =6.0V - 16 31 - 37 ns
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Product data sheet Rev. 5 — 18 September 2014 12 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
[1] All typical values are measured at Tamb =25C.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] Typical values are measured at nominal supply voltage (VCC = 3.3 V).
[4] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+((CL + CSW) V CC2fo) where:
fi= input frequency in MHz, fo= output frequency in MHz
CL= output load capacitance in pF
CSW = maximum switch capacitance in pF;
VCC = supply voltage in Volts
N = number of inputs switching
(CLVCC2fo) = sum of the outputs.
tdis disable time E to nYn, nZ; see Figure 14 [2]
VCC =1.2V - 95 - - - ns
VCC =2.0V - 34 61 - 73 ns
VCC =2.7V - 26 46 - 54 ns
VCC = 3.0 V to 3.6 V ; CL=15pF [3] -17- - -ns
VCC = 3.0 V to 3.6 V [3] -2037- 44ns
VCC =4.5V - 18 32 - 38 ns
VCC =6.0V - 15 25 - 30 ns
Sn to nYn, nZ; see Figure 14 [2]
VCC =1.2V - 90 - - - ns
VCC =2.0V - 32 59 - 70 ns
VCC =2.7V - 24 44 - 52 ns
VCC = 3.0 V to 3.6 V ; CL=15pF [3] -16- - -ns
VCC = 3.0 V to 3.6 V [3] -1936- 42ns
VCC =4.5V - 17 31 - 36 ns
VCC =6.0V - 14 24 - 28 ns
CPD power dissipation
capacitance CL=50pF; f
i = 1 MHz;
VI=GNDtoV
CC
[4] -36- - -pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 15.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
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Product data sheet Rev. 5 — 18 September 2014 13 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
10.1 Waveforms
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 13. nYn, nZ to nZ, nYn propagation delays
001aak351
nYn or nZ
input
nZ or nYn
output
tPLH tPHL
VCC
VEE
VM
VM
VO
VEE
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 14. Enable and disabl e times
001aak352
tPLZ
tPHZ
switch OFF switch ONswitch ON
nYn or nZ output
LOW-to-OFF
OFF-to-LOW
nYn or nZ output
HIGH-to-OFF
OFF-to-HIGH
Sn, E input
VO
VO
VEE
VEE
VCC
VSS
VM
tPZL
tPZH
90 %
90 %
10 %
10 %
Table 9. Measurement points
Supply voltage Input Output
VCC VMVMVXVY
< 2.7 V 0.5VCC 0.5VCC VOL + 0.1VCC VOH 0.1VCC
2.7 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V
> 3.6 V 0.5VCC 0.5VCC VOL + 0.1VCC VOH 0.1VCC
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Product data sheet Rev. 5 — 18 September 2014 14 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 15. Test circuit for measuring switching times
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aak353
VEXT
VCC
VEE
VIVO
DUT
CL
RT
RL
RL
G
Table 10. Test data
Supply voltage Input Load VEXT
VCC VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
< 2.7 V VCC 6 ns 50 pF 1 kopen VEE 2VCC
2.7 V to 3.6 V 2.7 V 6 ns 15 pF, 50 pF 1 kopen VEE 2VCC
> 3.6 V VCC 6 ns 50 pF 1 kopen VEE 2VCC
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Product data sheet Rev. 5 — 18 September 2014 15 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
10.2 Additional dynamic parameters
[1] Adjust fi voltage to obtain 0 dBm level at output for 1 MHz (0 dBm = 1 mW into 50 ).
[2] Adjust fi voltage to obtain 0 dBm level at output for 1 MHz (0 dBm = 1 mW into 600 ).
Table 11. Additional dynamic characteristics
At recommended operating conditions; voltages are refe renced to GND (ground = 0 V); VI = GND or VCC (unless otherwise
specifie d ) ; tr = tf
6.0 ns; Tamb = 25
C.
Symbol Parameter Conditions Min Typ Max Unit
THD total harmonic
distortion fi= 1 kHz; CL= 50 pF; RL=10k; see Figure 20
VCC =3.0V; V
I=2.75V(p-p) - 0.8 - %
VCC =6.0V; V
I=5.5V(p-p) - 0.4 - %
fi= 10 kHz; CL= 50 pF; RL=10k; see Figure 20
VCC =3.0V; V
I=2.75V(p-p) - 2.4 - %
VCC =6.0V; V
I=5.5V(p-p) - 1.2 - %
f(3dB) 3 dB frequency
response CL= 50 pF; RL=50; see Figure 16 [1]
VCC = 3.0 V - 180 - MHz
VCC = 6.0 V - 200 - MHz
iso isolation (OFF-state) fi= 1 MHz; CL=50 pF; R
L=600; see Figure 18 [2]
VCC =3.0V - 50 - dB
VCC =6.0V - 50 - dB
Vct crosstalk voltage between digital inputs and switch;
fi= 1 MHz; CL=50 pF; R
L=600; see Figure 21 [2]
VCC =3.0V - 0.11 - V
VCC = 6.0 V - 0.12 - V
Xtalk crosstalk between switches; fi= 1 MHz; CL= 50 pF;
RL= 600 ;seeFigure 22
VCC =3.0V - 60 - dB
VCC =6.0V - 60 - dB
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Product data sheet Rev. 5 — 18 September 2014 16 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
10.2.1 Test circuits
VCC = 3.0 V; GND = 0 V; VEE =3.0 V; RL=50;
RSOURCE =1k.
Fig 16. Test circuit for measu ring frequency response Fig 17. Typical frequency response
dB
001aak355
GND
fi
2RL
2RL
CL
switch
GND = VEE
S1 to S3
E
nZ
nY0
VIH or VIL
VCC VCC
nY1
1
2
0.1 μF
001aak361
0
5
(dB)
−5
f (kHz)
10 106
105
102104
103
VCC = 3.0 V; GND = 0 V; VEE =3.0 V; RL=50;
RSOURCE =1k.
Fig 18. Test circuit for measuring isolation (OFF-state) Fig 19. Typical isolation (OFF-state) as function of
frequency
dB
001aak356
V
CC
fi
2RL
2RL
CL
switch
GND = V
EE
S1 to S3
E
nZ
nY0
V
IH
or V
IL
V
CC
V
CC
nY1
1
2
0.1 μF
001aak360
−50
0
(dB)
−100
f (kHz)
10 106
105
102104
103
74LV4053 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 18 September 2014 17 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
Fig 20. Test circuit for measuring total harmonic distortion
D
001aak354
GND
fi
2RL
2RL
CL
switch
GND = VEE
S1 to S3
E
nZ
nY0
VIH or VIL
VCC VCC
nY1
1
2
10 μF
a. Test circuit
b. Input and output pulse defi nitions
VI may be connected to Sn or E.
Fig 21. Test circuit for measuring crosstalk voltage between digital inputs and switch
001aak357
V
IH
or V
IL
V
CC
switch
GND = V
EE
S1 to S3
E
nZ
nY0
V
CC
V
CC
nY1
1
2
GV
2RL
2RL
2RL
2RL
CLVO
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74LV4053 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 18 September 2014 18 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
a. Switch closed condition
b. Switch open condition
Fig 22. Test circuit for measuring crosstalk between switches
001aak358
GND VO
2RL
2RL
CL
RL
2RL
GND = VEE
S1 to S3
E
nZ
nY0
VIH or VIL
VCC VCC
2RL
VCC
nY1
VI
0.1 μF
dB
001aak359
GND VI
2RL
2RL
RL
2RL
GND = VEE
S1 to S3
E
nZ
nY0
VIH or VIL
VCC VCC
2RL
VCC
2RL
VCC
nY1
VOCLdB
74LV4053 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 18 September 2014 19 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
11. Package outline
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74LV4053 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 18 September 2014 20 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
Fig 24. Package outline SOT109-1 (SO16)
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74LV4053 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 18 September 2014 21 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
Fig 25. Package outline SOT338-1 (SSOP16)
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74LV4053 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 18 September 2014 22 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
Fig 26. Package outline SOT403-1 (TSSOP16)
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74LV4053 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 18 September 2014 23 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
Fig 27. Package outline SOT763-1 (DHVQFN16)
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74LV4053 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 18 September 2014 24 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
12. Abbreviations
13. Revision history
Table 12. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Trans istor Logic
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LV4053 v.5 20140918 Product data sheet - 74LV4053 v.4
Modifications: •Figure 7: Figure note added for DHVQFN16 package.
74LV4053 v.4 20090810 Product data sheet - 74LV4053 v.3
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Added type number 74LV4053BQ (DHVQFN16 package)
•RON values changed in Section 2.
•Package version SOT38-1 changed to SOT38-4 in Section 3, and Figure 23.
74LV4053 v.3 19980623 Product specification - 74LV4053 v.2
74LV4053 v.2 19970715 Product specification - -
74LV4053 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 18 September 2014 25 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
14. Legal information
14.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
14.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidenta l ,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconduct ors’ aggregate and cumulat ive liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associate d with t heir
applications and products.
NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the obj ective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74LV4053 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 18 September 2014 26 of 27
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors prod uct is automotive qualified,
the product is not suitable for automotive use. It i s neither qua lified nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) versio n of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
14.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
© NXP Semiconductors N.V. 2014. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 18 September 2014
Document identifier: 74LV4053
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
16. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
9.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
9.2 ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 8
9.3 On resistance waveform and test circuit. . . . . 10
10 Dynamic characteristics . . . . . . . . . . . . . . . . . 11
10.1 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10.2 Additional dynamic parameters . . . . . . . . . . . 15
10.2.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
12 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 24
13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24
14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25
14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25
14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
15 Contact information. . . . . . . . . . . . . . . . . . . . . 26
16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27