19-0281; Rev 2; 8/12
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
EVALUATION KIT AVAILABLE
MAX3747A/MAX3747B
Typical Application Circuit
General Description
The MAX3747A/MAX3747B multirate limiting amplifiers
function as data quantizers for OC-3 through OC-48 syn-
chronous optical network (SONET), Fibre-Channel, and
Gigabit Ethernet optical receivers. They are pin-for-pin
compatible with the SY88993V from Micrel
Semiconductor, Inc. The amplifiers accept a wide range
of input voltages and provide constant-level, current-
mode logic (CML) output voltages with controlled edge
speeds. The MAX3747A/MAX3747B output voltages are
800mVP-P. The MAX3747B has enhanced LOS operation
under overload conditions.
The MAX3747A/MAX3747B limiting amplifiers feature a
programmable loss-of-signal detect (LOS) and an
optional disable function (DISABLE) that can be com-
bined to implement squelch.
The MAX3747A/MAX3747B are available in a 3mm, 10-
pin µMAX® package ideal for small form-
factor receivers.
Applications
Gigabit Ethernet SFP/SFF Optical Transceiver Modules
1G/2G Fibre-Channel SFP/SFF Optical Transceiver
Modules
Multirate OC-3 to OC-48 FEC SFP/SFF Optical
Transceiver Modules
10G LX4 Transceiver Modules
Features
oPin Compatible with Micrel SY88993V
o155Mbps to 3.2Gbps Operation
o> 57dB of Gain
o< 10-12 BER with 2mVP-P Input Amplitude
o18mA Supply Current
oChatter-Free LOS with Programmable Threshold
oOutput DISABLE Function
oPECL-Compatible Inputs
Ordering Information
MAX3745
SUPPLY FILTER
VCC
MAX4004
DS1859
VCC
3-INPUT
DIAGNOSTIC
MONITOR
SFP OPTICAL RECEIVER
5-PIN TO-HEADER
HOST BOARD
HOST FILTER
SERDES
50Ω
50Ω
MAX3747A
MAX3747B
VREF TH GND LOS DISABLE
IN-
IN+
OUT-
OUT+
VCC
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
50Ω50Ω
RTH1
RTH2
RTH1 + RTH2 ≥ 5kΩ
VCC_RX
VCC_HOST
LOS
4.7kΩ TO 10kΩ
PART TEMP RANGE PIN-PACKAGE
MAX3747AEUB+ -40°C to +85°C 10 µMAX
MAX3747BEUB+ -40°C to +85°C 10 µMAX
Pin Configuration appears at end of data sheet.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
2Maxim Integrated
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = +2.97V to +3.63V, CML output load is 50Ωto VCC, TA= -40°C to +85°C. Typical values are at VCC = +3.3V and TA= +25°C,
unless otherwise specified.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Power-Supply Voltage (VCC).................................-0.5V to +4.5V
Voltage at IN+, IN- ..........................(VCC - 2.4V) to (VCC + 0.5V)
Voltage at DISABLE, LOS, TH, VREF ..........-0.5V to (VCC + 0.5V)
Current into LOS ...................................................-1mA to +9mA
Current into VREF ..................................................................2mA
Differential Input Voltage (IN+ - IN-) .....................................2.5V
Continuous Current at CML Outputs
(OUT+, OUT-) ..............................................-25mA to +25mA
Continuous Power Dissipation (TA= +70°C)
10-Pin µMAX (derate 6.9mW/°C above +70°C) ...........552mW
Operating Junction Temperature Range (TJ) .......-55°C to +150°C
Storage Ambient Temperature Range (TS)...........-55°C to +150°C
Lead Temperature (soldering, 10s)......................................+300°C
Soldering Temperature (reflow)............................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
M AX 3747A i ncl ud i ng the C M L outp ut cur r ent 36 41
M AX 3747B i ncl ud i ng the C M L outp ut cur r ent 38 43
MAX3747A excluding the CML output
current 18 24
Supply Current (Note 2) ICC
MAX3747B excluding the CML output
current 20 26
mA
Power-Supply Noise Rejection PSNR f < 2MHz 30 dB
INPUT SPECIFICATION
Input Sensitivity VIN-MIN (Note 3) 4 mV
P
-
P
Input Overload VIN-MAX (Note 3) 1200 mV
P
-
P
OUTPUT SPECIFICATION
Output Resistance ROUT (Note 4) 42 50 58 Ω
Differential Output Return Loss DUT is powered on, f < 3GHz 15 dB
CML Differential Output Voltage MAX3747A/MAX3747B
4mVP-P ≤ VIN ≤ 1200mVP-P 600 800 1000 mV
P
-
P
Differential Output Signal When
Disabled
AC-coupled outputs, VIN-MAX applied to the
input (Note 4) 15 mV
P
-
P
Data-Output Transition Time 20% to 80% (Note 4) 70 120 ps
TRANSFER CHARACTERISTIC
K28.5 pattern at 3.2Gbps 13.2 19
PRBS 223 - 1 equivalent pattern at 2.7Gbps
(Note 6) 14 25
K28.5 pattern at 2.1Gbps 12 17
Deterministic Jitter (Notes 4, 5) DJ
P RBS 22 3 - 1 eq ui val ent p atter n at 155M b p s
(Note 6) 85 150
ps
P
-
P
Random Jitter VIN = 4mVP-P (Notes 4, 7) 3.5 5 psRMS
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
3
Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.97V to +3.63V, CML output load is 50Ωto VCC, TA= -40°C to +85°C. Typical values are at VCC = +3.3V and TA= +25°C,
unless otherwise specified.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input-Referred Noise VIN = 4mVP-P (Note 4) 120 150 µVRMS
Low-Frequency Cutoff 6.4 kHz
LOS Hysteresis 10log(VDEASSERT / VASSERT) (Note 4) 1.25 dB
MAX3747A (Notes 4, 8)
LOS Assert/Deassert Time MAX3747B (Notes 4, 8, 9) 2.3 40.0 µs
Low LOS Assert Level VTH = -1.3V (Notes 4, 10) 2.5 4.1 5.9 mV
P
-
P
Low LOS Deassert Level VTH = -1.3V (Notes 4, 10) 6.2 9.3 mV
P
-
P
Medium LOS Assert Level VTH = -0.68V (Notes 4, 10) 22.0 29.0 36.0 mV
P
-
P
Medium LOS Deassert Level VTH = -0.68V (Notes 4, 10) 44.8 62.0 mV
P
-
P
High LOS Assert Level VTH = -0.114V (Notes 4, 10) 36.0 53.7 63.6 mV
P
-
P
High LOS Deassert Level VTH = -0.114V (Notes 4, 10) 86.0 115 mV
P
-
P
TTL/CMOS I/O
VREF Voltage VREF VCC -
1.35
VCC -
1.3V
VCC -
1.19 V
LOS Output High Voltage VOH RLOS = 4.7kΩ to 10kΩ to VCC_HOST (3V) 2.4 V
LOS Output Low Voltage VOL RLOS = 4.7kΩ to 10kΩ to VCC_HOST (3.6V) 0.4 V
DISABLE Input High VIH 2.0 V
DISABLE Input Low VIL 0.8 V
DISABLE Input Current RLOS = 4.7kΩ to 10kΩ to VCC_HOST 10 µA
Note 1: The data-input transition time is controlled by a 4th-order Bessel filter with f-3dB = 0.75 x 2.667GHz for all data rates of
2.667Gbps and below. The f-3db = 0.75 x 3.2GHz for a data rate of 3.2Gbps.
Note 2: Supply current is measured with unterminated outputs or with AC-coupled output termination (see Figure 1).
Note 3: Between sensitivity and overload, all AC specifications are met and the output is 0.95 x limited output amplitude.
Note 4: Guaranteed by design and characterization.
Note 5: The deterministic jitter (DJ) caused by the input filter is not included in the DJ generation specification.
Note 6: The PRBS 223 - 1 equivalent pattern consists of a K28.5 pattern plus 240 ones plus K28.5 pattern plus 240 zeros.
Note 7: Random jitter was measured without using a filter at the input.
Note 8: The signal at the input is switched between two amplitudes, Signal_ON and Signal_OFF, as shown in Figure 2A.
Note 9: The signal at the input is switched between 1.2VP-P and Signal_OFF as shown in Figure 2B.
Note 10: VTH is the voltage at pin 5 referenced to VCC (see Figure 5).
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
4Maxim Integrated
MAX3747A
MAX3747B
VCC
ICC
(SUPPLY
CURRENT)
IOUT
(CML OUTPUT
CURRENT)
50I50I
Figure 1. Power-Supply Current Measurement
6dB
1dB
0V
VIN
TIME
SIGNAL_ON
SIGNAL_OFF
MAXIMUM DEASSERT LEVEL FOR A GIVEN VTH
MINIMUM ASSERT LEVEL FOR A GIVEN VTH
MAXIMUM POWER-DETECT WINDOW
Figure 2A. LOS Deassert Threshold—Set 1dB Below Receiver
Sensitivity
6dB
0V
VIN
TIME
SIGNAL_ON = 1.2VP-P (OVERLOAD)
SIGNAL_OFF
MAXIMUM DEASSERT LEVEL FOR A GIVEN RTH1/RTH2 RATIO
MINIMUM ASSERT LEVEL FOR A GIVEN RTH1/RTH2 RATIO
MAXIMUM POWER-DETECT WINDOW
Figure 2B. LOS Deassert Threshold—Operating at Input
Overload
Typical Operating Characteristics
(VCC = +3.3V, TA= +25°C, unless otherwise noted.)
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
5
Maxim Integrated
OUTPUT EYE DIAGRAM
(MINIMUM INPUT)
MAX3747A/MAX3747B toc01
60mV/div
50ps/div
3.2Gbps, 223 - 1 PRBS, 4mVP-P
OUTPUT EYE DIAGRAM
(MAXIMUM INPUT)
MAX3747A/MAX3747B toc02
60mV/div
50ps/div
3.2Gbps, 223 - 1 PRBS, 1200mVP-P
OUTPUT EYE DIAGRAM
(MINIMUM INPUT)
MAX3747A/MAX3747B toc03
60mV/div
70ps/div
2.7Gbps, 223 - 1 PRBS, 4mVP-P
OUTPUT EYE DIAGRAM
(MAXIMUM INPUT)
MAX3747A/MAX3747B toc04
60mV/div
70ps/div
2.7Gbps, 223 - 1 PRBS, 1200mVP-P
OUTPUT EYE DIAGRAM AT +100°C
MAX3747A/MAX3747B toc05
60mV/div
80ps/div
2.125Gbps, CJTPAT, 50mVP-P
10
25
20
15
30
35
45
40
50
-40 -20 -10-30 0 10 20 30 40 50 60 70 80
SUPPLY CURRENT vs. TEMPERATURE
(EXCLUDES OUTPUT CURRENT)
MAX3747A/MAX3747B toc06
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
TRANSFER FUNCTION
(OUTPUT VOLTAGE vs. INPUT VOLTAGE)
MAX3747A/MAX3747B toc07
DIFFERENTIAL INPUT (mVP-P)
DIFFERENTIAL OUTPUT (mVP-P)
4321
100
200
300
400
500
600
700
800
900
1000
0
05
MAX3747A/MAX3747B
0
1.5
1.2
0.9
0.6
0.3
1.8
2.1
2.7
2.4
3.0
-40 -20 -10-30 0 10 20 30 40 50 60 70 80
RANDOM JITTER vs. TEMPERATURE
MAX3747A/MAX3747B toc08
TEMPERATURE (°C)
RANDOM JITTER (psRMS)
VIN = 50mVP-P, FREQ = 2.7Gbps
RANDOM JITTER vs. INPUT AMPLITUDE
MAX3747A/MAX3747B toc09
DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
RANDOM JITTER (psRMS)
100010010
1
2
3
4
5
0
1 10,000
3.2Gbps
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA= +25°C, unless otherwise noted.)
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
6Maxim Integrated
BIT-ERROR RATIO vs. INPUT VOLTAGE
MAX3747A/MAX3747B toc10
DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
BIT-ERROR RATIO (10-12)
986 72 3 4 51
1000
2000
3000
4000
5000
6000
7000
8000
9000
10,000
11,000
12,000
13,000
1
010
MAXIM
MAX3747A/MAX3747B
MICREL
SY88993V
DETERMINISTIC JITTER
vs. INPUT AMPLITUDE
MAX3747A/MAX3747B toc11
DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
DETERMINISTIC JITTER (psP-P)
100010010
5
10
15
20
25
0
1 10,000
3.2Gbps, K28.5 PATTERN
0
25
20
15
10
5
30
35
40
-40 -20 -10-30 0 10 20 30 40 50 60 70 80
DETERMINISTIC JITTER
vs. TEMPERATURE
MAX3747A/MAX3747B toc12
TEMPERATURE (°C)
DETERMINISTIC JITTER (ps)
FREQ = 3.2Gbps
PATTERN = K28.5
VIN = 500mVP-P
VIN = 5mVP-P
LOS ASSERT/DEASSERT TIMES vs. INPUT
AMPLITUDE (LOW RTH1/RTH2 SETTINGS)
MAX3747A/MAX3747B toc13
INPUT AMPLITUDE (mVP-P)
LOS ASSERT/DEASSERT TIME (µs)
1200200 600 800 1000400
5
10
15
20
25
30
35
40
0
0 1400
MAX3747B
LOS ASSERT
LOS DEASSERT
LOS ASSERT/DEASSERT TIMES vs. INPUT
AMPLITUDE (HIGH RTH1/RTH2 SETTINGS)
MAX3747A/MAX3747B toc14
INPUT AMPLITUDE (mVP-P)
LOS ASSERT/DEASSERT TIME (µs)
1200200 600 800 1000400
5
10
15
20
25
30
35
40
0
0 1400
MAX3747B
LOS ASSERT
LOS DEASSERT
ASSERT/DEASSERT vs. VTH
MAX3747A/MAX3747B toc15
VTH (V)
ASSERT/DEASSERT (mVP-P)
-1.2
10
20
30
40
50
60
70
90
110
80
100
120
0
-1.4 0-0.2-0.4-0.6-0.8-1.0
VTH (V) = VOLTAGE AT PIN 5 (V)
WITH RESPECT TO VCC
DEASSERT
ASSERT
5
20
15
10
25
30
40
35
-40 -20 -10-30 0 10 20 30 40 50 60 70 80
ASSERT/DEASSERT vs. TEMPERATURE
MAX3747A/MAX3747B toc16
TEMPERATURE (°C)
ASSERT/DEASSERT (mV)
VTH = -1.1V, FREQ = 2.7Gbps
PATTERN = PRBS 223 - 1
ASSERT
DEASSERT
OUTPUT RETURN vs. FREQUENCY (SDD22)
(INPUT SIGNAL LEVEL = -60dBm)
MAX3747A/MAX3747B toc17
FREQUENCY (MHz)
SDD22 (dB)
1000
-20
-10
0
10
20
30
-30
100 10,000
INPUT RETURN vs. FREQUENCY (SDD11)
(INPUT SIGNAL LEVEL = -60dBm)
MAX3747A/MAX3747B toc18
FREQUENCY (MHz)
SDD11 (dB)
1000
-20
-10
0
10
20
30
-30
100 10,000
Detailed Description
The limiting amplifiers consist of a multistage amplifier,
offset-correction circuitry, an output buffer, and loss-of-
signal detect circuitry (see the
Functional Diagram
).
Input Stage
The input stage is shown in Figure 3. It provides 50Ωter-
mination to VREF for each input signal, IN+ and IN-. The
MAX3747A/MAX3747B should be AC-coupled.
Multistage Amplifier
The high-bandwidth multistage amplifier provides approx-
imately 61dB of gain for the MAX3747A/MAX3747B.
Offset Correction Loop
The MAX3747A/MAX3747B are susceptible to DC offsets
in the signal path because they have high gain. In com-
munication systems using NRZ data with a 50% duty
cycle, pulse-width distortion present in the signal or gener-
ated in the transimpedance amplifier appears as an input
offset and is reduced by the offset correction loop.
The offset correction loop sets a low-frequency cutoff of
3.2kHz.
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
7
Maxim Integrated
Pin Description
NAME
PIN MAX3747A/
MAX3747B
MICREL
SY8893V
FUNCTION
1 DISABLE EN
Disable Function Pin. The data outputs are held static when this pin is asserted high,
transistor-to-transistor logic (TTL). The data outputs are enabled when this pin is held
low. LOS functions remain active when outputs are disabled. For normal operation
connect to GND.
2 IN+ DIN Noninverted Input Signal
3IN- DIN Inverted Input Signal
4V
REF VREF Reference Voltage for LOS Threshold Setting
5 TH LOSLVL
Loss-of-Signal Level Set. A voltage on this pin created by a two-resistor divider sets
the threshold level. Connect one resistor from this pin to VCC and another from this pin
to VREF (see Figure 5).
6 GND GND Ground
7 LOS LOS
Loss of Signal. Open collector for the MAX3747A; internal 100kΩ pullup to VCC for the
MAX3747B. LOS is high when the level of the input signal drops below the preset
threshold set by the TH input. LOS is deasserted low when the signal level is above
the threshold.
8OUT- DOUT Inverted Data Output, CML
9 OUT+ DOUT Noninverted Data Output, CML
10 VCC VCC Positive Power Supply
MAX3747A
MAX3747B
50Ω
50Ω
VREF
VCC
ESD
STRUCTURES
Figure 3. Differential Input Stage
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
8Maxim Integrated
CML Output Buffer
The CML outputs of the MAX3747A/MAX3747B limiting
amplifiers provide high tolerance to impedance mis-
matches and inductive connectors. The output current
is approximately 16mA for the MAX3747A/MAX3747B.
Connecting the DISABLE pin to VCC disables the out-
put. If the LOS pin is connected to the DISABLE pin,
the outputs OUT+ and OUT- are at a static voltage
(squelch) whenever the input signal level drops below
the LOS threshold. The output buffer can be AC- or DC-
coupled to the load (Figure 4).
The MAX3747A/MAX3747B output is 800mVP-P.
MAX3747A
MAX3747B 50Ω50Ω
DIGITAL
OFFSET
CORRECTION
VREF SIGNAL DETECT
50Ω
50Ω
IN+
IN-
VREF
VREF TH LOS
VCC
VCC
OUT+
DISABLE
OUT-
RTH1
RTH1 + RTH2 ≥ 5kΩ
RTH2
Functional Diagram
50Ω50Ω
VCC
OUT+
OUT-
DISABLEDISABLE
Q4 Q2Q1Q3
DISABLE
DATA
ESD
STRUCTURES
Figure 4. CML Output Buffer
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
9
Maxim Integrated
Loss-of-Signal Indicator
The MAX3747A/MAX3747B are equipped with LOS cir-
cuitry that indicates when the input signal is below a pro-
grammable threshold, set by a voltage on the TH pin
(see the
Typical Operating Characteristics
). The voltage
on the TH pin is set by two resistors, one connecting
from the TH pin to VCC and the other connecting from TH
to VREF (Figure 5). An RMS power detector compares
the input signal amplitude with this threshold and feeds
the signal-detect information to the LOS output, which is
open collector. To prevent LOS chatter in the region of
the programmed threshold, approximately 2dB of hys-
teresis is built into the LOS assert/deassert function.
Once asserted, LOS is not deasserted until the input
amplitude rises to the required level. Figure 6 shows the
LOS output circuit.
Applications Information
Program the LOS Assert Threshold
Program the LOS assert threshold according to Figure
5. The combination of RTH1 and RTH2 should be
greater than or equal to 5kΩ, see the Assert/Deassert
vs. VTH graph in the
Typical Operating Characteristics
.
Select the Coupling Capacitor
When AC-coupling is desired, coupling capacitors CIN
and COUT should be selected to minimize the receiv-
er’s deterministic jitter. Jitter is decreased as the input
low-frequency cutoff (fIN) is decreased:
fIN = 1/[2π(50)(CIN)]
For all applications, the recommended value for CIN
and COUT is 0.1µF, which provides fIN equal to 32kHz.
Refer to Application Note HFAN-1.1:
Choosing AC-
Coupling Capacitors
on the Maxim website
(www.maximintegrated.com)
.
TH
VREF
RTH1
RTH2
VCC
VTH = (RTH2 x (VREF - VCC)) / (RTH1 + RTH2)
VTH IS VCC REFERENCED
RTH1 + RTH2 ≥ 5kΩ
Figure 5. MAX3747A/MAX3747B LOS Threshold Circuit
ESD
STRUCTURE
VCC
LOS
*
*100kΩ PULLUP (MAX3747B ONLY)
Figure 6. MAX3747A/MAX3747B LOS Output Circuit
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
10 Maxim Integrated
Chip Information
PROCESS: SiGe Bipolar
1
+
2
3
4
5
10
9
8
7
6
VCC
OUT+
OUT-
LOSVREF
IN-
IN+
DISABLE
MAX3747A
MAX3747B
µMAX
TOP VIEW
GNDTH
Pin Configuration
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE OUTLINE NO. LAND
PATTERN NO.
10 µMAX U10CN+1 21-0061 90-0330
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________
11
© 2012 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 5/05 Initial release —
1 10/07 Release of the MAX3747B. 1–10
2 8/12 Removed MAX3747 from data sheet, updated Electrical Characteristics.1–10
