February 1996 - Linear Technology

FEBRUARY 1996 VOLUME VI NUMBER 1

continued on page 3

New LTC1435–LTC1439

DC/DC Controllers

Feature Value

and Performance

by Randy Flatness, Steve Hobrecht

and Milton Wilcox

Introduction

The new LTC1435–LTC1439 multiple-

output DC/DC controllers bring

unprecedented levels of value to sup-

plies for notebook computers and

other battery-powered equipment,

while eliminating previous perfor-

mance barriers. For example, a new

Adaptive Power™ output stage allows

two previously incompatible param-

eters, constant frequency operation

and good low current efficiency, to

coexist in the same power supply. A

second breakthrough allows N-chan-

nel power MOSFETs to be used

exclusively, while maintaining low

dropout operation previously avail-

able only with P-channel MOSFETs.

Other innovations include an auxiliary

linear regulator loop, a phase-locked

loop (PLL) to synchronize the oscillator

to an external source, a self-contained

power-on-reset (POR) timer and pro-

grammable run delays useful for

staging output voltages.

Excellent system functionality

means that 1-, 2-, 3- or even 4-output

power supplies are easily constructed

using a minimum number of induc-

tors. Table 1 illustrates a few of the

many possible output combinations

and the magnetics required.

For maximum flexibility, internal

resistive feedback dividers are select-

able via programming pins for 3.3V,

5V and 12V output voltages, or a

regulator may be configured with an

adjustable output voltage to meet any

processor requirement.

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rebmuNtraPegakcaPsegatloVtuptuO*scitengaM

5341CTLOSnip-61V9–V5.1elbatsujdAL)1(

6341CTLPOSQnip-42V9.2/V3.3L)1(

7341CTLPOSSnip-82V21/V5T)1(

8341CTLPOSSnip-82V3.3/V5L)2(

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, LTC and LT are registered trademarks of Linear Technology Corporation.

Adaptive Power, Burst Mode and C-Load are trademarks of Linear Technology Corporation.

IN THIS ISSUE . . .

COVER ARTICLE

New LTC

1435–LTC1439 DC/DC

Controllers Feature Value

and Performance................. 1

Randy Flatness, Steve Hobrecht

and Milton Wilcox

Editor’s Page....................... 2

Richard Markell

LTC in the News .................. 2

DESIGN FEATURES

New 12-Bit ADC Squeezes

100ksps from 10mW ........... 7

William C. Rempfer and Ringo Lee

The LT

1511 3A Battery

Charger Charges All Battery

Types, Including Lithium-Ion

......................................... 11

Chiawei Liao

LTC1520 High Speed Line

Receiver Provides Precision

Propagation Delay and Skew

......................................... 14

Victor Fleury

The LTC1446 and LTC1446L:

World’s First Dual 12-Bit DACs

in SO-8 Packages .............. 16

Hassan Malik and Jim Brubaker

LT1490/LT1491 Over-the-Top

Dual and Quad Micropower

Rail-to-Rail Op Amps ......... 18

Jim Coelho-Sousae

LT1512/LT1513 Battery

Chargers Operate with Input

Voltages Above or Below the

Battery Voltage ................. 20

Bob Essaff

DESIGN IDEAS ............. 24–35

(complete list on page 24)

DESIGN INFORMATION

Simple Resistive Surge

Protection for

Interface Circuits .............. 36

Bryan Nevins

New Device Cameos ........... 38

LINEAR TECHNOLOGY

Linear Technology Magazine • February 1996

EDITOR'S PAGE

On Breadboarding

New integrated circuits don’t come

easy these days. Marketeers would

have you build a new Pentium

Pro

class microprocessor in a few months.

Never mind the half-million transis-

tors that all have to work correctly for

the product to come out right the first

time.

Simulation may be the way to go

when faced with one-half million tran-

sistors and a year’s time to market,

but what about in the analog world

where LTC excels? No analog product

in this or perhaps even the next cen-

tury will have one-tenth the transistor

count of a microprocessor. The semi-

conductor world has come to rely

heavily on simulations; and, in fact,

we at LTC do our share of simula-

tions; but, as the photo shows, we

also do our share of breadboarding.

It may be that the mere mention of

breadboarding shows my age. What

could be simpler than building a cir-

cuit from discrete transistors, diodes,

resistors, chewing gum and piano

wire? Once built, the circuit can be

tested node by node, and after the

design is proven to work over its

required electrical and environmen-

tal parameters, it can be put into

production.

In the IC design world, the simula-

tion is king because breadboarding is

hard. Transistors don’t come out of a

catalog; instead they are “kit parts”—

the types of transistors that can be

made on a particular wafer-fab pro-

cess. All capacitors must be small

values, since only these are supported

by the IC process; and so forth and so

on. The implementation is not easy,

but the reward justifies the labors.

What is the reward?

The reward is an IC that works the

first time—or at least the second time.

Breadboarding makes you look at the

circuit from a system point of view.

Can it be integrated into the system in

which it is intended to work? Are all

the hooks there? Breadboarding is

not always an option because of the

increased complexity of today’s ICs,

but we try to use it whenever we can

to complement simulation. Bread-

boarding helps us get it right “the first

time.”

This issue of Linear Technology

begins our sixth year of publication.

We have expanded our publishing

schedule to four times per year. We

continue to ask for feedback from our

readership. Call, FAX or write to us at

the numbers on the back page.

by Richard Markell

Figure 1. Breadboard of upcoming LTC microprocessor product?

continued on page 22

LTC in the News...

The only company in the history of

Silicon Valley to achieve continuous

sales growth over 40 consecutive

quarters is Linear Technology Corp.

In January, LTC announced record

second-quarter net sales of more than

$96 million, an increase of 55% over

the same quarter of 1995.

“This solid 10-year record vali-

dates both the strength of our market

and the effectiveness of our strategy

to be a broad-based supplier of high

performance analog circuits,” said

Robert Swanson, president and CEO.

“We attained record levels of sales

and profits and generated an addi-

tional $20 million in cash,” he said.

Shortly before LTC ended its sec-

ond fiscal quarter, Forbes magazine

again listed the company on its “Honor

Roll” of “The Best Small Companies

in America.” It was the sixth year in

a row in which Linear Technology

was included among “only a handful

of companies (that) have what it takes

to be a long-term repeater on our 200

Best Small Companies in America

list.” The magazine made special

mention of LTC and observed that a

$10,000 investment in Linear six

years ago would be worth about

$170,000 today.

“All chip companies are not cre-

ated equal,” said the influential Cabot

Market Letter for investors in its De-

cember 1, 1995, issue. “Linear

Technology is ... the leader in its

market. (The company’s) chips don’t

deal with data. They interact with the

real world to monitor, amplify or

transform continuous analog signals

associated with real-world phenom-

ena like temperature, pressure,

weight, position, height, speed or

sound.

“That’s diversity in the extreme.

In fact, LTC markets over 4,700

different products to over 9,000

manufacturers worldwide. Industrial

applications use 40% of the firm’s

output, computers 30%, telecom-

munications 15%, military 10% and

other 5%. International sales ac-

count for about half of the total.”

Pentium is a registered trademark of Intel Corporation.

Linear Technology Magazine • February 1996

A Brief History of High

Efficiency DC/DC Conversion

The 90% efficiency barrier was de-

molished several years ago, at least at

high output currents, by DC/DC con-

trollers adapted to drive external

synchronous power MOSFETs, which

largely eliminated the catch-diode

losses. However, the efficiency of these

converters plummeted when the out-

put current dropped, because the

fixed-gate-charge losses for the large

MOSFETs became an increasing per-

centage of the power delivered to the

load. Expressed differently, the qui-

escent (unloaded) current was

unacceptably high—often over 10mA.

Linear Technology’s LTC1148 fam-

ily of DC/DC controllers introduced

in late 1992 was the first in the indus-

try to extend high efficiency operation

over the entire load range required by

notebook computers and other por-

table electronics. This breakthrough

was achieved through Burst Mode™

operation, which turns both synchro-

nous MOSFETs off for increasing

periods as the load current drops. In

this way, the gate charge losses are

made proportional to the load cur-

rent, thus maintaining high efficiency.

Along with the gate-charge savings

came an attendant reduction in qui-

escent current, to less than 200µA for

the LTC1148.

Burst Mode operation received

immediate acceptance and is in use

today in a wide range of battery-

powered electronics. However, the

approach of intermittently operating

large power MOSFETs at low output

currents carries one drawback: the

operating frequency must inherently

be variable, and will enter the audio

range at some currents. This draw-

back, while not a problem in many

applications, is becoming an increas-

ing concern as communications and

multimedia features are added to

portable computers.

The LTC143X family controllers use

a constant frequency, current mode

PWM architecture in which the user

can set the oscillator frequency from

50kHz to 400kHz via an external ca-

pacitor. But how to break through the

constant frequency/low current effi-

ciency barrier?

Adaptive Power Mode—

Constant Frequency

without the Efficiency Hit

Adaptive Power mode, available in all

family members except the LTC1435

and LTC1438, optimizes efficiency

without changing frequency by auto-

matically switching between the two

output stages shown in Figure 1. The

first stage uses large synchronous N-

channel MOSFETs when operating at

high currents, and the second uses a

small (0.5Ω) N-channel MOSFET and

Schottky diode when operating at low

currents. The transition point between

the two output stages scales with the

maximum current, which is set by

the current sense resistor for each

regulator. The large MOSFETs oper-

ate above approximately 5% of the

maximum output current, whereas

the small MOSFET operates below

this current level, but at the same

constant frequency.

Because the low current “baby”

MOSFET (available in SOT-23) has

much lower gate charge than the large

synchronous MOSFETs, far less effi-

ciency loss is incurred as the load

current drops. Eventually, as the load

current is reduced below approxi-

mately 1% of the maximum current,

the loop begins skipping cycles and

the frequency does begin to decrease.

However, it does not enter the audio

region until the load current has fallen

even further. This performance comes

at little penalty in quiescent current,

which, at around 200µA, is nearly as

low as that of the LTC1148.

Burst Mode operation is also pos-

sible in all LTC1435–LTC1439

controllers for even higher efficien-

cies at the expense of more frequency

variability. To activate Burst Mode

operation, the small MOSFET is sim-

ply not installed. When the load

current falls to where both large

MOSFETs are turned off, the output

capacitor supports the load until the

error amplifier increases the I

SWITCH

DRIVE

SWITCH

NODE

SYNCHRONOUS

MOSFET

DRIVERS

HIGH

CURRENT

OPERATION

LOW

CURRENT

OPERATION

VIN

VOUT

COUT

SMALL

MOSFET

DRIVER

SENSE

OUTPUT CURRENT

100

EFFICIENCY (%)

10A1mA 10mA 1A100mA

(1)

(2)

(3)

Figure 1. Adaptive Power output stage automatically switches to efficiency-saving small

MOSFET at low currents, while continuing to operate at a constant frequency.

Figure 2. 10V to 5V conversion efficiency

versus output current for three operating

modes: 1) forced continuous operation; 2)

Adaptive Power mode (constant frequency);

and 3) Burst Mode.

LTC1435–LTC1439, continued from page 1

DESIGN FEATURES

Linear Technology Magazine • February 1996

voltage to 0.6V, at which point the

large MOSFETs resume operation.

Whether in Adaptive Power mode

or Burst Mode, the large MOSFETs

can always be forced into continuous

operation, independent of load cur-

rent, by forcing the SFB pin low (more

on this later). Figure 2 gives a com-

parison of efficiencies in a 3A regulator

for the three possible operating modes:

forced continuous operation, Adap-

tive Power mode and Burst Mode.

Low Dropout without

P-Channel MOSFETs

An important feature of the LTC1148

family is its ability to stay in regula-

tion with the input voltage only slightly

above the output, a condition known

as low dropout. The LTC1148 achieves

this by using a P-channel MOSFET

switch that can operate at up to 100%

duty cycle; in other words, it can

connect the output to the input in

dropout mode. This feature is impor-

tant because it allows the maximum

energy to be extracted from low volt-

age battery packs such as two

lithium-ion cells (5.4V typical end-of-

life voltage).

The LTC143X family changes to an

all N-channel output stage to accrue

the benefits of lower R

DS(ON)

and lower

cost than corresponding P-channel

MOSFETs. Driving N-channel MOS-

FETs requires the floating high-side

driver shown in Figure 3; however,

the bootstrap capacitor powering the

floating driver requires periodic re-

charging, which can occur only when

the top MOSFET is turned off and the

bottom MOSFET is turned on. In past

N-channel controllers, this recharge

interval was guaranteed by forcing a

minimum off-time during every oscil-

lator cycle.

To relieve the duty cycle limitation

resulting from minimum off-time con-

trol, the LTC1435–LTC1439 detect

the onset of dropout by counting the

number of oscillator pulses that have

passed without the top MOSFET turn-

ing off. Only when the count reaches

10 is a minimum off-time forced. This

extends the duty cycle capability from

around 90% to 99% while still guar-

anteeing that the top MOSFET

bootstrap capacitor remains charged.

Thus, dropout performance compa-

rable to the LTC1148 can be achieved.

Auxiliary Output

Voltages Made Easy

The new LTC143X family of DC/DC

controllers has also been designed

with many “hooks” to make the addi-

tion of extra output voltages easy, as

can be seen from two representative

applications. The first, shown in Fig-

ure 4, is a cost effective LTC1437

switcher/linear combination with 5V/

3A and 12V/200mA outputs. The

main switcher loop is set to 5V by

strapping the V

PROG

pin high. Other

output options include 3.3V (V

PROG

low) and adjustable (V

PROG

open).

The 12V output in Figure 4’s cir-

cuit is provided by the auxiliary linear

regulator operating in conjunction

with a secondary winding feedback

loop using the SFB pin mentioned

earlier. The turns ratio for the trans-

former is 1:2.2, resulting in a

secondary output voltage of approxi-

mately 15V. The secondary resistive

divider causes the SFB pin voltage to

drop below the internal 1.19V refer-

ence if the secondary output is loaded

and the 5V output has little or no

load. This forces continuous opera-

tion as necessary to guarantee

sufficient headroom for the linear

regulator to maintain 12V regulation

independent of the 5V load. The aux-

iliary output is turned on and off with

the AUX ON pin.

The auxiliary regulator can also be

used in an adjustable mode, deter-

mined by the voltage on the AUX DR

pin. When the AUX DR voltage is

higher than 9.5V, as is the case in

Figure 4, the regulator automatically

configures itself for fixed 12V opera-

tion using an internal AUX FB

resistive divider. When AUX DR is

less than 8.5V, the internal divider is

removed and the user can adjust the

output voltage via an external divider

referenced to 1.19V. The external aux-

iliary regulator PNP pass transistor is

sized for the desired output current;

SWITCH

DRIVE

FORCED MINIMUM

OFF-TIME

LOW-SIDE

DRIVER

BOOTSTRAP

CAPACITOR

FLOATING

HIGH-SIDE

DRIVER

VOUT

COUT

SENSE

÷10 COUNTER

CLOCK

RESET

OSCILLATOR

INT VCC VIN

Figure 3. Operation at up to 99% duty cycle is made possible by

10 counter logic, which ensures low dropout.

DESIGN FEATURES

Linear Technology Magazine • February 1996

in this case a SOT-223 device is used

to deliver up to 200mA.

Synchronizable, Triple-

Output, Low Dropout Supply

The LTC1439-based supply shown in

Figure 5 is an example of how three

logic supply voltages, 5V, 3.3V and

2.9V, can be easily derived using only

two simple inductors. The two main

DC/DC controller loops are used to

supply 5V/3A and 3.3V/5.5A. Up to

2.5A of the 3.3V output current is

then used to supply a 2.9V output

using the adjustable capability of the

auxiliary linear regulator.

The 2.9V output also illustrates

the use of an external NPN pass tran-

sistor with the auxiliary regulator.

Because only 0.4V is dropped across

the NPN transistor, 2.9V efficiency

remains in the 85% range. And thanks

to the 99% duty cycle capability of the

switcher loops, Figure 5’s supply can

maintain all three output voltages in

regulation down to V

= 5.2V with a

2A load on the 5V output.

The phase-locked loops built into

the LTC1437 and LTC1439 offer a

convenient means of synchronization

for the applications in Figures 4 and

5. The internal oscillator is actually a

voltage-controlled oscillator (VCO)

controlled by the voltage on the PLL

LPF pin. When no PLL IN signal is

present, the PLL LPF goes low, caus-

ing the oscillator to run at its minimum

frequency (f

MIN

= 180kHz with C

OSC

56pF). Applying a 3.3V or 5V logic

signal of any duty cycle to the PLL IN

pin will cause the oscillator frequency

to lock to the logic signal frequency

and to track it up to a maximum of

MAX

= 2 × f

MIN

. A logic signal may also

be coupled to PLL LPF to effect a 2:1

frequency shift, provided that the ini-

tial frequency has been set to less

than 200kHz.

Starting Up in Sequence

Power supply sequencing upon initial

application of input power is a critical

issue. This is particularly true in ap-

plications where the controllers are

left on continually, which will fre-

quently be the case since the quiescent

current is very low. The LTC143X

family has unique combined run and

soft-start pins and power-on-reset

10k 0.01µF

10k

51pF

28V (MAX)

OSC

PLL IN

PROG

PLL LPF

RUN/SS

LBO

POR

SFB

LBI

SENSE+

TGS

TGL

SENSE–

O SENSE

EXT V

AUX FB

AUX DR

BOOST

INT V

DR V

SGND PGND AUX ON

T1 = DALE LPE-8562-A092

*CENTRAL SEMICONDUCTOR



LTC1436

0.1µF

EXT.

CLOCK

56pF

510pF

IRF7403

IRLML2803

IRF7403

MBRS140

*CMDSH-3

1000pF

2.2µF

0.033Ω

OUT1

5V/3A

OUT2

12V/200mA

100µF

10V

×2

4.7µF

25V

0.1µF

3.3µF

35V

22µF

35V

×2

0.1µF

100

T1 MBRS1100

100k

47k

1MEG

ZETEX

FZT749

26V

Figure 4. High efficiency, constant-frequency, dual-output supply delivers 3A at 5V and 250mA at 12V.

DESIGN FEATURES

Linear Technology Magazine • February 1996

5.2V-25V

BG1

SENSE1+



SW1

BG1

TGS1

TGL1

SENSE1–

EXT V

PLL IN

TH1

PLL LPF

RUN/SS1

OSC

BOOST1

BG2

SENSE2+

SW2



TGS2

TGL2

SENSE2–

O SENSE2

AUX ON

TH2

AUX FB

RUN/SS2

AUX DR

BOOST2

SFB1 INT V

PROG1

PROG2

LB1 LB0 SGND PGND POR2

Si4412

IRLML2803

Si4412

MBRS140

*CMDSH-3

1000pF

0.1µF

1000pF

0.033Ω

100µF

10V

×2

22µF

35V

×2

0.1µF

100

10k 1000pF

LTC1439

0.1µF

EXT.

CLOCK

10µH

220pF

10k 0.01µF

56pF

Si4410

IRLML2803

Si4410

MBRS140

*CMDSH-3

1000pF

4.7nF

2.2µF

0.02Ω

OUT2

3.3V/3A

OUT3

2.9V/2.5A

OUT1

5V/3A

221k

47k

100

100µF

10V

×2

330µF

6.3V

0.1µF

22µF

35V

×2

0.1µF

100

10k

1000pF

0.05µF

10µH

220pF

51pF

316k

ZETEX

ZTX849

MMBT2907ALT1

*CENTRAL SEMICONDUCTOR

outputs that greatly ease start-up

sequencing and reset issues.

The RUN/SS pins have internal

3µA pull-ups whenever V

is present.

An external capacitor to ground is

charged by this current to provide

both a start delay and soft-start char-

acteristic. At initial application of

input power, or following a shutdown,

the RUN/SS voltage will be low. As

the RUN/SS voltage ramps up, the

associated controller remains shut

down until the voltage reaches 1.3V.

Thus by using different value capaci-

tors for the two RUN/SS pins in an

LTC1438 or LTC1439, one controller

can be forced to always start before

the other.

Once the RUN/SS voltage passes

1.3V, the controller starts with the

initial peak inductor current at ap-

proximately one third of its maxi-

mum value and ramps up from there,

reaching normal operation at 3V. Fig-

ure 6 is a photograph showing the

3.3V output staged to start 10ms

before the 5V output when power is

first applied to Figure 5’s circuit.

Power-On Reset

Monitor Included

An internal regulation monitor is

continually monitoring the main con-

troller output in the LTC1436/

LTC1437, and the controller 2 output

(3.3V in Figure 5) in the LTC1438/

LTC1439. When out of regulation or

in shutdown mode, the POR open

drain output pulls low. At start-up,

once the output voltage has reached

5% of its final value, an internal timer

is started, after which the POR pin is

released. The timer is accomplished

by counting 2

oscillator cycles, yield-

ing a delay-to-release reset of

approximately 300ms in a typical ap-

plication.

Figure 5. High efficiency, constant-frequency, triple-output logic supply features 200mV dropout.

Figure 6. Start-up of 3.3V and 5V supplies is

easily staged upon initial application of input

power.

DESIGN FEATURES

continued on page 22

Linear Technology Magazine • February 1996

New 12-Bit ADC Squeezes

100ksps from 10mW by William C. Rempfer

and Ringo Lee

Until now, 12-bit 100ksps ADCs

have needed as much as 100mW to do

their jobs. That has changed with the

new LTC1274 and LTC1277. These

complete, parallel-output 12-bit ADCs

sample at 100ksps while drawing only

10mW. They have some new features

that make them very attractive for

applications in the 100ksps range

and below:

❏Complete ADC with reference

and sample-and-hold

❏10mW power dissipation from 5V

or ±5V supplies

❏Nap and Sleep power-down

modes

❏Reference Ready (REFRDY) signal

indicating wake-up from Sleep

mode

❏Unipolar/bipolar conversions

❏Separate conversion-start input

❏High-Z analog inputs can be

MUXed or AC coupled

❏12-bit or 2-byte parallel I/O

❏3V logic supply interface

(LTC1277)

This article will describe the new

devices and show how they can be

used to save power, improve perfor-

mance and simplify the design of new

systems.

10mW, 100ksps and More

As Figure 1 shows, the LTC1274 and

LTC1277 come complete with a

switched capacitor ADC, a very wide

band sample-and-hold, a reference

and power-down circuitry. They pro-

vide parallel I/O in a 12-bit (LTC1274)

or 8-bit (LTC1277) format. In addi-

tion to the normal microprocessor

interface signals, they have conver-

sion start inputs and data ready

outputs for latching the parallel data

when the conversion is complete. Two

power-down modes are available: Nap

mode drops the supply current from

2mA to 160µA and provides instant

wake-up. Sleep mode drops supply

12-BIT

SWITCHED CAP

ADC

OUTPUT

LATCHES

CONTROL

LOGIC

AND

TIMING

POWER DOWN

CIRCUITRY

REFERENCE

SLEEPREFRDY

REF

2.42V

0V TO 4.096V

OR

±2.048V

D11

1212

LTC1274

BUSY

CONVST

+SAMPLE-

AND-HOLD

12-BIT

SWITCHED CAP

ADC

OUTPUT

LATCHES

CONTROL

LOGIC

AND

TIMING

POWER DOWN

CIRCUITRY

REFERENCE

NAP SLEEP

LOGIC



3V OR 5V

REFRDY

REF

2.42V

0V TO 4.096V

OR

±2.048V

D0/D8

LTC1277

BUSY

CONVST

HBEN

–

SAMPLE-

AND-HOLD 1212

current below 1µA, and has a longer

wake-up time. A power-good signal

(REFRDY) is provided to indicate when

wake-up from Sleep has been achieved

and to ensure that the system is oper-

ating correctly. The devices are

available in 24-pin SO-packages in

commercial and industrial tempera-

ture ranges.

New Features Save Power

Figure 2 shows how the LTC1274 and

LTC1277 add to LTC’s low power,

high speed ADC family. At 10mW,

these new ADCs have the lowest power

dissipation available today. In

Figure 1. The new ADCs come complete with wideband sample-and-hold and reference. They

sample at 100ksps on 10mW and provide novel power-down options.

DESIGN FEATURES

MAXIMUM SAMPLING RATE (sps)

100

200

POWER DISSIPATION (mW)

1.5M1M100k 500k

LTC 12-BIT PARALLEL SAMPLING ADCs

LTC1410

LTC1279

160mW + NAP/SLEEP

60mW + NAP

LTC1274/7

10mW + NAP/SLEEP

Figure 2. The LTC1274/LTC1277 offer very

low power consumption for applications at

100ksps and below.

Linear Technology Magazine • February 1996

addition, they have two power-down

modes that save even more power.

Take a Nap and

Wake Up Quickly

Table 1 shows the shutdown options

available. Nap mode allows the

LTC1277 to be powered down and

reawakened quickly. When NAP is

taken low, everything but the refer-

ence shuts down and the supply

current drops from 2mA to 160µA.

When NAP is brought back high, the

device wakes up instantly (400ns typi-

cal). Figure 3 shows the conversion

timing when using Nap mode. First,

NAP is taken high and one or more

conversions are performed. After the

last conversion, the NAP pin is taken

back low. This method can reduce the

power dissipation by a factor of up to

12.5 for slower sample rates (see Fig-

ure 4). At sample rates below 10ksps,

the current flattens out at the Nap-

mode value of 160µA.

Sleep Mode: More Restful

but Slower Wake-Up.

Power drain can be reduced even

further with Sleep mode. Taking

SLEEP low invokes a complete shut-

down of the ADC. The internal

reference powers off and the supply

current drops to less than 1µA. When

the reference is turned off, its output

bypass capacitor starts to discharge.

Bringing SLEEP high powers the

device back up. A wake-up time is

required for the internal reference to

slew its output back to the desired

value and settle. This time is rela-

tively slow and variable. It depends

on the reference bypassing and load-

ing, on the slewing current of the

internal reference and on how far the

reference has fallen away from its

desired value. The longer the device is

shut down, the farther the reference

output will discharge and the longer

the wake-up time will be. Depending

on these factors, Sleep-mode wake-

up time can vary from less than 1ms

to 40ms. conversion results may have been

erroneous.

The LTC1274 and LTC1277 solve

both problems with a new output

signal called REFRDY (reference

ready), which monitors the internal

reference and indicates when it has

settled. This signal tells the user ex-

actly when the system is ready to

convert. No extra power need be

wasted in some arbitrarily long delay

time. Also, full assurance is given

that the device is ready to go and that

the results will be accurate. Figure 5

shows the power-up sequence from

Sleep mode. The REFRDY signal indi-

cates readiness to convert.

Power the Reference

First, Then the ADC

The LTC1277 can save even more

power during wake-up from Sleep

mode. If a converter is awakened from

Sleep mode directly to full-power

mode, it draws its full supply current

as the reference slews. This is unnec-

essary and wastes power. The

NAP POWER OFF POWER ON POWER OFF

CONVST

WAKEUP TIME (400ns TYP.)

BUSY

CONVERSION TIME (6µs TYP.)

DATA OUTPUT OLD DATA AVAILABLE NEW DATA AVAILABLE

SAMPLE RATE (ksps)

160µA

1mA

2mA

SUPPLY CURRENT

100050

NAP MODE

BETWEEN

CONVERSIONS

ACTIVE MODE

Figure 3. The LTC1277 wakes up from Nap mode quickly, converts and is

then powered down. Data can be read at any time, even in shutdown.

Figure 4. Using Nap mode between conver-

sions cuts power by a factor of up to 12.5 as

the sample rate is reduced. Sleep mode cuts

power even more.

DESIGN FEATURES

How Do I Know You’re

Awake?... REFRDY!

In the past, ADCs with complete shut-

down (including the reference) have

offered no indication of when the

converter’s reference was powered up

and ready to operate. Users had to

wait some arbitrarily long time to

allow a worst-case device to wake up

under worst-case conditions. This

caused two problems: first, the full-

power drain of the converter was

wasted during this long delay time.

Even worse, since no assurance was

given that enough time had elapsed,

The LTC1274 and LTC1277

are attractive new

converters. They bring new

levels of power savings,

performance and versatility

to the 12-bit 100ksps

ADC arena

LTC1277 

LOGIC INPUTS

 OPERATING SUPPLY WAKE-UP

 NAP SLEEP MODE CURRENT TIME

 1 1 ACTIVE 2mA —

 0 1 NAP 160 µA 400ns

 X 0 SLEEP 0.3 µA 4ms

Table 1. LTC1277 Shutdown Options

Linear Technology Magazine • February 1996

LTC1277 can prevent this waste if the

REFRDY output is tied to the NAP

input (see Figure 6). This connection

allows the device to go from Sleep

mode to Nap mode until the reference

is ready. REFRDY then releases the

ADC from Nap mode and the device is

ready to convert. Figure 6 shows how

the converter draws only 160µA dur-

ing the reference settling time instead

of the full 2mA current. This can cut

power dissipation by a factor of two to

four in applications where Sleep mode

is used.

Unbeatable AC and DC

The LTC1274 and LTC1277 bring

unusually high performance to the

100ksps speed range. They offer ex-

cellent DC and AC specifications and

an extremely linear, wideband sample-

and-hold, which is suitable for

undersampling. DC specifications

include maximum INL and DNL of

±1LSB with no missing codes guaran-

teed. Figure 7 shows a typical linearity

of far better than 12 bits (typically 14

bits). Drift of the internal reference is

30ppm/°C max.

AC specifications such as signal to

noise and distortion (SINAD) and THD

are specified at 71dB and 76dB

minimum. These are very good speci-

fications for a 12-bit ADC, but the

impressive thing is that they are speci-

fied at twice the Nyquist frequency.

This AC performance is made pos-

sible by an extremely linear, wideband

sample-and-hold design. Figure 8

shows a plot of the ADC performance

as the analog input frequency is in-

creased. This is the real test of a

sample-and-hold because, as the

input frequency increases, the

sample-and-hold must slew faster

without distortion in order to track

the signal accurately. Also, at high

input slew rates, any excess aperture

jitter of the sample-and-hold shows

up as a degradation of the noise floor.

As the Figure shows, the devices excel

in this area with good noise and dis-

tortion at 1, 2, 5 or even 10 times the

Nyquist frequency.

SLEEP POWER OFF POWER ON POWER OFF

CONVST

REF

REFRDY

Simplify the System Design

The new converters have both analog

and digital features that make them

easier to use and eliminate external

hardware.



SLEEP

NAPV

REF

10µFREFRDY

SLEEP

REFRDY

LTC1277

OUTPUT CODE

–1.00

INTEGRAL NONLINEARITY ERROR (LSB)

–0.50

0.50

1.00

512 1024 1536 2048 2560 3072 3584 4096

SAMPLE

= 100kHz

SLEEP

ADC CURRENT

DRAIN

SLEEP

0.3µANAP

160µAPOWER ON

2mA 0.3µA

CONVST

REF

REFRDY = NAP

Figure 5. On power-up from Sleep mode, the REFRDY signal indicates when the ADC’s

reference has fully awakened from sleep mode and is ready for conversions.

Figure 7. Typical linearity is better than 12

bits (typically 14 bits). Linearity is guaran-

teed to be

1LSB maximum over temperature.

Figure 8. The LTC1274/LTC1277 can

accurately sample very wideband input

signals. Their SINAD and THD are nearly

theoretical at up to five times Nyquist and

still usable at ten times Nyquist.

INPUT FREQUENCY (Hz)

2 X NYQUIST

SIGNAL/(NOISE + DISTORTION), SINAD, (dB)

2M10k 100k 1M

THD

SINAD

VIN = 0dB

VIN = −20dB

VIN = −60dB

fSAMPLE = 100kHz

5 X NYQUIST

10 X NYQUISTNYQUIST

DESIGN FEATURES

Figure 6. Tying the LTC1277’s NAP input to its REFRDY output saves

power by delaying the turn-on of power until the reference is settled.

Linear Technology Magazine • February 1996

Analog Flexibility

Figure 9 shows some of the analog

features of the ADCs. Both devices

contain a sample and hold. The

LTC1277 has a differential input that

allows the input range to be offset.

The input range for both converters

automatically switches from 0V–

4.096V unipolar with V

grounded,

to ±2.048V bipolar when V

is tied to

−5V. The internal reference can be

overdriven with an external 2.5V ref-

erence to improve the full-scale

temperature coefficient. In bipolar

mode, the reference pin can be driven

with an op amp to provide a 2:1 AGC

function.

The analog inputs are high imped-

ance, making them easy to multiplex

with an inexpensive CMOS MUX. No

errors are caused because no DC

currents are drawn through the MUX’s

on resistance. The high-Z inputs also

eliminate the AC-coupling problems

found on competitive devices. (Many

of these other converters use inter-

nal, resistive level shifters to generate

bipolar input spans. These internal

resistors charge up the AC-coupling

cap and pull the input up toward full

scale; as a result, part of the signal

gets clipped.) To AC couple the

LTC1274 and LTC1277, simply use a

series C and an R to ground (or to

wherever you desire the DC level to

be) on the analog input.

Digital Simplicity

The digital interface is shown in Fig-

ure 10. In addition to the well known

microprocessor interface signals (CS,

RD, etc.), the LTC1274 and LTC1277

provide several new signals. A sepa-

rate convert-start input (CONVST)

allows operation from an external

sample clock, if desired. This frees

the microprocessor from having to

request conversions at precise sample

intervals, which is often impossible.

In this mode, the sample signal starts

a conversion. When it is complete, the

ADC interrupts the microprocessor

(with the BUSY signal) and the

microprocessor reads the data asyn-

AC COUPLING

CD4051

OR

LTC1391

Hi Z

MUXABLE

INPUT A

–

OFFSET

BIPOLAR

MODE

UNIPOLAR

MODE

REF

INTERNAL

REFERENCE

EXTERNAL

REFERENCE

2.5V TO 5V

2:1 AGC 

GAIN ADJUST

2.5V

–5V

LTC1277

–

DATA

OUTPUTS

BUSY

LOGIC

REFRDY

8-BIT BUS (1277)

OR

12-BIT DATA (1274)

INTERRUPT TO µP

OR LATCH SIGNAL FOR

DATA OUTPUT

3V LOGIC INTERFACE

SUPPLY (1277)

CONVERSION READY

SIGNAL TO µP

CONVST

OPERATES FROM

EXTERNAL SAMPLE

CLOCK OR µP

Figure 9. Analog flexibility includes easy AC coupling and MUXing, offsetting the input span,

unipolar or bipolar inputs and a reference pin that can be overdriven.

chronously. Alternatively, CONVST

can be tied to RD, which allows the

microprocessor to read data and start

conversions in the old fashioned way.

Output data is available as a 12-bit

word (LTC1274) or as two 8-bit bytes

(LTC1277). Both converters have

BUSY signals that indicate when out-

put data is ready to be latched. An

output logic supply allows the

LTC1277 to interface directly to 3V

systems.

Conclusion

The LTC1274 and LTC1277 are at-

tractive new converters. They bring

new levels of power savings, perfor-

mance and versatility to the 12-bit

100ksps ADC arena. Their 10mW

power levels and novel shutdown

modes must be considered by power-

sensitive designers. The clean

wideband sampling capability and low

noise make them ideal for signal-

capture applications. And the flexible

feature set can simplify the system

design. These devices are a “must

see” for users of sampling ADCs.

DESIGN FEATURES

Figure 10. The digital hookup is simple, with

an external conversion start input, 8- or 12-

bit data outputs, data-ready signal (BUSY),

reference-ready signal (REFRDY) and a 3V

logic-interface supply (LTC1277).

Authors can be contacted

at (408) 432-1900

Linear Technology Magazine • February 1996

The LT1511 3A Battery Charger

Charges All Battery Types,

Including Lithium-Ion by Chiawei Liao

The LT1511 current mode PWM

battery charger is the simplest, most

efficient solution for fast charging

modern rechargeable batteries,

including lithium-ion (Li-Ion),

nickel-metal-hydride (NiMH) and

nickel-cadmium (NiCd) that require

constant-current and/or constant-

voltage charging. The internal switch

is capable of delivering 3A DC current

(4A peak current). Full charging cur-

rent can be programmed by resistors

or by a DAC to within 5%, and the

trickle charge current can be pro-

grammed to 10% accuracy. With

0.5% reference voltage accuracy,

the LT1511 meets the critical

–

0.7V

1.5V

BAT

REF

GND

SLOPE COMPENSATION

PWM

CA2

–

CA1

–

6.7V

REF

2.465V

SHUTDOWN

200kHz

OSCILLATOR

R1

PROG

OUT

BOOST

SENSE

SPIN

BAT

PROG

BAT

0VP

BAT

PROG

BAT

= (I

PROG

)(R

)

PROG

75k

= 0.64

Ω

–

CL1

CLP

100mV

CLN

COMP1

COMP2

= R

)

2.465V

PROG



(())

Figure 1. LT1511 block diagram

DESIGN FEATURES

Linear Technology Magazine • February 1996

100mV

–

500Ω

CLP

CLN

LT1511

1µF

CL1

AC ADAPTER

OUTPUT



= 100mV

ADAPTER CURRENT LIMIT

Figure 2. Adapter current limiting

Figure 3. PWM current programming

lower current, I

PROG

, fed into the PROG

pin. Amplifier CA2 compares the out-

put of CA1 with the programmed

current and drives the PWM loop to

force them to be equal. High DC accu-

racy is achieved with averaging

capacitor C

PROG

. Note that I

PROG

has

both AC and DC components. I

PROG

goes through R1 and generates a ramp

signal that is fed to the PWM control

comparator C1 through buffer B1 and

level-shift resistors R2 and R3, form-

ing the current mode inner loop. The

Boost pin drives the switch NPN Q

into saturation and reduces power

loss. For batteries such as lithium-

ion that require both constant-current

and constant-voltage charging, the

0.5%, 2.465V reference and the am-

plifier VA reduce the charging current

when the battery voltage reaches the

preset level. For NiMH and NiCd, VA

can be used for overvoltage protec-

tion. When the input voltage is not

present, the charger goes into low

current (3µA typically) sleep mode as

the input drops 0.7V below the bat-

tery voltage. To shut down the charger,

simply pull the V

pin low with a

transistor.

Adapter Limiting

An important feature of the LT1511 is

the ability to automatically adjust

charging current to a level that avoids

overloading the wall adapter. This

allows the product to operate at the

same time that batteries are being

charged, without requiring complex

load-management algorithms. Addi-

tionally, batteries will automatically

be charged at the maximum possible

rate of which the adapter is capable.

This feature is created by sensing

total adapter output current and ad-

justing charging current downward if

a preset adapter-current limit is ex-

ceeded. True analog control is used,

with closed-loop feedback ensuring

that adapter load current remains

within limits. Amplifier CL1 in Figure

2 senses the voltage across R

. When

this voltage exceeds 100mV, the am-

plifier will override the programmed

charging current and limit adapter

current to 100mV/R

. A lowpass fil-

ter formed by 500Ω and 1µF is required

to eliminate switching noise.

Charging Current

Programming

The basic formula for charging cur-

rent is

BAT

= I

PROG

2.465V

PROG

where R

PROG

is the total resistance

from PROG pin to ground.

For example, 3A charging current

is needed. To have low power dissipa-

tion in R

and enough signal to drive

the amplifier CA1, let R

= 100mV/

3A = 0.0033Ω. This limits R

power

to 0.3W. Let R

PROG

= 5k, then

= R

= (I

BAT

)(R

PROG

)(R

)

2.465V

(3A)(5k)(0.033)

2.465V

== 200Ω



Charging current can also be pro-

grammed by pulse-width modulating

PROG

at a frequency higher than a few

kHz (Figure 3). Charging current will

be proportional to the duty cycle of

the switch, with full current at 100%

duty cycle.

PWM

PROG

4.7k

300Ω

PROG

PROG

1µF

Q1

VN2222

LT1511

BAT

= (DC)(3A)

constant-voltage charging require-

ment for lithium cells.

The LT1511 is equipped with a

voltage-control loop to control charg-

ing voltage and a current-control loop

to control charging current. A third

control loop is provided to regulate

the current drawn from the AC

adapter. This allows simultaneous

equipment operation and battery

charging without overloading the

adapter. Charging current is reduced

to keep the adapter current within

specified levels.

The LT1511 can charge batteries

ranging from 1V to 20V. Ground sens-

ing of current is not required and the

battery’s negative terminal can be

tied directly to ground. A saturating

switch running at 200kHz gives high

charging efficiency and small induc-

tor size. A blocking diode is not

required between the chip and the

battery because the chip goes into

sleep mode and drains only 3µA when

the wall adapter is unplugged. Soft-

start and shutdown features are also

provided. The LT1511 is available in

a 24-pin fused-lead power SO wide

package with a thermal resistance of

30°C/W.

Operation

The LT1511 is a current mode PWM

step-down (buck) switcher. The DC

battery-charging current is pro-

grammed by a resistor, R

PROG

(or by a

DAC output current), at the PROG

pin (see the block diagram in Figure

1). Amplifier CA1 converts the charg-

ing current through R

to a much

DESIGN FEATURES

Linear Technology Magazine • February 1996

R2

5.49k

R1

49.3k

PROG

0.33µFQ1

VN2222

LT1511



Lithium-Ion Charging

The 3A lithium battery charger (Fig-

ure 4) charges lithium-ion batteries

at a constant 3A until the battery

voltage reaches a limit set by R3 and

R4. The charger will then automati-

cally go into a constant-voltage mode,

with the current decreasing to zero

over time as the battery reaches full

charge. This is the normal regimen

for lithium-ion charging, with the

charger holding the battery at “float”

voltage indefinitely. In this case no

external sensing of full charge is

needed.

Current though the R3/R4 divider

is set at 15µA to minimize battery

drain when the charger is off. The

input current to the OVP pin is 3nA

and this error can be neglected.

With divider current set at 15µA,

R4 = 2.465/15mA = 162k and

R3 = (R4)(V

BAT

− 2.465) 162k(8.4 − 2.465)

2.465 2.465

= 390k

Lithium-ion batteries typically re-

quire float-voltage accuracy of 1% to

2%. The accuracy of the LT1511 OVP

voltage is ±0.5% at 25°C and ±1% over

full temperature. This leads to the

possibility that very accurate (0.1%)

resistors might be needed for R3 and

R4. Actually, the temperature of the

LT1511 will rarely exceed 50°C in

float mode because charging currents

have tapered off to a low level, so

0.25% will normally provide the re-

quired level of overall accuracy.

Nickel-Cadmium and Nickel-

Metal-Hydride Charging

The circuit in the 3A lithium battery

charger (Figure 4) can be modified as

shown in Figure 5 to charge NiCd or

NiMH batteries. For example, two-

level charging is needed; 2A when Q1

is on and 200mA when Q1 is off. For

2A full current, the current sense

resistor (R

) should be increased to

0.05Ω, so that enough signal (10mV)

will be across R

at 0.2A trickle charge

to keep charging current accurate.

For a two-level charger, R1 and R2

are found from

R1 = R2 =

(2.465)(4000) (2.465)(4000)

LOW



− I

LOW

All battery chargers with fast charge

rates require some means to detect

the full-charge state in the battery in

order to terminate the high charging

current. NiCd batteries are typically

charged at high current until tem-

perature rise or battery voltage

decrease is detected as an indication

of nearly full charge. The charging

current is then reduced to a much

lower value and maintained as a con- Figure 5. 2-step charging



SW

BOOST

COMP1



CLN



UV

PROG

OVP SENSE BAT

C1

1µF



ADAPTER CURRENT SENSE



500Ω

†



UNDERVOLTAGE LOCKOUT

R6

(ADAPTER INPUT)

11V TO 25V

BAT

10µF

PROG

1µF

*

10µF

300ΩR

PROG

4.93k

0.33µF

0.47µF

S3

200Ω

S2

200Ω

L1**

10µH

D2

1N4148 200pF

S1

0.033Ω

BATTERY CURRENT

SENSE



390k

0.25%

BATTERY 

VOLTAGE SENSE



162k

0.25%

50pF

OUT



22µF

TANT

4.2V

LT1511

NOTE: COMPLETE LITHIUM-ION CHARGER,

NO TERMINATION REQUIRED. R

, R7 

AND C1 ARE OPTIONAL FOR I

LIMITING

*TOKIN 25V CERAMIC SURFACE MOUNT

**10µH COILTRONICS CTX10-4

†

CONSULT LT1151 DATA SHEET FOR R5 VALUE

TO MAIN SYSTEM POWER

SPIN

D1

MBR340

GND CLP

2 Li-Ion

Figure 4. 3 Amp lithium-ion battery charger

stant trickle charge. An intermediate

“top off” current may be used for a

fixed time period to reduce 100%

charge time.

NiMH batteries are similar in chem-

istry to NiCd but have two differences

related to charging. First, the inflec-

tion characteristic in battery voltage

as full charge is approached is not

nearly as pronounced. This makes it

more difficult to use dV/dt as an

indicator of full charge, and tempera-

ture change is more often used, with

a temperature sensor in the battery

pack. Second, constant trickle charge

may not be recommended. Instead, a

moderate level of current is used on a

pulse basis (1% to 5% duty cycle) with

the time-averaged value substituting

for a constant low trickle.

If overvoltage protection is needed,

R3 and R4 should be calculated ac-

cording to the procedure described in

lithium-ion charging section. The OVP

DESIGN FEATURES

continued on page 22

Linear Technology Magazine • February 1996

LTC1520 High Speed Line Receiver

Provides Precision Propagation Delay

and Skew by Victor Fleury

Introduction

The LTC1520 is a 50Mbit/s, low

power, precision quad line receiver

that translates differential input sig-

nals into CMOS/TTL output logic

levels. The receivers employ a unique

architecture that guarantees excel-

lent performance over process and

temperature, with propagation delay

of 18ns ±2ns. The architecture af-

fords low same-channel skew (|t

PHL

PLH

| < 600ps), and low channel-to-

channel propagation-delay variation

(< 600ps). A new short-circuit detec-

tion technique permits indefinite

shorts to power or ground.

Circuit Description

Short-channel CMOS circuitry typi-

cally has very wide performance

variations. This is due in part to the

large percentage variation in channel

length and to second-order mobility

and threshold effects. Increasing

channel length not only decreases

the drive capability of CMOS devices,

but also increases the devices’ gate

capacitance (less current charging

more capacitance). In effect, we see

CMOS propagation delays varying as

(square of the channel length). For

example, the propagation delay of

typical CMOS line receivers can vary

as much as 500% over process and

temperature. In applications where

high speed clock and data waveforms

are sent over long distances, propa-

gation delay and skew uncertainties

pose system design constraints. The

LTC1520 addresses this problem. The

propagation delays change by ±20%,

a better than 10 times performance

improvement.

The design was fabricated using

Linear Technology’s high performance

CMOS process. The CMOS design

makes it possible to achieve high speed

and low DC power consumption with-

out sacrificing ruggedness against

overload or ESD damage. CMOS also

allows for tighter propagation-delay

skew. Figure 1 shows a block diagram

of the LTC1520 signal path. The in-

put differential pair amplifies the

minimum 500mV (at speed) input

signal level. Note the input resistor

network, which expands the input

common mode range (the LTC1520

has an input common mode range

extending from 0V to 5V, whereas the

LTC1518 and LTC1519 are future

products that will have an input com-

mon mode range from −7V to +12V).

The output is fed into another differ-

ential amplifier that switches a

specified amount of current into its

load capacitance. These two stages

must have enough gain to switch all

the available current. The output of

the second stage is a valid logic level

that feeds inverters.

High Data Rates

The LTC1520 can propagate pulses

(Figure 2) of shorter duration than its

propagation delay (20ns maximum).

To obtain this high data rate (through-

put), it is necessary to distribute the

total propagation delay as evenly as

possible between the stages. This al-

lows rail-to-rail swing at the output of

each stage. For example, if the output

of the second stage has a 3V to 5V

output swing, the succeeding inverter

will never trip high. The minimum

number of stages is also limited by

the maximum rise/fall times allowed

at the output (~3.5ns). However, the

–

IN+

DIFF

BIAS 4BIASTRIM

–

GM OUT OUTPUT

IN−

PROPTRIM



Figure 1. LTC1520 block diagram

DESIGN FEATURES

Linear Technology Magazine • February 1996

maximum number of stages is limited

by the maximum propagation delay

(latency).

Consistent

Propagation Delay

The inherent temperature and pro-

cess tolerance, along with bias and

delay trimming, make it possible to

guarantee a propagation delay win-

dow more than an order of magnitude

tighter than that of the typical CMOS

line receiver.

Temperature Stability

For large V

and a given channel

length, the propagation delay of in-

verters increases with temperature.

To keep temperature stability, the

first two stages must have a delay

that decreases with temperature. This

was accomplished via a current source

whose current is inversely pro-

portional to mobility. Therefore,

with increasing temperatures, the

inverter’s delay goes up as the delays

of the first two stages go down.

Process Tolerance

At a given temperature and V

, the

inverter delays vary as µC

W/L. The

delays of the first and second stages

vary inversely with µC

W/L. The

effect of process variations on total

propagation delay are canceled out to

the extent that we are able to match

the µC

W/L of the bias, inverters

and differential stages. We include

trims in both the bias network and in

the signal path. For short channel

length processes, we add capacitance

evenly between one inverter and the

second differential stage to maintain

temperature stability.

Low Skew

Skew is typically caused by the un-

equal charging versus discharging of

both internal and external capaci-

tances. Unequal excitation of high

frequency zeroes also contributes to

skew. Therefore, it is necessary to

keep the signal in differential form as

much as possible. The first stage is

differential-in/differential-out. It

switches a multiple of the tail current

into its capacitive load. Two differen-

tial stages are used to maintain

charging versus discharging symme-

try and to equalize feedthrough effects.

Figure 3 shows two adjacent channels.

Low Overshoot

The LTC1520 can achieve maximum

speeds with all four receivers operat-

ing simultaneously (500mV input

differential signal), while maintain-

ing low output overshoot. Small

on-chip resistors help mitigate the

effect of parasitic bond wire and lead-

frame inductances. Note that the

system designer also needs to mini-

mize printed circuit board parasitic

inductances by placing surface mount

ceramic bypass capacitors very close

to the LTC1520. Low overshoot and

ringing is desirable to reduce electro-

magnetic interference.

Short-Circuit Protection

and Automatic Reset

Typical foldback short-circuit protec-

tion can lead to oscillation, slower

rise/fall times and exaggerated skew.

This family’s novel short-circuit pro-

tection method avoids these problems

by sensing the output voltage. If the

output remains in the wrong state for

longer than about 60ns, the output is

shut off and a small, known current

(~20mA, positive or negative, depend-

ing on V

/Gnd short) is dumped into

the output. The circuit then detects

when the short is removed and takes

itself out of short-circuit mode. This

avoids having to power the part up/

down after detecting a short.

NOTE: STUBS CONNECTED TO R

MUST BE EQUIDISTANT AND SHORT.

MC10116

TWISTED PAIR

100

120ΩR

1/4

LTC1520

1/4

LTC1520

1/4

LTC1520

Figure 2. Typical propagation delay: V

500mV, 15ns pulse width Figure 3. Typical channel-to-channel

propagation delay is <600ps. (Two channels

are overlaid here; the differences cannot be

distinguished on this oscillograph.)

Figure 4. Typical LTC1520 application

DESIGN FEATURES

continued on page 23

5ns/DIV

Linear Technology Magazine • February 1996

The LTC1446 and LTC1446L:

World’s First Dual 12-Bit DACs

in SO-8 Packages by Hassan Malik and

Jim Brubaker

Dual 12-Bit Rail-to-Rail

Performance in a Tiny SO-8

The LTC1446 and LTC1446L are dual

12-bit, single-supply, rail-to-rail

voltage output digital-to-analog con-

verters. Both of these parts include

an internal reference and two DACs

with rail-to-rail output buffer amplifi-

ers, packed in a small, space-saving

8-pin SO or PDIP package. These are

12-bit monotonic DACs with DNL

guaranteed to be less than 0.5LSB.

They have an easy-to-use SPI-com-

patible interface, with a digital output

pin that allows several DACs to be

daisy-chained to save board space. A

power-on reset initializes the outputs

to zero-scale at power-up.

The LTC1446 has an output swing

of 0V to 4.095V, making each LSB

equal to 1mV. It operates from a single

4.5V to 5.5V supply, dissipating

3.5mW (I

typical = 700µA). The

LTC1446L has an output swing of 0V

to 2.5V. It can operate on a single

supply with a wide range of 2.7V to

5.5V. It dissipates 1.35mW (I

typi-

cal = 450µA) at a 3V supply.

Circuit Topology

Complete Stand-Alone

Performance

Figure 1 shows a block and pin dia-

gram of the LTC1446 and LTC1446L.

Both parts have rail-to-rail output

buffer amplifiers and an internal ref-

erence, offering the user convenient

stand-alone performance. The data

inputs for both DAC A and DAC B are

clocked into one 24-bit shift register.

The first 12-bit segment is for DAC A

and the second is for DAC B. The MSB

is loaded first and LSB last in both of

these 12-bit segments. The data is

latched into the shift register on the

rising edge of clock. The clock pin has

a hysteresis of about 150mV to make

it less sensitive to noise. When all the

data has been shifted in, it is loaded

into the DAC registers when CS/LD

goes high. This also updates both 12-

bit DACs and internally disables the

CLK signal. Data in the 24-bit shift

OUT

pin, allowing the user to daisy-chain

several DACs together. An internal

power-on reset clears the shift regis-

–

24-BIT

SHIFT

POWER ON

RESET

DAC

B

DAC

A

REFERENCE

12-BIT

DAC-B V

OUTB

–

12-BIT

DAC-A V

OUTA

6 GND

1CLK

OUT

3CS/LD

Figure 1. 12-bit rail-to-rail performance in an SO-8 package

DESIGN FEATURES

Linear Technology Magazine • February 1996

ters and DAC registers to all zeros

and forces both the buffer amplifier

outputs to zero-scale. The LTC1446L

has an internal reference of 1.22V

and the amplifier gain is about 2.05,

giving a convenient full scale of 2.5V.

The LTC1446 reference is 2.048V and

the amplifier gain is 2.0, giving it a full

scale of 4.095V.

Patented Architecture

Guarantees Monotonicity

The LTC1446 family uses a propri-

etary architecture that was first used

in the LTC1257 and is described in

more detail in Volume III, Number 3 of

Linear Technology. This novel archi-

tecture is inherently monotonic and

has excellent 12-bit DNL, with a maxi-

mum specification of 0.5LSB.

LTC1296

50k

74HC04

22µF

µPCLK

8 ANALOG

INPUT CHANNELS

OUT

CH0

COM

SSO REF–

CH7

REF+

50k

0.1µF

100Ω

LTC1446

CS/LD

CLK

OUT

OUTB

GND

OUTA

0.1µF

Figure 2. Typical application for the LTC1446L or LTC1446

Figure 3. An autoranging 8-channel ADC with shutdown

LTC1446L/1446

CLK LTC1446L: 0V TO 2.5V

LTC1446: 0V TO 4.095V

LTC1446L: 2.7V TO 5.5V

LTC1446: 4.5V TO 5.5V

LTC1446L: 0V TO 2.5V

LTC1446: 0V TO 4.095V

0.1µF

µP

CS/LD

OUT

OUTB

GND

OUTA

High Performance

Rail-to-Rail Buffers

The rail-to-rail amplifiers on these

parts can swing to within a few milli-

volts of either rail when unloaded,

giving them true rail-to-rail perfor-

mance. When swinging close to the

rails, the effective output impedance

is about 50Ω. The op amps are ca-

pable of sinking or sourcing over 5mA

at a 5V supply. The mid-scale glitch at

the output is 20nV-s and the digital

feedthrough is a negligible 0.15nV-s.

DESIGN FEATURES

continued on page 23

The LTC1446 and

LTC1446L are the world’s

only DACs that offer dual

12-bit stand-alone

performance in an 8-pin

SO or PDIP package.

…these DACs

do not compromise

on performance…

A Wide Range of Applications

Some of the typical applications for

these parts include digital calibra-

tion, industrial process control,

automatic test equipment, cellular

telephones and portable, battery-pow-

ered applications. Figure 2 shows how

these parts are typically used.

An Autoranging 8-Channel

ADC with Shutdown

Figure 3 shows how to use one

LTC1446 to make an autoranging

ADC. The microprocessor sets the

reference span and the common pin

for the analog input by loading the

appropriate digital code into the

LTC1446. V

OUT A

controls the com-

mon pin for the analog inputs to the

LTC1296 and V

OUT B

controls the ref-

erence span by setting the REF+ pin

on the LTC1296. The LTC1296 has a

shutdown pin that goes low in shut-

down mode. This will turn off the PNP

transistor supplying power to the

LTC1446. The resistor and capacitor

on the LTC1446 outputs act as a

lowpass filter for noise.

Authors can be contacted

at (408) 432-1900

Linear Technology Magazine • February 1996

LT1490/LT1491 Over-the-Top

Dual and Quad Micropower

Rail-to-Rail Op Amps by Jim Coelho-Sousae

Introduction

The LT1490 is Linear Technology’s

lowest power, lowest cost and small-

est dual rail-to-rail input and output

operational amplifier. The ability to

operate with its inputs above V

, its

high performance-to-price ratio and

its availability in the MSOP package,

sets the LT1490 apart from other

amplifiers. A unique input stage al-

lows the LT1490 to operate with input

common mode voltages up to 30V

above the positive supply. The LT1490

has a quiescent current of less than

50µA per amplifier, and can operate

with supply voltages from 2.5V to

44V. The ability to withstand reverse

supply voltages of up to 25V is an-

other unique feature of the LT1490.

For single 5V supply operation, typi-

cal specifications include 300µV input

offset voltage, 3nA input bias cur-

rent, 200pA input offset current,

open-loop voltage gain of one million

into a 10k load, 0.07V/µs slew rate,

100dB common mode rejection ratio

and 98dB power supply rejection ra-

tio. The output can swing to within

22mV of either rail with no load. The

output current drive is typically

±20mA, and the part is stable with

capacitive loads of up to 5000pF.

Additional performance specifications

are shown in Table 1.

The LT1490 dual is available with

industry-standard pinout in 8-pin

MSOP, 8-pin SO or 8-pin mini-DIP

packages. The LT1491 quad is avail-

able with industry-standard pinout

in 14-pin SO or 14-pin mini-DIP

packages.

Going Over the Top

Key to the unique operation of the

LT1490 is the input stage, shown in

Figure 1. Similar to other rail-to-rail

op amps, the LT1490 uses two input

stages to achieve input rail-to-rail

operation. Device Q7 controls which

stage is active by steering the tail

current between the two stages as a

function of the input common mode

voltage. The LT1490 has three modes

of operation.

Mode 1: V

< V

− 1V

For input common mode voltages

between V

and V

− 1V, the PNP

stage (Q5–Q6) is active, and Q7 and

the NPN stage (Q1–Q4) are off. Since

Q7 is off, 2µA of current flows through

Q5–Q6. The input bias current is the

base current of Q5 or Q6, typically

4nA, as shown in Figure 2. The input

offset voltage for this stage is trimmed

to less than 300µV.

Mode 2: V

− 1V < V

< V

When the input common mode volt-

age reaches V

− 1V, Q7 turns on,

diverting the current from Q5–Q6 to

the NPN stage. When the PNP stage is

completely off, 2µA flows through the

2× current mirror D3–Q8. The 4µA

current through Q8 sets the bias for

the NPN input stage. In this mode,

Q1–Q2 act as emitter followers, driv-

ing a differential amplifier formed by

Q3–Q4. The input bias current for

this mode of operation is the base

current of Q1 or Q2, typically 20nA.

When the common mode voltage

reaches V

− 0.2V, Q1–Q2 begin to

saturate due to the forward voltage of

D1–D2, as shown in Figure 2. This

DESIGN FEATURES

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V3=V

V5=V

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Linear Technology Magazine • February 1996

causes the input bias current to in-

crease. At V

= V

the input bias

current is typically 200nA. The input

offset voltage of the NPN stage is not

trimmed, but is typically 600µV.

Mode 3: V

< V

+ 44V

As Figure 2 shows, when V

= V

the NPN input stage is beginning to

saturate but is not yet fully satu-

rated. When V

is approximately

equal to V

+ 0.2V, Schottky diodes

D1–D2 reverse bias, causing Q1–Q2

to fully saturate. In this condition,

the base current of Q1–Q2 is equal to

the emitter current, typically 4µA.

The Schottkys, in combination with

special geometries for the input de-

vices Q1–Q2, are the key to the unique

above-the-rail operation of the

LT1490. The input offset voltage for

this mode of operation is typically

600µV.

Reverse Battery Protection

The LT1490 can withstand reverse

supply voltages of up to 25V. The

inputs are also protected for excur-

sions below V

. The protection

consists of a 1k resistor in series with

each input, which limits the current

through the associated substrate di-

ode. The part will not be damaged if

the current through the substrate

diode is less than 10mA.

An Over-the-Top Application

The battery current monitor circuit

shown in Figure 3 demonstrates the

LT1491’s ability to operate with its

inputs above the positive supply rail.

COMMON MODE VOLTAGE (V)

–10nA

20nA

10nA

0nA

30nA

4µA

2µA

6µA

INPUT BIAS CURRENT

5.63.8 4.0 4.2 4.4 4.8 5.0 5.2 5.44.6

MODE 3

MODE 1

MODE 2

= 5V, 0V

TO SECOND STAGE

Q4 Q7

–IN

D1 D2 2µA

Q3 V

CC–



1.0V

Q2 Q6

+IN

In this application, a conventional

amplifier would be limited to a battery

voltage between 5V and ground, but

the LT1491 can handle battery volt-

ages as high as 44V. The LT1491 can

be shut down by removing V

. With

removed the input leakage is less

than 0.1nA. No damage to the LT1491

will result from inserting the 12V

battery backward.

When the battery is charging, Amp

B senses the voltage drop across RS.

The output of Amp B causes QB to

drain sufficient current through RB

to balance the inputs of Amp B. Like-

wise, Amp A and QA form a closed

loop when the battery is discharging.

The current through QA or QB is

proportional to the current in RS; this

current flows into RG, which converts

it back to a voltage. Amp D buffers

and amplifies the voltage across RG.

Amp C compares the output of Amp A

–

1/4

LT1491

–

1/4

LT1491

RA

RS

0.2Ω

CHARGER

VOLTAGE

BATTERY

= 12V

SUPPLY

= 5V, 0V

LOGIC

RA'

–

1/4

LT1491

–

1/4

LT1491

RB

RB'

90.9k

RG

10k

S1 S1 = OPEN, GAIN = 1

S1 = CLOSED, GAIN = 10

LOGIC HIGH (5V) = CHARGING

LOGIC LOW (0V) = DISCHARGING

NOTE: RA = RB

OUT

RS RG/RA GAIN

OUT

GAIN

()

(

)



BATTERY



= = AMPS

Figure 1. LT1490 input stage

Figure 2. Input bias current characteristics

over all three modes of operation

Figure 3. LT1491 battery current monitor—an “over-the-top” application

DESIGN FEATURES

continued on page 22

Linear Technology Magazine • February 1996

LT1512/LT1513 Battery Chargers

Operate with Input Voltages Above or

Below the Battery Voltage by Bob Essaff

Introduction

The LT1512 and LT1513 form a

unique family of constant-current,

constant-voltage battery chargers that

can charge batteries from input volt-

ages above or below the battery

voltage. This feature can help sim-

plify system design and add product

flexibility by allowing battery charg-

ing from multiple sources, such as a

wall adapter, a 12V automotive sys-

tem or a 5V power supply, all with the

same circuit. The constant-current,

constant-voltage architecture makes

the LT1512 and LT1513 well suited

for charging NiCd, NiMH, lead-acid or

lithium-ion batteries.

Both devices are current mode

switching regulators that operate at a

fixed frequency of 500kHz. Product

features include a ±1% reference-volt-

age tolerance, 2.7V minimum input

voltage, easy external synchroniza-

tion and 12µA supply current in

shutdown mode. The LT1512 and

LT1513 also include low loss on-chip

power switches rated for 1.5 Amps

and 3 Amps respectively. High fre-

quency switching allows the use of

small surface mount inductors and

capacitors, and the battery can be

directly grounded.

Operation

The LT1512 and LT1513 are specifi-

cally optimized to use the SEPIC

converter topology, which is shown in

Figure 1’s typical application. The

SEPIC (single-ended primary induc-

tance converter) topology has several

advantages for battery-charging ap-

one inductor core, although two sepa-

rate inductors can be used.

The topology is essentially identi-

cal to a 1:1 transformer-flyback circuit

except for the addition of capacitor

C2, which forces identical AC volt-

ages across both windings. This

capacitor performs three tasks: it

eliminates the power loss and voltage

spikes usually caused by a flyback-

converter’s leakage inductance; it

forces the input current and the cur-

rent in resistor R3 to be a triangle

wave riding on top of a DC component

instead of forming a large amplitude

square wave; and it eliminates the

voltage spikes across the output di-

ode when the switch turns on.

When the battery is below its float

voltage, set by R1 and R2, the charger

is in the constant-current mode. The

suggested value for R2 is 12.4k. R1 is

calculated from:

R1 = V

OUT

− 1.245

1.245

R2 + (3 × 10

−7

)

where V

OUT

= battery float voltage

Charging current in the battery,

which also flows through R3, devel-

ops a voltage on the I

pin. The I

pin’s 100mV sense voltage sets the

LT1512

CHARGE

SHUTDOWN I

L1A*

L1B*

0.5A

•

GND

WALL

ADAPTER

INPUT

S/S

C3

22µF

25V

C2**

1µF

× 2

C5

0.1µF

*

L1A, L1B ARE TWO 33µH WINDINGS ON A

COMMON CORE: COILTRONICS CTX33-3

AVX1206Y2105KAT1A

C4

0.1µF

R4

24Ω

R3

0.2Ω

C1

22µF

25V

D1

MBRS130LT3

INDUCTOR = 33µH

LT1513

LT1512

INPUT VOLTAGE (V)

1.2

1.0

0.8

0.6

0.4

0.2

1.4

1.6

2.0

1.8

2.2

2.4

CURRENT (A)

300 5 10 20 2515

SINGLE LITHIUM 

CELL (4.1V)

SINGLE LITHIUM 

CELL (4.1V)

DOUBLE LITHIUM 

CELL (8.2V)

DOUBLE LITHIUM 

CELL (8.2V)

Figure 1. Battery charger with 0.5A output current

Figure 2. Maximum charging current

DESIGN FEATURES

The LT1512 and LT1513

form a unique family of

constant-current, constant-

voltage battery chargers

that can charge batteries

from input voltages above or

below the battery voltage.

This feature can help

simplify system design and

add product flexibility…

plications. It will operate with input

voltages above or below the battery

voltage, has no path for battery

discharge when turned off, and elimi-

nates the snubber losses of flyback

designs. It also has a current sense

point that is ground referred and need

not be connected directly to the bat-

tery. The two inductors shown are

actually two identical windings on

Linear Technology Magazine • February 1996

programmed charging current to I

CHG

= 100mV/R3. The RC filter formed by

R4 and C4 smoothes the signal pre-

sented to the I

pin.

Charging current remains constant

until the battery reaches its float volt-

age, at which point the LT1512/

LT1513 changes to the constant-

voltage mode. In this mode, the

charging current will taper off as re-

quired to keep the battery at its float

voltage. The circuit’s maximum in-

put voltage is partly determined by

the battery voltage. When the switch

is off, the voltage on the V

pin is

equal to the input voltage, which is

stored across C2, plus the battery

voltage. Both the LT1512 and LT1513

have a maximum input voltage rating

of 30V and a maximum rated switch

voltage of 35V, thereby limiting input

voltage to 30V or 35V minus the bat-

tery voltage, whichever is less.

Figure 2 shows the maximum avail-

able charging current for a single-cell

or double-cell lithium battery pack.

Note that the actual programmed

charging current will be independent

of the input voltage if it does not

exceed the values shown.

Figure 4. Shutdown controlled disconnect

LT1512

L1A

L1B

•

GND

S/S

22µF

25V

C2

1µF

× 2

0.47µF

Q1 = SILICONIX Si9410DY

C2 = AVX1206Y2105KAT1A

0.1µF

24Ω

R3B

0.24Ω

R3A

2Ω

C1

22µF

25V

MBRS130LT3

HI CHARGE

LOW CHARGE

CHARGE

SHUTDOWN

Figure 3. 50mA/400mA programmable battery charger

LT1512/LT1513

CHARGE

SHUTDOWN

GND

VFB

S/S

Q1

VN2222

BATTERY

Programming

the Charge Current

As mentioned earlier, charging cur-

rent is set by R3, where I

CHG

= 100mV/

R3. The charge current is programmed

by changing the effective value of R3,

as shown in Figure 3. In the low

charge mode, Q1 is off, setting charge

current to I

CHG LOW

= 100mV/R3A, or

100mV/2Ω = 50mA. In the high-

charge mode, Q1 is on, and charge

current is I

CHG HI

= 100mV/R3A +

100mV/(R3B + Q1’s R

DS(ON)

), or

100mV/2Ω + 100mV/(0.24Ω + 0.04Ω))

= 50mA + 357mA = 407mA. Note that

Q1’s R

DS(ON)

is a factor in the high-

charge mode, requiring the use of a

low R

DS(ON)

FET.

Off-State Leakage

Charging can be terminated by placing

the LT1512/LT1513 into shutdown

mode. If the battery remains con-

nected to the charger when in the off

state, two leakage paths that load the

battery must be considered.

The first is the 100µA resistor-

divider feedback current that flows

through R1 and R2. This current can

be eliminated with the addition of a

FET, Q1, between R1 and the R2/V

junction, as shown in Figure 4. In this

example, pulling the charge/shut-

down input above 3.75V will activate

charging and turn on Q1, whereas

driving the charge/shutdown input

below 0.6V will shut down the

LT1512/LT1513 and turn off Q1.

The second leakage path to con-

sider is in the output diode, D1 (Figure

1). When the charger is in the off

state, the output diode sees a reverse

voltage equal to the battery voltage.

Though the Schottky diode reverse

leakage may typically be only 10µA,

its guaranteed specifications are

much worse, up to 1mA. One solution

is to change the output diode to an

ultra-fast silicon diode, such as an

MUR-110. The higher forward voltage

of the silicon diode will decrease the

circuit’s efficiency, but these diodes

have reverse leakage specifications

below 5µA.

Conclusion

With the ability to operate from input

voltages above or below the battery

voltage, the LT1512 and LT1513 bat-

tery chargers offer increased flexibility

for portable systems.

DESIGN FEATURES

Authors can be contacted

at (408) 432-1900

Linear Technology Magazine • February 1996

The POR output can also help stage

output voltages. For example, if the

auxiliary regulator is on in Figure 5,

the 2.9V output will come up simulta-

neously with the 3.3V output. In other

applications, however, the POR out-

put could be used to hold the AUX ON

pin low, thus delaying the auxiliary

start-up until POR releases.

EXT V

Reduces Quiescent Current

Power for the top and bottom MOS-

FET drivers and for most of the other

control circuitry is derived from the

INT V

pin. When the EXT V

pin is

open or at a low voltage, an internal

5V low dropout regulator supplies

INT V

power from V

. If EXT V

taken above 4.7V, the 5V regulator is

In this issue we introduce the

LTC1439. This IC is a constant-fre-

quency, synchronous, triple output

DC/DC converter optimized for bat-

tery operated applications. The part

(and its brethren) are the next-gen-

eration of ICs designed for the rapidly

expanding portable computer and

equipment marketplace. These de-

Editor's Page, continued from page 2

and Amp B to determine the polarity

of the current through RS. The scale

factor for V

OUT

with S1 open is 1V/A.

With S1 closed the scale factor is 1V/

100mA, and current as low as 5mA

can be measured.

Conclusion

The LT1490 provides features not

previously available in an operational

amplifier. The combination of “Over-

the-Top” operation, reverse battery

protection, micropower operation and

MSOP package enables the LT1490/

LT1491 to solve application problems

beyond the reach of previous opera-

tional amplifiers.

LT1490, continued from page 19

turned off and an internal switch is

turned on to connect EXT V

to INT

The EXT V

pin is normally con-

nected to the 5V output to allow INT

power to be derived from the

regulator itself. Quiescent current is

then reduced because driver and con-

trol currents are scaled by a factor

approximately equal to the 5V con-

troller duty cycle. EXT V

can also be

connected to other external high effi-

ciency sources, up to a maximum of

10V.

In addition to the other features

discussed above, most versions of the

LTC143X family also contain an un-

committed comparator referenced to

1.19V with an open-drain output pin,

useful in a wide variety of applica-

tions. The auxiliary regulator error

amplifier is also usable as a second

comparator.

Conclusion

The LTC1435–LTC1439 multiple out-

put DC/DC controllers offer a

tremendous amount of flexibility and

functionality while removing many of

the trade-offs that previously existed

in battery-powered supplies. With

these new controllers it is possible to

have high efficiency and low quies-

cent current without giving up

constant frequency operation, and to

have low dropout without giving up

N-channel MOSFETs. The wide vari-

ety of output voltage and current levels

achievable using minimum magnet-

ics makes these parts the logical

choice for next-generation designs.

DESIGN FEATURES

LTC1435–LTC1439, continued from page 6

pin should be grounded if not used.

When a microprocessor DAC output

is used to control charging current, it

must be capable of sinking current at

a compliance up to 2.5V if connected

directly to the PROG pin.

Conclusion

The LT1511 is a simple, cost effective

solution for charging batteries at cur-

rents of up to 3A. Battery packs

ranging from 1V to 20V can

be charged, independent of their

chemistry.

LT1511, continued from page 13

vices were developed in conjunction

with many customers and incorpo-

rate many requested features. We

continue to highlight new products in

the Design Features section. In this

issue, we spotlight several new bat-

tery-charging products, including the

LT1511, LT1512 and LT1513. Also

featured are some new converter

products, the LTC1446 and

LTC1446L D-to-A converters, and the

LTC1277 and LTC1273 A-to-D con-

verters. Many other products are

introduced in this issue. We also in-

clude our usual complement of circuit

ideas and applications.

…a royally screwed-up circuit

represents a learning opportunity…

—Derek Bowers

A circuit always works the way it is

supposed to. It never disobeys any

laws of physics…

—Tom Fredericksen

The circuit doesn’t care about fair.

—Jim Williams

There is always a way out.

—George Philbrick

From Analog Circuit Design:

Art, Science and Personalities.

Edited by Jim Williams. Butterworth-

Hienemann, 1991.

Linear Technology Magazine • February 1996

Other Features

❏The part can be “hot swapped”

without dragging the line down

or causing latchup

❏Output high with shorted or

floating inputs

❏Three-state outputs

❏High input resistance (>20k) to

allow multiple parallel receivers

Applications

The LTC1520 is designed for high

speed data/clock transmission over

short to medium distances. Its rail-

LTC1518–LTC1520, continued from page 15

DESIGN FEATURES

to-rail input common mode range

allows it to be driven via long PC

board traces, coaxial lines or long

(hundreds of feet) twisted pairs. It

can be used in networking hubs,

servers, routers, bridges, repeaters

and other local-area and telecommu-

nications switching networks. Figure

4 shows a typical LTC1520

application. The LTC1518/LTC1519,

plannned for future release, are

RS485 compatible (LTC488, LTC489

pin-for-pin compatible) high speed

(50Mbit/s) line receivers. The high

input resistance (>20k) allows more

receivers to be connected on one line.

The LTC1518/LTC1519 will conform

to the expanded RS485 input com-

mon mode range (−7V to +12V), while

providing nearly the same perfor-

mance as the LTC1520.

Conclusion

The LTC1520 high speed, low power

line receiver uses a unique architec-

ture with propagation delay and skew

performance unmatched by any

CMOS, TTL or ECL line receiver/com-

parator. Its ruggedness, precise timing

control and fault detection features

make it easy to use in a wide variety

of high speed data transmission ap-

plications.

Figure 4. A wide-swing, bipolar output DAC with digitally controlled offset

LTC1446

50k

15V

–15V

CLK

0.1µF

µP

CS/LD

OUT

OUTB

GND

OUTA

OUT

8.190

A: V

OUTA

≅ 0V

B: V

OUTA

≅ 2.048V

C: V

OUTA

≅ 4.095V

4.094

–4.096

–8.190

OUT

= 2 {V

OUTB

–V

OUTA

}

100k

10k

–

LT1077

A Wide-Swing,

Bipolar-Output DAC with

Digitally Controlled Offset

Figure 4 shows how to use an LTC1446

and an LT1077 to make a wide bipo-

lar-output-swing 12-bit DAC with an

offset that can be digitally pro-

grammed. V

OUTA

, which can be set by

loading the appropriate digital code

LTC1446, continued from page 17

for DAC A, sets the offset. As this

value changes, the transfer curve for

the output moves up and down, as

shown in the figure.

Conclusion

The LTC1446 and LTC1446L are the

world’s only DACs that offer dual 12-

bit stand-alone performance in an

8-pin SO or PDIP package. Along with

their amazing density, these DACs do

not compromise on performance, of-

fering excellent 12-bit DNL and very

low power dissipation. This allows

the user to use circuit board space

very efficiently, without sacrificing

performance.

Linear Technology Magazine • February 1996

500kHz Buck-Boost Converter

Needs No Heat Sink by Mitchell Lee

analysis showed that, in spite of the

500kHz operating frequency, a high

permeability (µ

= 125) Magnetics Inc.

Kool Mµ

core exhibited the best effi-

ciency when compared to powdered

iron materials. Copper loss is mini-

mized by the use of the high-perm

Kool Mµ material, with only a slight

core-loss penalty.

Maximum available output cur-

rent varies with input voltage, and is

shown (for 3A peak switch current) in

Figure 2. Efficiencies for several in-

put voltages are shown in Figure 3. At

a 2.7V input, most of the loss is tied

up in the LT1371 switch, whereas the

output diode is the dominant source

of loss with high inputs. Because

FBNFB

S/S

OFF ON

SWV

2.7V – 20V

INPUT

VCGND

LT1371

33µF

20V

OS-CON

L1

HL-8798*

100µF

20V

OS-CON

150µF

6.3V

OS-CON

5V

OUTPUT

3.6kΩ

1.2kΩ

4.7nF

47nF

20kΩ

MBRS340T3

L1 = HURRICANE ELECTRONICS LAB HL-8798

(801) 635-2003, FAX (801) 635-2495

COILTRONICS CTX10-4

(407)241-7876, FAX(407)241-9339

+ +

INPUT (V)

1000

500

1500

2000

OUTPUT (mA)

20010515

LOAD (mA)

EFFICIENCY (%)

20000 1000500 1500

= 12V

= 5V

= 2.7V

Figure 1. 5V, 9W converter operates over wide

input range with good efficiency.

Figure 2. Maximum available output current

Figure 3. Efficiency of Figure 1’s circuit

DESIGN IDEAS

500kHz Buck-Boost

Converter Needs

No Heat Sink ................. 24

Mitchell Lee

Power Management and

High Efficiency Switcher

Maximize Nine-Volt

Battery Life ................... 25

Vince Salvidio

Testing and Troubleshooting

an IRDA Link Using

the LT1319.................... 26

Frank Cox

The LTC1266 Operates

from >12V and Provides 3.3V

Out at 12A..................... 30

Craig Varga

12 Volt Output

from the LT1377 ........... 32

John Seago

The LTC1516 Converts Two

Cells to 5V with High

Efficiency at Extremely

Light Loads ................... 34

Sam Nork

Multichannel A/D Uses a

Single Antialiasing Filter

...................................... 35

Sean Gold and Kevin R. Hoskins

Thanks to an efficient 0.25W

switch, the LT1371 SEPIC converter

shown in Figure 1 operates at full

power with no heatsink. Up to 9W at

5V output is available, and the circuit

works over a wide range of input

voltages extending from the LT1371’s

2.7V minimum to 20V, limited by the

rating of the capacitors.

A 1:1 bifilar-wound toroid is used

as the magnetic element. A careful

these losses are small, surface mount

construction provides adequate dis-

sipation, eliminating the need for

heatsinks.

In this application, the synchroni-

zation feature of the LT1371 is not

used. When driven with an external

clock signal at the shutdown/sync

pin (S/S), the chip can be synchro-

nized to any frequency between

600kHz and 800kHz.

Kool Mµ is a registered trademark of Magnetics, Inc.

Authors can be contacted

at (408) 432-1900

Linear Technology Magazine • February 1996

Power Management and

High Efficiency Switcher Maximize

Nine-Volt Battery Life by Vince Salvidio

The LTC1174 (3.3V, 5V and ad-

justable versions) can convert a 9V

battery source to system power with

very high efficiency. Efficiency is over

90% at load currents from 20mA to

425mA and over 85% at a load cur-

rent of 4mA. For a given load,

maximum battery life can be obtained

by minimizing shutdown current

during system shutdown and maxi-

mizing converter efficiency during

operation. A single control line to the

LTC1174 can be used to select shut-

down mode or operational mode, as

required.



RUN RUN

5 SEC

TIME

STANDBY* STANDBY

0.250A

*STANDBY TIME IS LONG

AVG

< 5mA

100k

DSQ

100k

R1

200k

C1

0.1µF

100k

TO

CONTROLLER

ANY FRONT PANEL SWITCH

1/2 CD4012

1/2 CD4013

0.22µF22µF*9V

100k

2N2222

FROM OPEN

COLLECTOR OUTPUT

OF CONTROLLER

1 = ON, 0 = OFF

100k

TO PIN 1

OF LTC1174

0.0068µF

93.1k

30.9k

FOR MINIMUM RF NOISE

USE LTC1174 - ADJUSTABLE

WITH ABOVE NETWORK

LBIN

367

PGM

GND SD

OUT

D1

1N5818

L1**

50µH

LTC1174-5 0.1µF 100µF*

5V TO CONTROLS,

ETC.

 * AVX TPS

** CTX50-4

For this circuit, power-up is initi-

ated by a low level signal on the NAND

gate. This signal could come from any

front-panel switch or from an exter-

nal interrupt signal. The system power

is turned off by means of a low level

signal from a controller/logic device.

In either case, the control signal to

the LTC1174 must be latched. (A

latched turn-off signal ensures a

known state on the LTC1174 shut-

down pin during the collapse of the

+5V supply.)

The CD4012 and CD4013 are pow-

ered from the battery; the 2N2222

provides simple level shifting to the

battery rail. R1 and C1 ensure that

the circuit remains in power-down

mode during battery replacement. The

circuit shown here provides approxi-

mately 90% efficiency at 250mA load

current, and consumes less than 1µA

shutdown current. Turn-on and turn-

off transitions are very clean.

Figure 1. Schematic diagram, high efficiency DC/DC converter

Figure 2. Load profile

DESIGN IDEAS

Linear Technology Magazine • February 1996

Testing and Troubleshooting an IRDA

Link Using the LT1319

Introduction

This Design Idea presents a complete

infrared receiver that transforms

modulated photodiode signals into

digital levels. It is intended to facili-

tate the evaluation of the LT1319

infrared receiver building block in IR

serial communication links. The cir-

cuit can be configured for IRDA SIR

(InfraRed Data Association Serial

InfraRed), IRDA FIR

(InfraRed Data

Association Fast InfraRed) or Sharp/

Newton modulations with the appro-

priate jumpers.

by Frank Cox

LT1319 Receiver Description

A block diagram of the LT1319 with

the external filters for IRDA-SIR and

Sharp/Newton is shown in Figure 1.

This diagram is simplified for clarity

and shows only the basic compo-

nents for IRDA-SIR and Sharp

modulations. The preamp is a low

noise (2pA√Hz), high bandwidth

(7MHz) current-to-voltage converter

that transforms the photocurrent to a

voltage. The 7MHz bandwidth sup-

ports data rates up to 4MBaud. The

low noise allows for links of 2 meters

or more. When full bandwidth is not

required, sensitivity can be increased

by reducing the noise further with a

lowpass filter on the preamp output.

Encircling the preamp is a loop

formed by GM1, C

, a buffer and R

For low frequency signals, the loop

forces the output of the preamp to the

bias voltage (2V). High frequency sig-

nals are unaffected by the loop, so the

preamp output is effectively AC

coupled. The break frequency set by

GM1, C

and the ratio of R

to R

easily modified, since C

is a single

capacitor to ground.

–

DATA L

DIG_GND



500Ω



10k

BIAS



15k



500Ω



LOW FREQUENCY

COMPARATOR

COMP 1

–

A3

= 20

–

A2

= 20

–

A1

FILTER

BUFFER

–

PREAMP



GEN



10k



33k



1µF



50k



50k

GM2

GM3

–

IRDA-SIR

DATA



500Ω



10k

BIAS



500Ω

HIGH FREQUENCY

COMPARATOR

COMP 2

–

A6

= 20

–

A5

= 20

–

A4

FILTER

BUFFER

–



–



GM1

–



0.1µF



1µF



10nF



1nF



100pF

BYPASS

SHDN



10µF



10µF



0.1µF



3nF

FILT2

FILT1

FILTINL

FILT2L

FILTIN

BIAS

PREOUT

PHOTO-

DIODE

AN_GND

IPD



100µH

NOTE: EXTERNAL COMPONENTS ARE SHOWN

FOR AN IRDA AND SHARP/NEWTON DATA RECEIVER.



SHARP DATA

Figure 1. Block diagram of LT1319 with external filters for IRDA SIR and Sharp modulations

DESIGN IDEAS

Linear Technology Magazine • February 1996

After the preamp stage there are

two separate channels, each contain-

ing a high input impedance filter

buffer, two gain stages with lowpass

loops, and a comparator. The main

difference between the channels is

the response times of the compara-

tors—25ns and 60ns. For modulation

schemes with pulse widths down to

125ns, the 25ns comparator with its

active pull-up output stage is ideal.

The 60ns comparator with its open

collector output and 5kΩ internal pull-

up resistor is suitable for more modest

speeds, such as the 1.6ms pulses

seen with IRDA-SIR.

Buffers A1 and A4 allow the use of

a wide range of external filtering op-

tions to optimize sensitivity and

selectivity for specific modulation

methods. The external components

shown are a 4.8MHz lowpass for IRDA-

SIR/FIR, formed by R

and C

, and

a 500kHz LC tank circuit with a Q of

3 for Sharp/Newton, formed by R

and L

The loops containing GM2 and GM3

surround the gain stages and func-

tion similarly to the preamp loop.

They also provide accurate threshold

setting at the comparator inputs by

forcing the DC level of the differential

gain stages to zero. The threshold is

set by the current into pin 11, which

is multiplied by 4 in the V

generator

and then sunk through R

and R

For an R

of 30kΩ the current into

pin 11 is about 130µA. Referred to the

filter buffer inputs, the comparator

threshold is 0.65mV. The circuit has

jumper-selected capacitors to opti-

mize the AC loop highpass filters for

the modulation in use. These and a

squelch circuit are not shown here;

for complete details see the LT1319

data sheet.

Other features of the LT1319 in-

clude a shutdown pin that reduces

the supply current from a nominal

14mA to 500µA. The shutdown fea-

ture is active low. In this circuit, the

supply current in shutdown mode

also includes the current in the mode-

selection jumpers, which can range

from 0mA to 2mA.

To reduce false output transitions

due to power supply noise, the preamp

and gain stages have separate analog

grounds and are operated off an in-

ternally regulated 4V supply bypassed

at pin 16. The comparators, shut-

down and threshold circuitry operate

directly off the 5V supply and are

returned to digital ground. To provide

a low noise bias point for the amplifi-

ers an internal 1.9V reference is

generated and is bypassed externally

at pin 5.

For more detailed information

about the LT1319, consult the LT1319

data sheet.

Filtering

For IRDA-SIR modulations, the

preamp AC loop is set for a corner

frequency of less than 1kHz and the

RC lowpass section after the preamp

is set for a break frequency of 4.8MHz.

The AC loop highpass on the gain

stage for the fast frequency compara-

tor is set at 400kHz for SIR and 2.5MHz

for FIR.

The low speed channel has an LC

tank circuit with a center frequency

of 500kHz and a Q of 3, which is set

by R

. This forms a bandpass filter

for signals using the Sharp modula-

1

2

3

4

5

6

7

16

15

14

13

12

11

10

AN_GND

IN

FILT1

PREOUT

BIAS



FILTINL

FILT2L

FILTIN

BYPASS



SHDN

DATAL

DIG_GND



DATA

FILT2

U1

LT1319 R



30k



10k



0.1µFC



10µF

B3

10µF

E5

IRDA-SIR/FIR

DATA

E4

SHARP OR 

TV DATA



10k



D3

BAS16

Q2

MMBT3906LT1



Q1

MMBT941LT1

E1

SHDN E3

GND

E2



15k



10nF



33pF



0.1µFC



2.7nF NOTES:

1. FOR IRDA-SIR/FIR OR TV REMOTE,

Q5 SHOULD BE TURNED ON WITH 

A HIGH LOGIC INPUT

2. FOR IRDA-SIR, Q6 SHOULD BE TURNED 

ON WITH A HIGH LOGIC INPUT

3. FOR SHARP ASK, C

= 1nF, L

= 100µH

4. FOR TV REMOTE, C

= 33nF, L

= 470µH



1nF C



470pF



1µF



100µH



330pF

D1

TEMIC

BPV22NF

DGND

AGND



1µF

Q5

MMBT3904LT1 Q6

MMBT3904LT1



5.1k



5.1k

JMP1

SHARP

IRDA

JMP2

FIR

SIR

D2

HSDL-4220



6.8Ω

1/2W

Q3

2N7002 Q4

2N7002



100Ω



10k

E6

DRIVER

DGND DGND

Figure 2. Schematic diagram

DESIGN IDEAS

Linear Technology Magazine • February 1996

tion. The preamp AC-loop highpass

corner is set to about 200kHz by C

and the gain stage highpass is set to

130kHz.

Operation

The most straightforward way of

evaluating IR links with the LT1319

infrared receiver is to have a separate

LED transmitter, such as that shown

in the upper right-hand corner of

Figure 2, that can be placed a mea-

sured distance from the receiver. The

pulses to drive this transmitter can

be obtained from a suitable pulse

generator that has a TTL output, or

from the system that will use the IR

link, if available. Use coax cable and

place a suitable termination on the

input of the transmitter board to en-

sure good pulse fidelity.

The onboard jumpers should be

set for the modulation desired. For

example, for IRDA-SIR modulation

set the IRDA/Sharp jumper to the

IRDA side and the SIR/FIR jumper to

the SIR side. Connect an oscilloscope

to the appropriate output of the cir-

cuit and apply a 5V power source

capable of supplying greater than

25mA to the E2 (V

) and E3 (GND)

terminals. Set the transmitter close

to the receiver (~10cm), input an ap-

propriate modulated signal to E4 or

E5, and verify the basic operation of

the receiver using the modulation

photographs (Figures, 3, 4 and 5) as

a guide.

From here you can test the receiver

over the desired range, transmitter

power, angle of incidence or what-

ever. It is helpful to set up a space for

an optical range that is clear of ob-

stacles, reflections and interference.

Later, when the basic operation of the

IR link is established, the receiver can

be tested against any interference

that the final system may encounter.

For more sophisticated testing a bit-

error-rate test (BERT) set is usually

required, as are the circuits to modu-

late and demodulate the digital

signals.

0 1 0 0 1 1 0 1 0 

NRZ DATA

IRDA-SIR

DATA RATES: 2400Bd TO 115kBd

BIT INTERVAL: 417µs TO 8.7µs

PULSE WIDTH: 3/16 OF INTERVAL OR 1.63µs

0 1 0 0 1 1 0 1 0 

NRZ DATA

IRDA-FIR

DATA RATES: FIXED AT 1.15MBd

BIT INTERVAL: 870ns

PULSE WIDTH: 1/4 OF INTERVAL OR 217ns

(3a)

(4a)

DESIGN IDEAS

Figure 3. IRDA-SIR modulation

(3c)

RECEIVER OUTPUT

TRANSMITTER INPUT

IRDA-SIR 1m

(3b)

RECEIVER OUTPUT

TRANSMITTER INPUT

IRDA-SIR 0.5m

RECEIVER OUTPUT

TRANSMITTER INPUT

IRDA-SIR 0.5m

(3d)

RECEIVER OUTPUT

TRANSMITTER INPUT

IRDA-SIR 12cm

(3e)

Figure 4. IRDA-FIR modulation

(4b)

RECEIVER OUTPUT

TRANSMITTER INPUT

IRDA-FIR 1m

RECEIVER OUTPUT

TRANSMITTER INPUT

IRDA-FIR 8cm

(4c)

Linear Technology Magazine • February 1996

0 1 0 1 1

DATA RATE: 9600Bd T0 38.4kBd

AMPLITUDE SHIFT KEYING ON 500kHz CARRIER

A ONE IS ENCODED AS A BURST FROM 52 CYCLES 

TO 13 CYCLES OF THE CARRIER DEPENDING ON THE MODULATION RATE

IRDA-SIR

Because SIR systems transmit a pulse

for a zero and nothing for a one (refer

to the IRDA-SIR modulation diagram,

Figure 3a), the four photographs dem-

onstrating the SIR modulation show

a sequence of zeros. In all these pho-

tographs the input data to the

transmitter is shown on the bottom

and the output of the IR receiver is

shown on the top. The Figures 3b and

3c show received data at 1m and

0.5m. The only difference is a slight

increase of the received pulse width,

which presents no problem.

The third photograph of data from

a range of 0.5m (Figure 3d) shows

extraneous narrow pulses caused by

interference from the Sharp data out-

put of the circuit. Because of the

sensitivity of the LT1319, transitions

on this output can couple back into

the receiver. This problem can be

avoided either by shielding this out-

put or, if it is not to be used, tying it

to ground.

The last photograph in the se-

quence (Figure 3e) shows receiver data

from a range of 12cm. As the range is

decreased from 1m the pulse width

on the output increases, reaching a

maximum at this point. Here, a

squelch circuit (see data sheet for

operational details) takes over. Even-

tually, at very close range, the squelch

is overwhelmed and the pulse width

begins to widen again, but at no time

should the pulse be wider than 8ms

over the full IRDA range of 1cm to 1m.

IRDA-FIR

With the exception of data rate and

pulse width, FIR is very similar to SIR

(refer to the FIR modulation diagram—

Figure 4a). The same precautions

about interference from the other

output apply to both FIR and SIR.

The first FIR photograph shows the

receiver output at a range of 1m. The

output pulse is slightly wider than

the input, but this is acceptable. As

the range is decreased, the pulse

width narrows until about 8cm, where

it reaches a minimum. Further de-

creasing the range causes the pulse

to widen, but to no more than 800ns

over the IRDA-FIR operating range of

1m to 4cm.

Sharp

Sharp IR modulation encodes a one

as a burst of 500kHz square waves

and a zero as nothing (refer to the

Sharp modulation diagram, Figure

5a). The photographs show a one

followed by a zero pattern at a modu-

lation rate of 38.4kHz (13 cycles of

carrier). The first photograph (Figure

5b) shows data received at a range of

2m. Note that there are 14 pulses in

the received burst. An LC tank band-

pass circuit is used to filter the Sharp

modulation in Figure 1’s circuit. Ring-

ing in the time-domain response of

this filter causes the receiver output

to have extra pulses or be otherwise

distorted. The next photograph (Fig-

ure 5c), showing data received at 0.5m,

has the most pulse distortion. How-

ever, the output still does not intrude

into the next bit interval enough to

obscure the difference between a one

or a zero. To ensure correct demodu-

lation, a valid zero should have a

minimum of 12 pulses. The last pho-

tograph (Figure 5d) shows the received

data at 1cm, where filter ringing

causes one extra pulse.

Conclusion

The infrared transmission of data

between peripherals is in its infancy.

As is usual in the computer world,

every manufacturer wants to trans-

mit as rapidly as possible. This article

has presented methods of testing IR

transmission via several modulation

schemes. As the technology of IR data

transmission matures, LTC will be at

the forefront with applications

support.

Note:

The IRDA prefers the title “High Speed Extension

to SIR” for this modulation.

DESIGN IDEAS

RECEIVER OUTPUT

TRANSMITTER INPUT

SHARP 2m

(5b)

RECEIVER OUTPUT

TRANSMITTER INPUT

SHARP 0.5m

(5c)

RECEIVER OUTPUT

TRANSMITTER INPUT

SHARP 1cm

(5d)

Figure 5. Sharp modulation

(5a)

Linear Technology Magazine • February 1996

The LTC1266 Operates From

≥

12V and

Provides 3.3V Out at 12A by Craig Varga

Introduction

The LTC1266 synchronous buck con-

troller is specified for an absolute

maximum voltage of 20V on either its

input or its gate-drive supply. If it

is acceptable to the designer to drive

a P-type high-side MOSFET switch,

the part will handle input voltages of

up to 18V while providing reasonable

design margin. However, if the output

current is fairly high, making it desir-

able to use an N-type high-side

MOSFET, the highest safe nominal

input is approximately 11V. If 5V is

also available, a bootstrap circuit can

be used to provide high-side gate

drive while maintaining adequate

Figure 1. 12V in to 3.3V out at 12A

DESIGN IDEAS

TDRV

Q4

VN2222LL

Q6

MPS2222

PWRV

PINV

BINH

SENSE–

1. ALL POLARIZED CAPACITORS ARE AVX TYPE TPS OR EQUIVALENT

BDRV

PGND

LBO

U1

LTC1266



LBIN

SGND

E1

S/D

SENSE+

C1

1000pF

C13

1µF

C14, 300pF

C3

1000pF

C16

0.1µF

R6

12V

R11

4.3k

R10

220Ω

R10

10k

R9

220Ω

C2

3300pF

R8

51Ω

R12

5.1Ω

R13

1.0Ω

R4

0.015Ω

R5

0.015Ω

R1

100Ω

R2

100Ω

R3

6.04k, 1%

C7

100µF

16V

C8

100µF

16V

C17

0.001µF

C9

100µF

16V

C10

100µF

16V

C4

330µF

6.3V

C5

330µF

6.3V

C6

330µF

6.3V

C15

330µF

6.3V

OUT

3.3V

12A

C11

100µF

16V

C12

100µF

16V

Q1

Si4410

Q5

2N3906

678

D1

MBR120T3

D3

MBR0520LT3

Q3

Si4410 678

Q2

Si4410 678

D2

MBRS320T3

L1

4µH

design margin on the gate-drive sup-

ply. However, if still higher input

voltages are to be used reliably, this

approach will no longer prove ad-

equate. The simple, low-cost circuits

presented here solve this problem,

adding an incremental cost that is

probably less than the cost difference

between N- and P-type FETs.

Circuit Description

and Operation

The design in Figure 1 relies on a

floating high-side driver that provides

enough gate-drive capability to easily

switch a large power MOSFET. The

LTC1266 is configured to drive a

P-channel MOSFET by tying pin 3

(PINV) to ground. This is required

because there will be a net inversion

by the floating driver. Q4 controls the

driver stage and provides gate-dis-

charge capability through D3. When

the low-side switches are on, C16

charges to 12V through D1. When the

LTC1266 signals Q1 to turn on, Q4 is

turned off. R11 provides base current

for Q6, which, in conjunction with

Q5, acts like an SCR. Once fired, the

regenerative behavior of Q5 and Q6

rapidly charges the gate of Q1. Since

C16 is referenced to the source of Q1,

the top of C16 rises above the 12V

supply rail as Q1 turns on, forcing

Linear Technology Magazine • February 1996

strap supply. Figure 2 shows a 24V

input design. As the input supply

voltage is increased, one thing to

watch for is the potential for overlap

in the high- and low-side turn-on/

turn-off transitions. The LTC1266 is

designed to prevent shoot-through

by actually waiting until the gate

voltage of one switch is low before

allowing the other switch to be turned

on. Using the floating driver defeats

this capability, so this condition must

be checked for. The high-side drive

turn-on time may be reduced by low-

ering the value of R11. Using a larger

device for Q4 will speed up the turn-

off transition. The value of C16 may

also need to be a bit larger if R11 is

reduced to limit drooping of the boot-

strap supply voltage.

Figure 2. 24V in to 3.3V out at 12A

the gate of Q1 to nearly 24V above

ground. When the LTC1266 takes pin

1 high, Q4 turns on, pulling charge

from the gate capacitance of Q1

through D3. This back biases the

base-emitter junction of Q6, forcing

the pull-up circuit, and therefore Q1,

off.

Since the input voltage is high rela-

tive to the output, the nominal duty

factor of the high-side switch is small

(in this case approximately 31%). As

a result, the RMS current through Q1

is relatively low. By contrast, the low-

side switches are on nearly 70% of the

time, and therefore see a much higher

RMS current. This explains why

the low-side switch employs two

MOSFETs, whereas the high-side

switch uses only one. Schottky diode

D2 is used to help keep the body

diodes of Q2 and Q3 from turning on

during the short dead time before

switching transitions. These body di-

odes exhibit relatively long reverse

recovery times, contributing to com-

mutation losses. The Schottky diode

improves overall efficiency several per-

cent, but the circuit will function

correctly without it. Switching losses

in the two low-side switches are nearly

zero, since these devices are turned

on and off into nearly zero volts (the

forward drop of the Schottky).

There is no fundamental limitation

on how high the maximum input volt-

age can be with this approach. The

drive level shift is limited by the break-

down rating of Q4. Obviously, the

power transistors and input capaci-

tors must be rated for the intended

input voltage. A low power 12V sup-

ply is needed to provide power for the

LTC1266 and voltage for the boot-

DESIGN IDEAS

TDRV

Q4

VN2222LL

Q6

MPS2222

Q7

MPS2222A

PWRV

PINV

BINH

SENSE–

1. ALL POLARIZED CAPACITORS ARE AVX TYPE TPS OR EQUIVALENT UNLESS NOTED OTHERWISE.

2. L1 CONSISTS OF 15 TURNS OF #16 AWG ON MAG. INC. 77848-A7 Kool Mµ CORE

3. C12 AND C13 ARE PANASONIC TYPE HF OR EQUIV.

BDRV

PGND

LBO

U1

LTC1266



LBIN

SGND

E1

S/D

SENSE+

C1

1000pF

C11

1µF

C7, 470pF

C3

1000pF

C9

0.1µF

R6

R11

4.3k

R14

20k

R10

220Ω

R7

10k

R9

220Ω

C2

3300pF

R8

51Ω

R12

5.1Ω

R13

1.0Ω, 1/4W

R4

0.015Ω

R5

0.015Ω

R1

100Ω

R2

100Ω

R3

6.04k, 1%

C12

330µF

35V

SEE NOTE 3

C10

0.001µF

C13

330µF

35V

SEE NOTE 3

C4

330µF

6.3V

C5

330µF

6.3V

C6

330µF

6.3V

C15

330µF

6.3V

OUT

3.3V

12A

Q1

Si4410

Q5

2N3906

678

D2

MBR0520LT3

D4

MBR0540LT3

Q3

Si4410 678

Q2

Si4410 678

D1

MBRS340T3

L1

7µH

24V IN

D3

1N759

12V

Linear Technology Magazine • February 1996

12 Volt Output from the LT1377

by John Seago

Many applications use positive and

negative voltages, with only one volt-

age requiring tight regulation. Often,

cost and board space are more impor-

tant than regulation of the second

output. An equal output of opposite

polarity can be added to a boost con-

figuration by means of a negative

charge pump. This two-output con-

figuration is shown in Figure 1. The

1MHz switching frequency of the

LT1377 decreases required board

space, and the availability of both

positive and negative feedback ampli-

fiers allows regulation of either positive

or negative output.

In the circuit of Figure 1, the

LT1377 with L1, D1, D2 and C6 make

up a positive boost circuit. As the

internal power switch in the IC turns

on, the voltage at pin 8 goes low and

energy is stored in inductor L1. When

the power switch turns off, L1 trans-

fers energy through diodes D1 and

D2 to capacitor C6 and the positive

output load. C6 supplies load current

when the power switch is on. Resis-

tors R2 and R3 provide feedback from

the positive output. R1, C3 and C4

provide loop compensation. C1 is the

input capacitor and C2 provides local

decoupling for the IC.

The charge pump consists of two

capacitors, two diodes and a small

inductor. When the power switch

turns off, L1 also replenishes the

charge on C5, forward biasing D3.

When the power switch turns on, the

charge on C5 reverse biases D3, for-

ward biases D4 and supplies energy

to C7 and the negative output load.

L2 attenuates capacitive current

spikes. D2 was added so that the

voltage drop across both D1 and D2

would be approximately equal to the

sum of the voltage drops of D3, D4

and the saturation voltage of the power

switch in the LT1377. This makes

both output voltages approximately

equal but opposite in polarity. D1 and

D2 can be replaced with a single

Schottky diode if equal outputs are

not required.

Voltage and current waveforms of

the internal power switch are shown

in Figure 2. These measurements were

taken at pin 8 of the LT1377 with the

circuit powered from a 5V supply.

Figure 3 shows the ripple voltage from

each output. The high frequency

spikes can be attenuated with a small

LC filter if necessary.

The circuit of Figure 1 was in-

tended to operate from a 5V supply

L1

10µH

L2

0.047µH

D1

MURS110

R2

86.6k

R3

10k

R1

D2

MURS110

SGND PGND

U1

LT1377

S/S V

4V TO 10V

INPUT

–12V

OUTPUT

12V

OUTPUT

C1

10µF

25V

Y5U

C5

10µF

25V

Y5U

C6

2.2µF

25V

Y5U

C7

2.2µF

25V

Y5U

D3

MBRS130L

D4

MBRS130L

C2

0.47µF

C3

0.0047µF

C1 = C5 = 1E106ZY5U-C205-M, TOKIN (408) 432-8020

C6 = C7 = 1E225ZY5U-C203. TOKIN (408) 432-8020

L1 = CTX10-1P, COILTRONICS (407) 241-7876

L2 = PM20-R047M, GARRETT (805) 922-0594

C4

0.047µF

NFB



and provide ±12V outputs at 100mA

each. It operates over an input range

of 4V to 10V and load current varia-

tions from 15mA to 100mA. The

regulated positive output voltage re-

mains constant for changes in the

input voltage and load current, while

the voltage of the unregulated nega-

tive output changes as shown in

Figure 4. Line and load regulation of

the unregulated output will improve

with smaller changes of input voltage

or load current.

A common requirement is for the

positive output to regulate the major-

ity of power while the negative output

supplies a much smaller, unregu-

lated bias current. Measurements

taken on the test circuit of Figure 1

showed the unregulated −12V output

had less than ±1% variation for a

fixed 15mA load while the input volt-

age changed from 4V to 10V with a

load current change of 15mA to

200mA on the regulated positive

output.

Occasionally, it is more important

to regulate the negative output than

the positive output. The circuit in

Figure 5 is the same as that shown in

Figure 1, except feedback resistors

R2 and R3 have different values and

Figure 1. Positive output regulated supply

DESIGN IDEAS

Linear Technology Magazine • February 1996

INPUT VOLTAGE

–10.75

–11.25

–11.00

–11.50

–11.75

–12.25

–12.00

–12.50

–12.75

–13.00

OUTPUT VOLTAGE

100231458967

±15mA LOAD

±50mA LOAD

±100mA LOAD

provide feedback from the negative

output to the negative feedback am-

plifier of the LT1377. Figure 6 shows

the variation in unregulated positive

output for input voltage and load

current variations.

INPUT VOLTAGE

10.75

11.25

11.00

11.50

11.75

12.25

12.00

12.50

12.75

13.00

OUTPUT VOLTAGE

100231458967

±100mA LOAD

±50mA LOAD

±15mA LOAD

L1

10µH

L2

0.047µH

D1

MURS110

R3

2.21k

R2

8.25k

R1

D2

MURS110

SGND PGND

U1

LT1377

S/S V

4V TO 10V

INPUT

–12V

OUTPUT

12V

OUTPUT

C1

10µF

25V

Y5U

C5

10µF

25V

Y5U

C6

2.2µF

25V

Y5U

C7

2.2µF

25V

Y5U

D3

MBRS130L

D4

MBRS130L

C2

0.47µF

C3

0.0047µF

C4

0.047µF

NFB

C1 = C5 = 1E106ZY5U-C205-M, TOKIN (408) 432-8020

C6 = C7 = 1E225ZY5U-C203, TOKIN (408) 432-8020

L1 = CTX10-1P, COILTRONICS (407) 241-7876

L2 = PM20-R047M, GARRETT (805) 922-0594

Figure 4. Unregulated negative output voltage

with positive output voltage regulated

Figure 6. Unregulated positive output voltage

with negative output voltage regulated

Figure 5. Negative output regulated dual supply

DESIGN IDEAS

Figure 2. Switch voltage and current waveforms

0.5µs/DIV

SWITCH

VOLTAGE

5V/DIV

PIN 8

SWITCH CURRENT

0.5A/DIV

PIN 8

Figure 3. Output ripple voltage

0.5µs/DIV

12V OUTPUT

RIPPLE

0.1V/DIV

COUPLED

–12V OUTPUT

RIPPLE

0.1V/DIV

COUPLED

Linear Technology Magazine • February 1996

The LTC1516 Converts Two Cells

to 5V with High Efficiency at

Extremely Light Loads by Sam Nork

Many battery-powered applications

require very small amounts of load

current from the regulated supply

over long periods of time, followed by

moderate load currents for short pe-

riods of time. In these types of

applications (for example, remote

data-acquisition systems, hand-held

remote controls, and the like), the

discharge rate of the battery is domi-

nated by the overall current demands

under low load conditions. In such

low load systems, a primary source of

battery drain is the DC/DC converter

that converts the battery voltage to a

regulated supply.

The circuit shown in Figure 1 con-

verts an input voltage from two cells

to 5V using a switched-capacitor

charge-pump technique. An integral

comparator on the LT1516 senses

the output voltage and enables the

charge pump as the output begins to

droop. The charge pump’s 2-phase

clock controls the internal switching

of flying caps C1 and C2. (See Figure

2.) On phase one of the clock, the

flying caps are connected between

and GND. On phase two, the

negative plate of C1 is connected to

, the negative plate of C2 is con-

nected to the positive plate of C1, and

the positive plate of C2 is connected

to the output. During this phase of

the clock, the potential on the top

plate of C2 is approximately 3 ×V

and the charge is dumped from C2

onto the output cap to raise the out-

put voltage. The repeated charging

and discharging of C1 and C2 contin-

ues at a nominal frequency of 600kHz

until the output voltage has risen

above the internal comparator’s trip

point.

When the battery cells are fully

charged (approximately 1.5V per cell,

for a nominal 3V V

), the circuit

+ +

1

8

7

C1+

C1–

SHDN

2

CELLS

10µF

C1 = C2 = 0.22µF

10µF

C2C1

LTC1516

ON/OFF

C2+

C2–

GND

OUT

4

5

6

OUT

= 

5V ±4%

OUT

= 

0mA TO 20mA

OUT

(mA)

100

EFFICIENCY (%)

1000.01 1.00.1 10

= 2V

= 3V V

= 2.75V

= 2.5V

= 2.25V

S2A

S2B

S2C

S1A

S1B

S1C

S1D

0.22µF

10µF

0.22µF

+

–

+

–

10µF

OUT

CHARGE PUMP

operates as a voltage doubler to main-

tain regulation. In doubler mode, only

C2 is charged to V

and discharged

onto V

OUT

when the charge pump is

enabled. As the batteries discharge

and/or the load increases, the circuit

will change from doubler mode to

tripler mode. Under light load condi-

tions, the part will remain in doubler

mode until V

has dropped below

2.55V. Under heavier loads, the part

will go into tripler mode at a higher

to maintain regulation. By switch-

ing operating modes as the V

and

the load conditions change, the

LTC1516 optimizes overall efficiency

for the life of the batteries. As shown

in Figure 3, Figure 1’s circuit achieves

better than 70% efficiency with load

currents from 50µA to 20mA for al-

most the entire life of the batteries.

Figure 3. Efficiency versus V

OUT

for Figure 1’s

circuitFigure 1. 2-cell to 5V converter

Figure 2. LT1516 charge pump in tripler

mode, discharge cycle

DESIGN IDEAS

Authors can be contacted

at (408) 432-1900

Linear Technology Magazine • February 1996

Multichannel A/D Uses a

Single Antialiasing Filter by Sean Gold and

Kevin R. Hoskins

The circuit in Figure 1 demon-

strates how the LTC1594’s

independent analog multiplexer can

simplify the design of a 12-bit data

acquisition system. All four channels

are MUXed into a single 1kHz, fourth-

order Sallen-Key antialiasing filter,

which is designed for single-supply

operation. Since the LTC1594’s data

converter accepts inputs from ground

to the positive supply, rail-to-rail op

amps were chosen for the filter to

maximize dynamic range. The LT1368

dual rail-to-rail op amp is compen-

sated for the 0.1µF load capacitors

–

CH0

CH1

CH2

CH3

SHA IN

REF



COM

GND



MUX OUT



CS

CLK



OUT



LTC1594

7.5k

1µF

0.1µF

ANALOG

INPUTS

7.5k

0.1µF

0.015µF

C1

0.1µF

DATA OUT

CLOCK

DATA IN

CHIP SELECT

0.03µF

C2

0.1µF

0.03µF

0.015µF

1/2

LT1368

1/2

LT1368

(C1 and C2) that help reduce the

amplifier’s output impedance and

improve supply rejection at high fre-

quencies. The filter contributes less

than 1LSB of error due to offsets and

bias currents. The filter’s noise and

distortion are less than −72dB for a

100Hz, 2V

P–P

offset sine input.

The combined MUX and A/D er-

rors result in an integral nonlinearity

error of ±3LSB (maximum) and a dif-

ferential nonlinearity error of ±3/4LSB

(maximum). The typical signal-to-

noise plus distortion ratio is 68dB,

with approximately −78dB of total

harmonic distortion. The LTC1594 is

programmed through a 4-wire serial

interface that allows efficient data

transfer to a wide variety of micro-

processors and microcontrollers.

Maximum serial clock speed is

200kHz, which corresponds to a

10.5kHz sampling rate

The complete circuit consumes

approximately 800µA from a single

5V supply. For ratiometric measure-

ments, the A/D’s reference can also

be taken from the 5V supply. Other-

wise, an external reference should be

used.

Figure 1. Simple data acquisition system takes advantage of the LTC1594’s

MUX OUT/SHA IN loop to filter analog signals prior to A/D conversion

DESIGN IDEAS

Linear Technology Magazine • February 1996

Simple Resistive Surge Protection

for Interface Circuits by Bryan Nevins

Surges and Circuits

Many interface circuits must survive

surge voltages such as those created

by lightning strikes. These high volt-

ages cause the devices within the IC

to break down and conduct large cur-

rents, causing irreversible damage to

the IC. Engineers must design cir-

cuits that tolerate the surges expected

in their environments. They can quan-

tify the surge tolerance of circuitry by

using a surge standard. Standards

differ mainly in their voltage levels

and wave forms. At LTC, we test surge

resistance using the circuit of Figure

1. We describe the voltage wave form

(Figure 2) by its peak value V

, the

“front time” T

(roughly, the rise time),

and the “time to half-value” T

1/2

(roughly, the time from the beginning

of the pulse to when the pulse decays

to half of V

). Surges are similar to

ESD, but challenge circuits in a dif-

ferent way. A surge may rise to 1kV in

10ms, whereas an ESD pulse might

rise to 15kV in only a few ns. However,

the surge lasts for more than 100ms,

whereas the ESD pulse decays in

about 50ns. Thus, the surge chal-

lenges the power dissipation ability of

the protection circuitry, whereas the

ESD challenges the turn-on time and

peak current handling. The Linear

Technology LT1137A has on-chip

circuitry to withstand ESD pulses up

to 15kV (IEC 801-2). This circuitry

also increases the surge tolerance of

the LT1137A relative to a standard

1488/1489.

Designing for

Surge Tolerance

Many designers enhance the surge

tolerance of a circuit by placing a

transient voltage suppressor (TVS) in

parallel with the vulnerable IC pins,

as shown in Figure 3. The TVS con-

tains Zener diodes, which break down

at a certain voltage and shunt the

surge current to ground. Thus, the

TVS clamps the voltage at a level safe

for the IC. The TVS, like any protection

circuitry increases the manufactur-

ing cost and complexity of the circuit.

Alternately, designers can use a se-

ries resistor to protect the vulnerable

pins, as shown in Figure 4. The resis-

tor reduces the current flowing into

the IC to a safe level. Resistive protec-

tion simplifies design and inventory

and may offer lower cost. The resis-

tance must be large enough to protect

the IC, but not so large that it de-

grades the frequency performance of

the circuit. Larger surge amplitudes

require increased resistance to pro-

tect the IC. More robust ICs need less

resistance for protection against a

given surge amplitude. Linear’s

LT1137A is protected by a much

smaller resistor than a 1488, as shown

in Figure 5. These curves are empiri-

cal “rules of thumb.” You should test

actual circuits.

The series resistor may have an

adverse effect on the frequency per-

formance of the circuit. When

protecting a receiver, the resistor has

little effect. Figures 6a and 6b show

the effect of a 600Ω resistor on the

driver-output wave form. A 600Ω re-

sistor is adequate for 1kV surges, but

has minimal effect on the driver wave

form up to 130kbaud, even with a

worst-case load of 3kΩ||2.5nF.

You must choose the series resis-

tor carefully to withstand the surge.

Unfortunately, neither voltage ratings

nor power ratings provide an adequate

basis for choosing surge-tolerant

resistors. Usually, through-hole re-

sistors will withstand much larger

DUT

COUT

0.05µF

4kV

C1

7µF

3kV

VP

HV SUPPLY

R1

50Ω

R2

75Ω, 2W

RB

10k

Tf CONTROLLED BY R2 × COUT

T1/2 CONTROLLED BY C1 × R1

VP SET BY HV SUPPLY

TIME

1/2

CONTROLLED BY R2 × C

OUT



1/2

CONTROLLED BY C1 × R1

SET BY HV SUPPLY

VOLTAGE

~ 10µs

1/2

= 120µs

0.1µF0.1µF

–

1488

TVS

Figure 1. LTC surge-test circuit: T

controlled by R2 × C

OUT

; T

1/2

controlled by C1 × R1; V

set

up by HV supply

Figure 2. LTC surge-test waveform

Figure 3. 1488 line driver with TVS surge

protection

DESIGN INFORMATION

Linear Technology Magazine • February 1996

0.1µF

2 × 0.1µF

0.1µF

1

2

3

4

5

6

7

8

9

10

11

12

13

28

27

26

25

24

23

22

21

20

19

18

17

16

LT1137A

TO LOGIC

TO LINE

ON/OFF5V

V+

V–

LT1137A SAFE CURVE

1488 SAFE CURVE

R SERIES (Ω)

200

400

600

800

1000

1200

SAFE SURGE V

(V)

6000 100 200 300 500400

V–

0.1µF

2 × 0.1µF

0.1µF

1

2

3

4

5

6

7

8

9

10

11

12

13

28

27

26

25

24

23

22

21

20

19

18

17

16

LT1137A

130k baud

ON/OFF5V

V+

2.5nF 3kΩ

SCOPE

carbon film resistors against surges

up to about 1200V. Unfortunately,

using series or parallel combinations

of resistors does not increase the surge

handling as one would expect.

Resistive Surge Protection

The LT1137A has proprietary circuitry

that makes it more robust against

ESD and surges than the standard

Figure 4. 1137A with resistive surge protection Figure 6a. Testing line driver output wave form

Figure 5. Safe curves for 1488 (SN75188N)

and LT1137A. Safe curves represent the

highest V

for which no IC damage occurred

after 10 surges.

surges than surface mount resistors

of the same value and power rating.

Typical 1/8 Watt surface mount re-

sistors are not suitable for protecting

the LT1137A. If you use surface

mount components, you may need

ratings of 1W or more. With the

LT1137A, you can use carbon film

1/4W through-hole resistors against

surges up to about 900V, and 1/2W

DESIGN INFORMATION

1488/1489. The greater surge toler-

ance of the LT1137A makes it practical

to use resistive surge protection, re-

ducing inventory and component cost

relative to TVS surge protection. The

major considerations are the surge

tolerance required, the resulting

resistor value needed, resistor robust-

ness and frequency performance.

2V/DIV

Figure 6b. Output wave forms with series resistor

RS = 0Ω

130k baud

5µs/DIV RS = 600Ω

130k baud

2V/DIV

5µs/DIV

Linear Technology Magazine • February 1996

New Device Cameos

NEW DEVICE CAMEOS

LT1351: 250µA, 3MHz,

200V/µs C-Load™ Op Amp

with Shutdown

The LT1351 is an ideal operational

amplifier for low power applications

that also require high speed, low dis-

tortion, outstanding output drive, fast

settling or stability with a capacitive

load.

The LT1351 slews at 200V/µs and

has a gain bandwidth of 3MHz while

drawing a frugal 250µA of supply

current. Output drive is not compro-

mised: the LT1351 can drive a 1kΩ

load to ±12V on ±15V supplies or 20V

peak-to-peak at 20kHz with less than

.03% THD + Noise. Settling time is a

remarkable 700ns for a 10V step set-

tling to 0.1% and 1250ns for 0.01%.

The LT1351 is stable with any capaci-

tive load, so it is excellent as a buffer

or for driving A-to-D converters.

The DC specifications are outstand-

ing for an amplifier with such stellar

AC credentials. Maximum input speci-

fications include 600µV offset voltage,

50nA bias current and 15nA offset

current. Voltage gain is 30V/mV mini-

mum driving 2kΩ.

The LT1351 is specified for supply

voltages from ±2.5V to ±15V. The shut-

down pin reduces supply current to a

mere 10µA.

The LT1351 comes in the industry

standard pinout in 8-lead plastic SO

and MSOP surface mount packages,

as well as the venerable 8-lead mini-

DIP.

LT1207 Dual 60MHz, 250mA

Current Feedback Amplifier

The LT1207 is a dual version of the

LT1206 high speed current feedback

amplifier. Like the LT1206, each CFA

in the dual version has excellent video

characteristics: 60MHz bandwidth,

250mA minimum output-drive cur-

rent, 400V/µs minimum slew rate,

low differential gain (0.02% typical)

and low differential phase (0.17° typi-

cal). The LT1207 includes a pin for an

optional compensation network,

which can help stabilize the amplifier

for heavy capacitive loads. Both am-

plifiers have thermal and current limit

circuits that provide protection

against fault conditions. These capa-

bilities make the LT1207 well suited

for driving difficult loads, such as

cables in video or digital communica-

tions systems.

Operation is fully specified for sup-

plies from ±5V to ±15V. Supply current

is typically 20mA per amplifier, and

there are two separate micropower

shutdown controls that drop supply

current to less than 200µA per ampli-

fier. When shut down, the outputs

assume high impedance states. The

shutdown controls can also be used

to lower supply current for reduced-

bandwidth applications.

The LT1207 is available in a low

thermal resistance, 16-lead SOIC

package. Consult the factory regard-

ing industrial grade parts.

LTC1400 Complete SO-8,

12-Bit, 400ksps ADC

with Shutdown

The LTC1400 is a complete 2.1µs,

400ksps, serial 12-bit A-to-D con-

verter that draws only 75mW from 5V

or ±5V supplies. It is the first com-

plete 12-bit ADC to be offered in an

SO-8 package. This easy-to-use de-

vice comes complete with a 200ns

sample-and-hold and a precision

reference. Unipolar and bipolar con-

version modes add to the ADC’s

flexibility. The LTC1400 has both Nap

and Sleep modes. In the Nap mode, it

consumes only 6mW and can wake

up and convert immediately after

shutdown. In the Sleep mode, it typi-

cally consumes 30µW. On power-up

from Sleep mode, a reference-ready

(REFRDY) signal is available in the

serial data word to indicate that the

reference has settled and the chip is

ready to convert.

The LTC1400 converts 0V to 4.096V

unipolar inputs from a single 5V sup-

ply and ±2.048V bipolar inputs from

±5V supplies. Maximum DC specs

include ±1LSB INL, ±1LSB DNL and

25ppm/°C drift over commercial and

industrial temperature ranges. Out-

standing AC performance includes

70dB S/(N + D) and 78dB THD at the

input frequency of 100kHz over

temperature.

The 3-wire serial port allows effi-

cient data transfers over a compact

interface to a wide range of micropro-

cessors, microcontrollers and DSPs.

LT1371 and LT1373:

High Frequency, Low Supply

Current, High Efficiency

Switching Regulators

The LT1371 and LT1373 are mono-

lithic, high frequency, current mode

switching regulators. They feature

faster switching with increased

efficiency and use small inductors—

4.7µH for the LT1371 or 15µH for the

LT1373—and both can be used in all

standard switching configurations,

including boost, buck, flyback, for-

ward, inverting and “Cuk.” A high

efficiency switch is included on the

die, along with all oscillator, control

and protection circuitry.

The LT1371 switches at 500kHz,

typically consumes only 4mA and has

higher efficiency than previous parts;

the LT1373 switches at 250kHz, typi-

cally consumes only 1mA and has

even higher efficiency. High frequency

switching allows small inductors to

be used with both devices. The sur-

face mount versions of the LT1371

and LT1373 DC/DC converter cir-

cuitry consume less than 0.6 square

inches of board space.

New design techniques increase

flexibility and maintain ease of use.

Switching is easily synchronized to

an external logic-level source. A logic

low on the shutdown pin reduces

supply current to 12µA. Unique er-

ror-amplifier circuitry can regulate

positive or negative output voltage

while maintaining simple frequency-

compensation techniques. Nonlinear

error-amplifier transconductance re-

duces output overshoot on start-up

Linear Technology Magazine • February 1996

Burst Mode

is a trademark of Linear

Technology Corporation. , LT and LTC are

registered trademarks used only to identify

products of Linear Technology Corp. Other

product names may be trademarks of the

companies that manufacture the products.

Information furnished by Linear Technol-

ogy Corporation is believed to be accurate

and reliable. However, Linear Technology

makes no representation that the circuits

described herein will not infringe on existing

patent rights.

For further information on the

above or any of the other devices

mentioned in this issue of Linear

Technology, use the reader service

card or call the LTC literature ser-

vice number: 1-800-4-LINEAR. Ask

for the pertinent data sheets and

application notes.

NEW DEVICE CAMEOS

or overload recovery. Oscillator fre-

quency shifting protects external

components during overload

conditions.

The LT1371 is available in SO,

7-lead TO220 and DD packages; the

LT1373 is available in 8-pin SO or

DIP packages.

LT1501: Adaptive-Frequency

Current Mode, Micropower

Switching Regulator

The LT1501, LT1501-3.3 and

LT1501-5 are adaptive-frequency cur-

rent mode, step-up switching

regulators with internal loop

compensation. In contrast with pulse-

skipping type switching regulators,

this family uses a current mode to-

pology that provides low noise

operation and excellent system per-

formance. The LT1501 family also

features a low battery comparator

and light-load Burst Mode operation.

The LT1501 has a 750mA power

switch and can be set to operate at

frequencies up to 600kHz. This fam-

ily of devices can operate from supply

voltages as low as 1.8V. The quies-

cent current of 160µA can be further

reduced to 6µA in shutdown mode.

Available in 8-pin SO packaging,

the LT1501 is a versatile switcher

family featuring both current mode

performance and simple system

design.

LTC1538-AUX/LTC1539:

High Efficiency Dual

Synchronous DC/DC

Controllers for Portable and

Notebook Computer

Applications

The LTC1538-AUX/LTC1539 are dual

synchronous step-down switching

regulator controllers that drive exter-

nal N-Channel power MOSFETs in a

fixed-frequency architecture. The

LTC1539 Adaptive Power™ output

stage drives synchronous N-Channel

MOSFETs at high currents, and

switches to a low power output stage

at low currents to maintain high effi-

ciency without resorting to variable

frequency operation. The LTC1538-

AUX employs Burst Mode operation

at low currents to achieve low quies-

cent current.

Key features that distinguish the

LTC1538-AUX/LTC1539 from the

similar LTC1438/LTC1439 devices

are the circuits that remain active

even when both of the switching con-

trollers are shut down—a 5V linear

regulator (LTC1538-AUX and

LTC1539) and a voltage comparator

(LTC1539 only). The 5V regulator is

capable of supplying 25mA (typical)

with a dropout of less than 0.5V while

exhibiting an output impedance of

less than 1Ω. The comparator has its

positive input tied to the 2% accurate,

internal 1.19V voltage reference. A

CMOS open-drain output can be ex-

ternally pulled up to a power supply

of 12V or less and can sink more than

10mA. The standby supply current

with the 5V linear regulator and volt-

age comparator active is only 50µA.

An auxiliary 0.5A linear regulator,

available in both the LTC1538-AUX

and LTC1539, uses an external PNP

pass device to provide a low noise, low

dropout 12V or adjustable output.

This same regulator can be config-

ured to provide a linear 3.3V to 2.9V/

3A supply with the addition of a low

saturation NPN pass device. A sec-

ondary feedback control pin, SFB,

guarantees regulation on secondary

windings regardless of the primary

load by forcing continuous operation

as required.

Internal resistive dividers provide

pin-selectable output voltages of 3.3V

and 5V on the first controller of both

devices. The second controller in the

LTC1539 can be programmed to 3.3V,

5V or adjustable according to the

connection of the V

PROG

pin, whereas

the second controller in the LTC1538

is adjustable.

The LTC1539 features a phase-

locked loop (PLL) for synchronization

to an external source, and a power-

on reset timer (POR) that generates a

signal delayed by 65536/F

CLK

(typi-

cally 300ms) after the output is within

7.5% of the regulated output voltage.

The LTC1539 is further differentiated

from the LTC1439 by the fact that

POR monitors the first controller

rather than the second.

The operating current levels are

user programmable via external cur-

rent sense resistors. A wide input

supply range allows operation from

3.5V to 36V (maximum). The

LTC1538-AUX is available in a 28-pin

SSOP package and the LTC1539

comes in a 36-pin SSOP.

LTC7545A:

Multiplying 12-Bit DAC

The LTC7545A is a 4-quadrant mul-

tiplying, current-output 12-bit DAC.

It is a superior, pin-compatible re-

placement for the industry standard

AD7545A. It has improved accuracy

and stability, reduced sensitivity to

external amplifier VOS, lower output

capacitance and reduced cost.

The LTC7545A has a parallel 12-

bit-wide microprocessor-compatible

interface. This DAC has excellent ac-

curacy and stability, with INL and

DNL guaranteed at 1/2 LSB MAX

over temperature. Gain error is 1 LSB

MAX, eliminating adjustments in most

applications. Typical applications are

process control, and software pro-

grammable gain, attenuation and

filtering.

The LTC7545A comes in 20-pin SO

and PDIP packages and is available in

commercial and industrial tempera-

ture grades.

Linear Technology Magazine • February 1996

AppleTalk



is a registered trademark of Apple Computer, Inc.

LINEAR TECHNOLOGY CORPORATION

1630 McCarthy Boulevard

Milpitas, CA 95035-7417

(408) 432-1900 FAX (408) 434-0507

For Literature Only: 1-800-4-LINEAR

DESIGN TOOLS

Applications on Disk

NOISE DISK

This IBM-PC (or compatible) progam allows the user to calculate circuit noise

using LTC op amps, determine the best LTC op amp for a low noise application,

display the noise data for LTC op amps, calculate resistor noise, and calculate

noise using specs for any op amp. Available at no charge.

SPICE MACROMODEL DISK

This IBM-PC (or compatible) high density diskette contains the library of LTC

op amp SPICE macromodels. The models can be used with any version of

SPICE for general analog circuit simulations. The diskette also contains

working circuit examples using the models, and a demonstration copy of

PSPICE

by MicroSim. Available at no charge.

Technical Books

1990 Linear Databook • Volume I — This 1440 page collection of data sheets

covers op amps, voltage regulators, references, comparators, filters, PWMs,

data conversion and interface products (bipolar and CMOS), in both commer-

cial and military grades. The catalog features well over 300 devices. $10.00

1992 Linear Databook Supplement — This 1248 page supplement to the

1990 Linear Databook

is a collection of all products introduced since then.

The catalog contains full data sheets for over 140 devices. The

1992 Linear

Databook Supplement

is a companion to the

1990 Linear Databook

, which

should not be discarded. $10.00

1994 Linear Databook • Volume III — This 1826 page supplement to the

1990 Linear Databook

and

1992 Linear Databook Supplement

is a collection

of all products introduced since 1992. A total of 152 product data sheets are

included with updated selection guides. The

1994 Linear Databook Volume III

is a supplement to the 1990 and 1992 Databooks, which should not be

discarded.

$10.00

1995 Linear Databook • Volume IV — This 1152 page supplement to the

1990, 1992 and 1994 Linear Databooks

is a collection of all products introduced

since 1994. A total of 80 product data sheets are included with updated

selection guides. The

1995 Linear Databook Vol IV

is a companion to the

1990,

1992 and 1994 Linear Databooks

, which should not be discarded. $10.00

Linear Applications Handbook • Volume I — 928 pages full of application

ideas covered in depth by 40 Application Notes and 33 Design Notes.

This catalog covers a broad range of “real world” linear circuitry. In addition to

detailed, systems-oriented circuits, this handbook contains broad tutorial

content together with liberal use of schematics and scope photography.

A special feature in this edition includes a 22 page section on SPICE

macromodels. $20.00

1993 Linear Applications Handbook • Volume II — Continues the stream

of “real world” linear circuitry initiated by the

1990 Handbook

. Similar in scope

to the 1990 edition, the new book covers Application Notes 41 through 54 and

Design Notes 33 through 69. Additionally, references and articles from non-

LTC publications that we have found useful are also included. $20.00

Interface Product Handbook

— This 424 page handbook features LTC’s

complete line of line driver and receiver products for RS232, RS485,

RS423, RS422, V.35 and AppleTalk



applications. Linear’s particular

expertise in this area involves low power consumption, high numbers of

drivers and receivers in one package, mixed RS232 and RS485 devices, 10kV

ESD protection of RS232 devices and surface mount packages.

Available at no charge.

SwitcherCAD Handbook — This 144 page manual, including disk, guides

the user through SwitcherCAD—a powerful PC software tool which aids in the

design and optimization of switching regulators. The program can cut days off

the design cycle by selecting topologies, calculating operating points and

specifying component values and manufacturer's part numbers. $20.00

1995 Power Solutions Brochure,

First Edition

— This 64 page collection

of circuits contains real-life solutions for common power supply design

problems. There are over 45 circuits, including descriptions, graphs and

performance specifications. Topics covered include PCMCIA power manage-

ment, microprocessor power supplies, portable equipment power supplies,

micropower DC/DC, step-up and step-down switching regulators, off-line

switching regulators, linear regulators and switched capacitor conversion.

Available at no charge.

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