To our custo mers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corpor ation took over all the business of both
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Renesas Electronics document. W e appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
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R1EX25002ASA00A/R1EX25004ASA00A
R1EX25002ATA00A/R1EX25004ATA00A
Serial Peripheral Interface
2k EEPROM (256-word × 8-bit)
4k EEPROM (512-word × 8-bit)
Electrically Erasable and Programmable Read Only Memory
REJ03C0357-0002
Preliminary
Rev.0.02
Jan.14.2009
Description
R1EX25xxx Series is the Serial Peripheral Interface compatible (SPI) EEPROM (Electrically Erasable and
Programmable ROM). It realizes high speed, low power consumption and a high level of reliability by employing
advanced MONOS memory technology and CMOS process and low voltage circuitry technology. It also has a 16-byte
page programming function to make it’s write operation faster.
Note: Renesas Technology’s serial EEPROM are authorized for using consumer applications such as cellular phones,
camcorders, audio equipments. Therefore, please contact Renesas Technology’s sales office before using
industrial applications such as automotive systems, embedded controllers, and meters.
Features
• Single supply: 1.8 V to 5.5 V
• Serial Peripheral Interface compatible (SPI bus)
SPI mode 0 (0,0), 3 (1,1)
• Clock frequency: 5 MHz (2.5 V to 5.5 V), 3 MHz (1.8 V to 5.5 V)
• Power dissipation:
Standby: 2µA (max)
Active (Read): 2 mA (max)
Active (Write): 2.5 mA (max)
• Automatic page write: 16-byte/page
• Write cycle time: 5 ms
• Endurance: 1,000k Cycles @ 25 °C
• Data retention: 100 Years @ 25 °C
• Small size packages: SOP-8pin, TSSOP-8pin
• Shipping tape and reel
TSSOP-8pin: 3,000 IC/reel
SOP-8pin : 2,500 IC/reel
• Temperature range: −40 to +85 °C
• Lead free product.
Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Technology's Sales Dept. regarding specifications
REJ03C0357-0002 Rev.0.02 Jan.14 .2009
page 1 of 20
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 2 of 20
Ordering Information
Type No. Internal organization Operating voltage Frequency Package
R1EX25002ASA00A 2-kbit (256 × 8-bit) 1.8 V to 5.5 V 5 MHz
(2.5 V to 5.5 V)
R1EX25004ASA00A 4-kbit (512 × 8-bit) 3 MHz
(1.8 V to 5.5V)
150mil 8-pin plastic SOP
PRSP0008DF-B
(FP-8DBV)
Lead free
R1EX25002ATA00A 2-kbit (256 × 8-bit) 1.8 V to 5.5 V 5 MHz
(2.5 V to 5.5 V)
R1EX25004ATA00A 4-kbit (512 × 8-bit) 3 MHz
(1.8 V to 5.5 V)
8-pin plastic TSSOP
PTSP0008JC-B
(TTP-8DAV)
Lead free
Pin Arrangement
8-pin SOP/TSSOP
(Top view)
1
2
3
4
8
7
6
5
V
CC
HOLD
C
D
S
Q
W
V
SS
Pin Description
Pin name Function
C Serial clock
D Serial data input
Q Serial data output
S Chip select
W Write protect
HOLD Hold
VCC Supply voltage
VSS Ground
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 3 of 20
Block Diagram
High voltage generator
Memory array
Y-select & Sense amp.
Serial-parallel converter
Address generator
Control logic
Y
decoder X
decoder
V
CC
V
SS
S
W
C
HOLD
D
Q
Absolute Maximum Ratings
Parameter Symbol Value Unit
Supply voltage relative to VSS V
CC −0.6 to + 7.0 V
Input voltage relative to VSS V
IN −0.5*2 to +7.0*3 V
Operating temperature range*1 Topr −40 to +85 °C
Storage temperature range Tstg −55 to +125 °C
Notes: 1. Including electrical characteristics and data retention.
2. VIN (min): −3.0 V for pulse width ≤ 50 ns.
3. Should not exceed VCC + 1.0 V.
DC Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply voltage VCC 1.8 5.5 V
V
SS 0 0 0 V
Input voltage VIH V
CC × 0.7 V
CC + 0.5*2 V
V
IL −0.3*1 V
CC × 0.3 V
Operating temperature range Topr −40 +85 °C
Notes: 1. VIN (min): −1.0 V for pulse width ≤ 50 ns.
2. VIN (max): VCC + 1.0 V for pulse width ≤ 50 ns.
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter
Symbol
Min
Typ
Max
Unit Test
conditions
Input capacitance (D,C, S, W ,HOLD) Cin*1 6.0 pF Vin = 0 V
Output capacitance (Q) CI/O*1 8.0 pF Vout = 0 V
Note: 1. Not 100% tested.
Memory cell characteristics (VCC = 1.8 V to 5.5 V)
Ta=25°C Ta=85°C Notes
Endurance 1,000k Cycles min. 100k Cycles min 1
Data retention 100 Years min. 10 Years min. 1
Notes: 1. Not 100% tested.
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 4 of 20
DC Characteristics
Parameter Symbol Min Max Unit Test conditions
Input leakage current
I
LI 2 µA VCC = 5.5 V, VIN = 0 to 5.5 V
(S, D, C, HOLD, W)
Output leakage current ILO 2 µA VCC = 5.5 V, VOUT = 0 to 5.5 V
(Q)
VCC current Standby ISB 2 µA VIN = VSS or VCC,
VCC = 5.5 V
Active ICC1 2 mA VCC = 5.5 V, Read at 5 MHz
VIN = VCC × 0.1/VCC × 0.9
Q = OPEN
I
CC2 2.5 mA VCC = 5.5 V, Write at 5 MHz
VIN = VCC × 0.1/VCC × 0.9
Output voltage VOL1 0.4 V VCC = 5.5 V, IOL = 2 mA
V
OL2 0.4 V VCC = 2.5 V, IOL = 1.5 mA
V
OH1 V
CC × 0.8 V VCC = 5.5 V, IOH = −2 mA
V
OH2 V
CC × 0.8 V VCC = 2.5 V, IOH = −0.4 mA
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 5 of 20
AC Characteristics
Test Conditions
• Input pules levels:
VIL = VCC × 0.2
VIH = VCC × 0.8
• Input rise and fall time: ≤ 10 ns
• Input and output timing reference levels: VCC × 0.3, VCC × 0.7
• Output reference levels: VCC × 0.5
• Output load: 100 pF (Ta = −40 to +85°C, VCC = 2.5 V to 5.5 V)
Parameter Symbol Alt Min Max Unit Notes
Clock frequency fC f
SCK 5 MHz
S active setup time tSLCH t
CSS1 90 ns
S not active setup time tSHCH t
CSS2 90 ns
S deselect time tSHSL t
CS 90 ns
S active hold time tCHSH t
CSH 90 ns
S not active hold time tCHSL 90 ns
Clock high time tCH t
CLH 90 ns 1
Clock low time tCL t
CLL 90 ns 1
Clock rise time tCLCH t
RC 1 µs 2
Clock fall time tCHCL t
FC 1 µs 2
Data in setup time tDVCH t
DSU 20 ns
Data in hold time tCHDX t
DH 30 ns
Clock low hold time after HOLD not active tHHCH 70 ns
Clock low hold time after HOLD active tHLCH 40 ns
Clock high setup time before HOLD active tCHHL 60 ns
Clock high setup time before HOLD not
active tCHHH 60 ns
Output disable time tSHQZ t
DIS 100 ns 2
Clock low to output valid tCLQV t
V 70 ns
Output hold time tCLQX t
HO 0 ns
Output rise time tQLQH t
RO 50 ns 2
Output fall time tQHQL t
FO 50 ns 2
HOLD high to output low-Z tHHQX t
LZ 50 ns 2
HOLD low to output high-Z tHLQZ t
HZ 100 ns 2
Write time tW t
WC 5 ms
Notes: 1. tCH + tCL ≥ 1/fC
2. Not 100% tested.
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 6 of 20
(Ta = −40 to +85°C, VCC = 1.8 V to 5.5 V)
Parameter Symbol Alt Min Max Unit Notes
Clock frequency fC f
SCK 3 MHz
S active setup time tSLCH t
CSS1 100 ns
S not active setup time tSHCH t
CSS2 100 ns
S deselect time tSHSL t
CS 150 ns
S active hold time tCHSH t
CSH 100 ns
S not active hold time tCHSL 100 ns
Clock high time tCH t
CLH 150 ns 1
Clock low time tCL t
CLL 150 ns 1
Clock rise time tCLCH t
RC 1 µs 2
Clock fall time tCHCL t
FC 1 µs 2
Data in setup time tDVCH t
DSU 30 ns
Data in hold time tCHDX t
DH 50 ns
Clock low hold time after HOLD not active tHHCH 140 ns
Clock low hold time after HOLD active tHLCH 90 ns
Clock high setup time before HOLD active tCHHL 120 ns
Clock high setup time before HOLD not
active tCHHH 120 ns
Output disable time tSHQZ t
DIS 200 ns 2
Clock low to output valid tCLQV t
V 120 ns
Output hold time tCLQX t
HO 0 ns
Output rise time tQLQH t
RO 100 ns 2
Output fall time tQHQL t
FO 100 ns 2
HOLD high to output low-Z tHHQX t
LZ 100 ns 2
HOLD low to output high-Z tHLQZ t
HZ 100 ns 2
Write time tW t
WC 5 ms
Notes: 1. tCH + tCL ≥ 1/fC
2. Not 100% tested.
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 7 of 20
Timing Waveforms
Serial Input Timing
S
C
t
CHSL
t
SLCH
t
CHDX
t
CLCH
t
CHCL
t
SHCH
t
CHSH
t
SHSL
t
DVCH
MSB IN LSB IN
D
QHigh Impedance
Hold Timing
t
CHHL
S
HOLD
C
D
Q
t
HLCH
t
CHHH
t
HLQZ
t
HHQX
t
HHCH
Output Timing
S
C
D
QLSB OUT
ADDR
LSB IN
t
QLQH
t
QHQL
t
SHQZ
t
CH
t
CL
t
CLQV
t
CLQX
t
CLQV
t
CLQX
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 8 of 20
Pin Function
Serial data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of serial
clock (C).
Serial data input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be
written. Values are latched on the rising edge of serial clock (C).
Serial clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at serial data input
(D) are latched on the rising edge of serial clock (C). Data on serial data output (Q) changes after the falling edge of
serial clock (C).
Chip select (S)
When this input signal is high, the device is deselected and serial data output (Q) is at high impedance. Unless an
internal write cycle is in progress, the device will be in the standby mode. Driving chip select (S) low enables the
device, placing it in the active power mode. After power-up, a falling edge on chip select (S) is required prior to the
start of any instruction.
Hold (HOLD)
The hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device.
During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and serial clock (C)
are don’t care. To start the hold condition, the device must be selected, with chip select (S) driven low.
Write protect (W)
This input signal is used to protect the memory against write instructions. When write protect (W) is held low, write
instructions (WRSR, WRITE) are ignored. No action on this signal can interrupt a write cycle that has already started.
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 9 of 20
Functional Description
Status Register
The following figure shows the Status Register Format. The Status Register contains a number of status and control
bits that can be read or set (as appropriate) by specific instructions.
Status Register Format
1 1 1 1 BP1 BP0 WEL WIP
Block Protect Bits
Write Enable Latch Bits
Write In Progress Bits
b0b7
WIP bit: The W rite In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register
cycle.
WEL bit: The W rite Enable Latch (WEL) bit ind icates the status of the internal Write Enable Latch.
BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be protected
against Write in structions.
Instructions
Each instruction starts with a single-byte code, as summarized in the following table . If an invalid instruction is sent
(one not contained in the following table), the device automatically deselects itself.
Instruction Set
Instruction Description Instruction Format
WREN Write Enable 0000 ×110
WRDI Write Disable 0000 ×100
RDSR Read Status Register 0000 ×101
WRSR Write Status Register 0000 ×001
READ Read from Memory Array 0000 A011
WRITE Write to Memory Array 0000 A010
Notes: 1. “×” is Don’t care.
2. “A” is A8 address on the R1EX25004A, and Don’t care on the R1EX25002A.
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 10 of 20
Write Enable (WREN):
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is
to send a Write Enable instruction to the device. As shown in the fo llowin g fig ur e, to sen d th is instru ction to th e dev ice,
chip select (S) is driven low, and the bits of the instruction byte are shifted in, on serial data input (D). The device then
enters a wait state. It waits for the device to be deselected, by chip select (S) being driven high.
Write Enable (WREN) Sequence
S
W
C
D
Q
Instruction
0123456
High-Z
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
7
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 11 of 20
Write Disable (WRDI):
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown
in the following fig ure, to send this instructio n to the device, chip select (S) is driven low, an d the bits of the instruction
byte are shifted in, on serial data input (D).
The device then enters a wait state. It waits for the device to be deselected, by chip select (S) being driven high. The
Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion
WRITE protect (W) is driven low
Write Disable (WRDI) Sequence
S
W
C
D
Q
Instruction
10 234567
High-Z
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 12 of 20
Read Status Register (RDSR):
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at
any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is
recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also
possible to read the Status Register continuously, as shown in the following figure.
Read Status Register (RDSR) Sequence
S
W
C
D
Q
Status Register Out
01234567
012345677
8 9 10 11 12 13 14 15
High-Z
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
The status and control bits of the Status Register are as follows:
WIP bit: The W rite In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register
cycle. When set to 1, such a cycle is in progress. When reset to 0, no such cycles are in progress.
WEL bit: The W rite Enable Latch (WEL) bit ind icates the status of the internal W rite Enable Latch. When set to 1, the
internal Write Enab le Latch is set. When set to 0, th e internal Write Enable Latch is reset an d no Write or Write Status
Register instructions are accepted.
BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software
protected against Write instructions. These bits are written with the Write Status Register (W RSR) instruction. When
one or both of the Block Protect (BP1, BP0) bits are set to 1, the relevant memory area (as defined in the Status
Register Format table) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can
be written provided that the Hardware Protected mode has not been set.
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 13 of 20
Write Status Register (WRSR):
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can b e
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded and executed, the device sets the Write Enable Latch(WEL). The instruction sequence is
shown in the following figure. The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of
the Status Register. b6, b5 and b4 are always read as 0. Chip select (S) must be driven high after the rising edge of
serial clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as chip select (S) is driven high, the
self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in
progress, the Status Reg ister may still be read to check the value of the Write In Progress (WIP) bit. The W rite In
Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, an d is 0 when it is completed. When th e
cycle is completed, Write Enable Latch( WEL) is reset. The Write Status Register (WRSR) instruction allows the user
to change the values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-only,
as defined in the Status Register Format table.
The contents of Block Protect (BP1, BP0) bits are frozen at their current values just before the start of the execution of
the Write Status Register (WRSR) instruction. The new, updated values take effect at the moment of completion of the
execution of Write Status Register (WRSR) instruction.
Write Status Register (WRSR) Sequence
S
W
C
D
Q
Status Register In
MSB
01234567
01234567
8 9 10 11 12 13 14 15
High-Z
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 14 of 20
Read from Memory Array (READ):
As shown in the following figure, to send this instruction to the device, ch ip select (S) is first driven low. The bits of
the instruction byte and the address bytes are then shifted in, on serial data input (D). The addresses are loaded into an
internal address register, and the byte of data at that address is shifted out, on serial data output (Q). The most
significant address (A8) should be sent as fifth bit in the instruction byte.
If chip select (S) continues to be dr iven low, the internal addr ess register is automatically incremented, and the byte of
data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued
indefinitely. The whole memory can, therefore, be read with a single READ instruction.
The Read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can occur at
any time during the cycle. The addressed first byte can be any byte within any page. The instruction is not accepted,
and is not executed, if a Write cycle is currently in progress.
Read from Memory Array (READ) Sequence
S
W
C
D
Q
8-Bit Address
Data Out 2Data Out 1
01234567
A0A1A2A3A5A6A7A8
8 9 10 12 13 14 15 16 17 18 19 20 21 22 23
High-Z
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
012345677
Instruction
Note: 1. Depending on the memory size, as shown in the following table, the most significant address bits are don’t
care.
Address Range Bits
Device R1EX25004A R1EX25002A
Address bits A8 to A0 A7 to A0
Note: 1. A8 is don’t care on the R1EX25002A.
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 15 of 20
Write to Memory Array (WRITE):
As shown in the following figure, to send this instruction to the device, ch ip select (S) is first driven low. The bits of
the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (D).
The instruction is terminated by driving chip select (S) high at a byte boundary of the input data. In the case of the
following figur e, this occurs after the eighth bit of the data byte has been latched in , indicating that the instruction is
being used to write a single byte. The self-timed Write cycle starts, and continues for a period tWC (as specified in AC
Characteristics). At the end of the cycle, th e Write In Progress (WIP) bit is reset to 0.
If, though, chip select (S) continues to be driven low, as shown in the following figure, the next byte of the input data is
shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be
written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the
number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the
beginning of the page, and the previo us data there are overwritten with the incoming data. (The page size of these
device is 32 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
If the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before)
If a Write cycle is already in progress
If the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
If Write Protect (W) is low
Byte Write (WRITE) Sequence (1 Byte)
S
W
C
D
Q
8-Bit Address Data Byte 1
01234567
0123A5A6A7
8 9 10 12 13 14 15 16 17 18 19 20 21 22 23
High-Z
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
4567A0A1A2
A3
Instruction
A8
Note: 1. Depending on the memory size, as shown in Address Range Bits table, the most significant address bit is
don’t care.
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 16 of 20
Byte Write (WRITE) Sequence (Page)
S
W
C
D
Q
8-Bit Address Data Byte 1
01234567
0123A5A6A7
8 9 10 12 13 14 15 16 17 18 19 20 21 22 23
High-Z
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
4567A0A1A2A3
Instruction
S
W
C
D
Q
Data Byte 3 Data Byte N
24 25 26 27 28 29 30 31
7
32 33 34 35 36 37 38 39
High-Z
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0
Data Byte 2
A8
Note: 1. Depending on the memory size, as shown in Address Range Bits table, the most significant address bit is
don’t care.
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 17 of 20
Data Protect
The Block Protect bits (BP1, BP0) define the area of memory that is protected against the execution of write cycle, as
summarized in the following table.
When Write Protect (W) is driv en low, write to memory array (WRITE) and write status register (WRSR) are disabled,
and WEL bit is reset.
Write Protected Block Size
Status register bits Array addresses protected
BP1 BP0 Protected blocks R1EX25004A R1EX25002A
0 0 None None None
0 1 Upper quarter 180h − 1FFh C0h − FFh
1 0 Upper half 100h − 1FFh 80h − FFh
1 1 Whole memory 000h − 1FFh 00h − FFh
Hold Condition
The hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking
sequence.
During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and serial clock (C)
are don’t care.
To enter the hold condition, the device must be selected, with chip select (S) low.
Normally, the device is kept selected, for the whole duration of the hold condition. Deselecting the device while it is in
the hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to
reset any processes that had been in progress.
The hold condition starts when the hold (HOLD) signal is driven low at the same time as serial clock (C) already being
low (as shown in the following figure).
The hold condition ends when the hold (HOLD) signal is driven high at the same time as serial clock (C) already being
low.
The following figure also shows what happens if the rising and falling edges are not timed to coincide with serial clock
(C) being low.
Hold Condition Activation
C
HOLD
HOLD status HOLD status
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 18 of 20
Notes
Data Protection at VCC On/Off
When VCC is turned on or off, noise on S inputs generated by external circuits (CPU, etc) may act as a trigger and turn
the EEPROM to unintentional program mode. To prevent this unintentional programming, this EEPROM have a power
on reset function. Be careful of the notices described below in order for the power on reset function to operate
correctly.
• S should be fixed to VCC during VCC on/off. Low to high or high to low transition during VCC on/off may
cause the trigger for the unintentional programming.
• VCC should be turned on/off after the EEPROM is placed in a standby state.
• VCC should be turned on from the ground level (VSS) in order for the EEPROM not to enter the unintentional
programming mode.
• VCC turn on speed should be slower than 10 µs/V.
• When WRSR or WRITE instruction is executed before VCC turns off, VCC should be turned off after waiting
write cycle time (tW).
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 19 of 20
Package Dimensions
R1EX25002ASA00A/R1EX25004ASA00A (PRSP0008DF-B / Previous Code: FP-8DBV)
PRSP0008DF-BP-SOP8-3.9x4.89-1.27
A
L
e
c
b
D
E
A
b
c
θ
x
y
H
Z
L
2
1
1
E
1
MASS[Typ.]
0.08g
4.89
1.06
0.25
0
°
8
°
6.02
0.15 0.20 0.25
0.45
0.102 0.14 0.254
3.90
0.406 0.60 0.889
1.73
Reference
Symbol
Dimension in Millimeters
Min Nom Max
Previous CodeJEITA Package Code RENESAS Code
FP-8DBV
5.15
1
A
p
0.35 0.40
6.205.84
1.27
0.10
0.69
Index mark
E
1
y
xM
p
*3
*2
*1
F
4
85
D
E
H
A
Zb
p
Terminal cross section
( Ni/Pd/Au plating )
b
c
Detail F
1
1
L
L
A
θ
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
e
R1EX25002Axx00A/R1EX25004Axx00A
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 20 of 20
R1EX25002ATA00A/R1EX25004ATA00A (PTSP0008JC-B / Previous Code: TTP-8DAV)
PTSP0008JC-BP-TSSOP8-4.4x3-0.65
A
L
e
c
b
D
E
A
b
c
θ
x
y
H
Z
L
2
1
1
E
1
MASS[Typ.]
0.034g
3.00
1.00
0.13
0
°
8
°
6.40
0.10 0.15 0.20
0.25
0.03 0.07 0.10
4.40
0.40 0.50 0.60
1.10
Reference
Symbol
Dimension in Millimeters
Min Nom Max
Previous CodeJEITA Package Code RENESAS Code
TTP-8DAV
3.30
1
A
p
0.15 0.20
6.606.20
0.65
0.10
0.805
*1
85
E
*2
Index mark
14
*3
p
Mx
y
F
A
D
E
H
Zb
Detail F
1
1
A
L
L
θ
p
Terminal cross section
( Ni/Pd/Au plating )
c
b
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
e
Revision History R1EX25002Axx00A/R1EX25004Axx00A
Data Sheet
Contents of Modification Rev. Date Page Description
0.01 Jan.25, 2008 Initial issue
0.02 Jan.14, 2009 P1
P3
P4
P5/P6
Features
Endurance cycles change 106 cycles to 1,000k cycles @25°C.
Data retentions years change 10 years to 100 years @25°C.
Capacitance new is described.
Memory cell characteristics new is described.
DC characteristics
Output voltage VOH1, VOH2 test conditions change IoL to IoH.
AC characteristics
Erase/Write endurance is deleted.
Notes1. change Not 100% tested.
Notes3 deleted.
Notes:
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