SRAM MT5C6401 64K x 1 SRAM PIN ASSIGNMENT (Top View) SRAM MEMORY ARRAY 22-Pin DIP (C) (300 MIL) AVAILABLE AS MILITARY SPECIFICATIONS A0 A1 A2 A3 A4 A5 A6 A7 Q WE\ Vss * SMD 5962-86015 * MIL-STD-883 FEATURES * Speeds: 12, 15, 20, 25, 35, 45, 55, and 70ns * Battery Backup: 2V data retention * High-performance, low-power CMOS double-metal process * Single +5V (+10%) Power Supply * Easy memory expansion with CE\ * All inputs and outputs are TTL compatible OPTIONS MARKING * Timing 12ns access 15ns access 20ns access 25ns access 35ns access 45ns access 55ns access 70ns access -12 -15 -20 -25 -35 -45* -55* -70* * Package(s) Ceramic DIP (300 mil) C No. 105 Vcc A15 A14 A13 A12 A11 A10 A9 A8 D CE\ The Micross Components SRAM family employs high-speed, low-power CMOS designs using a four-transistor memory cell. Micross Components SRAMs are fabricated using double-layer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, Austin Semiconductor offers chip enable (CE\) on all organizations. This enhancement can place the outputs in High-Z for additional flexibility in system design. The X1 configuration features separate data input and output. Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ goes LOW. The device offers a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements. All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible. L For more products and information please visit our web site at www.micross.com *Electrical characteristics identical to those provided for the 35ns access devices. MT5C6401 Rev. 1.2 01/10 22 21 20 19 18 17 16 15 14 13 12 GENERAL DESCRIPTION * Operating Temperature Ranges Industrial (-40oC to +85oC) IT Military (-55oC to +125oC) XT * 2V data retention/low power 1 2 3 4 5 6 7 8 9 10 11 Micross Components reserves the right to change products or specifications without notice. 1 SRAM MT5C6401 FUNCTIONAL BLOCK DIAGRAM VCC GND A D A A A I/O CONTROL A ROW DECODER A 65,536-BIT MEMORY ARRAY Q CE\ A (LSB) WE\ COLUMN DECODER POWER DOWN (LSB) A A A A A A A A A TRUTH TABLE MODE STANDBY READ WRITE MT5C6401 Rev. 1.2 01/10 CE\ H L L WE\ X H L DQ HIGH-Z Q HIGH-Z POWER STANDBY ACTIVE ACTIVE Micross Components reserves the right to change products or specifications without notice. 2 SRAM MT5C6401 ABSOLUTE MAXIMUM RATINGS* Voltage on any Input Relative to Vss................-2.0V to +7.0V Voltage on Vcc Supply Relative to Vss............-1.0V to +7.0V Voltage Applied to Q.........................................-1.0V to +7.0V Storage Temperature......................................-65oC to +150oC Power Dissipation.................................................................1W Max Junction Temperature............................................+175C Lead Temperature (soldering 10 seconds)...................+260oC Short Circuit Output Current...........................................50mA *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC < TC < 125oC; VCC = 5V +10%) DESCRIPTION Input High (Logic 1) Voltage CONDITIONS VIH MIN 2.2 VIL -0.5 0.8 V 0V < VIN < VCC ILI -10 10 A Outputs Disabled 0V < VOUT < VCC ILO -10 10 A Output High Voltage IOH = -4.0mA VOH 2.4 --- V 1 Output Low Voltage IOL = 8.0mA VOL --- 0.4 V 1 Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current SYM MAX UNITS NOTES Vcc+1.0V V 1 1, 2 CONDITIONS SYM -12 -15 MAX -20 -25 -35 Power Supply Current: Operating CE\ < VIL; VCC = MAX Output Open Icc 140 125 110 100 90 mA Power Supply Current: Standby CE\ > VIH; VCC = MAX ISBT1 45 41 36 33 30 mA ISBT2 25 25 25 25 25 mA ISBC2 5 5 5 5 5 mA PARAMETER f = 1/tRC (MIN) Hz UNITS NOTES 3 CE\ > VIH; All Other Inputs < VIL or > VIH, VCC = MAX f = 0 Hz CE\ > (VCC -0.2); VCC = MAX All Other Inputs < 0.2V or > (VCC - 0.2V), f = 0 Hz CAPACITANCE DESCRIPTION Input Capacitance Output Capacitance MT5C6401 Rev. 1.2 01/10 CONDITIONS o TA = 25 C, f = 1MHz Vcc = 5V SYM MAX UNITS NOTES CI 6 pF 4 CO 7 pF 4 Micross Components reserves the right to change products or specifications without notice. 3 SRAM MT5C6401 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 5) (-55oC < TC < 125oC; VCC = 5V +10%) DESCRIPTION READ CYCLE READ cycle time Address access time Chip Enable access time Output hold from address change Chip Enable to output in Low-Z Chip disable to output in High-Z Chip Enable to power-up time Chip disable to power-down time WRITE CYCLE WRITE cycle time Chip Enable to end of write Address valid to end of write Address setup time Address hold from end of write WRITE pulse width Data setup time Data hold time Write disable to output in Low-Z Write Enable to output in High-Z MT5C6401 Rev. 1.2 01/10 -12 -15 -20 -25 -35 SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES tRC tAA tACE tOH tLZCE tHZCE tPU tPD 12 tWC tCW tAW tAS tAH tWP tDS tDH 12 10 10 0 0 10 7 0 2 0 tLZWE tHZWE 15 12 10 2 2 20 15 13 2 2 7 0 2 2 8 0 12 6 2 2 0 7 8 15 ns ns ns ns ns ns ns ns ns ns 2 2 0 15 0 25 25 20 20 0 0 20 12 0 2 0 35 ns ns ns ns ns ns ns ns 35 25 12 20 20 15 15 0 0 15 10 0 2 0 35 25 20 10 15 15 12 12 0 0 12 8 0 2 0 25 20 15 10 35 25 25 0 0 25 15 0 2 0 7 6, 7 7 6, 7 Micross Components reserves the right to change products or specifications without notice. 4 SRAM MT5C6401 AC TEST CONDITIONS 480 Input pulse levels ...................................... Vss to 3.0V Input rise and fall times ......................................... 5ns Input timing reference levels ................................ 1.5V Output reference levels ....................................... 1.5V Output load ................................. See Figures 1 and 2 Q Q 5 pF 255 Fig. 1 Output Load Equivalent NOTES Fig. 2 Output Load Equivalent 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE. 8. WE\ is HIGH for READ cycle. 9. Device is continuously selected. Chip enable is held in its active state. 10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC = READ Cycle Time. 12. Chip enable (CE\) and write enable (WE\) can initiate and terminate a WRITE cycle. 1. 2. 3. All voltages referenced to VSS (GND). -3V for pulse width < 20ns ICC is dependent on output loading and cycle rates. The specified value applies with the outputs unloaded, and f = 1 Hz. t RC (MIN) 4. This parameter is sampled. 5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. 6. tHZCE and tHZWE are specified with CL = 5pF as in Fig. 2. Transition is measured 500mV typical from steady state voltage, allowing for actual tester RC time constant. DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only) DESCRIPTION CONDITIONS VCC for Retention Data Data Retention Current SYM MIN MAX UNITS VDR 2 --- V NOTES CE\ > (VCC - 0.2V) VCC = 2V ICCDR --- 300 A VIN > (VCC - 0.2V) or < 0.2V VCC = 3V ICCDR --- 500 A tCDR 0 --- ns 4 tR tRC --- ns 4, 11 Chip Deselect to Data Retention Time Operation Recovery Time LOW Vcc DATA RETENTION WAVEFORM VCC 4.5V DATA RETENTION MODE 4.5V V > 2V DR tCDR CE\ VIH VIL tR VDR DON'T CARE UNDEFINED MT5C6401 Rev. 1.2 01/10 Micross Components reserves the right to change products or specifications without notice. 5 SRAM MT5C6401 READ CYCLE NO. 1 8, 9 READ CYCLE NO. 2 7, 8, 10 Q DON'T CARE UNDEFINED MT5C6401 Rev. 1.2 01/10 Micross Components reserves the right to change products or specifications without notice. 6 SRAM MT5C6401 WRITE CYCLE NO. 1 12 (Chip Enabled Controlled) WRITE CYCLE NO. 2 7, 12, 13 (Write Enabled Controlled) DON'T CARE UNDEFINED MT5C6401 Rev. 1.2 01/10 Micross Components reserves the right to change products or specifications without notice. 7 SRAM MT5C6401 MECHANICAL DEFINITIONS* Micross Case #105 (Package Designator C) SMD 5962-86015, Case Outline X S D S2 A Q L1 E L S1 b1 e b Pin 1 E1 c SYMBOL A b b1 c D E E1 e L L1 Q S S1 S2 SMD SPECIFICATIONS MIN MAX --0.200 0.014 0.023 0.030 0.065 0.008 0.015 --1.260 0.220 0.310 0.290 0.320 0.100 BSC 0.125 0.200 0.150 --0.015 0.060 --0.080 0.005 --0.005 --- NOTE: These dimensions are per the SMD. Micross' package dimensional limits may differ, but they will be within the SMD limits. * All measurements are in inches. MT5C6401 Rev. 1.2 01/10 Micross Components reserves the right to change products or specifications without notice. 8 SRAM MT5C6401 ORDERING INFORMATION EXAMPLE: MT5C6401C-45L/883C Device Number Package Speed Options** Process Type ns MT5C6401 C -12 L /* MT5C6401 MT5C6401 C -15 L /* C -20 L /* MT5C6401 C -25 L /* MT5C6401 C -35 L /* MT5C6401 C -45 L /* MT5C6401 C -55 L /* MT5C6401 C -70 L /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range 883C = Full Military Processing -40oC to +85oC -55oC to +125oC -55oC to +125oC ** OPTIONS L = 2V Data Retention/Low Power MT5C6401 Rev. 1.2 01/10 Micross Components reserves the right to change products or specifications without notice. 9 SRAM MT5C6401 MICROSSTO DSCC PART NUMBER CROSS REFERENCE* Micross Package Designator C SMD 5962-86015 Micross Part # MT5C6801C-35/883C MT5C6801C-35L/883C MT5C6801C-45/883C MT5C6801C-45L/883C MT5C6801C-55/883C MT5C6801C-55L/883C SMD Part # 5962-8601501XA 5962-8601502XA 5962-8601503XA 5962-8601504XA 5962-8601505XA 5962-8601506XA *Micross part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD. MT5C6401 Rev. 1.2 01/10 Micross Components reserves the right to change products or specifications without notice. 10