SRAM
MT5C6401
MT5C6401
Rev. 1.2 01/10
Micross Components reserves the right to change products or speci cations without notice.
1
FEATURES
Speeds: 12, 15, 20, 25, 35, 45, 55, and 70ns
Battery Backup: 2V data retention
High-performance, low-power CMOS double-metal
process
Single +5V (+10%) Power Supply
Easy memory expansion with CE\
All inputs and outputs are TTL compatible
OPTIONS MARKING
• Timing
12ns access -12
15ns access -15
20ns access -20
25ns access -25
35ns access -35
45ns access -45*
55ns access -55*
70ns access -70*
• Package(s)
Ceramic DIP (300 mil) C No. 105
• Operating Temperature Ranges
Industrial (-40oC to +85oC) IT
Military (-55oC to +125oC) XT
2V data retention/low power L
*Electrical characteristics identical to those provided for the 35ns ac-
cess devices.
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-86015
• MIL-STD-883
GENERAL DESCRIPTION
The Micross Components SRAM family employs high-speed,
low-power CMOS designs using a four-transistor memory cell.
Micross Components SRAMs are fabricated using double-layer
metal, double-layer polysilicon technology.
For exibility in high-speed memory applications, Austin
Semiconductor offers chip enable (CE\) on all organizations.
This enhancement can place the outputs in High-Z for additional
exibility in system design. The X1 con guration features
separate data input and output.
W riting to these devices is accomplished when write enable
(WE\) and CE\ inputs are both LOW. Reading is accomplished
when WE\ remains HIGH and CE\ goes LOW. The device of-
fers a reduced power standby mode when disabled. This
allows system designs to achieve low standby power require-
ments.
All devices operate from a single +5V power supply and all
inputs and outputs are fully TTL compatible.
64K x 1 SRAM
SRAM MEMORY ARRAY
For more products and information
please visit our web site at
www.micross.com
22-Pin DIP (C)
(300 MIL)
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
A0
A1
A2
A3
A4
A5
A6
A7
Q
WE\
Vss
Vcc
A15
A14
A13
A12
A11
A10
A9
A8
D
CE\
SRAM
MT5C6401
MT5C6401
Rev. 1.2 01/10
Micross Components reserves the right to change products or speci cations without notice.
2
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
ROW DECODER
65,536-BIT
MEMORY ARRAY
I/O CONTROL
VCC GND
D
WE\
A
A
A
A
A
A
A
COLUMN DECODER
A A A A A A A A A
POWER
DOWN
CE\
(LSB)
(LSB)
Q
MODE CE\ WE\ DQ POWER
STANDBY H X HIGH-Z STANDBY
READ L H Q ACTIVE
WRITE L L HIGH-Z ACTIVE
SRAM
MT5C6401
MT5C6401
Rev. 1.2 01/10
Micross Components reserves the right to change products or speci cations without notice.
3
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Input Relative to Vss................-2.0V to +7.0V
Voltage on Vcc Supply Relative to Vss............-1.0V to +7.0V
Voltage Applied to Q.........................................-1.0V to +7.0V
Storage Temperature…...................................-65oC to +150oC
Power Dissipation.................................................................1W
Max Junction Temperature............................................+175°C
Lead Temperature (soldering 10 seconds)...................+260oC
Short Circuit Output Current...........................................50mA
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operation section of this speci cation is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TC < 125oC; VCC = 5V +10%)
CAPACITANCE
DESCRIPTION CONDITIONS SYM MIN MAX UNITS NOTES
Input High (Logic 1) Voltage VIH 2.2 Vcc+1.0V V 1
Input Low (Logic 0) Voltage VIL -0.5 0.8 V 1, 2
Input Leakage Current 0V < VIN < VCC ILI-10 10 μA
Output Leakage Current Outputs Disabled
0V < VOUT < VCC
ILO-10 10 μA
Output High Voltage IOH = -4.0mA VOH 2.4 --- V 1
Output Low Voltage IOL = 8.0mA VOL --- 0.4 V 1
SYM -12 -15 -20 -25 -35 UNITS NOTES
I
cc
140 125 110 100 90 mA 3
Power Supply
Current: Standby I
SBT1
45 41 36 33 30 mA
I
SBT2
25 25 25 25 25 mA
I
SBC2
55555mA
Power Supply
Current: Operating
PARAMETER
CE\ > (V
CC
-0.2); V
CC
= MAX
All Other Inputs < 0.2V
or > (V
CC
- 0.2V), f = 0 Hz
CE\ > V
IH
; V
CC
= MAX
f = 1/t
RC
(MIN) Hz
MAX
CONDITIONS
CE\ < V
IL
; V
CC
= MAX
Output Open
CE\ > V
IH
; All Other Inputs
< V
IL
or > V
IH
, V
CC
= MAX
f = 0 Hz
DESCRIPTION CONDITIONS SYM MAX UNITS NOTES
Input Capacitance CI6pF 4
Output Capacitance CO7pF 4
TA = 25oC, f = 1MHz
Vcc = 5V
SRAM
MT5C6401
MT5C6401
Rev. 1.2 01/10
Micross Components reserves the right to change products or speci cations without notice.
4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55oC < TC < 125oC; VCC = 5V +10%)
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
READ CYCLE
READ cycle time tRC 12 15 20 25 35 ns
Address access time tAA 12 15 20 25 35 ns
Chip Enable access time tACE 10 13 15 20 25 ns
Output hold from address change tOH 22222 ns
Chip Enable to output in Low-Z tLZCE 22222 ns7
Chip disable to output in High-Z tHZCE 7 8 10 12 15 ns 6, 7
Chip Enable to power-up time tPU 00000 ns
Chip disable to power-down time tPD 12 15 20 25 35 ns
WRITE CYCLE
WRITE cycle time tWC 12 15 20 25 35 ns
Chip Enable to end of write tCW 10 12 15 20 25 ns
Address valid to end of write tAW 10 12 15 20 25 ns
Address setup time tAS 00000 ns
Address hold from end of write tAH 00000 ns
WRITE pulse width tWP 10 12 15 20 25 ns
Data setup time tDS 7 8 10 12 15 ns
Data hold time tDH 00000 ns
Write disable to output in Low-Z tLZWE 22222 ns7
Write Enable to output in High-Z tHZWE 060708010015ns 6, 7
NOTES
DESCRIPTION -12
SYMBOL UNITS
-35-25-20-15
SRAM
MT5C6401
MT5C6401
Rev. 1.2 01/10
Micross Components reserves the right to change products or speci cations without notice.
5
AC TEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
NOTES
1. All voltages referenced to VSS (GND).
2. -3V for pulse width < 20ns
3. ICC is dependent on output loading and cycle rates.
The speci ed value applies with the outputs
unloaded, and f = 1 Hz.
tRC (MIN)
4. This parameter is sampled.
5. Test conditions as speci ed with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tHZCE and tHZWE are speci ed with CL = 5pF as in Fig.
2. Transition is measured ±500mV typical from steady state
voltage, allowing for actual tester RC time constant.
7. At any given temperature and voltage condition,
tHZCE is less than tLZCE, and tHZWE is less than tLZWE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enable is held in
its active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. t
RC = READ Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate
and terminate a WRITE cycle.
Fig. 1 Output Load
Equivalent Fig. 2 Output Load
Equivalent
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DON’T CARE
UNDEFINED
LOW Vcc DATA RETENTION WAVEFORM
DATA RETENTION MODE
VDR > 2V
4.5V 4.5V
VDR
tCDR tR
VIH
VIL
VCC
CE\
5 pF
Q
255
480
Q
DESCRIPTION SYM MIN MAX UNITS NOTES
V
CC
for Retention Data V
DR
2 --- V
V
CC
= 2V I
CCDR
--- 300 μA
V
CC
= 3V I
CCDR
--- 500 μA
Chip Deselect to Data
Retention Time t
CDR
0 --- ns 4
Operation Recovery Time t
R
t
RC
--- ns 4, 11
CONDITIONS
Data Retention Current
CE\ > (V
CC
- 0.2V)
V
IN
> (V
CC
- 0.2V)
or < 0.2V
SRAM
MT5C6401
MT5C6401
Rev. 1.2 01/10
Micross Components reserves the right to change products or speci cations without notice.
6
DON’T CARE
UNDEFINED
READ CYCLE NO. 1 8, 9
READ CYCLE NO. 2 7, 8, 10
Q
SRAM
MT5C6401
MT5C6401
Rev. 1.2 01/10
Micross Components reserves the right to change products or speci cations without notice.
7
WRITE CYCLE NO. 2 7, 12, 13
(Write Enabled Controlled)
DON’T CARE
UNDEFINED
WRITE CYCLE NO. 1 12
(Chip Enabled Controlled)
SRAM
MT5C6401
MT5C6401
Rev. 1.2 01/10
Micross Components reserves the right to change products or speci cations without notice.
8
MECHANICAL DEFINITIONS*
Micross Case #105 (Package Designator C)
SMD 5962-86015, Case Outline X
NOTE: These dimensions are per the SMD. Micross’ package dimensional limits
may differ, but they will be within the SMD limits.
* All measurements are in inches.
D
E
Pin 1
A
Q
L
eb
b1
S1
L1
S
S2
E1 c
MIN MAX
A --- 0.200
b 0.014 0.023
b1 0.030 0.065
c 0.008 0.015
D --- 1.260
E 0.220 0.310
E1 0.290 0.320
e
L 0.125 0.200
L1 0.150 ---
Q 0.015 0.060
S --- 0.080
S1 0.005 ---
S2 0.005 ---
SYMBOL
0.100 BSC
SMD SPECIFICATIONS
SRAM
MT5C6401
MT5C6401
Rev. 1.2 01/10
Micross Components reserves the right to change products or speci cations without notice.
9
*AVAILABLE PROCESSES
IT = Industrial Temperature Range -40oC to +85oC
XT = Extended Temperature Range -55oC to +125oC
883C = Full Military Processing -55oC to +125oC
** OPTIONS
L = 2V Data Retention/Low Power
ORDERING INFORMATION
Device Number Package
Type Speed
ns Options** Process
MT5C6401 C -12 L /*
MT5C6401 C -15 L /*
MT5C6401 C -20 L /*
MT5C6401 C -25 L /*
MT5C6401 C -35 L /*
MT5C6401 C -45 L /*
MT5C6401 C -55 L /*
MT5C6401 C -70 L /*
EXAMPLE: MT5C6401C-45L/883C
SRAM
MT5C6401
MT5C6401
Rev. 1.2 01/10
Micross Components reserves the right to change products or speci cations without notice.
10
MICROSSTO DSCC PART NUMBER
CROSS REFERENCE*
Micross Package Designator C
SMD 5962-86015
Micross Part # SMD Part #
MT5C6801C-35/883C 5962-8601501XA
MT5C6801C-35L/883C 5962-8601502XA
MT5C6801C-45/883C 5962-8601503XA
MT5C6801C-45L/883C 5962-8601504XA
MT5C6801C-55/883C 5962-8601505XA
MT5C6801C-55L/883C 5962-8601506XA
*Micross part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.