ADC08B200CIVS/NOPB - Texas Instruments High-Performance Analog

ADC08B200

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SNAS388F –MARCH 2007–REVISED APRIL 2013

ADC08B200 / ADC08B200Q 8-Bit, 200 MSPS A/D Converter with Capture Buffer

Check for Samples: ADC08B200

1FEATURES DESCRIPTION

The ADC08B200 is a high speed analog-to-digital

2• Single-Ended Input converter (ADC) with an integrated capture buffer.

• Selectable Capture Buffer Size The 8-bit, 200 MSPS A/D core is based upon the

• PLL for Clock Multiplication proven ADC08200 with integrated track-and-hold and

is optimized for low power consumption. This device

• Reference Ladder Top and Bottom Accessible contains a selectable size capture buffer of up to

• Linear Power Scaling with Sample Rate 1,024 bytes that allows fast capture of an input signal

• FPGA Training Pattern with a slower readout rate. An on-chip clock PLL

circuit provides the option of on-chip clock rate

• AEC-Q100 Grade 2 Qualified multiplication to provide the high speed sampling

• Power-Down Feature clock.

The ADC08B200 is resistant to latch-up and the

APPLICATIONS outputs are short-circuit proof. The top and bottom of

• Laser Ranging the ADC08B200's reference ladder are available for

• RADAR connections, enabling a wide range of input

possibilities. The digital outputs are TTL/CMOS

• Pulse Capturing compatible with a separate output power supply pin

to support interfacing with 2.7V to 3.3V logic. The

KEY SPECIFICATIONS digital inputs and outputs are low voltage TTL/CMOS

(PLL Bypassed) compatible and the output data format is straight

binary.

• Resolution 8 Bits

• Maximum Sampling Frequency 200 MSPS The ADC08B200Q runs on an Automotive Grade

(min) Flow and is AEC-Q100 Grade 2 Qualified.

• DNL ±0.4 LSB (typ) The ADC08B200 is offered in a 48-pin plastic

package (TQFP) and is specified over the extended

• ENOB (fIN= 49 MHz) 7.2 bits (typ) industrial temperature range of −40°C to +105°C. An

• THD (fIN= 49 MHz) −53 dBc (typ) evaluation board is available to assist in the easy

• Power Consumption evaluation of the ADC08B200.

– Operating (50 MHz) Input 2 mW / Msps (typ)

– Power Down 2.15 mW (typ)

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

VRT

VRM

256

SWITCHES

CLOCK

GEN

COARSE/FINE

COMPARATORS

ENCODER

& ERROR

CORRECTION

CLK

COARSE/FINE

COMPARATORS

ENCODER

& ERROR

CORRECTION

GND

VIN

MUX 8

VRB

VIN

GND

MULT(1:0)

PDADCRESET

8DATA

OUT

VDR

GND

(pin 30)

CAPTURE

BUFFER

MUX 8

FLAG

LOGIC

WRITE

CONTROL

WEN BSIZE(1:0)

ASW

WENSYNC

REN

RCLK

READ

CONTROL

Read Pointer

Write

Pointer

Sampling Clock D

OUTPUT

DRIVERS

ADC08B200

VDR

DRDY

DR GND

ASW

OEDGE/TEN

WEN

WENSYNC

RCLK

REN

GND

RESET

BSIZE1

BSIZE0

GND

VRT

GND

VIN

SIG GND

GND

VRM

VRB

GND

CLK

GND

PDADC

MUL1

MUL0

ADC08B200

SNAS388F –MARCH 2007–REVISED APRIL 2013

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PIN CONFIGURATION

Figure 1. TQFP Package

See Package Number PFB0048A

Block Diagram

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SNAS388F –MARCH 2007–REVISED APRIL 2013

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

6 VIN Analog signal input. Conversion range is VRB to VRT.

Analog Input that is the high (top) side of the reference ladder

of the ADC. Voltage on VRT and VRB inputs define the VIN

3 VRT conversion range. VRT should be more positive than VRB.

Bypass well.

Analog input that is the mid-point of the reference ladder. This

9 VRM pin should be bypassed to a quiet point in the ground plane

with a 0.1 µF capacitor. DO NOT LOAD this pin.

Analog Input that is the low side (bottom) of the reference

10 VRB ladder of the ADC. The voltages on VRT and VRB inputs define

the VIN conversion range. Bypass well.

Chip Power Down input. When this pin is high, the entire chip

13 PD is in the Power Down mode. Any data in the capture buffer is

lost and the output pins hold the last byte that was output.

ADC Power Down Input. When this pin is high, the ADC is

41 PDADC powered down. The capture buffer is active and the data

within it may be clocked out.

CMOS/TTL compatible digital clock Input. When the PLL is

bypassed, the clock signal at this pin is the ADC sampling

clock and VIN is sampled on the rising edge of this clock input.

46 CLK When the PLL is enabled, the signal at this input is the

reference clock, which is multiplied to provide a higher

frequency sample clock.

Buffer Read Clock input. When the capture buffer is enabled,

this input signal is used to read the data from the internal

19 RCLK buffer. The data output and the buffer empty flag (EF)

transition with the rise of this clock.

Write Enable input. A high level at this input causes a byte of

17 WEN data to be written into the capture buffer with the rise of each

sample clock.

Read Enable input. A high level at this input causes a byte of

data to be read from the capture buffer with the rise of each

20 REN RCLK input. This rise of the REN input should be synchronous

with the RCLK input and should not be high while the WEN

input is high.

Device Reset Input. A high level at this input resets all control

22 RESET logic on the chip.

Output Enable input. A high level at this input enables the

37 OE output buffers. A low level at this input puts the digital data

output pins into a high impedance state.

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Pin No. Symbol Equivalent Circuit Description

Output Edge Select or Test Mode Enable input. If this input is

high, the data outputs transition with the rising edge of the

14 OEDGE/TEN DRDY output. If this input is low, the data outputs transition

with the falling edge of the DRDY output. Forcing a potential

of VA/2 at this input enables the Test Mode.

Synchronized WEN output. The WEN control input is

18 WENSYNC synchronized on-chip with the internal sample clock and is

provided at this output.

Data Ready output. This signal transitions with the transition of

31 DRDY the digital data outputs and indicates that the output data is

ready.

26 thru 29

and D0–D7 Digital data digital Outputs. D0 is the LSB, D7 is the MSB.

33 thru 36 Buffer Full Flag. This output is high when the capture buffer is

16 FF full.

Buffer Empty Flag. This output is high when the capture buffer

15 EF is empty.

Auto-Stop Write input. This pin has a dual function. With the

buffer enabled, this pin acts as the ASW input. When this

input is high, writing to the buffer is halted when the capture

25 ASW buffer is full (FF high). When the buffer is disabled, this pin is

ignored. When the device is in Test Mode, this pin acts as the

Output Edge Select signal, functioning in accordance with the

description of the OEDGE/TEN pin.

Buffer Size input. These inputs determine the size of the

23,24 BSIZE(1:0) buffer, as described in the Functional Description.

Clock Multiply Factor input. These inputs determine the

38, 39 MULT(1:0) internal clock PLL's multiplication factor.

Positive analog supply pin. Connect to a voltage source of

1, 4, 12 VA+3.3V.

43, 44, 48 VPPLL supply pin. Connect to a voltage source of +3.3V.

40 VDDigital core supply pin. Connect to a voltage source of +3.3V.

Power supply for the output drivers. Connect to a voltage

32 VDR source of 2.7V to VD.

2, 5, 8, 11, 21, GND The ground return for the chip core.

42, 45, 47

7 SIG GND Analog input signal ground.

30 DR GND The ground return for the output drivers.

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS (1)(2)(3)

Supply Voltage (VA, VP, VD, VDR) -0.3V to 3.8V

Driver Supply Voltage (VDR) -0.3V to VA+0.3V

Voltage on Any Input or Output Pin −0.3V to VA

Reference Voltage (VRT, VRB) GND to VA

Input Current, Data Outputs ±1 mA

Input Current all other pins (4) ±25 mA

Package Input Current (4) ±50 mA

Power Dissipation at TA= 25°C See (5)

ESD Susceptibility (6) Human Body Model 2500V

Machine Model 200V

Charged Device Model 1000V

Soldering Temperature, Infrared, 10 seconds 235°C

Storage Temperature −65°C to +150°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For specifications and test conditions, see the Electrical

Characteristics. The specifications apply only for the test conditions listed. Some performance characteristics may degrade when the

device is not operated under the listed test conditions.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.

(4) When the input voltage at any pin exceeds the power supplies (that is, less than GND or DR GND, or greater than VA, VP, VDor VDR),

the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can

safely exceed the power supplies with an input current of 25 mA to two.

(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by

TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula

PDMAX = (TJmax −TA) / θJA.

(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩresistor. Machine model is 220 pF discharged through ZERO

Ohms.

OPERATING RATINGS (1)(2)

Operating Temperature Range −40°C ≤TA≤+105°C

Supply Voltage (VA) +3.0V to +3.6V

Driver Supply Voltage (VDR) +2.7V to (VA+ 0.3V)

Maximum Supply Voltage VD, VPVA+ 0.3V

CLK Frequency PLL Bypassed 1 to 210 MHz

PLL used 15 to 105 MHz

RCLK Frequency (3) 2 - 210 MHz

RCLK Duty Cycle 35% to 65%

Ground Difference |GND - DR GND| 0V to 300 mV

Upper Reference Voltage (VRT) 0.5V to (VA−0.3V)

Lower Reference Voltage (VRB) 0V to (VRT −0.5V)

Reference Delta (VRT −VRB) 0.5V to 2.3V

VIN Voltage Range VRB to VRT

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For specifications and test conditions, see the Electrical

Characteristics. The specifications apply only for the test conditions listed. Some performance characteristics may degrade when the

device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.

(3) RCLK should be stopped with the buffer is not being read.

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PACKAGE THERMAL RESISTANCE

Package θJA

48-Lead TQFP 76 °C/W

CONVERTER ELECTRICAL CHARACTERISTICS

The following specifications apply for VA= VD= VP= VDR = +3.3VDC, VRT = +1.9V, VRB = 0.3V, CL= 10 pF, fCLK = 200 MHz at

50% duty cycle, OEDGE/TEN = 1, Buffer and PLL bypassed. Boldface limits apply for TJ= TMIN to TMAX: all other limits TJ=

25°C (1)(2)

Units

Parameter Test Conditions Typ(3) Limits (3) (Limits)

DC ACCURACY

INL Integral Non-Linearity ±0.55 ±1.3 LSB (max)

DNL Differential Non-Linearity ±0.40 ±0.9 LSB (max)

Missing Codes 0(max)

−80 mV (min)

FSE Full Scale Error −39 0mV (max)

VOFF Zero Scale Offset Error 55 70 mV (max)

ANALOG INPUT AND REFERENCE CHARACTERISTICS

VRB V (min)

VIN Input Voltage 1.6 VRT V (max)

(CLK LOW) 3 pF

CIN VIN Input Capacitance VIN = 0.75V +0.5 Vrms (CLK HIGH) 4 pF

RIN Analog Input Resistance >1 MΩ

FPBW Full Power Bandwidth 500 MHz

VAV (max)

VRT Top Reference Voltage 1.9 0.5 V (min)

VRT −0.5 V (max)

VRB Bottom Reference Voltage 0.3 0V (min)

0.5 V (min)

VRT -Reference Voltage Delta 1.6

VRB 2.3 V (max)

145 Ω(min)

RREF Reference Ladder Resistance VRT to VRB 160 200 Ω(max)

DIGITAL INPUT CHARACTERISTICS

OEDGE/TEN 2.2 2.7 V (min)

VIH Logic High Input Voltage Others 1.6 2.1 V (min)

OEDGE/TEN 0.9 0.5 V (max)

VIL Logic Low Input Voltage Others 1.3 0.7 V (max)

(1) The analog inputs are protected as shown below. Input voltage magnitudes up to VA+ 300 mV or to 300 mV below GND will not

damage this device. However, errors in the A/D conversion can occur if the input goes above VAor below GND by more than 100 mV.

For example, if VAis 3.3VDC the input voltage must be ≤3.4VDC to ensure accurate conversions.

(2) To ensure accuracy, it is required that VA, VD, VPand VDR be well bypassed. Each supply pin should be decoupled with separate

bypass capacitors.

(3) Typical figures are at TJ= 25°C, and represent most likely parametric norms. Test limits are specified to Texas Instrument's AOQL

(Average Outgoing Quality Level).

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CONVERTER ELECTRICAL CHARACTERISTICS (continued)

The following specifications apply for VA= VD= VP= VDR = +3.3VDC, VRT = +1.9V, VRB = 0.3V, CL= 10 pF, fCLK = 200 MHz at

50% duty cycle, OEDGE/TEN = 1, Buffer and PLL bypassed. Boldface limits apply for TJ= TMIN to TMAX: all other limits TJ=

25°C (1)(2)

Units

Parameter Test Conditions Typ(3) Limits (3) (Limits)

Operational 10 µA

OEDGE/TEN

IIH Logic High Input Current VIH = VDR = VA= 3.6V Test Mode 70 µA

Others 10 nA

Operational −10 µA

OEDGE/TEN

IIL Logic Low Input Current VIL = 0V, VDR = VA= 3.0V Test Mode −600 µA

Others −50 nA

CIN Logic Input Capacitance 3 pF

DIGITAL OUTPUT CHARACTERISTICS

VOH High Level Output Voltage VA= VDR = 3.0V, IOH =−5 mA 3.0 2.4 V (min)

VOL Low Level Output Voltage VA= VDR = 3.0V, IOL = 5 mA 0.25 0.5 V (max)

COUT Digital Output Capacitance 2 pF

DYNAMIC PERFORMANCE

fIN = 10 MHz, VIN = FS −0.25 dB 7.4 Bits

fIN = 49 MHz, VIN = FS −0.25 dB 7.2 6.8 Bits (min)

ENOB Effective Number of Bits fIN = 49 MHz, VIN = FS −0.25 dB, PLL x8 7.2 Bits

fIN = 100 MHz, VIN = FS −0.25 dB 7.0 Bits

fIN = 100 MHz, VIN = FS −0.25 dB, PLL x4 6.9 Bits

fIN = 10 MHz, VIN = FS −0.25 dB 46 dBc

fIN = 49 MHz, VIN = FS −0.25 dB 45 42.7 dBc (min)

SINAD Signal-to-Noise & Distortion fIN = 49 MHz, VIN = FS −0.25 dB, PLL x8 45 dBc

fIN = 100 MHz, VIN = FS −0.25 dB 44 dBc

fIN = 100 MHz, VIN = FS −0.25 dB, PLL x4 43.4 dBc

fIN = 10 MHz, VIN = FS −0.25 dB 47 dBc

fIN = 49 MHz, VIN = FS −0.25 dB 46.3 43.7 dBc (min)

SNR Signal-to-Noise Ratio fIN = 49 MHz, VIN = FS −0.25 dB, PLL x8 45.8 dBc

fIN = 100 MHz, VIN = FS −0.25 dB 45.6 dBc

fIN = 100 MHz, VIN = FS −0.25 dB, PLL x4 45.6 \dBc

fIN = 10 MHz, VIN = FS −0.25 dB 56 dBc

fIN = 49 MHz, VIN = FS −0.25 dB 56 dBc

SFDR Spurious Free Dynamic Range fIN = 49 MHz, VIN = FS −0.25 dB, PLL x8 56 dBc

fIN = 100 MHz, VIN = FS −0.25 dB 50 dBc

fIN = 100 MHz, VIN = FS −0.25 dB, PLL x4 49.7 dBc

fIN = 10 MHz, VIN = FS −0.25 dB −55 dBc

fIN = 49 MHz, VIN = FS −0.25 dB −53 dBc

THD Total Harmonic Distortion fIN = 49 MHz, VIN = FS −0.25 dB, PLL x8 −53 dBc

fIN = 100 MHz, VIN = FS −0.25 dB −49 dBc

fIN = 100 MHz, VIN = FS −0.25 dB, PLL x4 -47.5 dBc

fIN = 10 MHz, VIN = FS −0.25 dB −57 dBc

fIN = 49 MHz, VIN = FS −0.25 dB −55 dBc

HD2 2nd Harmonic Distortion fIN = 49 MHz, VIN = FS −0.25 dB, PLL x8 −55 dBc

fIN = 100 MHz, VIN = FS −0.25 dB −50 dBc

fIN = 100 MHz, VIN = FS −0.25 dB, PLL x4 −49.9 dBc

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CONVERTER ELECTRICAL CHARACTERISTICS (continued)

The following specifications apply for VA= VD= VP= VDR = +3.3VDC, VRT = +1.9V, VRB = 0.3V, CL= 10 pF, fCLK = 200 MHz at

50% duty cycle, OEDGE/TEN = 1, Buffer and PLL bypassed. Boldface limits apply for TJ= TMIN to TMAX: all other limits TJ=

25°C (1)(2)

Units

Parameter Test Conditions Typ(3) Limits (3) (Limits)

fIN = 10 MHz, VIN = FS −0.25 dB −62 dBc

fIN = 49 MHz, VIN = FS −0.25 dB −63 dBc

HD3 3rd Harmonic Distortion fIN = 49 MHz, VIN = FS −0.25 dB, PLL x8 −62 dBc

fIN = 100 MHz, VIN = FS −0.25 dB −56 dBc

fIN = 100 MHz, VIN = FS −0.25 dB, PLL x4 −54.6 dBc

f1= 11 MHz, VIN = FS −6.25 dB

IMD Intermodulation Distortion -50 dBc

f2= 12 MHz, VIN = FS −6.25 dB

POWER SUPPLY CHARACTERISTICS

DC Input 72.5 mA

IAAnalog Supply Current fIN = 50 MHz 76.8 88.3 mA (max)

PD High 0.3 mA

DC Input, Buffer bypassed 1.2 mA

fIN = 50 MHz, Buffer bypassed 1.6 2.1 mA (max)

IDDigital Core Supply Current fIN = 50 MHz, 1k writing to Buffer (4) 38 42.4 mA

PDADC High, reading Buffer (4) 1.1 mA

PD High 0.3 mA

PLL x2 8.8 10.1 mA (max)

IPPLL Supply Current PLL disabled 3.6 4.3 mA (max)

PD High 60 µA

DC Input 7 mA

IDR Output Driver Supply Current fIN = 50 MHz 41 57 mA (max)

PD High 25 µA

DC Input, Buffer bypassed, PLL x2 97.5 mA

(5)

50 MHz Input, writing to Buffer, PLL X2

IA+ ID164.6 198 mA (max)

(5)

+ IP+ Total Operating Current

IDR PDADC = Hi, reading Buffer, 20 mA

RCLK = 200 MHz, D.C. input

PD High 0.65 mA

DC Input, Buffer & PLL bypassed 306 mW

50 MHz Input, writing to Buffer, PLL X2 543 653 mW (max)

(5)

PC Power Consumption PDADC High, reading Buffer, PLL disabled (5) 66 mW

PD High 2.15 mW

D.C. Power Supply Rejection

PSRR1FSE change with 3.0V to 3.6V change in VA48 dB

Ratio

A.C. Power Supply Rejection

PSRR2SNR reduction with 200 mV at 10MHz on supply TBD dB

Ratio

(4) This current or power is used only during the short time that the buffer is being written to or read from, depending upon the specification.

(5) This current or power is used only during the short time that the buffer is being written to or read from, depending upon the specification.

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CONVERTER TIMING CHARACTERISTICS

The following specifications apply for VA= VDR = +3.3VDC, VRT = +1.9V, VRB = 0.3V, CL= 50 pF, fCLK = 200 MHz at 50% duty

cycle, OEDGE/TEN = 1, Buffer and PLL bypassed. Boldface limits apply for TJ= TMIN to TMAX: all other limits TJ= 25°C

(1)(2)

Units

Parameter Test Conditions Typ (3) Limits (3) (Limits)

PLL Disabled 210 200 MHz (min)

fC1 Maximum Input Clock Rate Using PLL 15 105 MHz (min)

PLL Disabled 1 MHz

fC2 Minimum Input Clock Rate Using PLL 15 MHz

tCL Minimum CLK Low Time (4) 1.7 ns (min)

tCH Minimum CLK High Time (4) 1.7 ns (min)

fRC1 Maximum RCLK Rate (5) 210 200 MHz (min)

fRC2 Minimum RCLK Rate (5) 2 MHz

tRCL Minimum RCLK Low Time (4) 2.0 ns (min)

tRCH Minimum RCLK High Time (4) 2.0 ns (min)

ΔDC DRDY to RCLK Duty Cycle Delta 0.3 ±3 %

−0.8 ns (min)

tSU REN to RCLK Set-Up Time −0.4 4.0 ns (max)

RCLK Rising Edge to DRDY Rising 2.4 ns (min)

tRR 3.8

Edge 5.9 ns (max)

RCLK Falling Edge to DRDY Falling

tRF 3.5 ns

Edge

tSKDR Skew of DRDY Rising Edge to DATA 160 ps

RCLK Falling Edge to First DATA 1.8 ns (min)

tSKR 2.3

Byte 7.4 ns (max)

Skew of DRDY Rising Edge to EF

tSKEF 36 ps

Rising Edge

tCFF CLK Rising Edge to FF Rising Edge 4.2 ns

FF Rising Edge to WENSYNC Falling

tFFW ASW pin high 4.2 ns

Edge

CLK Rising Edge to WENSYNC 2.4 ns (min)

tCW PLL Disabled 3.5

Rising Edge 5.5 ns (max)

Write Clock

tRST RESET Pulse Width (4) 4Cycles (min)

CL= 10 pF 0.9 ns

Output Data Rise Time

tr(0.4V to 2.5V) CL= 20 pF 2 ns

(1) The analog inputs are protected as shown below. Input voltage magnitudes up to VA+ 300 mV or to 300 mV below GND will not

damage this device. However, errors in the A/D conversion can occur if the input goes above VAor below GND by more than 100 mV.

For example, if VAis 3.3VDC the input voltage must be ≤3.4VDC to ensure accurate conversions.

(2) To ensure accuracy, it is required that VA, VD, VPand VDR be well bypassed. Each supply pin should be decoupled with separate

bypass capacitors.

(3) Typical figures are at TJ= 25°C, and represent most likely parametric norms. Test limits are specified to Texas Instrument's AOQL

(Average Outgoing Quality Level).

(4) This parameter is specified by design and/or characterization and is not production tested.

(5) RCLK should be stopped with the buffer is not being read.

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CONVERTER TIMING CHARACTERISTICS (continued)

The following specifications apply for VA= VDR = +3.3VDC, VRT = +1.9V, VRB = 0.3V, CL= 50 pF, fCLK = 200 MHz at 50% duty

cycle, OEDGE/TEN = 1, Buffer and PLL bypassed. Boldface limits apply for TJ= TMIN to TMAX: all other limits TJ= 25°C (1)(2)

Units

Parameter Test Conditions Typ (3) Limits (3) (Limits)

CL= 10 pF 1.4 ns

Output Data Fall Time

tf(2.4V to 0.4V) CL= 20 pF 3.2 ns

4.0 ns (min)

Reading Buffer 7.0

RCLK Rising Edge to Data Output 11.7 ns (max)

tODF Fall to 0.4V Buffer bypassed, PLL disabled 5.5 ns

2.3 ns (min)

Reading Buffer 6.5

RCLK Rising Edge to Data Output 13.1 ns (max)

tODR Rise to 2.5V Buffer bypassed, PLL disabled 5.5 ns

RCLK Rising Edge to Data Output 2.4 ns (min)

tOHF Reading Buffer 3.8

Fall to 2.5V 5.5 ns (max)

RCLK Rising Edge to Data Output 2.6 ns (min)

tOHR Reading Buffer 4.5

Rise to 0.4V 6.9 ns (max)

Output Falling (2.4V to 0.4V) 1.5 V / ns

tSLEW Output Slew Rate Output Rising (0.4V to 2.5V) 2.3 V / ns

PLL Enabled 20 µs

tDRDY1 PD Low to Device Active PLL Bypassed 2 µs

tDRDY2 PDADC Low to Device Active 2 µs

Pipeline Delay (Latency) 6 Clock Cycles

PLL on 3.4 ns

CLK Rise to

tAD Sampling (Aperture) Delay Acquisition of Data PLL off 3.9 ns

PLL Bypassed 2 ps rms

tAJ Aperture Jitter PLL Enabled in x8 mode (6) 7 ps rms

(6) Jitter with the PLL enabled is measured with 32k samples and the PLL in the x8 multiplication mode.

SPECIFICATION DEFINITIONS

APERTURE (SAMPLING) DELAY is that time delay after the rise of the sample clock until the input signal is

sampled within the ADC.

APERTURE JITTERis the variation in aperture delay from sample to sample. Aperture jitter shows up as input

noise.

CLOCK DUTY CYCLE is the ratio of the time that the clock waveform is at a logic high to the total time of one

clock period.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB. Measured at 200 MSPS with a ramp input.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion Ratio, or SINAD. ENOB is defined as (SINAD – 1.76) / 6.02 and says that the converter is

equivalent to a perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

FULL-SCALE ERROR is a measure of how far the last code transition is from the ideal 1½ LSB below VRT and

is defined as:

FSE = Vmax + 1.5 LSB – VRT

where

• Vmax is the voltage at which the transition to the maximum (full scale) code occurs (1)

INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

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THD = 20 x log + . . . + AAf22

f102

Af12

ADC08B200

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SNAS388F –MARCH 2007–REVISED APRIL 2013

zero scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code

transition). The deviation of any given code from this straight line is measured from the center of that code

value. The end point test method is used. Measured at 200 MSPS with a ramp input.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to the ADC input at the same time. it is defined as the ratio of the

power in the second and third order intermodulation products to the power in one of the original

frequencies. IMD is usually expressed in dBFS.

MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These

codes cannot be reached with any input value.

OFFSET ERRORis the error in the input voltage required to cause the first code transition. It is defined as the

difference between the voltage required to cause the first code transition and the ideal voltage (1/2 LSB)

to cause that transition.

VOFF = VZT −1/2 LSB = VZT - (VRT −VRB) / 512

where

• VZT is the first code transition input voltage (2)

OUTPUT DELAY is the time delay after the rising edge of the RCLK input before the data update is present at

the output pins.

OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of CLK or RCLK output.

PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that

data is presented to the output driver stage. New data is available at every clock cycle, but the data lags

the conversion by the Pipeline Delay plus the Output Delay.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power

supply voltage. For the ADC08B200, PSRR1 is the ratio of the change in Full-Scale Error that results from

a change in the DC power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c.

signal riding upon the power supply is rejected at the output.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output

to the rms value of the sum of all other spectral components below one-half the sampling frequency, not

including harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of

the input signal at the output to the rms value of all of the other spectral components below half the clock

frequency, including harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR)is the difference, expressed in dB, between the rms values of the

input signal at the output and the peak spurious signal, where a spurious signal is any signal present in

the output spectrum that is not present at the input.

TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic

levels at the output to the level of the fundamental at the output. THD is calculated as

where

• Af1 is the RMS power of the fundamental (output) frequency

• Af2 through Af10 are the RMS power of the first 9 harmonic frequencies in the output spectrum (3)

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4 Clock Rises

Input

CLK

WEN

WENSYNC

Vin

tAD

Actual Sample Point

tCW

tCFF

tFFW

Sampling

Clock

WEN

Buffer

Contents

RCLK

REN

FF asserted

FF cleared

EF cleared

EF asserted

Buffer Full

Buffer Empty

ADC08B200

SNAS388F –MARCH 2007–REVISED APRIL 2013

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TIMING DIAGRAMS (PLL BYPASSED)

Figure 2. ADC08B200 Data Capture and Read Operation

Figure 3. ADC08B200 Capture and Write Enable Timing

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