Short Form Dat a Sheet February 2013 MAX24605, MAX24610 5- or 10-Output Clock Multiplier / Jitter Attenuator ICs General Description Features The MA X24605 and MA X24610 are flexible, highperformance clock multiplier and jitter attenuator ICs that include a DPLL and t wo independent APLLs. When locked t o one of two input clock signals, the devic e performs any-to-any frequency conversion. From any input clock frequency 2k Hz to 750MHz the devic e can produce frequency-locked APLL output frequencies up to 750MHz and as many as 10 output clock signals that are integer divisors of the APLL frequencies. Input jitter can be attenuat ed by an internal low-bandwidth DP LL. The DPLL also provides glitchless switching between input clocks and numeric ally controlled oscillator capability. Input switching can be manual or automatic. Using only a low-c ost crystal or oscillator, the device can also serve as a frequency synthesizer IC. Output jitter is typically 0.18 to 0.3ps RMS for an APLL-only integer multiply and 0.25 to 0.4ps RMS for APLL-only fractional multiply or DPLL+APLL operation. Applications Jitter Attenuation, Frequency Conversion and Frequency Synthesis Applications in a Wide Variety of Equipment Types Ordering Information PART OUTPUTS TEMP RANGE PINPACKAGE MAX24605EXG+ 5 -40 to +85 81-CSBGA MAX24610EXG+ 10 -40 to +85 81-CSBGA +Denotes a lead(Pb)-free/RoHS-compliant package. Input Clocks One Crystal Input Two Differential or CMOS/TTL Inputs Differential to 750MHz, C MOS/TTL to 160MH z Continuous Input Clock Quality Monitoring Automatic or Manual Clock Selection Glitchless Reference Switching Low-Bandwidth DPLL Programmable Bandwidth, 4Hz to 400Hz Attenuates Input Jitter up to Several UI Manual Phase Adjustment Two APLLs Plus 5 or 10 Output Clocks APLLs Perform High Resolution Fractional-N Clock Multiplication An y Output Frequency from <1Hz to 750MH z Each Output Has an Independent Divider Output Jitter Typically 0.18 to 0.3ps RMS for APLL-Only Integer Multiply and 0.25 to 0.4ps RMS for Other Modes (12kHz to 20MH z) Outputs are CML or 2xCMOS, Can Interface to LVDS, L VPECL, HSTL, SSTL and HCSL CMOS Output Voltage from 1.5V to 3.3V General Features Automatic Self-Configuration at Power-Up from External EEPROM Memory Uses External Crystal, Oscillator or Clock Signal As Master Clock Internal Compensation for Local Oscillator Frequency Error SPI Processor Interface 1.8V + 3.3 V Operation (5V Tolerant) -40 to +85C Operating Temp. Range 10mm x 10mm CSBGA Package 1 MAX24605, MAX24610 1. Application Examples Figure 1-1. Frequency Multiplication and Fanout of Ethernet Clock s XIN OC1P/N OC2P/N OC3P/N OC4P/N OC5P/N OC6P/N OC7P/N OC8P/N OC9P/N OC10P/N 50MHz XOUT Any combination of 25MHz, 125MHz, 156.25MHz and related Ethernet frequencies Any combination of differential or 2x single-ended signal format 2. Block Diagram Figure 2-1. Block Diagram Input Block DPLL Scaler, Divider, Monitor Jitter Filtering, Holdover Figure 5-8 Figure 5-7 APLL2 3.7-4.2GHz, Sub-ps jitter, Fractional-N XO SPI Interface SDI SDO SCLK CS_N SS / GPIO4 GPIO2 AC / GPIO3 GPIO1 TEST INTREQ B C D DIV1 OC1POS/NEG DIV2 OC2POS/NEG DIV3 OC3POS/NEG DIV4 OC4POS/NEG DIV5 OC5POS/NEG DIV6 OC6POS/NEG DIV7 OC7POS/NEG DIV8 OC8POS/NEG DIV9 OC9POS/NEG DIV10 OC10POS/NEG MAX24610 onl y MAX24610 onl y JTAG and HW Control and Status Pins RST_N A JTRST_N JTMS JTCLK JTDI JTDO IC1POS/NEG IC2POS/NEG MCLKOSCP/N XIN XOUT APLL1 3.7-4.2GHz, Sub-ps jitter, Fractional-N Figure 5-10 3. Detailed Features 3.1 * * * * * * * Input Block Features Two input clocks, differential or CMOS/ TTL signal format Input clocks can be any frequency from 1Hz up to 750MHz Per-input fractional scaling (i.e. multiplying by N/D where N is a 16-bit integer and D is a 32-bit integer and N<D) to undo 64B/66B and FEC scaling (e.g. 64/66, 238/255, 237/255, 236/255) All inputs constantly monitored by programmable activity monitors and frequency monitors Fast activity monitor can disqualify the selected reference after a few missing clock cycles Frequency measurement with 1.25ppm resolution Frequency monitor thresholds with 1.25ppm or 5ppb resolution 2 MAX24605, MAX24610 3.2 * * * * * * * * * * * * 3.3 * * * * 3.4 * * * * * * * * 3.5 * * * * * * * DPLL Features Very high-resolution DPLL architecture Sophisticated state machine aut omatically transitions bet ween free-run, locked, and digital hold states Revertive or nonrevertive reference selection algorithm Programmable bandwidth from 4Hz to 400Hz Separately configurable acquisition bandwidth and locked bandwidth Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10 or 20 Multiple phase detectors: phase/ frequency and multicycle Phase/frequency locking (360 capture) or nearest-edge phase locking (180 capture) Multicycle phase detection and locking (up to 8191UI) improves jitter tolerance and lock time Output phase adjustment up to 200ns in 6ps steps with respect to selected input referenc e High-resolution frequency and phase measurement Numerically controlled oscillator (NCO) mode allows system software to steer DP LL frequency APLL Features Two independent APLLs simultaneously product two frequency families from the same reference clock or different reference clocks Very high-resolution fractional scaling (i.e. non-int eger multiplication) Output jitter is typically 0.18 to 0.3ps RMS for APLL-only integer multiply and 0.25 to 0.4ps RMS for APLL-only fractional multiply or DPLL+APLL operation (12kHz to 20MH z integration band, for output frequencies >100MHz) Bypass mode for each APLL supports system testing and allows device to be used in fanout applications Output Clock Features Ten low-jitter output clocks Each output can be one differential output or two CMOS/ TTL outputs Outputs easily interface with CML, LVDS, LVPECL, HS TL, SSTL, HCSL components Each output can be any integer divisor of either APLL output clock Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN Can also produc e clock frequencies for microprocessors, ASICs, FPGAs and other components Per-output delay adjustment Per-output enable/disable General Features SPI serial microprocessor interface Optional automatic self-configuration at power-up from external EEPROM memory Four general-purpose I/O pins Register set can be write-protected Can operate as DPLL+APLL for jitter filtering or as APLL only Local oscillator can be nearly any frequency from 10MHz to 210MHz Internal compensation for local oscillator frequency error 3 Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com . Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (949) 380-610 0 Sales: +1 (949) 380-613 6 Fax: +1 (949) 215-4996 (c) 2013 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.