2008-2011 Microchip Technology Inc. DS22126E-page 1
23A640/23K640
Device Selection Table
Features:
• Max. Clock 20 MHz
• Low-Power CMOS Technology:
- Read Current: 3 mA at 1 MHz
- Standby Current: 4 A Max. at +85°C
• 8192 x 8-bit Organization
• 32-Byte Page
•HOLD
pin
• Flexible Operating modes:
- Byte read and write
- Page mode (32 Byte Page)
- Sequential mode
• Sequential Read/Write
• High Reliability
• Temperature Ranges Supported:
• Pb-Free and RoHS Compliant, Halogen Free
Pin Function Table
Description:
The Microchip Technology Inc. 23X640 are 64 Kbit
Serial SRAM devices. The memory is accessed via a
simple Serial Peripheral Interface (SPI) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a Chip
Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused,
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
The 23X640 is available in standard packages
including 8-lead PDIP and SOIC, and advanced
packaging including 8-lead TSSOP.
Package Types (not to scale)
Part Number VCC Range Page Size Temp. Ranges Packages
23K640 2.7-3.6V 32 Byte I, E P, SN, ST
23A640 1.5-1.95V 32 Byte I P, SN, ST
- Industrial (I):
- Automotive (E):
-40C
-40C
to
to
+85C
+125C
Name Function
CS Chip Select Input
SO Serial Data Output
VSS Ground
SI Serial Data Input
SCK Serial Clock Input
HOLD Hold Input
VCC Supply Voltage
CS
SO
NC
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
PDIP/SOIC/TSSOP
(P, SN, ST)
64K SPI Bus Low-Power Serial SRAM
23A640/23K640
DS22126E-page 2 2008-2011 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................4.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +0.3V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias...............................................................................................................-40°C to 125°C
ESD protection on all pins...........................................................................................................................................2kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C
Automotive (E): T
A = -40°C to +125°C
Param.
No. Sym. Characteristic Min. Typ(1) Max. Units Test Conditions
D001 VCC Supply voltage 1.5 — 1.95 V 23A640 (I-Temp)
D001 VCC Supply voltage 2.7 — 3.6 V 23K640 (I, E-Temp)
D002 VIH High-level input
voltage
.7 VCC —VCC +0.3 V
D003 VIL Low-level input
voltage
-0.3 —
0.2xV
CC
0.15xV
CC
V
V 23K640 (E-Temp)
D004 VOL Low-level output
voltage
——0.2VIOL = 1 mA
D005 VOH High-level output
voltage
VCC -0.5 — — V IOH = -400 A
D006 ILI Input leakage
current
——±0.5ACS = VCC, VIN = VSS OR VCC
D007 ILO Output leakage
current
——±0.5ACS = VCC, VOUT = VSS OR VCC
D008 ICC Read
Operating current
—
—
—
—
—
—
3
6
10
mA
mA
mA
FCLK = 1 MHz; SO = O
FCLK = 10 MHz; SO = O
FCLK = 20 MHz; SO = O
D009 ICCS
Standby current
—
—
—
0.2
1
5
1
4
10
A
A
A
CS = VCC = 1.8V, Inputs tied to
VCC or VSS
CS = VCC = 3.6V, Inputs tied to
VCC or VSS
CS = VCC = 3.6V, Inputs tied to
VCC or VSS @ 125°C
D010 CINT Input capacitance 7 pF VCC = 0V, f = 1 MHz, Ta = 25°C
(Note 1)
D011 VDR RAM data retention
voltage (2)
—1.2— V
Note 1: This parameter is periodically sampled and not 100% tested. Typical measurements taken at room
temperature (25°C).
2: This is the limit to which VDD can be lowered without losing RAM data. This parameter is periodically
sampled and not 100% tested.
2008-2011 Microchip Technology Inc. DS22126E-page 3
23A640/23K640
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C
Automotive (E): TA = -40°C to +125°C
Param.
No. Sym. Characteristic Min. Max. Units Test Conditions
1FCLK Clock frequency —
—
—
—
10
16
16
20
MHz
MHz
MHz
MHz
VCC 1.5V (I-Temp)
VCC 1.8V (I-Temp)
VCC 3V (E-Temp)
VCC 3.0V (I-Temp)
2T
CSS CS setup time 50
32
32
25
—
—
—
—
ns
ns
ns
ns
VCC 1.5V (I-Temp)
VCC 1.8V (I-Temp)
VCC 3.0V (E-Temp)
VCC 3.0V (I-Temp)
3T
CSH CS hold time 50
50
50
50
—
—
—
—
ns
ns
ns
ns
VCC 1.5V (I-Temp)
VCC 1.8V (I-Temp)
VCC 3.0V (E-Temp)
VCC 3.0V (I-Temp)
4T
CSD CS disable time 50
32
32
25
—
—
—
—
ns
ns
ns
ns
VCC 1.5V (I-Temp)
VCC 1.8V (I-Temp)
VCC 3.0V (E-Temp)
VCC 3.0V (I-Temp)
5 Tsu Data setup time 10
10
10
10
—
—
—
—
ns
ns
ns
ns
VCC 1.5V (I-Temp)
VCC 1.8V (I-Temp)
VCC 3.0V (E-Temp)
VCC 3.0V (I-Temp)
6THD Data hold time 10
10
10
10
—
—
—
—
ns
ns
ns
ns
VCC 1.5V (I-Temp)
VCC 1.8V (I-Temp)
VCC 3.0V (E-Temp)
VCC 3.0V (I-Temp)
7TRCLK rise time — 2 us Note 1
8T
FCLK fall time — 2 us Note 1
9THI Clock high time 50
32
32
25
—
—
—
—
ns
ns
ns
ns
VCC 1.5V (I-Temp)
VCC 1.8V (I-Temp)
VCC 3.0V (E-Temp)
VCC 3.0V (I-Temp)
10 TLO Clock low time 50
32
32
25
—
—
—
—
ns
ns
ns
ns
VCC 1.5V (I-Temp)
VCC 1.8V (I-Temp)
VCC 3.0V (E-Temp)
VCC 3.0V (I-Temp)
11 TCLD Clock delay time 50
32
32
25
—
—
—
—
ns
ns
ns
ns
VCC 1.5V (I-Temp)
VCC 1.8V (I-Temp)
VCC 3.0V (E-Temp)
VCC 3.0V (I-Temp)
12 TVOutput valid from clock low —
—
—
—
50
32
32
25
ns
ns
ns
ns
VCC 1.5V (I-Temp)
VCC 1.8V (I-Temp)
VCC 3.0V (E-Temp)
VCC 3.0V (I-Temp)
13 THO Output hold time 0 — ns Note 1
Note 1: This parameter is periodically sampled and not 100% tested.
23A640/23K640
DS22126E-page 4 2008-2011 Microchip Technology Inc.
TABLE 1-3: AC TEST CONDITIONS
14 TDIS Output disable time —
—
—
—
20
20
20
20
ns
ns
ns
ns
VCC 1.5V (I-Temp)
VCC 1.8V (I-Temp)
VCC 3.0V (E-Temp)
VCC 3.0V (I-Temp)
15 THS HOLD setup time 10 — ns —
16 THH HOLD hold time 10 — ns —
17 THZ HOLD low to output High-Z 10 — ns —
18 THV HOLD high to output valid — 50 ns —
TABLE 1-2: AC CHARACTERISTICS (CONTINUED)
AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C
Automotive (E): TA = -40°C to +125°C
Param.
No. Sym. Characteristic Min. Max. Units Test Conditions
Note 1: This parameter is periodically sampled and not 100% tested.
AC Waveform:
Input pulse level 0.1 VCC to 0.9 VCC
Input rise/fall time 5 ns
Operating temperature -40°C to +125°C
CL = 100 pF —
Timing Measurement Reference Level:
Input 0.5 VCC
Output 0.5 VCC
2008-2011 Microchip Technology Inc. DS22126E-page 5
23A640/23K640
FIGURE 1-1: HOLD TIMING
FIGURE 1-2: SERIAL INPUT TIMING
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
SCK
SO
SI
HOLD
16
15 15 16
18
17
Don’t Care 5
High-Impedance
n + 2 n + 1 n n - 1
n
n + 2 n + 1 n nn - 1
CS
SCK
SI
SO
65
8
711
3
LSB in
MSB in
High-Impedance
2
4
CS
SCK
SO
10
9
12
MSB out LSB out
3
14
Don’t Care
SI
13
23A640/23K640
DS22126E-page 6 2008-2011 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
2.1 Principles of Operation
The 23X640 is a 8192-byte Serial SRAM designed to
interface directly with the Serial Peripheral Interface
(SPI) port of many of today’s popular microcontroller
families, including Microchip’s PIC® microcontrollers. It
may also interface with microcontrollers that do not
have a built-in SPI port by using discrete I/O lines
programmed properly in firmware to match the SPI
protocol.
The 23X640 contains an 8-bit instruction register. The
device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 23X640 in ‘HOLD’ mode.
After releasing the HOLD pin, operation will resume
from the point when the HOLD was asserted.
2.2 Modes of Operation
The 23A256/23K256 has three modes of operation that
are selected by setting bits 7 and 6 in the STATUS
register. The modes of operation are Byte, Page and
Burst.
Byte Operation
– is selected when bits 7 and 6 in the
STATUS register are set to
00
. In this mode, the read/
write operations are limited to only one byte. The
Command followed by the 16-bit address is clocked into
the device and the data to/from the device is transferred
on the next 8 clocks (Figure 2-1, Figure 2-2).
Page Operation
– is selected when bits 7 and 6 in the
STATUS register are set to
10
. The 23A640/23K640 has
1024 pages of 32 Bytes. In this mode, the read and write
operations are limited to within the addressed page (the
address is automatically incremented internally). If the
data being read or written reaches the page boundary,
then the internal address counter will increment to the
start of the page (Figure 2-3, Figure 2-4).
Sequential Operation
– is selected when bits 7 and 6
in the STATUS register are set to
01
. Sequential opera-
tion allows the entire array to be written to and read
from. The internal address counter is automatically
incremented and page boundaries are ignored. When
the internal address counter reaches the end of the
array, the address counter will roll over to 0x0000
(Figure 2-5, Figure 2-6).
2.3 Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 23X640 followed
by the 16-bit address, with the first MSB of the address
being a “don’t care” bit. After the correct READ
instruction and address are sent, the data stored in the
memory at the selected address is shifted out on the
SO pin.
If operating in Page mode, after the first byte of data is
shifted out, the next memory location on the page can
be read out by continuing to provide clock pulses. This
allows for 32 consecutive address reads. After the
32nd address read the internal address counter wraps
back to the byte 0 address in that page.
If operating in Sequential mode, the data stored in the
memory at the next address can be read sequentially
by continuing to provide clock pulses. The internal
Address Pointer is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached (1FFFh),
the address counter rolls over to address 0000h,
allowing the read cycle to be continued indefinitely.
The read operation is terminated by raising the CS pin
(Figure 2-1).
2.4 Write Sequence
Prior to any attempt to write data to the 23X640, the
device must be selected by bringing CS low.
Once the device is selected, the Write command can
be started by issuing a WRITE instruction, followed by
the 16-bit address, with the first three MSBs of the
address being a “don’t care” bit, and then the data to be
written. A write is terminated by the CS being brought
high.
If operating in Page mode, after the initial data byte is
shifted in, additional bytes can be shifted into the
device. The Address Pointer is automatically
incremented. This operation can continue for the entire
page (32 Bytes) before data will start to be overwritten.
If operating in Sequential mode, after the initial data
byte is shifted in, additional bytes can be clocked into
the device. The internal Address Pointer is automati-
cally incremented. When the Address Pointer reaches
the highest address (1FFFh), the address counter rolls
over to (0000h). This allows the operation to continue
indefinitely, however, previous data will be overwritten.
2008-2011 Microchip Technology Inc. DS22126E-page 7
23A640/23K640
FIGURE 2-1: BYTE READ SEQUENCE
FIGURE 2-2: BYTE WRITE SEQUENCE
TABLE 2-1: INSTRUCTION SET
Instruction Name Instruction Format Description
READ 0000 0011 Read data from memory array beginning at selected address
WRITE 0000 0010 Write data to memory array beginning at selected address
RDSR 0000 0101 Read STATUS register
WRSR 0000 0001 Write STATUS register
SO
SI
SCK
CS
0 234567891011 21222324252627282930311
0100000115 14 13 12 210
76543210
Instruction 16-bit Address
Data Out
High-Impedance
SO
SI
CS
9 1011 2122232425262728293031
0000000115 14 13 12 21076543210
Instruction 16-bit Address Data Byte
High-Impedance
SCK
0 23456718
23A640/23K640
DS22126E-page 8 2008-2011 Microchip Technology Inc.
FIGURE 2-3: PAGE READ SEQUENCE
FIGURE 2-4: PAGE WRITE SEQUENCE
76543210
Page X, Word Y
SI
CS
9 1011 2122232425262728293031
15 14 13 12 210
16-bit Address
SCK
0 23456718
SO
CS
76543210
Page X, Word 0
SCK
32 34 35 36 37 38 3933
76543210
Page X, Word 31
76543210
Page X, Word Y+1
Page X, Word Y
SO
High Impedance
SI
01000001
Instruction
SI
CS
9 1011 2122232425262728293031
15 14 13 12 21076543210
16-bit Address
SCK
0 23456718
CS
SI 76543210
Page X, Word 0
76543210
Page X, Word 31
76543210
Page X, Word Y+1
Page X, Word Y
Page X, Word Y
SCK
32 34 35 36 37 38 3933
00000001
Instruction
2008-2011 Microchip Technology Inc. DS22126E-page 9
23A640/23K640
FIGURE 2-5: SEQUENTIAL READ SEQUENCE
SI
CS
9 1011 2122232425262728293031
15 14 13 12 210
76543210
Instruction 16-bit Address
Page X, Word Y
SCK
0 23456718
SO
CS
76543210
Page X+1, Word 1
SCK
76543210
Page X+1, Word 0
76543210
Page X, Word 31
SO
CS
76543210
Page X+n, Word 31
SCK
76543210
Page X+n, Word 1
76543210
Page X+1, Word 31
SO
SI
SI
01000001
23A640/23K640
DS22126E-page 10 2008-2011 Microchip Technology Inc.
FIGURE 2-6: SEQUENTIAL WRITE SEQUENCE
SI
CS
9 1011 2122232425262728293031
0000000115 14 13 12 21076543210
Instruction 16-bit Address Data Byte 1
SCK
0 23456718
SI
CS
41 42 43 46 47
76543210
Data Byte n
SCK
32 34 35 36 37 38 3933 40
76543210
Data Byte 3
76543210
Data Byte 2
44 45
2008-2011 Microchip Technology Inc. DS22126E-page 11
23A640/23K640
2.5 Read Status Register Instruction
(RDSR)
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time. The STATUS register is
formatted as follows:
TABLE 2-2: STATUS REGISTER
The mode bits indicate the operating mode of the
SRAM. The possible modes of operation are:
0 0 = Byte mode (default operation)
1 0 = Page mode
0 1 = Sequential mode
1 1 = Reserved
Write and read commands are shown in Figure 2-7 and
Figure 2-8.
The HOLD bit enables the Hold pin functionality. It must
be set to a ‘0’ before HOLD pin is brought low for HOLD
function to work properly. Setting HOLD to ‘1’ disables
feature.
Bits 2 through 5 are reserved and should always be set
to ‘0’. Bit 1 will read back as ‘1’ but should always be
written as ‘0’.
See Figure 2-7 for the RDSR timing sequence.
FIGURE 2-7: READ STATUS REGISTER TIMING SEQUENCE (RDSR)
76543210
W/R W/R – – – – – W/R
MODE MODE 00001HOLD
W/R = writable/readable.
SO
SI
CS
91011 12131415
11000000
7654 2 10
Instruction
Data from STATUS Register
High-Impedance
SCK
0 23456718
3
23A640/23K640
DS22126E-page 12 2008-2011 Microchip Technology Inc.
2.6 Write Status Register Instruction
(WRSR)
The Write Status Register instruction (WRSR) allows the
user to write to the bits in the STATUS register as
shown in Table 2- 2. This allows for setting of the Device
operating mode. Several of the bits in the STATUS
register must be cleared to ‘0’. See Figure 2-8 for the
WRSR timing sequence.
FIGURE 2-8: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
2.7 Power-On State
The 23X640 powers on in the following state:
• The device is in low-power Standby mode
(CS =1)
• A high-to-low-level transition on CS is required to
enter active state
SO
SI
CS
91011 12131415
01000000
7654 210
Instruction Data to STATUS Register
High-Impedance
SCK
0 23456718
3
2008-2011 Microchip Technology Inc. DS22126E-page 13
23A640/23K640
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3 - 1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
When the device is deselected, SO goes to the high-
impedance state, allowing multiple parts to share the
same SPI bus. After power-up, a low level on CS is
required, prior to any sequence being initiated.
3.2 Serial Output (SO)
The SO pin is used to transfer data out of the 23X640.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
3.3 Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
3.4 Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 23X640. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
3.5 Hold (HOLD)
The HOLD pin is used to suspend transmission to the
23X640 while in the middle of a serial sequence without
having to retransmit the entire sequence again. It must
be held high any time this function is not being used.
Once the device is selected and a serial sequence is
underway, the HOLD pin may be pulled low to pause
further serial communication without resetting the
serial sequence. The HOLD pin must be brought low
while SCK is low, otherwise the HOLD function will not
be invoked until the next SCK high-to-low transition.
The 23X640 must remain selected during this
sequence. The SI, SCK and SO pins are in a high-
impedance state during the time the device is paused
and transitions on these pins will be ignored. To resume
serial communication, HOLD must be brought high
while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
Hold functionality is disabled by the STATUS register
bit.
Name PDIP/SOIC
TSSOP Function
CS 1 Chip Select Input
SO 2 Serial Data Output
VSS 4Ground
SI 5 Serial Data Input
SCK 6 Serial Clock Input
HOLD 7 Hold Input
VCC 8 Supply Voltage
23A640/23K640
DS22126E-page 14 2008-2011 Microchip Technology Inc.
4.0 PACKAGING INFORMATION
4.1 Package Marking Information
T/XXXNNN
XXXXXXXX
YYWW
8-Lead PDIP
8-Lead SOIC (3.90 mm)
XXXXYYWW
XXXXXXXT
NNN
I/P 1L7
23K640
0528
Example:
Example:
SN 0528
23K640I
1L7
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3
e
3
e
8-Lead TSSOP Example:
XXXX
TYWW
NNN
K640
I837
1L7
2008-2011 Microchip Technology Inc. DS22126E-page 15
23A640/23K640
N
E1
NOTE 1
D
123
A
A1
A2
L
b1
b
e
E
eB
c
23A640/23K640
DS22126E-page 16 2008-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2011 Microchip Technology Inc. DS22126E-page 17
23A640/23K640
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
23A640/23K640
DS22126E-page 18 2008-2011 Microchip Technology Inc.
! ""#$%& !'
2008-2011 Microchip Technology Inc. DS22126E-page 19
23A640/23K640
() )"* ! (+%+( !
D
N
E
E1
NOTE 1
12
b
e
c
A
A1
A2
L1 L
φ
23A640/23K640
DS22126E-page 20 2008-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2011 Microchip Technology Inc. DS22126E-page 21
23A640/23K640
APPENDIX A: REVISION HISTORY
Revision A (12/2008)
Original Release.
Revision B (01/2009)
Revised Section 2.5: Added a paragraph.
Revision C (04/2009)
Removed Preliminary status; Revised Standby
Current; Revised Table 1-1, Param. No. D009; Revised
TSSOP Package marking information; Revised
Product ID.
Revision D (08/2010)
Revised Table 1-1, Param. No. D009; Revised
Package Drawings.
Revision E (10/2010)
Revised Parameter D003 in Table 1-1: DC Character-
istics.
23A640/23K640
DS22126E-page 22 2008-2011 Microchip Technology Inc.
NOTES:
2008-2011 Microchip Technology Inc. DS22126E-page 23
23A640/23K640
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representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
23A640/23K640
DS22126E-page 24 2008-2011 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO: Technical Publications Manager
RE: Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS22126E23A640/23K640
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2008-2011 Microchip Technology Inc. DS22126E-page 25
23A640/23K640
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTape & Reel
Device
Device: 23A640 =
23K640 =
64 Kbit, 1.8V, SPI Serial SRAM
64 Kbit, 3.6V, SPI Serial SRAM
Tape & Reel: Blank =
T=
Standard packaging (tube)
Tape & Reel
Temperature
Range:
I=
E=
-40C to+85C
-40°C to +125°C
Package: P=
SN =
ST =
Plastic PDIP (300 mil body), 8-lead
Plastic SOIC (3.90 mm body), 8-lead
TSSOP, 8-lead
Examples:
a) 23K640-I/ST = 64 Kbit, 3.6V Serial SRAM,
Industrial temp., TSSOP package
b) 23A640T-I/SN = 64 Kbit, 1.8V Serial SRAM,
Industrial temp., Tape & Reel, SOIC package
c) 23K640-E/ST = 64 Kbit, 3.6V Serial SRAM,
Automotive temp., TSSOP package
–
X
Temp Range
23A640/23K640
DS22126E-page 26 2008-2011 Microchip Technology Inc.
NOTES:
2008-2011 Microchip Technology Inc. DS22126E-page 27
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-674-7
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS22126E-page 28 2008-2011 Microchip Technology Inc.
AMERICAS
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Worldwide Sales and Service
08/02/11
