3.3 V Slew Rate Limited, Half- and
Full-Duplex, RS-485/RS-422 Transceivers
Data Sheet ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005-2011 Analog Devices, Inc. All rights reserved.
FEATURES
Operate with 3.3 V supply
Interoperable with 5 V logic
EIA RS-422 and RS-485 compliant over full
common-mode range
Data rate options
ADM3483/ADM3488: 250 kbps
ADM3485/ADM3490/ADM3491: 10 Mbps
Half- and full-duplex options
Reduced slew rates for low EMI (ADM3483 and ADM3488)
2 nA supply current in shutdown mode
(ADM3483/ADM3485/ADM3491)
Up to 32 transceivers on the bus
−7 V to +12 V bus common-mode range
Specified over the –40°C to +85°C temperature range
8 ns skew (ADM3485/ADM3490/ADM3491)
8-lead SOIC and 14-lead SOIC (ADM3491 only) packages
APPLICATIONS
Low power RS-485/RS-422 applications
Telecom
Industrial process control
HVAC
GENERAL DESCRIPTION
The ADM3483/ADM3485/ADM3488/ADM3490/ADM3491 are
low power, differential line transceivers designed to operate using a
single 3.3 V power supply. Low power consumption, coupled with a
shutdown mode, makes the ADM3483/ADM3485/ADM3488/
ADM3490/ADM3491 ideal for power-sensitive applications.
The ADM3488/ADM3490/ADM3491 feature full-duplex com-
munication, while the ADM3483/ADM3485 are designed for
half-duplex communication.
FUNCTIONAL BLOCK DIAGRAMS
R
D
RO
V
CC
RE
DI
DE
ADM3483/
ADM3485
A
GND
B
05524-027
Figure 1.
R
D
RO
DI
ADM3488/
ADM3490
A
B
Z
Y
05524-026
V
CC
GND
Figure 2.
R
D
RO
RE
DI
DE
ADM3491
A
B
Z
Y
05524-025
Figure 3.
The ADM3483/ADM3488 feature slew rate limited drivers that
minimize EMI and reduce reflections caused by improperly ter-
minated cables, allowing error-free data transmission at data rates
up to 250 kbps.
The ADM3485/ADM3490/ADM3491 transmit at up to 10 Mbps.
The receiver input impedance is 12 kΩ, allowing up to 32 trans-
ceivers to be connected on the bus. A thermal shutdown circuit
prevents excessive power dissipation caused by bus contention or
by output shorting. If a significant temperature increase is detected
in the internal driver circuitry during fault conditions, then the
thermal shutdown circuit forces the driver output into a high
impedance state. If the inputs are unconnected (floating), the
receiver contains a fail-safe feature that results in a logic high
output state. The parts are fully specified over the commercial
and industrial temperature ranges. The ADM3483/ADM3485/
ADM3488/ADM3490 are available in 8-lead SOIC_N; the
ADM3491 is available in a 14-lead SOIC_N.
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491 Data Sheet
Rev. E | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 4
Timing Specifications—ADM3485/ADM3490/ADM3491.... 5
Timing Specifications—ADM3483/ADM3488........................ 5
Timing Specifications—
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491...... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Test Circuits..................................................................................... 11
Switching Characteristics .............................................................. 13
Circuit Description......................................................................... 14
Devices with Receiver/Driver Enables
(ADM3483/ADM3485/ADM3491)......................................... 14
Devices Without Receiver/Driver Enables—
ADM3488/ADM3490................................................................ 14
Reduced EMI and Reflections (ADM3483/ADM3488) ....... 14
Low Power Shutdown Mode
(ADM3483/ADM3485/ADM3491)......................................... 14
Driver Output Protection.......................................................... 14
Propagation Delay...................................................................... 14
Typical Applications................................................................... 14
Line Length vs. Data Rate ......................................................... 15
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 18
REVISION HISTORY
11/11—Rev. D to Rev. E
Changes to Digital I/O Voltage (DE, RE, DI) Parameter,
Table 6 ................................................................................................ 7
Moved Typical Performance Characteristics Section.................. 9
Moved Test Circuits Section.......................................................... 11
Moved Switching Characteristics Section ................................... 13
Changes to Note 1, Table 8............................................................ 14
Changes to Outline Dimensions................................................... 17
12/10—Rev. C to Rev. D
Changes to Figure 33...................................................................... 15
8/10—Rev. B to Rev. C
Changes to Table 2, Driver Input Logic......................................... 4
10/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Added ADM3491 ...............................................................Universal
Changes to Specifications Section...................................................4
Changes to Typical Applications Section .................................... 14
7/06—Rev. 0 to Rev. A
Changes to Applications ...................................................................1
Changes to General Description .....................................................1
Changes to Figure 19...................................................................... 10
Changes to Typical Applications Section .................................... 13
Changes to Figure 31 and Figure 32............................................. 14
Updated Outline Dimensions....................................................... 15
10/05—Revision 0: Initial Version
Data Sheet ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
Rev. E | Page 3 of 20
Table 1. ADM34xx Part Comparison
Part No.
Guaranteed
Data Rate (Mbps)
Supply
Voltage (V)
Half-/Full-
Duplex
Slew Rate
Limited
Driver/Receiver
Enable
Shutdown
Current (nA)
Pin
Count
ADM3483 0.25 3.0 to 3.6 Half Yes Yes 2 8
ADM3485 10 3.0 to 3.6 Half No Yes 2 8
ADM3488 0.25 3.0 to 3.6 Full Yes No N/A 8
ADM3490 10 3.0 to 3.6 Full No No N/A 8
ADM3491 10 3.0 to 3.6 Full No Yes 2 14
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491 Data Sheet
Rev. E | Page 4 of 20
SPECIFICATIONS
VCC = 3.3 V ± 0.3 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Output Voltage (VOD) 2.0 V RL = 100 Ω (RS-422), VCC = 3.3 V ± 5% (see Figure 17)
1.5 V RL = 54 Ω (RS-485) (see Figure 17)
1.5 V RL = 60 Ω (RS-485), VCC = 3.3 V (see Figure 18)
∆ |VOD| for Complementary Output States1 0.2 V RL = 54 Ω or 100 Ω (see Figure 17)
Common-Mode Output Voltage (VOC) 3 V RL = 54 Ω or 100 Ω (see Figure 17)
∆ |VOC| for Common-Mode Output Voltage1 0.2 V RL = 54 Ω or 100 Ω (see Figure 17)
DRIVER INPUT LOGIC
CMOS Input Logic Threshold Low (VIL) 0.8 V
DE, DI, RE
CMOS Input Logic Threshold High (VIH) 2.0 V
DE, DI, RE
CMOS Logic Input Current (IIN1) ±2 µA
DE, DI, RE
1.0 mA VIN = 12 V, DE = 0 V, VCC = 0 V or 3.6 V Input Current—A, B (IIN2)
−0.8 mA VIN = −7 V, DE = 0 V, VCC = 0 V or 3.6 V
0.1 µA
VIN = 12 V, DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V,
ADM3491 only
Output Leakage—Y, Z (IO)
−0.1 µA
VIN = −7 V, DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V,
ADM3491 only
0.01 µA
VIN = 12 V, DE = 0 V, RE = VCC, VCC = 0 V or 3.6 V,
ADM3491 only
Output Leakage (Y, Z) in Shutdown Mode (IO)
−0.01 µA
VIN = −7 V, DE = 0 V, RE = VCC, VCC = 0 V or 3.6 V,
ADM3491 only
RECEIVER
Differential Input Threshold Voltage (VTH) −0.2 +0.2 V −7 V < VCM < +12 V
Input Hysteresis (∆ VTH) 50 mV VCM = 0 V
CMOS Output Voltage High (VOH) VCC – 0.4 V IOUT = −1.5 mA, VID = 200 mV (see Figure 19)
CMOS Output Voltage Low (VOL) 0.4 V IOUT = 2.5 mA, VID = 200 mV (see Figure 19)
Three-State Output Leakage Current (IOZR) ±1 µA VCC = 3.6 V, 0 V ≤ VOUT ≤ VCC
Input Resistance (RIN) 12 kΩ −7 V < VCM < +12 V
POWER SUPPLY CURRENT
1.1 2.2 mA
DE = VCC, RE = 0 V or VCC, no load, DI = 0 V or VCC
Supply Current (ICC)
0.95 1.9 mA
DE = 0 V, RE = 0 V, no load, DI = 0 V or VCC
Supply Current in Shutdown Mode (ISHDN) 0.002 1 µA
DE = 0 V, RE = VCC, DI = VCC or 0 V
−250 mA VOUT = −7 V Driver Short-Circuit Output Current (IOSD)
250 mA VOUT = 12 V
Receiver Short-Circuit Output Current (IOSR) ±8 ±60 mA 0 V < VRO < VCC
1∆VOD and ∆VOC are the changes in VOD and VOC, respectively, when DI input changes state.
Data Sheet ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
Rev. E | Page 5 of 20
TIMING SPECIFICATIONS—ADM3485/ADM3490/ADM3491
VCC = 3.3 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Output Delay (tDD) 1 22 35 ns
RL = 60 Ω (see Figure 20 and Figure 26)
Differential Output Transition Time (tTD) 3 8 25 ns
RL = 60 Ω (see Figure 20 and Figure 26)
Propagation Delay, Low-to-High Level (tPLH) 7 22 35 ns
RL = 27 Ω (see Figure 21 and Figure 27)
Propagation Delay, High-to-Low Level (tPHL) 7 22 35 ns
RL = 27 Ω (see Figure 21 and Figure 27)
|tPLH – tPHL| Propagation Delay Skew1 (tPDS) 8 ns
RL = 27 Ω (see Figure 21 and Figure 27)
DRIVER OUTPUT ENABLE/DISABLE TIMES (ADM3485/
ADM3491 ONLY)
Output Enable Time to Low Level (tPZL) 45 90 ns
RL = 110 Ω (see Figure 23 and Figure 29)
Output Enable Time to High Level (tPZH) 45 90 ns
RL = 110 Ω (see Figure 22 and Figure 28)
Output Disable Time from High Level (tPHZ) 40 80 ns
RL = 110 Ω (see Figure 22 and Figure 28)
Output Disable Time from Low Level (tPLZ) 40 80 ns
RL = 110 Ω (see Figure 23 and Figure 29)
Output Enable Time from Shutdown to Low Level (tPSL) 650 900 ns RL = 110 Ω (see Figure 23 and Figure 29)
Output Enable Time from Shutdown to High Level (tPSH) 650 900 ns RL = 110 Ω (see Figure 22 and Figure 28)
1 Measured on |tPLH (Y) − tPHL (Y)| and |tPLH (Z) − tPHL (Z)|.
TIMING SPECIFICATIONS—ADM3483/ADM3488
VCC = 3.3 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Output Delay (tDD) 600 900 1400 ns
RL = 60 Ω (see Figure 20 and Figure 26)
Differential Output Transition Time (tTD) 400 700 1200 ns
RL = 60 Ω (see Figure 20 and Figure 26)
Propagation Delay, Low-to-High Level (tPLH) 700 1000 1500 ns RL = 27 Ω (see Figure 21 and Figure 27)
Propagation Delay, High-to-Low Level (tPHL) 700 1000 1500 ns RL = 27 Ω (see Figure 21 and Figure 27)
|tPLH – tPHL| Propagation Delay Skew1 (tPDS) 100 ns
RL = 27 Ω (see Figure 21 and Figure 27)
DRIVER OUTPUT ENABLE/DISABLE TIMES (ADM3483 ONLY)
Output Enable Time to Low Level (tPZL) 900 1300 ns
RL = 110 Ω (see Figure 23 and Figure 29)
Output Enable Time to High Level (tPZH) 600 800 ns RL = 110 Ω (see Figure 22 and Figure 28)
Output Disable Time from High Level (tPHZ) 50 80 ns RL = 110 Ω (see Figure 22 and Figure 28)
Output Disable Time from Low Level (tPLZ) 50 80 ns RL = 110 Ω (see Figure 23 and Figure 29)
Output Enable Time from Shutdown to Low Level (tPSL) 1.9 2.7 µs RL = 110 Ω (see Figure 23 and Figure 29)
Output Enable Time from Shutdown to High Level (tPSH) 2.2 3.0 s RL = 110 Ω (see Figure 22 and Figure 28)
1 Measured on |tPLH (Y) − tPHL (Y)| and |tPLH (Z) − tPHL (Z)|.
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491 Data Sheet
Rev. E | Page 6 of 20
TIMING SPECIFICATIONS—ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
VCC = 3.3 V, TA = 25°C, unless otherwise noted.
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
RECEIVER
Time to Shutdown (tSHDN)
ADM3483/ADM3485/ADM34911 80 190 300 ns
Propagation Delay, Low-to-High Level (tRPLH)
ADM3485/ADM3490/ADM3491 25 65 90 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 24 and Figure 30)
ADM3483/ADM3488 25 75 120 ns
Propagation Delay, High-to-Low Level (tRPHL)
ADM3485/ADM3490/ADM3491 25 65 90 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 24 and Figure 30)
ADM3483/ADM3488 25 75 120 ns
|tPLH – tPHL| Propagation Delay Skew (tRPDS)
ADM3485/ADM3490/ADM3491 10 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 24 and Figure 30)
ADM3483/ADM3488 20 ns
RECEIVER OUTPUT ENABLE/DISABLE TIMES
(ADM3483/ADM3485/ADM3491 ONLY)
Output Enable Time to Low Level (tPRZL) 25 50 ns CL = 15 pF (see Figure 25 and Figure 31)
Output Enable Time to High Level (tPRZH) 25 50 ns CL = 15 pF (see Figure 25 and Figure 31)
Output Disable Time from High Level (tPRHZ) 25 45 ns CL = 15 pF (see Figure 25 and Figure 31)
Output Disable Time from Low Level (tPRLZ) 25 45 ns CL = 15 pF (see Figure 25 and Figure 31)
Output Enable Time from Shutdown to
Low Level (tPRSL)
720 1400 ns CL = 15 pF (see Figure 25 and Figure 31)
Output Enable Time from Shutdown to
High Level (tPRSH)
720 1400 ns CL = 15 pF (see Figure 25 and Figure 31)
1 The transceivers are put into shutdown by bringing the RE high and DE low. If the inputs are in this state for less than 80 ns, the parts are guaranteed not to enter
shutdown. If the parts are in this state for 300 ns or more, the parts are guaranteed to enter shutdown.
Data Sheet ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
Rev. E | Page 7 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
VCC to GND 7 V
Digital I/O Voltage (DE, RE, DI) −0.3 V to +6 V
Digital I/O Voltage (RO) VCC − 0.5 V to VCC + 0.5 V
Driver Output/Receiver Input Voltage −7.5 V to +12.5 V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +125°C
θJA Thermal Impedance
8-Lead SOIC 121°C/W
14-Lead SOIC 86°C/W
Lead Temperature
Soldering (10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491 Data Sheet
Rev. E | Page 8 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RO
1
RE
2
DE
3
DI
4
V
CC
8
B
7
A
6
GND
5
ADM3483/
ADM3485
TOP VIEW
(Not to Scale)
05524-028
Figure 4. ADM3483/ADM3485 Pin Configuration
V
CC 1
RO
2
DI
3
G
ND
4
A
8
B
7
Z
6
Y
5
ADM3488/
ADM3490
TOP VIEW
(Not to Scale)
05524-029
Figure 5. ADM3488/ADM3490 Pin Configuration
NC
1
RO
2
RE
3
DE
4
V
CC
14
V
CC
13
A
12
B
11
DI
5
Z
10
GND
6
Y
9
GND
7
NC
8
NC = NO CONNECT
ADM3491
TOP VIEW
(Not to Scale)
05524-030
Figure 6. ADM3491 Pin Configuration
Table 7. Pin Function Descriptions
ADM3483/
ADM3485 Pin No.
ADM3488/
ADM3490 Pin No.
ADM3491
Pin No. Mnemonic Description
1 2 2 RO
Receiver Output. When enabled, if A > B by 200 mV, then RO =
high. If A < B by 200 mV, then RO = low.
2 Not applicable 3
RE Receiver Output Enable. A low level enables the receiver output,
RO. A high level places it in a high impedance state. If RE is high
and DE is low, the device enters a low power shutdown mode.
3 Not applicable 4 DE
Driver Output Enable. A high level enables the driver differential
Output A and Output B. A low level places it in a high impedance
state. If RE is high and DE is low, the device enters a low power
shutdown mode.
4 3 5 DI
Driver Input. With a half-duplex part when the driver is enabled, a
logic low on DI forces A low and B high while a logic high on DI
forces A high and B low. With a full-duplex part when the driver is
enabled, a logic low on DI forces Y low and Z high while a logic
high on DI forces Y high and Z low.
5 4 6, 7 GND Ground.
Not applicable 5 9 Y Noninverting Driver Output.
Not applicable 6 10 Z Inverting Driver Output.
6 Not applicable Not applicable A Noninverting Receiver Input A and Noninverting Driver Output A.
Not applicable 8 12 A Noninverting Receiver Input A.
7 Not applicable Not applicable B Inverting Receiver Input B and Inverted Driver Output B.
Not applicable 7 11 B Inverting Receiver Input B.
8 1 13, 14 VCC Power Supply (3.3 V ± 0.3 V).
Not applicable Not applicable 1, 8 NC No Connect.
Data Sheet ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
Rev. E | Page 9 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
30
0
03
05524-012
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
.5
25
20
15
10
5
0.51.01.52.02.53.0
Figure 7. Output Current vs. Receiver Output Low Voltage
–
16
0
03
05524-013
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
.5
–14
–12
–10
–8
–6
–4
–2
0.51.01.52.02.53.0
Figure 8. Output Current vs. Receiver Output High Voltage
3.30
3.00
–40
05524-014
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
3.25
3.20
3.15
3.10
3.05
–30 –20 –10 0 10 20 30 40 50 60 70 80
Figure 9. Receiver Output High Voltage vs. Temperature, IRO = 1.5 mA
0.8
0
–40
05524-015
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
–30 –20 –10 0 10 20 30 40 50 60 70 80
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Figure 10. Receiver Output Low Voltage vs. Temperature, IRO = 2.5 mA
100
0
03
05524-016
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
.5
90
80
70
60
50
40
30
20
10
0.51.01.52.02.53.0
Figure 11. Driver Output Current vs. Differential Output Voltage
2.6
1.6
–40
05524-017
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
–30 –20 –10 0 10 20 30 40 50 60 70 80
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
Figure 12. Driver Differential Output Voltage vs. Temperature, RL = 54 Ω
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491 Data Sheet
Rev. E | Page 10 of 20
140
0
01
05524-018
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
2
120
100
80
60
40
20
246810
Figure 13. Output Current vs. Driver Output Low Voltage
–
125
–5
–7 3
05524-019
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
–115
–105
–95
–85
–75
–65
–55
–45
–35
–25
–15
–6 –5 –4 –3 –2 –1 0 1 2
Figure 14. Output Current vs. Driver Output High Voltage
1.2
0.3
–40
05524-020
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
–30 –20 –10 0 10 20 30 40 50 60 70 80
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
DE = RE = GND
DE = RE = X*
*X = DON’T CARE
Figure 15. Supply Current vs. Temperature
90
0
–40
05524-021
TEMPERATURE (°C)
SHUTDOWN CURRENT (nA)
–30 –20 –10 0 10 20 30 40 50 60 70 80
80
70
60
50
40
30
20
10
Figure 16. Shutdown Current vs. Temperature
Data Sheet ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
Rev. E | Page 11 of 20
TEST CIRCUITS
R
L
/2
R
L
/2 V
OC
A
/
Y
B/Z
V
OD
05524-003
Figure 17. Differential Output Voltage
and Common-Mode Voltage Drivers
V
CM
=
–7V TO +12V
V
CC
R
L
375
375
V
OD
D
05524-004
Figure 18. Differential Output Voltage Drivers
with Varying Common-Mode Voltage
0
5524-005
I
OH
(–)
I
OL
(+)
V
OH
V
OL
R
0
V
ID
Figure 19. CMOS Output Voltage High and
CMOS Output Voltage Low Receivers
D
GENERATOR
1
V
CC
50
C
L
R
L
=
60
C
L
= 15pF
2
05524-036
OUT
1
PPR = 250kHz, 50% DUTY CYCLE,
t
R
6.0ns, Z
O
=50.
2
C
L
INCLUDES PROBE AND STRAY CAPACITANCE.
Figure 20. Driver Differential Output Delay and Transition Times
D
V
OM
R
L
=27
OUT
C
L
=15pF
2
GENERATOR
1
V
CC
50
S1
V
OM
=
V
OH
+V
OL
2
1.5V
05524-037
1
PPR = 250kHz, 50% DUTY CYCLE,
t
R
6.0ns, Z
O
=50.
2
C
L
INCLUDES PROBE AND STRAY CAPACITANCE.
Figure 21. Driver Propagation Delays
DOUT
C
L
= 50pF
2
GENERATOR
1
50
S1
V
OM
=
V
OH
+V
OL
2
1.5V
R
L
= 110
0V OR 3V
05524-038
1
PPR = 250kHz, 50% DUTY CYCLE,
t
R
6.0ns, Z
O
=50.
2
C
L
INCLUDES PROBE AND STRAY CAPACITANCE.
Figure 22. Driver Enable and Disable Times (tPZH, tPSH, tPHZ)
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491 Data Sheet
Rev. E | Page 12 of 20
DOUT
C
L
= 50pF
2
GENERATOR
1
50
S1
0V OR 3V
V
CC
R
L
=110
05524-039
1
PPR = 250kHz, 50% DUTY CYCLE,
tR
6.0ns, Z
O
=50.
2
C
L
INCLUDES PROBE AND STRAY CAPACITANCE.
Figure 23. Driver Enable and Disable Times (tPZL, tPSL, tPLZ)
05524-040
GENERATOR
1
50C
L
=15pF
2
R
1.5V
0V
OM
=
V
CC
2
OUT
V
ID
1
PPR = 250kHz, 50% DUTY CYCLE,
t
R
6.0ns, Z
O
=50.
2
C
L
INCLUDES PROBE AND STRAY CAPACITANCE.
Figure 24. Receiver Propagation Delays
R
GENERATOR
1
50
C
L2
S3 S1
S2
V
CC
+1.5V
–1.5V V
ID
1k
05524-041
1
PPR = 250kHz, 50% DUTY CYCLE,
t
R
6.0ns, Z
O
=50.
2
C
L
INCLUDES PROBE AND STRAY CAPACITANCE.
Figure 25. Receiver Enable and Disable Times
Data Sheet ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
Rev. E | Page 13 of 20
SWITCHING CHARACTERISTICS
IN
OUT
1.5V 1.5V
+3
V
0
+2V
–2V
t
DD
t
DD
t
TD
t
TD
50%50%
10%10%
90%90%
05524-006
Figure 26. Driver Differential Output Delay and Transition Times
3
V
0V
V
OH
V
OL
V
OH
V
OL
V
OM
V
OM
V
OM
V
OM
IN
A/Y
OUT
B/Z
OUT
1.5V 1.5V
t
PLH
t
PHL
t
PHL
t
PLH
05524-007
Figure 27. Driver Propagation Delays
0
V
OH
0
3
V
1.5V1.5V
0.25V
IN
OUT V
OM
t
PZH
t
PHZ
05524-008
Figure 28. Driver Enable and Disable Times (tPZH, tPSH, tPHZ)
VOL
VCC
0
3
V
0.25V
IN
OUT
1.5V 1.5V
t
PSL
t
PLZ
VOM
05524-009
Figure 29. Driver Enable and Disable Times (tPZL, tPSL, tPLZ)
05524-010
3
V
0
V
CC
0
IN
OUT V
OM
V
OM
1.5V1.5V
t
RPHL
t
RPLH
Figure 30. Receiver Propagation Delays
+3
V
0
V
OH
0
S1 OPEN
S2 CLOSED
S3 = +1.5V
S1 CLOSED
S2 OPEN
S3 = –1.5V
S1 OPEN
S2 CLOSED
S3 = +1.5V
S1 CLOSED
S2 OPEN
S3 = –1.5V
+3
V
0
V
CC
V
OL
+3V
0
V
CC
V
OL
+3V
0
V
OH
0
1.5V
1.5V
1.5V
IN
OUT
IN
OUT
IN
OUT
IN
OUT
tPRZL
tPRSL
tPRLZ
tPRHZ
+0.25V
+0.25V
1.5V
1.5V
1.5V
tPRZH
tPRSH
0
5524-011
Figure 31. Receiver Enable and Disable Times
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491 Data Sheet
Rev. E | Page 14 of 20
CIRCUIT DESCRIPTION
The ADM3483/ADM3485/ADM3488/ADM3490/ADM3491 are
low power transceivers for RS-485 and RS-422 communications.
The ADM3483/ADM3488 transmit and receive at data rates up
to 250 kbps; the ADM3485/ADM3490/ADM3491 transmit at up to
10 Mbps. The ADM3488/ADM3490/ADM3491 are full-duplex
transceivers, while the ADM3483/ADM3485 are half-duplex
transceivers. Driver enable (DE) and receiver enable (RE) pins
are included on the ADM3483/ADM3485/ADM3491. When
disabled, the driver and receiver outputs are high impedance.
DEVICES WITH RECEIVER/DRIVER ENABLES
(ADM3483/ADM3485/ADM3491)
Table 8. Transmitting Truth Table
Transmitting Input Transmitting Output
RE DE DI B1 A
1 Mode
X2 1 1 0 1 Normal
X2 1 0 1 0 Normal
0 0 X2 High-Z3 High-Z3 Normal
1 0 X2 High-Z3 High-Z3 Shutdown
1 A and B outputs are Y and Z, respectively, for full-duplex part (ADM3491).
2 X = don’t care.
3 High-Z = high impedance.
Table 9. Receiving Truth Table
Receiving Input Receiving Output
RE DE1 A – B RO Mode
0 0 ≥ +0.2 V 1 Normal
0 0 ≤ −0.2 V 0 Normal
0 0 Inputs Open 1 Normal
1 0 X2 High-Z3 Shutdown
1 DE is a don’t care; X for the full-duplex part (ADM3491).
2 X = don’t care.
3 High-Z = high impedance.
DEVICES WITHOUT RECEIVER/DRIVER ENABLES—
ADM3488/ADM3490
Table 10. Transmitting Truth Table
Transmitting Input Transmitting Output
DI Z Y
1 0 1
0 1 0
Table 11. Receiving Truth Table
Receiving Input Receiving Output
A – B RO
≥ +0.2 V 1
≤ −0.2 V 0
Inputs open 1
REDUCED EMI AND REFLECTIONS
(ADM3483/ADM3488)
The ADM3483/ADM3488 are slew rate limited transceivers,
minimizing EMI and reducing reflections caused by improperly
terminated cables.
LOW POWER SHUTDOWN MODE
(ADM3483/ADM3485/ADM3491)
A low power shutdown mode is initiated by bringing RE high
and DE low. The devices do not shut down unless both the driver
and receiver are disabled (high impedance). In shutdown mode,
the devices typically draw only 2 nA of supply current. For these
devices, the tPSH and tPSL enable times assume the part is in the
low power shutdown mode; the tPZH and tPZL enable times assume
the receiver or driver was disabled, but the part is not shut down.
DRIVER OUTPUT PROTECTION
Two methods are implemented to prevent excessive output current
and power dissipation caused by faults or by bus contention.
Current limit protection on the output stage provides immediate
protection against short circuits over the whole common-mode
voltage range (see the Typical Performance Characteristics section).
In addition, a thermal shutdown circuit forces the driver outputs
into a high impedance state if the die temperature rises
excessively.
PROPAGATION DELAY
Skew time is the difference between the low-to-high and high-
to-low propagation delays. Small driver/receiver skew times help
maintain a symmetrical mark-space ratio (50% duty cycle).
The receiver skew time (|tPRLH − tPRHL|) is under 10 ns (20 ns
for ADM3483/ADM3488). The driver skew times are 8 ns for
ADM3485/ADM3490/ADM3491 and typically under 100 ns for
ADM3483/ADM3488.
TYPICAL APPLICATIONS
The ADM3483/ADM3485/ADM3491 transceivers are designed
for half-duplex bidirectional data communications on multipoint
bus transmission lines, Figure 32 and Figure 33 show typical
network applications circuits. The ADM3488 and the ADM3490
full-duplex transceivers are designed to be used in a daisy-chain
network topology or in a point-to-point application, see Figure 34
and Figure 35. The ADM3491 can be used as line repeat Figure 36.
To minimize reflections, the line must be terminated at both
ends in its characteristic impedance, and stub lengths off the main
line must be kept as short as possible. The slew rate limited
ADM3483/ADM3488 are more tolerant of imperfect termination.
Data Sheet ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
Rev. E | Page 15 of 20
LINE LENGTH vs. DATA RATE
The RS-485 and RS-422 standards cover line lengths up to 4000 feet. For line lengths greater than 4000 feet, see Figure 36.
B
A
R
D
RO
RE
DI
DE
ADM3483/
ADM3485 ADM3483/
ADM3485
ADM3483/
ADM3485 ADM3483/
ADM3485
B
AR
D
RO
RE
DI
DE
B
A
RD
RO RE DI
DE
B
A
R
D
RO RE DI
DE
05524-022
MA
X
IMUM NUMBER OF TRANSCEI
V
ERS ON BUS = 32
RTRT
NOTES
1. RT IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE.
VCC
R1
R2
Figure 32. ADM3483/ADM3485 Typical Half-Duplex RS-485 Network
R
D
RO
RE
DI
DE
ADM3491
ADM3491
A
B
Z
Y
05524-090
R
D
RO DIDE
A B Z Y
RE
R
D
RO
DI
DE
ADM3491
MASTER SLAVE
SLAVE
A
B
Z
Y
RE
MAXIMUM NUMBER OF NODES = 32
ADM3491
R
D
RO DIDE
A B Z Y
RE
SLAVE
NOTES
1.
R
T
IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE.
R
T
R
T
R
T
V
CC
R1
R2
R
T
V
CC
R1
R2
Figure 33. ADM3491 Typical Full-Duplex RS-485 Network
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491 Data Sheet
Rev. E | Page 16 of 20
B
A
R
D
RO
DI
Y
ZB
A
Y
Z
RO
DI
R
D
RD
RO
RD
MASTER
ADM3488/
ADM3490
ADM3488/
ADM3490
ADM3488/
ADM3490
SLAVE
SLAVE
ADM3488/
ADM3490
SLAVE
ABZY ABZY
DI RO DI
05524-042
Figure 34. ADM3488/ADM3490 Full-Duplex Daisy-Chain Network
B
A
R
D
RO
DI
Y
Z
MASTER
ADM3488/
ADM3490
R
D
RO
DI
B
A
Y
Z
SLAVE
ADM3488/
ADM3490
0
5524-043
Figure 35. ADM3488/ADM3490 Full-Duplex Point-to-Point Applications
R
D
RO
RE
DI
DE
ADM3491
A
B
Z
Y
DATA IN
DATA OUT
05524-091
NOTES
1. R
T
IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE.
R
T
R
T
Figure 36. Line Repeater for ADM3491
Data Sheet ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
Rev. E | Page 17 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 37. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AB
060606-A
14 8
7
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
45°
Figure 38. 14-Lead Narrow Body Small Outline [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491 Data Sheet
Rev. E | Page 18 of 20
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Ordering Quantity
ADM3483ARZ −40°C to +85°C 8-Lead Narrow Body Small Outline (SOIC_N) R-8
ADM3483ARZ–REEL7 −40°C to +85°C 8-Lead Narrow Body Small Outline (SOIC_N) R-8 1,000
ADM3485ARZ −40°C to +85°C 8-Lead Narrow Body Small Outline (SOIC_N) R-8
ADM3485ARZ–REEL7 −40°C to +85°C 8-Lead Narrow Body Small Outline (SOIC_N) R-8 1,000
ADM3488ARZ −40°C to +85°C 8-Lead Narrow Body Small Outline (SOIC_N) R-8
ADM3488ARZ–REEL7 −40°C to +85°C 8-Lead Narrow Body Small Outline (SOIC_N) R-8 1,000
ADM3490ARZ −40°C to +85°C 8-Lead Narrow Body Small Outline (SOIC_N) R-8
ADM3490ARZ–REEL7 −40°C to +85°C 8-Lead Narrow Body Small Outline (SOIC_N) R-8 1,000
ADM3491AR −40°C to +85°C 14-Lead Narrow Body Small Outline (SOIC_N) R-14
ADM3491AR-REEL −40°C to +85°C 14-Lead Narrow Body Small Outline (SOIC_N) R-14 2,500
ADM3491AR-REEL7 −40°C to +85°C 14-Lead Narrow Body Small Outline (SOIC_N) R-14 1,000
ADM3491ARZ −40°C to +85°C 14-Lead Narrow Body Small Outline (SOIC_N) R-14
ADM3491ARZ-REEL −40°C to +85°C 14-Lead Narrow Body Small Outline (SOIC_N) R-14 2,500
ADM3491ARZ-REEL7 −40°C to +85°C 14-Lead Narrow Body Small Outline (SOIC_N) R-14 1,000
1 Z = RoHS Compliant Part.
Data Sheet ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
Rev. E | Page 19 of 20
NOTES
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491 Data Sheet
Rev. E | Page 20 of 20
NOTES
©2005-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05524-0-11/11(E)