MM74HC4050N - Fairchild Semiconductor

Februa ry 198 4

Revised October 1999

MM74HC4049 • MM74HC4050 Hex Inverting Logic Level Down Converter • Hex Logic Level Down Converter

MM74HC4049 • MM74HC4050

Hex Inverting Logic Level Down Converter •

Hex Logic Level Down Converter

General Descript ion

The MM74HC4049 and the MM74HC4050 utilize

advanced silicon-gate CMOS technology, and have a mod-

ified input protection structure that enables these parts to

be used as logic level translators which will convert high

level logic to a low level logic while operating from th e low

logic supply. For example , 0–1 5V CMOS log ic can be con-

verted to 0–5 V logi c whe n usin g a 5V su pply. The modified

input protection has no diode connected to VCC, thus allow-

ing the input voltage to exceed the supply. The lower zener

diode protects the input from both positive and negative

static voltages. In addition each part can be used as a sim-

ple buffer or inverter without level translation. The

MM74HC4049 is pin and functionally compatible to the

CD4049BC and the MM74HC4050 is compatible to the

CD4050BC

Features

■Typical propagation delay: 8 ns

■Wide power supply range: 2V–6V

■Low quiescent supply current: 20 µA maximum (74HC)

■Fanout of 10 LS-TTL loads

Ordering Code:

Devices also available in Tape and Reel. Spe ci fy by append ing the suffix let t er “X” to the o rdering code.

Connection Diagrams

MM74HC4049 MM74HC4050

Order Num be r Packag e Num b er Packag e Desc rip ti on

MM74HC4049M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

MM74HC4049SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC4049MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153. 4.4mm Wide

MM74HC4049N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

MM74HC4050M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

MM74HC4050SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC4050MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153. 4.4mm Wide

MM74HC4050N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

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MM74HC4049 • MM74HC4050

Absolute Maximum Ratings(Note 1)

(Note 2) Recommended Operating

Conditions

Note 1: Absolute Maximum Ratings are those values beyond which dam-

age to the device may occur.

Note 2: Unles s ot herwise specified all v olt ages ar e referenc ed to grou nd.

Note 3: Power Dissipati on temperat ure deratin g — plastic “N” pa ckage: −

12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics (Note 4)

Note 4: F or a power supply of 5V ±10% the wor st case output vo ltages (VOH and VOL) occur f or HC at 4.5 V. Thus th e 4.5V values should be u sed wh en

designing with this supply. Worst case VIH and VIL occur at VCC = 5.5 V and 4. 5V respec t iv ely. (The VIH value at 5. 5V is 3.85V.) The wors t c as e leaka ge cur-

rent (IIN, ICC, IOZ) occur fo r C M OS at the higher volt age and so the 6.0V values sh ould be us ed.

Supply Voltage (VCC)−0.5 to +7.0V

DC Input Voltage (VIN)−1.5 to +18V

DC Output Voltage (VOUT)−0.5 to VCC +0.5V

Clamp Diode Current (IZK, IOK)−20 mA

DC Output Current, per pin (IOUT)±25 mA

DC VCC or GND Current, per pin (ICC)±50 mA

Storage Temperature Range (TSTG)−65°C to +150°C

Power Dissipation (PD)

(Note 3) 600 mW

S.O. Package only 500 mW

Lead Temperature (TL)

(Soldering 10 seconds) 26 0°C

Min Max Units

Supply Voltage (VCC)26V

DC In put Voltage 0 15 V

(VIN)

DC Output Vo ltage 0 VCC V

(VOUT)

Operating Temperature Range (TA)−40 +85 °C

Input Rise or Fall Times

(tr, tf) VCC

= 2.0V 1000 ns

VCC = 4.5V 500 ns

VCC = 6.0V 400 ns

Symbol Parameter Conditions VCC TA = 25°CT

A = −40°C to 85°CT

A = −55°C to 125°CUnits

Typ Guaranteed Limits

VIH Minimum HIGH Level Input 2.0V 1.5 1.5 1.5 V

Voltage 4.5V 3.15 3.15 3.15 V

6.0V 4.2 4.2 4.2 V

VIL Maximum LOW Level Input 2.0V 0.5 0.5 0.5 V

Voltage 4.5V 1.35 1.35 1.35 V

6.0V 1.8 1.8 1.8 V

VOH Minimum HIGH Level VIN = VIH or VIL

Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V

4.5V 4.5 4.4 4.4 4.4 V

6.0V 6.0 5.9 5.9 5.9 V

VIN = VIH or VIL

|IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V

|IOUT| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V

VOL Maximum LOW Level VIN = VIH or VIL

Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V

4.5V 0 0.1 0.1 0.1 V

6.0V 0 0.1 0.1 0.1 V

VIN = VIH or VIL

|IOUT| ≤ 4 mA 4.5V 0.2 0.26 0.33 0.4 V

|IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V

IIN Maximum Input Current VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA

VIN = 15V 2.0V ±0.5 ±5±5µA

ICC Maximum Quiescent Supply VIN = VCC or GND 6.0V 2.0 20 40 µA

Current IOUT = 0 µA

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MM74HC4049 • MM74HC4050

AC Electrical Characteristics

VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns

AC Electrical Characteristics

VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)

Note 5: CPD determines the no load dy namic po w er c onsumption, PD = CPD VCC2 f + ICC VCC, and the n o load dynam ic current consumption,

IS = CPD VCC f + ICC.

Symbol Parameter Conditions Typ Guaranteed Units

Limit

tPHL, tPLH Maximum Propagation Delay 8 15 ns

Symbol Parameter Conditions VCC TA = 25°CT

A = −40° to 85°CT

A = −55° to 125°CUnits

Typ Guaranteed Limits

tPHL, tPLH Maximum Propagation 2.0V 30 85 100 130 ns

Delay 4.5V 10 17 20 26 ns

6.0V 9 15 18 22 ns

tTHL, tTLH Maximum Output 2.0V 25 75 95 110 ns

Rise and Fall 4.5V 7 15 19 22 ns

Time 6.0V 6 13 16 19 ns

CPD Power Dissipation (per gate) 25 pF

Capacitance (Note 5)

CIN Maximum Input 5 10 10 10 pF

Capacitance

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MM74HC4049 • MM74HC4050

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

Package Number M16A

16-Lead Sma ll Outline Pac kage (SOP), EIAJ TYPE II, 5. 3mm Wide

Package Number M16D

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MM74HC4049 • MM74HC4050

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Packag e Num be r MTC 16

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MM74HC4049 • MM74HC4050 Hex Inverting Logic Level Down Converter • Hex Logic Level Down Converter

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E

Fairchild does no t assume any responsibility for use of any circuitry describ ed, no circuit pate nt licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a life su pport

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the fa i lure of the life su pp ort

device or system, or to affect its safety or effectiveness.