04/2011
ARA2000
Address-Programmable Reverse
Amplier with Step Attenuator
Data Sheet - Rev 2.3
FEATURES
• Low cost integrated amplier with step attenuator
• Attenuation Range: 0-58 dB, adjustable in 1dB
increments via a 3 wire serial control
• Meets DOCSIS distortion requirements at a
+60dBmV output signal level
• Programmable address allows multiple parts to
share control bus
• Low distortion and low noise
• Frequency range: 5-100MHz
• 5 Volt operation
• -40 to +85 oC temperature range
APPLICATIONS
• MCNS/DOCSIS Compliant Cable Modems
• CATV Interactive Set-Top Box
• Telephony over Cable Systems
• OpenCable Set-Top Box
• Residential Gateway
The ARA2000 is designed to provide the reverse path
amplication and output level control functions in a
CATV Set-Top Box or Cable Modem. It incorporates
a digitally controlled precision step attenuator that is
preceded by an ultra low noise amplier stage, and
followed by an ultra-linear output driver amplier. This
device uses a balanced circuit design that exceeds the
MCNS/DOCSIS requirement for harmonic performance
at a +60dBmV output level while only requiring a single
polarity +5V supply. Both the input and output are
matched to 75 ohms with an appropriate transformer.
The precision attenuator provides up to 58 dB of
attenuation in 1 dB increments. The ARA2000 has a
programmable address that allows multiple devices to
share a common control bus. The ARA2000 is offered
in a 28-pin SSOP package featuring a heat slug on
the bottom of the package.
PRODUCT DESCRIPTION
Figure 1: Cable Modem or Set Top Box Application Diagram
S12 Package
28 Pin SSOP
with Heat Slug
2Data Sheet - Rev 2.3
04/2011
ARA2000
Figure 2: Functional Block Diagram
Figure 3: Pin Out
Data Sheet - Rev 2.3
04/2011
3
ARA2000
Table 1: Pin Description
Notes:
(1) All N/C pins should be grounded.
(2) Pins should be AC-coupled. No external DC bias should be applied.
PIN NAME DESCRIPTION PIN NAME DESCRIPTION
1GND Ground 15 C0 Device Address 0
2 V
ATTN
Supply for Attenuator 16 C1 Device Address 1
3ATT
IN
(+) Attenuator (+) Input
(2)
17 N/C No Connection
(1)
4A1
OUT
(+) Amplifier A1 (+) Output 18 GND
CMOS
Ground for Digital CMOS
Circuit
5A1
IN
(+) Amplifier A1 (+) Input
(2)
19 ATT
OUT
(-) Attenuator (-) Output
(2)
6Vg1 Amplifier A1 (+/-) Control 20 A2
IN
(-) Amplifier A2 (-) Input
(2)
7 I
SET1
Amplifier A1 (+/-) Current
Adjust 21 A2
OUT
(-) Amplifier A2 (-) Output
8A1
IN
(-) Amplifier A1 (-) Input
(2)
22 I
SET2
Amplifier A2 (+/-) Current
Adjust
9A1
OUT
(-) Amplifier A1 (-) Output 23 Vg2 Amplifier A2 (+/-) Control
10 ATT
IN
(-) Attenuator (-) Input
(2)
24 A2
OUT
(+) Amplifier A2 (+) Output
11 V
CMOS
Supply For Digital CMOS
Circuit 25 A2
IN
(+) Amplifier A2 (+) Input
(2)
12 CLK Clock 26 ATT
OUT
(+) Attenuator (+) Output
(2)
13 DAT Data 27 N/C No Connection
(1)
14 EN Enable 28 GND Ground
4Data Sheet - Rev 2.3
04/2011
ARA2000
ELECTRICAL CHARACTERISTICS
Table 2: Absolute Minimum and Maximum Ratings
Table 3: Operating Ranges
Stresses in excess of the absolute ratings may cause permanent damage. Functional
operation is not implied under these conditions. Exposure to absolute ratings for extended
periods of time may adversely affect reliability.
The device may be operated safely over these conditions; however, parametric performance is
guaranteed only over the conditions dened in the electrical specications.
Notes:
1. Pins 3, 5, 8, 10, 19, 20, 25 and 26 should be AC-coupled. No external DC bias should be
applied.
2. Pins 7 and 22 should be grounded or pulled to ground through a resistor. No external DC
bias should be applied.
PARAMETER MIN MAX UNIT
Analog Supply (pins 2, 4, 9, 21, 24) 0 9 VDC
Digital Supply: V
CMOS
(pin 11) 06VDC
Amplifier Controls Vg1, Vg2 (pins 6, 23) -5 2 V
RF Power at Inputs (pins 5, 8) -+60 dBmV
Digital Interface (pins 12, 13, 14, 15, 16) -0.5 V
CMOS
+0.5 V
Storage Temperature -55 +200 C
Soldering Temperature -260 C
Soldering Time -5Sec
PARAMETER MIN TYP MAX UNIT
Amplifier Supply: V
DD
(pins 4, 9,21,24) 4.5 5.0 7.0 VDC
Attenuator Supply: V
ATTN
(pin 2) V
DD
-0.5 5.0 7.0 VDC
Digital Supply: V
CMOS
(pin 11) 3.0 -5.5 VDC
Digital Interface (pins 12, 13, 14, 15,16) 0-V
CMOS
V
Amplifier Controls Vg1, Vg2 (pins 6, 23) -5 1 2 V
Case Temperature -40 25 85 C
Data Sheet - Rev 2.3
04/2011
5
ARA2000
Note: As measured in ANADIGICS test xture
Table 4: DC Electrical Specications
TA=25°C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (TX enabled); Vg1, Vg2 = 0 V (TX disabled)
Table 5: AC Electrical Specications
TA=25°C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (TX enabled); Vg1, Vg2 = 0 V (TX disabled)
PARAMETER MIN TYP MAX UNIT COMMENTS
Gain (10 MHz) 27.5 29.3 30.5 dB 0 dB attenuation setting
Gain Flatness -
-
0.75
1.5
-
-dB 5 to 42 MHz
5 to 65 MHz
Gain Variation over Temperature --0.006 -dB/
8
C
Attenuation Steps
1 dB
2 dB
4 dB
8 dB
16 dB
32 dB
0.65
1.6
3.6
7.5
15.0
30.2
0.83
1.70
3.75
7.75
15.40
30.75
1.00
2.05
4.0
8.0
15.8
31.3
dB Monotonic
Maximum Attenuation 58.6 60.3 -dB
2
nd
Harmonic Distortion Level
(10 MHz) --75 -53 dBc +60 dBmV into 75 Ohms
3
rd
Harmonic Distortion Level
(10 MHz) --60 -53 dBc +60 dBmV into 75 Ohms
3
rd
Order Output Intercept 78 - - dBmV
1 dB Gain Compression Point -68.5 -dBmV
Noise Figure -3.0 4.0 dB Includes input balun loss
PARAMETER MIN TYP MAX UNIT COMMENTS
Amplifier A1 Current (pins 4, 9) -
-
48
2.4
80
6mA Tx enabled
Tx disabled
Amplifier A2 Current (pins 21, 24) -
-
77
3.7
120
9mA Tx enabled
Tx disabled
Attenuator Current (pin 2) -915 mA
Total Power Consumption -
-
0.67
75
1.08
150
W
mW
Tx enabled
Tx disabled
Thermal Resistance (
JC
) - 38 -C/W
6Data Sheet - Rev 2.3
04/2011
ARA2000
continued: AC Electrical Specications
TA=25°C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (TX enabled); Vg1, Vg2 = 0 V (TX disabled)
Note: As measured in ANADIGICS test xture
PARAMETER MIN TYP MAX UNIT COMMENTS
Output Noise Power
Active/ No Signal/ Min. Atten. Set
Active/ No Signal/ Max. Atten. Set.
-
-
-
-
-38.5
-53.8
dBmV Any 160 kHz bandwidth from
5 to 42 MHz
Isolation (45 MHz) in Tx disable mode -65 -dB
Difference in output signal
between Tx enable and Tx
disable
Differential Input Impedance -300 -Ohms between pins 5 and 8 (Tx
enabled)
Input Impedance -75 -Ohms with transformer (Tx enabled)
Input Return Loss
(75 Ohm characteristic impedance)
-
-
-20
-5
-12
-dB Tx enabled
Tx disabled
Differentail Output Impedance -300 -Ohms between pins 21 and 24
Output Impedance -75 -Ohms with transformer
Output Return Loss
(75 Ohm characteristic impedance)
-
-
-17
-15
-12
-10 dB Tx enabled
Tx disabled
Output Voltage Transient
Tx enable/ Tx disable
-
-
-
4
100
7mVp-p 0 dB attenuator setting
24 dB attenuator setting
Data Sheet - Rev 2.3
04/2011
7
ARA2000
Figure 4: Test Circuit
8Data Sheet - Rev 2.3
04/2011
ARA2000
Figure 5: Attenuation Level vs Control Word
Figure 6: Gain & Noise Figure vs Frequency
PERFORMANCE DATA
Figure 7: Gain & Noise Figure vs VDD
Data Sheet - Rev 2.3
04/2011
9
ARA2000
Figure 8: Gain & Noise Figure vs Temperature
Figure 9: Harmonic Distortion vs VDD
POUT = 58dBmV
Figure 10: Harmonic Distortion vs VDD
POUT = 58dBmV
10 Data Sheet - Rev 2.3
04/2011
ARA2000
Figure 11: Harmonic Distortion vs Temperature
POUT = 58dBmV
Figure 12: Harmonic Distortion vs Power Out
Figure 13: Transients vs Attenuation
POUT = 55dBmV at 0dB attenuation
Data Sheet - Rev 2.3
04/2011
11
ARA2000
Figure 14: Harmonic Performance over
Frequency POUT = +62dBmV
Figure 15: IIP2 & IIP3 vs Frequency
Figure 16: IIP2 & IIP3 vs VDD
12 Data Sheet - Rev 2.3
04/2011
ARA2000
Table 6: Programming Word
LOGIC PROGRAMMING
Table 7: Data Description Table 8: Device Address
Programming Instructions
The programming word is set through a 16 bit shift
register via the data, clock and enable lines. The
data is entered in order with the most signicant bit
(MSB) rst and the least signicant bit (LSB) last. The
enable line must be low for the duration of the data
entry, then set high to latch the shift register. The
rising edge of the clock pulse shifts each data value
into the register.
The device is selected when the logic inputs at pins
16 and 15 match the values of data bits C1 and C0,
respectively.
D ATA B IT D15 D14 D13 D12 D11 D10 D9D8D7D6D5D4D3D2D1D0
Value P7 P6 P5 P4 P3 P2 P1 P0 0 0 0 1 C1 C0 1 1
VALUE FUNCTION
( 1 = on, 0 = bypass)
P7 N/A
P6 N/A
P5 32 dB Attenuator Bit
P4 16 dB Attenuator Bit
P3 8 dB Attenuator Bit
P2 4 dB Attenuator Bit
P1 2 dB Attenuator Bit
P0 1 dB Attenuator Bit
Data Sheet - Rev 2.3
04/2011
13
ARA2000
Figure 17: Serial Data Input Timing
Table 9: Digital Interface Specication
PARAMETER MIN TYP MAX UNIT
Logic High Input: V
H
2.0 - - V
Logic Low Input: V
L
- - 0.8 V
Logic Input Current Consumption - - 0.01 mA
Data to Clock Set Up Time: t
CS
50 - - ns
Data to Clock Hold Time: t
CH
10 - - ns
Clock Pulse Width High: t
CWH
50 - - ns
Clock Pulse Width Low: t
CWL
50 - - ns
Clock to Load Enable Setup Time: t
ES
50 - - ns
Load Enable Pulse Width: t
EW
50 - - ns
Rise Time: t
R
-10 -ns
Fall Time: t
F
-10 -ns
tCS tCH
tCWL
tCWH
tES
tEW
DATA
CLOCK
ENABLE
OR
ENABLE
D15: MSB D14 D8D7D1D0: LSB
14 Data Sheet - Rev 2.3
04/2011
ARA2000
Data Sheet - Rev 2.3
03/2011
APPLICATION INFORMATION
Transmit Enable / Disable
The ARA2000 includes two amplication stages that
each can be shut down through external control pins
Vg1 and Vg2 (pins 6 and 23, respectively.) By applying
a slightly positive bias of typically +1.0 Volts, the
amplier is enabled. In order to disable the amplier,
the control pin needs to be pulled to ground.
A practical way to implement the necessary control is
to use bias resistor networks similar to those shown
in the test circuit schematic (Figure 4.) Each network
includes a resistor shunted to ground that serves as
a pull-down to disable the amplier when no control
voltage is applied. When a positive voltage is applied,
the network acts as a voltage divider that presents
the required +1.0 Volts to enable the amplier. By
selecting different resistor values for the voltage
divider, the network can accommodate different control
voltage inputs.
The Vg1 and Vg2 pins may be connected together
directly, and controlled through a single resistor
network from a common control voltage.
Amplier Bias Current
The Is e t pins (7 and 22) set the bias current for the
amplication stages. Grounding these pins results
in the maximum possible current. By placing a
resistor from the pin to ground, the current can be
reduced. The recommended bias conditions use the
conguration shown in the test circuit schematic in
Figure 4.
Thermal Layout Considerations
The device package for the ARA2000 features a heat
slug on the bottom of the package body. Use of the
heat slug is an integral part of the device design.
Soldering this slug to the ground plane of the PC board
will ensure the lowest possible thermal resistance for
the device, and will result in the longest MTF (mean
time to failure.)
A PC board layout that optimizes the benets of the
heat slug is shown in Figure 18. The via holes located
under the body of the device must be plated through
to a ground plane layer of metal, in order to provide a
sufcient heat sink. The recommended solder mask
outline is shown in Figure 19.
Figure 18: PC Board Layout
Data Sheet - Rev 2.3
04/2011
15
ARA2000
Figure 19: Solder Mask Outline
Output Transformer
Matching the output of the ARA2000 to a 75 Ohm load
is accomplished using a 2:1 turns ratio transformer. In
addition to providing an impedance transformation, this
transformer provides the bias to the output amplier
stage via the center tap.
The transformer also cancels even mode distortion
products and common mode signals, such as the
voltage transients that occur while enabling and
disabling the ampliers. As a result, care must be
taken when selecting the transformer to be used at
the output. It must be capable of handling the RF and
DC power requirements without saturating the core,
and it must have adequate isolation and good phase
and amplitude balance. It also must operate over
the desired frequency and temperature range for the
intended application.
ESD Sensitivity
Electrostatic discharges can cause permanent damage
to this device. Electrostatic charges accumulate on test
equipment and the human body, and can discharge
without detection. Proper precautions and handling
are strongly recommended. Refer to the ANADIGICS
application note on ESD precautions.
16 Data Sheet - Rev 2.3
04/2011
ARA2000
Figure 20: S12 Package Outline - 28 Pin SSOP with Heat Slug
PACKAGE OUTLINE
Data Sheet - Rev 2.3
04/2011
17
ARA2000
COMPONENT PACKAGING
Figure 22: Tape Dimensions
Volume quantities of the ARA2000 are supplied on
tape and reel. Each reel holds 3,500 pieces.
Figure 21: Reel Dimensions
18 Data Sheet - Rev 2.3
04/2011
ARA2000
NOTES
Data Sheet - Rev 2.3
04/2011
19
ARA2000
NOTES
20 Data Sheet - Rev 2.3
04/2011
ARA2000
NOTES
WARNING
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product
in any such application without written consent is prohibited.
IMPORTANT NOTICE
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A.
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
E-mail: Mktg@anadigics.com
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice.
The product specications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to
change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed
to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers
to verify that the information they are using is current before placing orders.
Data Sheet - Rev 2.3
04/2011
21
ARA2000
ORDERING INFORMATION
ORDER NUMBER TEMPERATURE
RANGE
PACKAGE
DESCRIPTION COMPONENT PACKAGING
ARA2000S12P1 -40 to 85 °C 28 Pin SSOP
with Heat Slug 3,500 piece tape and reel