W3E16M72SR-250BI - Microsemi Corp.

W3E16M72SR-XBX

Rev. 3 www.microsemi.com

Microsemi Corporation reserves the right to change products or speciﬁ cations without notice.

16Mx72 Registered DDR SDRAM

FEATURES

 Registered for enhanced performance of bus speeds of

200, 225, and 250 MHz

 Package:

• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm

 2.5V ±0.2V core power supply

 2.5V I/O (SSTL_2 compatible)

 Differential clock inputs (CK and CK#)

 Commands entered on each positive CK edge

 Internal pipelined double-data-rate (DDR) architecture; two

data accesses per clock cycle

 Programmable Burst length: 2,4 or 8

 Bidirectional data strobe (DQS) transmitted/received with

data, i.e., source-synchronous data capture (one per byte)

 DQS edge-aligned with data for READs; center-aligned with

data for WRITEs

 DLL to align DQ and DQS transitions with CK

 Four internal banks for concurrent operation

 Two data mask (DM) pins for masking write data

 Programmable IOL/IOH option

 Auto precharge option

 Auto Refresh and Self Refresh Modes

 Commercial, Industrial and Military Temperature Ranges

 Organized as 16M x 72

 Weight: W3E16M72SR-XBX - 2.5 grams typical

BENEFITS

 47% SPACE SAVINGS

 Glueless Connection to PCI Bridge/Memory Controller

 Reduced part count

 Reduced I/O count

• 49% I/O Reduction

 Reduced trace lengths for lower parasitic capacitance

 Suitable for hi-reliability applications

 Laminate interposer for optimum TCE match

 Upgradeable to 32M x 72 density (contact factory for

information)

* This product is subject to change without notice.

GENERAL DESCRIPTION

The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS,

dynamic random-access, memory using 5 chips containing

268,435,456 bits. Each chip is internally conﬁ gured as a quad-bank

DRAM. Each of the chip’s 67,108,864-bit banks is organized as

8,192 rows by 512 columns by 16 bits.

The 128 MB DDR SDRAM uses a double data rate architecture to

achieve high-speed operation. The double data rate architecture is

essentially a 2n-prefetch architecture with an interface designed to

transfer two data words per clock cycle at the I/O pins. A single read

or write access for the 128MB DDR SDRAM effectively consists

of a single 2n-bit wide, one-clock-cycle data tansfer at the internal

DRAM core and two corresponding n-bit wide, one-half-clock-cycle

data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally, along

with data, for use in data capture at the receiver. DQS is a strobe

transmitted by the DDR SDRAM during READs and by the memory

contoller during WRITEs. DQS is edge-aligned with data for READs

and center-aligned with data for WRITEs. Each chip has two data

strobes, one for the lower byte and one for the upper byte.

Monolithic Solution (mm) W3E16M72SR-XBX S

Area 5 x 265mm2 + 2 x 105mm2 = 1536mm2800mm247%

I/O Count 5 x 66 pins + 2 x 48 pins = 426 pins 219 Balls 49%

22.3

12.6

11.9

TSOP

11.9

TSOP

11.9

TSOP

11.9

TSOP

11.9 8.3

TSOP 25

W3E16M72SR-XBX

TSOP

W3E16M72SR-XBX

Rev. 3 www.microsemi.com

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FIGURE 1 – PIN CONFIGURATION

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

DQ1

DQ3

DQ6

DQ7

CAS#

CS#

VSS

CK3#

DQ56

DQ57

DQ60

DQ62

VSS

DQ30

DQ28

DQ25

DQ24

CK1

VCC

RVREF

DQ39

DQ38

DQ35

DQ33

VCC

DQ0

DQ2

DQ4

DQ5

DM0

WE#

RAS#

VSS

CK3

DM7

DQ58

DQ59

DQ61

DQ63

DQ31

DQ29

DQ27

DQ26

DM3

CK1#

VCCQ

RESET#

DM4

DQ37

DQ36

DQ34

DQ32

DQ14

DQ12

DQ10

DQ8

VCC

DQ55

DQ53

DQ51

DQ49

DQ17

DQ19

DQ21

DQ23

VSS

DQ40

DQ42

DQ44

DQ46

DQ15

DQ13

DQ11

DQ9

DM1

CK0

CKE

VCCQ

DQ54

DQ52

DQ50

DQ48

DQ16

DQ18

DQ20

DQ22

DM2

RCK0B

RCK1B

VSS

CK2

DM5

DQ41

DQ43

DQ45

DQ47

VSS

VCC

VCCQ

DQS7

DQS6

CK0#

VSS

DQS8

DM6

DQS9

VSS

VCC

VCCQ

VCC

VSS

VREF

RCK0

RCK1

VCC

CK2#

DQS4

DQS5

VCC

VSS

A12

DQS1

DM9

DQ73

DQ75

DQ77

DQ79

DNU

DQS2

DQ70

DQ68

DQ66

DQ64

A10

DNU

BA0

CK4

DQ72

DQ74

DQ76

DQ78

A11

DNU

BA1

DQ71

DQ69

DQ67

DQ65

VSS

VCC

VCCQ

DQS0

CK4#

VSS

VCC

VCCQ

VCC

VSS

DQS3

DM8

VCC

VSS

NOTE: DNU = Do Not Use; to be left unconnected for future upgrades. Pin D8 will be A13, D9 will be A14, and D10 will be A15 as needed.

NC = Not Connected Internally.

Top View

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REF

RESET#

0-12

0-1

# CK#

CAS#

CKE

DQML

DQMH

0-12

0-1

# CK#

RAS

CAS

WE#

RAS#

CKE

DQML

DQMH

0-12

0-1

# CK#

CKE

DQML

DQMH

0-12

0-1

# CK#

CKE

DQS

DQSL

DQS

DQSH

0-12

0-1

# CK#

CKE

DQS

DQSL

DQS

DQSH

REF

DQS

DQSL

DQS

DQSH

REF

DQS

DQSL

DQS

DQSH

REF

DQS

DQSL

DQS

DQSH

REF

DQML

DQMH

DQML

DQMH

CAS

RAS

CKE

REF

RESET#

RAS#

CAS#

WE#

CS#

CKE

REF

RESET#

0-12

SSTV16857

RCK

CS#

CAS# WE# RAS#

CS#

CAS# WE# RAS# CS#

CAS#

WE# RAS# CS#

FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM

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Rev. 3 www.microsemi.com

Microsemi Corporation reserves the right to change products or speciﬁ cations without notice.

The 128MB DDR SDRAM operates from a differential clock (CK and

CK#); the crossing of CK going HIGH and CK# going LOW will

be referred to as the positive edge of CK. Commands (address

and control signals) are registered at every positive edge of CK.

Input data is registered on both edges of DQS, and output data is

referenced to both edges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst oriented;

accesses start at a selected location and continue for a programmed

number of locations in a programmed sequence. Accesses begin

with the registration of an ACTIVE command, which is then followed

by a READ or WRITE command. The address bits registered

coincident with the ACTIVE command are used to select the bank

and row to be accessed. The address bits registered coincident

with the READ or WRITE command are used to select the bank

and the starting column location for the burst access.

The DDR SDRAM provides for programmable READ or WRITE

burst lengths of 2, 4, or 8 locations. An auto precharge function may

be enabled to provide a self-timed row precharge that is initiated

at the end of the burst access.

The pipelined, multibank architecture of DDR SDRAMs allows for

concurrent operation, thereby providing high effective bandwidth

by hiding row precharge and activation time.

An auto refresh mode is provided, along with a power-saving

power-down mode.

FUNCTIONAL DESCRIPTION

Read and write accesses to the DDR SDRAM are burst

oriented; accesses start at a selected location and continue for

a programmed number of locations in a programmed sequence.

Accesses begin with the registration of an ACTIVE command which

is then followed by a READ or WRITE command. The address

bits registered coincident with the ACTIVE command are used to

select the bank and row to be accessed (BA0 and BA1 select the

bank, A0-12 select the row). The address bits registered coincident

with the READ or WRITE command are used to select the starting

column location for the burst access.

Prior to normal operation, the SDRAM must be initialized. The

following sections provide detailed information covering device

initialization, register deﬁ nition, command descriptions and device

operation.

INITIALIZATION

DDR SDRAMs must be powered up and initialized in a predeﬁ ned

manner. Operational procedures other than those speciﬁ ed may

result in undeﬁ ned operation. Power must ﬁ rst be applied to VCC

and VCCQ simultaneously, and then to VREF (and to the system

VTT). VTT must be applied after VCCQ to avoid device latch-up,

which may cause permanent damage to the device. VREF can

be applied any time after VCCQ but is expected to be nominally

coincident with VTT. Except for CKE, inputs are not recognized as

valid until after VREF is applied. CKE is an SSTL_2 input but will

detect an LVCMOS LOW level after VCC is applied. Maintaining

an LVCMOS LOW level on CKE during power-up is required to

ensure that the DQ and DQS outputs will be in the High-Z state,

where they will remain until driven in normal operation (by a read

access). After all power supply and reference voltages are stable,

and the clock is stable, the DDR SDRAM requires a 200μs delay

prior to applying an executable command.

Once the 200μs delay has been satisﬁ ed, a DESELECT or NOP

command should be applied, and CKE should be brought HIGH.

Following the NOP command, a PRECHARGE ALL command

should be applied. Next a LOAD MODE REGISTER command

should be issued for the extended mode register (BA1 LOW and

BA0 HIGH) to enable the DLL, followed by another LOAD MODE

to reset the DLL and to program the operating parameters. Two-

hundred clock cycles are required between the DLL reset and any

READ command. A PRECHARGE ALL command should then be

applied, placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be

performed (tRFC must be satisﬁ ed.) Additionally, a LOAD MODE

bit deactivated (i.e., to program operating parameters without

resetting the DLL) is required. Following these requirements, the

DDR SDRAM is ready for normal operation.

MODE REGISTER

The Mode Register is used to deﬁ ne the speciﬁ c mode of operation

of the DDR SDRAM. This deﬁ nition includes the selection of a

burst length, a burst type, a CAS latency, and an operating mode,

as shown in Figure 3. The Mode Register is programmed via the

MODE REGISTER SET command (with BA0 = 0 and BA1 = 0)

and will retain the stored information until it is programmed again

or the device loses power. (Except for bit A8 which is self clearing).

Reprogramming the mode register will not alter the contents of the

memory, provided it is performed correctly. The Mode Register

must be loaded (reloaded) when all banks are idle and no bursts

are in progress, and the controller must wait the speciﬁ ed time

before initiating the subsequent operation. Violating either of these

requirements will result in unspeciﬁ ed operation.

Mode register bits A0-A2 specify the burst length, A3 speciﬁ es the

type of burst (sequential or interleaved), A4-A6 specify the CAS

latency, and A7-A12 specify the operating mode.

BURST LENGTH

Read and write accesses to the DDR SDRAM are burst oriented,

with the burst length being programmable, as shown in Figure

3. The burst length determines the maximum number of column

locations that can be accessed for a given READ or WRITE

command. Burst lengths of 2, 4 or 8 locations are available for

both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown operation or

incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of columns

equal to the burst length is effectively selected. All accesses for

that burst take place within this block, meaning that the burst will

wrap within the block if a boundary is reached. The block is uniquely

selected by A1-Ai when the burst length is set to two; by A2-Ai

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when the burst length is set to four (where Ai is the most signiﬁ cant

column address for a given conﬁ guration); and by A3-Ai when the

burst length is set to eight. The remaining (least signiﬁ cant) address

bit(s) is (are) used to select the starting location within the block. The

programmed burst length applies to both READ and WRITE bursts.

BURST TYPE

Accesses within a given burst may be programmed to be either

sequential or interleaved; this is referred to as the burst type and

is selected via bit M3.

The ordering of accesses within a burst is determined by the burst

length, the burst type and the starting column address, as shown

in Table 1.

TABLE 1 – BURST DEFINITION

Burst

Length Starting Column

Address Order of Accesses Within a Burst

Type = Sequential Type = In ter leaved

0 0-1 0-1

1 1-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

NOTES:

1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column

within the block.

2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column

within the block.

3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting column

within the block.

4. Whenever a boundary of the block is reached within a given sequence above, the following

access wraps within the block.

READ LATENCY

The READ latency is the delay, in clock cycles, between the

registration of a READ command and the availability of the ﬁ rst bit

of output data. The latency can be set to 2 or 2.5 clocks.

If a READ command is registered at clock edge n, and the latency

is m clocks, the data will be available by clock edge n+m. Table

2 below indicates the operating frequencies at which each CAS

latency setting can be used.

Reserved states should not be used as unknown operation or

incompatibility with future versions may result.

TABLE 2 – CAS LATENCY

SPEED ALLOWABLE OPERATING FREQUENCY (MHz)

CAS LATENCY = 2 CAS LATENCY = 2.5

-200  75  100

-225  100  112.5

-250  100  125

OPERATING MODE

The normal operating mode is selected by issuing a MODE

and bits A0-A6 set to the desired values. A DLL reset is initiated

by issuing a MODE REGISTER SET command with bits A7 and

A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to

the desired values. Although not required, JEDEC speciﬁ cations

recommend when a LOAD MODE REGISTER command is issued

M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

0 0 Valid

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst Length CAS Latency BT

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

M6-M0

M8 M7

Operating Mode

A10 A11

* M14 and M13

(BA0 and BA1 must be

"0, 0" to select

the base mode register

(vs. the extended

mode register).

BA0 BA1

Reserved Reserved

Reserved

M10

M11

1 0

- -

A12

M12

FIGURE 3 – MODE REGISTER DEFINITION

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to reset the DLL, it should always be followed by a LOAD MODE

All other combinations of values for A7-A12 are reserved for future

use and/or test modes. Test modes and reserved states should

not be used because unknown operation or incompatibility with

future versions may result.

EXTENDED MODE REGISTER

The extended mode register controls functions beyond those

controlled by the mode register; these additional functions are DLL

enable/disable, output drive strength, and QFC#. These functions

are controlled via the bits shown in Figure 5. The extended mode

to the mode register (with BA0 = 1 and BA1 = 0) and will retain the

stored information until it is programmed again or the device loses

power. The enabling of the DLL should always be followed by a

LOAD MODE REGISTER command to the mode register (BA0/

BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when all banks are

idle and no bursts are in progress, and the controller must wait the

speciﬁ ed time before initiating any subsequent operation. Violating

either of these requirements could result in unspeciﬁ ed operation.

OUTPUT DRIVE STRENGTH

The normal full drive strength for all outputs are speciﬁ ed to be

SSTL2, Class II. The DDR SDRAM supports an option for reduced

drive. This option is intended for the support of the lighter load and/

or point-to-point environments. The selection of the reduced drive

strength will alter the DQs and DQSs from SSTL2, Class II drive

strength to a reduced drive strength, which is approximately 54

percent of the SSTL2, Class II drive strength.

DLL ENABLE/DISABLE

The DLL must be enabled for normal operation. DLL enable is

required during power-up initialization and upon returning to normal

operation after having disabled the DLL for the purpose of debug

or evaluation. (When the device exits self refresh mode, the DLL

is enabled automatically.) Any time the DLL is enabled, 200 clock

cycles must occur before a READ command can be issued.

COMMANDS

The Truth Table provides a quick reference of available commands.

This is followed by a written description of each command.

DESELECT

The DESELECT function (CS# HiGH) prevents new commands

from being executed by the DDR SDRAM. The SDRAM is

effectively deselected. Operations already in progress are not

affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a

NOP to the selected DDR SDRAM (CS# is LOW). This prevents

unwanted commands from being registered during idle or wait

states. Operations already in progress are not affected.

LOAD MODE REGISTER

The Mode Registers are loaded via inputs A0-12. The LOAD MODE

and a subsequent executable command cannot be issued until

tMRD is met.

FIGURE 4 – CAS LATENCY

COMMAND READ NOP NOP NOP

CL = 2.5

DON'T CARE

TRANSITIONING DATA

DQS

T0 T1 T2 T2n T3 T3n

COMMAND READ NOP NOP NOP

CL = 2

DQS

CLK

CLK#

T0 T1 T2 T2n T3 T3n

Burst Length = 4 in the cases shown

Shown with nominal tAC and nominal tDSDQ

DATA

CLK

CLK#

FIGURE 5 – EXTENDED MODE REGISTER

DEFINITION

DLL

Enable

Disable

DLL DS

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Extended Mode

Address Bus

Operating Mode

A10

A11

BA0

BA1

QFC#

Drive Strength

Normal

Reduced

QFC# Function

Disabled

Reserved

E22

Operating Mode

Reserved

E2, E1, E0

Valid

E12

E10

A12

E11

1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)

2. The QFE# function is not supported.

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ACTIVE

The ACTIVE command is used to open (or activate) a row in a

particular bank for a subsequent access. The value on the BA0, BA1

inputs selects the bank, and the address provided on inputs A0-12

selects the row. This row remains active (or open) for accesses until

a PRECHARGE command is issued to that bank. A PRECHARGE

command must be issued before opening a different row in the

same bank.

READ

The READ command is used to initiate a burst read access to an

active row. The value on the BA0, BA1 inputs selects the bank, and

the address provided on inputs A0-8 selects the starting column

location. The value on input A10 determines whether or not AUTO

PRECHARGE is used. If AUTO PRECHARGE is selected, the row

being accessed will be precharged at the end of the READ burst;

if AUTO PRECHARGE is not selected, the row will remain open

for subsequent accesses.

WRITE

The WRITE command is used to initiate a burst write access to an

active row. The value on the BA0, BA1 inputs selects the bank, and

the address provided on inputs A0-8 selects the starting column

location. The value on input A10 determines whether or not AUTO

PRECHARGE is used. If AUTO PRECHARGE is selected, the row

being accessed will be precharged at the end of the WRITE burst;

if AUTO PRECHARGE is not selected, the row will remain open for

subsequent accesses. Input data appearing on the D/Qs is written to

the memory array subject to the DQM input logic level appearing

coincident with the data. If a given DQM signal is registered LOW,

the corresponding data will be written to memory; if the DQM signal

is registered HIGH, the corresponding data inputs will be ignored,

and a WRITE will not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the open row

in a particular bank or the open row in all banks. The bank(s) will

be available for a subsequent row access a speciﬁ ed time (tRP)

after the PRECHARGE command is issued. Except in the case of

concurrent auto precharge, where a READ or WRITE command to

a different bank is allowed as long as it does not interrupt the data

transfer in the current bank and does not violate any other timing

parameters. Input A10 determines whether one or all banks are

to be precharged, and in the case where only one bank is to be

precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1

are treated as “Don’t Care.” Once a bank has been precharged,

it is in the idle state and must be activated prior to any READ or

WRITE commands being issued to that bank. A PRECHARGE

command will be treated as a NOP if there is no open row in that

bank (idle state), or if the previously open row is already in the

process of precharging.

NOTES:

1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-12 deﬁ ne the op-code to be written to the selected Mode Register. BA0, BA1 select either the

mode register (0, 0) or the extended mode register (1, 0).

3. A0-12 provide row address, and BA0, BA1 provide bank address.

4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (non persistent),

while A10 LOW disables the auto precharge feature; BA0, BA1 provide bank address.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and

BA0, BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for

CKE.

8. Applies only to read bursts with auto precharge disabled; this command is undeﬁ ned (and

should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.

9. DESELECT and NOP are functionally interchangeable.

10. Used to mask write data; provided coincident with the corresponding data.

INPUTS OUTPUT

RESET# RCK RCK# INPUT

H HH

H LL

H L or H L or H X Q0

L X, or ﬂ oating X, or ﬂ oating X, or ﬂ oating L

TRUTH TABLE – COMMANDS (NOTE 1)

NAME (FUNCTION) CS# RAS# CAS# WE# ADDR

DESELECT (NOP) (9) H X X X X

NO OPERATION (NOP) (9) L H H H X

ACTIVE (Select bank and activate row) (3) L L H H Bank/Row

READ (Select bank and column, and start READ burst) (4) L H L H Bank/Col

WRITE (Select bank and column, and start WRITE burst) (4) L H L L Bank/Col

BURST TERMINATE (8) L H H L X

PRECHARGE (Deactivate row in bank or banks) ( 5) L L H L Code

AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7) L L L H X

LOAD MODE REGISTER (2) L L L L Op-Code

TRUTH TABLE – DM OPERATION

NAME (FUNCTION) DM DQs

WRITE ENABLE (10) L Valid

WRITE INHIBIT (10) H X

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AUTO PRECHARGE

AUTO PRECHARGE is a feature which performs the same

individual-bank PRECHARGE function described above, but without

requiring an explicit command. This is accomplished by using

A10 to enable AUTO PRECHARGE in conjunction with a speciﬁ c

READ or WRITE command. A precharge of the bank/row that is

addressed with the READ or WRITE command is automatically

performed upon completion of the READ or WRITE burst. AUTO

PRECHARGE is nonpersistent in that it is either enabled or

disabled for each individual READ or WRITE command. The

device supports concurrent auto precharge if the command to the

other bank does not interrupt the data transfer to the current bank.

AUTO PRECHARGE ensures that the precharge is initiated at the

earliest valid stage within a burst. This “earliest valid stage” is

determined as if an explicit precharge command was issued at

the earliest possible time, without violating tRAS (MIN).The user

must not issue another command to the same bank until the

precharge time (tRP) is completed. This is determined as if an

explicit PRECHARGE command was issued at the earliest possible

time, without violating tRAS (MIN).

BURST TERMINATE

The BURST TERMINATE command is used to truncate READ

bursts (with auto precharge disabled). The most recently registered

READ command prior to the BURST TERMINATE command will be

truncated. The open page which the READ burst was terminated

from remains open.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the

DDR SDRAM and is analogous to CAS#-BEFORE-RAS#

(CBR) REFRESH in conventional DRAMs. This command is

nonpersistent, so it must be issued each time a refresh is required.

The addressing is generated by the internal refresh controller. This

makes the address bits “Don’t Care” during an AUTO REFRESH

command. Each DDR SDRAM requires AUTO REFRESH cycles

at an average interval of 7.8125s (maximum).

To allow for improved efﬁ ciency in scheduling and switching

between tasks, some ﬂ exibility in the absolute refresh interval is

provided. A maximum of eight AUTO REFRESH commands can

be posted to any given DDR SDRAM, meaning that the maximum

absolute interval between any AUTO REFRESH command and

the next AUTO REFRESH command is 9 x 7.8125s (70.3s).

This maximum absolute interval is to allow future support for DLL

updates internal to the DDR SDRAM to be restricted to AUTO

REFRESH cycles, without allowing excessive drift in tAC between

updates.

Although not a JEDEC requirement, to provide for future functionality

features, CKE must be active (High) during the AUTO REFRESH

period. The AUTO REFRESH period begins when the AUTO

REFRESH command is registered and ends tRFC later.

SELF REFRESH*

The SELF REFRESH command can be used to retain data in the

DDR SDRAM, even if the rest of the system is powered down. When

in the self refresh mode, the DDR SDRAM retains data without

external clocking. The SELF REFRESH command is initiated like

an AUTO REFRESH command except CKE is disabled (LOW). The

DLL is automatically disabled upon entering SELF REFRESH and

is automatically enabled upon exiting SELF REFRESH (200 clock

cycles must then occur before a READ command can be issued).

Input signals except CKE are “Don’t Care” during SELF REFRESH.

The procedure for exiting self refresh requires a sequence of

commands. First, CK must be stable prior to CKE going back HIGH.

Once CKE is HIGH, the DDR SDRAM must have NOP commands

issued for tXSNR, because time is required for the completion of

any internal refresh in progress.

A simple algorithm for meeting both refresh and DLL requirements

is to apply NOPs for 200 clock cycles before applying any other

command.

* Self refresh available in commercial and industrial temperatures only.

W3E16M72SR-XBX

Rev. 3 www.microsemi.com

Microsemi Corporation reserves the right to change products or speciﬁ cations without notice.

ABSOLUTE MAXIMUM RATINGS

Parameter Unit

Voltage on VCC, VCCQ Supply relative to Vss -1 to 3.6 V

Voltage on I/O pins relative to VSS -1 to 3.6 V

Operating Temperature TA (Mil) -55 to +125 °C

Operating Temperature TA (Ind) -40 to +85 °C

Storage Temperature, Plastic -55 to +125 °C

NOTE: Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other

conditions greater than those indicated in the operational sections of this speciﬁ cation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

CAPACITANCE (NOTE 13)

Parameter Symbol Max Unit

Input Capacitance: CK/CK# CI1 8 pF

Addresses, BA0-1 Input Capacitance CA10 pF

Input Capacitance: All other input-only pins CI2 9 pF

Input/Output Capacitance: I/Os CIO 10 pF

BGA THERMAL RESISTANCE

Description Symbol Max Units Notes

Junction to Ambient (No Airﬂ ow) Theta JA 14.2 °C/W 1

Junction to Ball Theta JB 10.8 °C/W 1

Junction to Case (Top) Theta JC 4.1 °C/W 1

Note 1: Refer to AN #0001 at www.whiteedc.com in the application notes section for modeling conditions.

Parameter/Condition Min Max Unit

VIH AC high-level input voltage Data inputs VREF+310mV V

VIL AC low-level input voltage Data inputs VREF-310mV V

VIH High-level input voltage RESET# 1.7 V

VIL Low-level input voltage RESET# 0.7 V

Note: The RESET# input of the device must be held at a valid logic level (not ﬂ oating) to ensure proper device operation.

Parameter Test Conditions VCC and VCCQ Min Typ Max Unit

IIAll inputs VI = VCC or GND 2.7V -5 +5 μA

ICC

Static standby RESET# = GND 2.7V 10 μA

Static operating RESET# = VCC, VI = VIH(AC) or VIL(AC) IO = 0 112 mA

ICCD

Dynamic operating – clock

only

RESET# = VCC, VI = VIH(AC) or VIL(AC), CK and CK# switching 50% duty

cycle

IO = 0 2.5V

56 μA/ MHz

Dynamic operating – per each

data input

RESET# = VCC, VI = VIH(AC) or VIL(AC). CK and CK#

switching 50% duty cycle. All data input switching at one-half clock

frequency, 50% duty cycle

180 μA/clock

MHz

Note: All typical values are at VCC = 2.5V, TA = 25°C.

W3E16M72SR-XBX

Rev. 3 www.microsemi.com

Microsemi Corporation reserves the right to change products or speciﬁ cations without notice.

DDR DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1, 6)

VCC = +2.5V ± 0.2V; -55°C  TA +125°C

Parameter/Condition Symbol Min Max Units

Supply Voltage VCC 2.3 2.7 V

I/O Supply Voltage VCCQ 2.3 2.7 V

Input Hight Voltage: Logic 1; All inputs (21) VIH VREF + 0.15 VCC + 0.3 V

Input Low Voltage: Logic 0; All inputs (21) VIL -0.4 VREF - 0.15 V

Input Leakage Current: Any input 0V ≤ VIN ≤ VCC (All other pins not under test = 0V) II -2 2 μA

Output Leakage Current: I/Os are disabled; 0V ≤ VOUT ≤ VCC I

OZ -5 5 μA

Output Levels: Full drive option - x16

High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT)

Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)

IOH -16.8 – mA

IOL 16.8 – mA

Output Levels: Reduced drive option - 16 only

High Current (VOUT = VCCQ - 0.763V, minimum VREF, minimum VTT)

Low Current (VOUT = 0.763V, maximum VREF, maximum VTT)

IOHR -9 – mA

IOLR 9–mA

I/O Reference Voltage VREF 0.49 x VCCQ 0.51 x VCCQ V

I/O Termination Voltage VTT VREF - 0.04 VREF + 0.04 V

DDR ICC SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14, 54)

VCC = +2.5V ± 0.2V; -55°C  TA +125°C

Parameter/Condition Symbol

Max

250Mbps

266Mbps 200Mbps Units

OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cyle; Address

and control inputs changing once every two clock cycles; (22, 48) ICC0 625 600 mA

OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing

once per clock cycle (22, 48) ICC1 850 775 mA

PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW; (23, 32, 50) ICC2P 20 20 mA

IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle.

VIN = VREF for DQ, DQS, and DM (51) ICC2F 225 225 mA

ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW (23, 32, 50) ICC3P 150 150 mA

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs

changing twice per clock cycle; Address and other control inputs changing once per clock cycle (22) ICC3N 250 250 mA

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK

(MIN); IOUT = 0mA (22, 48) ICC4R 925 925 mA

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK

(MIN); DQ, DM, and DQS inputs changing twice per clock cycle (22) ICC4W 800 800 mA

AUTO REFRESH CURRENT tREF = tRC (MIN) (27, 50) ICC5 1225 1225 mA

tREF = 7.8125μs (27, 50) ICC5A 30 30 mA

SELF REFRESH CURRENT: CKE ≤ 0.2V Standard (11) ICC6 20 20 mA

OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, tRC =tRC (MIN); tCK = tCK (MIN); Address and control inputs change

only during Active READ or WRITE commands. (22, 49) ICC7 2000 2000 mA

W3E16M72SR-XBX

Rev. 3 www.microsemi.com

Microsemi Corporation reserves the right to change products or speciﬁ cations without notice.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS

(NOTES 1-5, 14-17, 33)

Parameter Symbol

266Mbps CL2.5

200Mbps CL2 250Mbps CL2.5

200Mbps CL2 200Mbps CL2.5

150Mbps CL2

UnitsMin Max Min Max Min Max

Access window of DQs from CLK/CLK# tAC -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns

CLK high-level width (30) tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK

CLK low-level width (30) tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK

Clock cycle time

CL = 2.5 (45, 52) tCK (2.5) 8 13 9 13 10 13 ns

CL = 2 (45, 52) tCK (2) 10 13 10 13 13 15 ns

DQ and DM input hold time relative to DQS (26, 31) tDH 0.5 0.5 0.5 ns

DQ and DM input setup time relative to DQS (26, 31) tDS 0.5 0.5 0.5 ns

DQ and DM input pulse width (for each input) (31) tDIPW 1.75 1.75 1.75 ns

Access window of DQS from CLK/CLK# tDQSCK -0.75 +0.75 -0.8 +0.8 -0.8 +0.8 ns

DQS input high pulse width tDQSH 0.35 0.35 0.35 tCK

DQS input low pulse width tDQSL 0.35 0.35 0.35 tCK

DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26) tDQSQ 0.5 0.5 0.5 ns

Write command to ﬁ rst DQS latching transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK

DQS falling edge to CLK rising - setup time tDSS 0.2 0.2 0.2 tCK

DQS falling edge from CLK rising - hold time tDSH 0.2 0.2 0.2 tCK

Half clock period (34) tHP tCH, tCL tCH, tCL tCH, tCL ns

Data-out high-impedance window from CLK/CLK# (18, 42) tHZ +0.75 +0.75 +0.75 ns

Data-out low-impedance window from CLK/CLK# (18, 43) tLZ -0.75 -0.75 -0.75 ns

Address and control input hold time (fast slew rate) (14) tIHF0.90 0.90 0.90 ns

Address and control input setup time (fast slew rate) (14) tISF0.90 0.90 0.90 ns

Address and control input hold time (slow slew rate) (14) tIHS 111ns

Address and control input setup time (slow slew rate) (14) tISS1 1 1 ns

LOAD MODE REGISTER command cycle time tMRD 15 15 15 ns

DQ-DQS hold, DQS to ﬁ rst DQ to go non-valid, per access (25, 26) tQH tHP - tQHS tHP - tQHS tHP - tQHS ns

Data hold skew factor tQHS 0.75 0.75 0.75 ns

ACTIVE to PRECHARGE command (35) tRAS 40 120,000 40 120,000 40 120,000 ns

ACTIVE to READ with Auto precharge command tRAP 20 20 20 ns

ACTIVE to ACTIVE/AUTO REFRESH command period tRC 65 65 65 ns

AUTO REFRESH command period (50) tRFC 75 75 75 ns

ACTIVE to READ or WRITE delay tRCD 20 20 20 ns

PRECHARGE command period tRP 20 20 20 ns

DQS read preamble (42) tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK

DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

ACTIVE bank a to ACTIVE bank b command tRRD 15 15 15 ns

DQS write preamble tWPRE 0.25 0.25 0.25 tCK

DQS write preamble setup time (20, 21) tWPRES 0 0 0 ns

DQS write postamble (19) tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

Write recovery time tWR 15 15 15 ns

Internal WRITE to READ command delay tWTR 111t

Data valid output window (25) na tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ ns

REFRESH to REFRESH command interval (23) tREFC 70.3 70.3 70.3 μs

Average periodic refresh interval (23) tREFI 7.8 7.8 7.8 μs

Terminating voltage delay to VCC (53) tVTD 000ns

Exit SELF REFRESH to non-READ command tXSNR 75 80 80 ns

Exit SELF REFRESH to READ command tXSRD 200 200 200 tCK

W3E16M72SR-XBX

Rev. 3 www.microsemi.com

Microsemi Corporation reserves the right to change products or speciﬁ cations without notice.

NOTES:

1. All voltages referenced to VSS.

2. Tests for AC timing, ICC, and electrical AC and DC characteristics may be conducted at

nominal reference/supply voltage levels, but the related speciﬁ cations and device operation are

guaranteed for the full voltage range speciﬁ ed.

3. Outputs measured with equivalent load:

50Ω

Reference

Point

30pF

Output

OUT

)

4. AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but

input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter

speciﬁ cations are guaranteed for the speciﬁ ed AC input levels under normal use conditions. The

minimum slew rate for the input signals used to test the device is 1V/ns in the range between

VIL(AC) and VIH(AC).

5. The AC and DC input level speciﬁ cations are as deﬁ ned in the SSTL_2 Standard (i.e., the

receiver will effectively switch as a result of the signal crossing the AC input level, and will

remain in that state as long as the signal does not ring back above [below] the DC input LOW

[HIGH] level).

6. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC

level of the same. Peak-to-peak noise (noncommon mode) on VREF may not exceed ±2 percent

of the DC value. Thus, from VCCQ/2, VREF is allowed ±25mV for DC error and an additional

±25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor.

7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is

expected to be set equal to VREF and must track variations in the DC level of VREF.

8. VID is the magnitude of the difference between the input level on CK and the input level on CK#.

9. The value of VIX and VMP are expected to equal VCCQ/2 of the transmitting device and must track

variations in the DC level of the same.

10. ICC is dependent on output loading and cycle rates. Speciﬁ ed values are obtained with minimum

cycle time with the outputs open.

11. Enables on-chip refresh and address counters.

12. ICC speciﬁ cations are tested after the device is properly initialized, and is averaged at the deﬁ ned

cycle rate.

13. This parameter is not tested but guaranteed by design. tA = 25°C, F = 1 MHz

14. Command/Address input slew rate = 0.5V/ns. For 266 MHz with slew rates 1V/ns and faster,

tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated:

tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH

has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is

uncertain.

15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK#

cross; the input reference level for signals other than CK/CK# is VREF.

16. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF

stabilizes, CKE  0.3 x VCCQ is recognized as LOW.

17. The output timing reference level, as measured at the timing reference point indicated in Note 3,

is VTT.

18. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These

parameters are not referenced to a speciﬁ c voltage level, but specify when the device output is

no longer driving (HZ) or begins driving (LZ).

19. The maximum limit for this parameter is not a device limit. The device will operate with a greater

value for this parameter, but system performance (bus turnaround) will degrade accordingly.

20. This is not a device limit. The device will operate with a negative value, but system performance

could be degraded due to bus turnaround.

21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The

case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in

progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time,

depending on tDQSS.

22. MIN (tRC or tRFC) for ICC measurements is the smallest multiple of tCK that meets the minimum

absolute value for the respective parameter. tRAS (MAX) for ICC measurements is the largest

multiple of tCK that meets the maximum absolute value for tRAS.

23. The refresh period 64ms. This equates to an average refresh rate of 7.8125μs. However, an

AUTO REFRESH command must be asserted at least once every 70.3μs; burst refreshing or

posting by the DRAM controller greater than eight refresh cycles is not allowed.

24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum

amount for any given device.

25. The valid data window is derived by achieving other speciﬁ cations - tHP (tCK/2), tDQSQ, and tQH (tQH = tHP

- tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data

valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is

uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below

for duty cycles ranging between 50/50 and 45/55.

26. Referenced to each output group: DQS0 with DQ0-DQ7; and DQS1 with DQ8-DQ15 of each chip.

27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command

period (tRFC [MIN]) else CKE is LOW (i.e., during standby).

28. To maintain a valid level, the transitioning edge of the input must:

a) Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC)

or VIH(AC).

b) Reach at least the target AC level.

c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC)

or VIH(DC).

29. The Input capacitance per pin group will not differ by more than this maximum amount for any

given device.

30. CK and CK# input slew rate must be  1V/ns (2V/ns differentially).

31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS

slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for

each 100mV/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain.

32. VCC must not vary more than 4% if CKE is not active while any bank is active.

33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same

amount.

34. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK#

inputs, collectively during bank active.

FIGURE A – PULL-DOWN CHARACTERISTICS FIGURE B – PULL-UP CHARACTERISTICS

-20

-40

-60

-80

-100

-120

-140

-160

-180

-200

0.0 0.5 1.0 1.5 2.0 2.5

VCCQ - VOUT (V)

IOUT (mA)

Maximum

Nominal high

Nominal low

Minimum

160

140

120

100

0.0 0.5 1.0 1.5 2.0 2.5

VOUT (V)

IOUT (mA)

Maximum

Nominal high

Nominal low

Minimum

W3E16M72SR-XBX

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Microsemi Corporation reserves the right to change products or speciﬁ cations without notice.

35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be

satisﬁ ed prior to the internal precharge command being issued.

36. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9 volts,

whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed

either -300mV or 2.2 volts, whichever is more positive.

37. Normal Output Drive Curves:

a) The full variation in driver pull-down current from minimum to maximum process, temperature

and voltage will lie within the outer bounding lines of the V-I curve of Figure A.

b) The variation in driver pull-down current within nominal limits of voltage and temperature is

expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure

c) The full variation in driver pull-up current from minimum to maximum process, temperature

and voltage will lie within the outer bounding lines of the V-I curve of Figure B.

d) The variation in driver pull-up current within nominal limits of voltage and temperature is

expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure

e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current

should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 Volt, and

at the same voltage and temperature.

f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%,

for device drain-to-source voltages from 0.1V to 1.0 Volt.

38. Reduced Output Drive Curves:

a) The full variation in driver pull-down current from minimum to maximum process, temperature

and voltage will lie within the outer bounding lines of the V-I curve of Figure C.

b) The variation in driver pull-down current within nominal limits of voltage and temperature is

expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure

c) The full variation in driver pull-up current from minimum to maximum process, temperature

and voltage will lie within the outer bounding lines of the V-I curve of Figure D.

d) The variation in driver pull-up current within nominal limits of voltage and temperature is

expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure

e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current

should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 V, and at

the same voltage and temperature.

f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%,

for device drain-to-source voltages from 0.1V to 1.0 V.

39. The voltage levels used are derived from a minimum VCC level and the referenced test load.

In practice, the voltage levels obtained from a properly terminated bus will provide signiﬁ cantly

different voltage values.

40. VIH overshoot: VIH(MAX) = VCCQ+1.5V for a pulse width  3ns and the pulse width can not be

greater than 1/3 of the cycle rate.

41. VCC and VCCQ must track each other.

42. This maximum value is derived from the referenced test load. In practice, the values obtained in a

typical terminated design may reﬂ ect up to 310ps less for tHZ(MAX) and the last DVW. tHZ(MAX)

will prevail over tDQSCK(MAX) + tRPST(MAX) condition. tLZ(MIN) will prevail over tDQSCK(MIN) +

tRPRE(MAX) condition.

43. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier.

44. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V. Alternatively,

VTT may be 1.35V maximum during power up, even if VCC/VCCQ are 0 volts, provided a minimum

of 42 ohms of series resistance is used between the VTT supply and the input pin.

45. The current part operates below the slowest JEDEC operating frequency of 83 MHz. As such,

future die may not reﬂ ect this option.

46. Reserved for future use.

47. Reserved for future use.

48. Random addressing changing 50% of data changing at every transfer.

49. Random addressing changing 100% of data changing at every transfer.

50. CKE must be active (high) during the entire time a refresh command is executed. That is, from

the time the AUTO REFRESH command is registered, CKE must be active at each rising clock

edge, until tRFC has been satisﬁ ed.

51. ICC2N speciﬁ es the DQ, DQS, and DM to be driven to a valid high or low logic level. ICC2Q is

similar to ICC2F except ICC2Q speciﬁ es the address and control inputs to remain stable. Although

ICC2F, ICC2N, and ICC2Q are similar, ICC2F is “worst case.”

52. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset.

This is followed by 200 clock cycles before any READ command.

53. All AC timings do not count extra clock needed on address and control signals to be registered.

54. DDR currents only. Register currents not included.

FIGURE C – PULL-DOWN CHARACTERISTICS FIGURE D – PULL-UP CHARACTERISTICS

0.0 0.5 1.0 1.5 2.0 2.5

VCCQ - VOUT (V)

IOUT (mA)

Maximum

Nominal high

Nominal low

Minimum

-10

-20

-30

-40

-50

-60

-70

-80

0.0 0.5 1.0 1.5 2.0 2.5

VOUT (V)

IOUT (mA)

Maximum

Nominal high

Nominal low

Minimum

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32.1 (1.264) MAX

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

25.1 (0.988)

MAX

0.61 (0.024) NOM

2.03 (0.080) MAX

19.05 (0.750) NOM

1.27 (0.050)

NOM

19.05 (0.750)

NOM

219 X Ø 0.762 (0.030) NOM

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

Bottom View

PACKAGE DIMENSION: 219 PLASTIC BALL GRID ARRAY (PBGA)

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ORDERING INFORMATION

MICROSEMI CORPORATION

PLASTIC DDR SDRAM

CONFIGURATION, 16M x 72

2.5V POWER SUPPLY

REGISTERED

FREQUENCY (MHz)

200 = 200MHz

225 = 225MHz

250 = 250MHz

PACKAGE:

B = 219 Plastic Ball Grid Array (PBGA)

DEVICE GRADE:

M = Military -55°C to +125°C

I = Industrial -40°C to +85°C

C = Commercial 0°C to +70°C

W 3E 16M 72 S R - XXX B X

W3E16M72SR-XBX

Rev. 3 www.microsemi.com

Microsemi Corporation reserves the right to change products or speciﬁ cations without notice.

Document Title

16M x 72 Registered DDR SDRAM Multi-Chip Package

Revision History

Rev # History Release Date Status

Rev 0 Initial Release August 2003 Advanced

Rev 1 Changes (Pg. 1, 15, 16)

1.1 Change mechanical drawing to new style

November 2003 Advanced

Rev 2 Changes (Pg. 1, 10, 11, 16)

2.1 Change status to Final

2.2 Update ICC speciﬁ cations table values

2.3 Change max storage temperature to 125°C

2.4 Delete VIH/VIL DC low-level input voltage operating condition speciﬁ cation.

2.5 Update capacitance table values

February 2005 Final

Rev 3 Changes (Pg. 1-16)

3.1 Change document layout from White Electronic Designs to Microsemi

July 2011 Final