LF147, LF347-N
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SNOSBH1D –MAY 1999–REVISED MARCH 2013
LF147/LF347 Wide Bandwidth Quad JFET Input Operational Amplifiers
Check for Samples: LF147,LF347-N
1FEATURES DESCRIPTION
The LF147 is a low cost, high speed quad JFET input
23• Internally Trimmed Offset Voltage: 5 mV max operational amplifier with an internally trimmed input
• Low Input Bias Current: 50 pA offset voltage ( BI-FET II™ technology). The device
• Low Input Noise Current: 0.01 pA/√Hz requires a low supply current and yet maintains a
large gain bandwidth product and a fast slew rate. In
• Wide Gain Bandwidth: 4 MHz addition, well matched high voltage JFET input
• High Slew Rate: 13 V/μsdevices provide very low input bias and offset
• Low Supply Current: 7.2 mA currents. The LF147 is pin compatible with the
standard LM148. This feature allows designers to
• High Input Impedance: 1012Ωimmediately upgrade the overall performance of
• Low Total Harmonic Distortion: ≤0.02% existing LF148 and LM124 designs.
• Low 1/f Noise Corner: 50 Hz The LF147 may be used in applications such as high
• Fast Settling Time to 0.01%: 2 μsspeed integrators, fast D/A converters, sample-and-
hold circuits and many other circuits requiring low
input offset voltage, low input bias current, high input
impedance, high slew rate and wide bandwidth. The
device has low noise and offset voltage drift.
Simplified Schematic Connection Diagram
¼ Quad
LF147 available as per JM38510/11906.
Figure 1. 14-Pin PDIP / CDIP / SOIC
Top View
See Package Number J0014A, D0014A or
NFF0014A
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2BI-FET II is a trademark of dcl_owner.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LF147, LF347-N
SNOSBH1D –MAY 1999–REVISED MARCH 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Absolute Maximum Ratings (1)(2)
LF147 LF347B/LF347
Supply Voltage ±22V ±18V
Differential Input Voltage ±38V ±30V
Input Voltage Range (3) ±19V ±15V
Output Short Circuit Duration (4) Continuous Continuous
Power Dissipation (5) (6) 900 mW 1000 mW
Tjmax 150°C 150°C
θjA CDIP (J) Package 70°C/W
PDIP (NFF) Package 75°C/W
SOIC Narrow (D) 100°C/W
SOIC Wide (D) 85°C/W
Operating Temperature Range See (7) See (7)
Storage Temperature Range −65°C≤TA≤150°C
Lead Temperature (Soldering, 10 sec.) 260°C 260°C
Soldering Information PDIP / CDIP Soldering (10 seconds) 260°C
SOIC Package Vapor Phase (60 seconds) 215°C
Infrared (15 seconds) 220°C
ESD Tolerance (8) 900V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
(4) Any of the amplifier outputs can be shorted to ground indefinitely, however, more than one should not be simultaneously shorted as the
maximum junction temperature will be exceeded.
(5) For operating at elevated temperature, these devices must be derated based on a thermal resistance of θjA.
(6) Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the
part to operate outside ensured limits.
(7) The LF147 is available in the military temperature range −55°C≤TA≤125°C, while the LF347B and the LF347 are available in the
commercial temperature range 0°C≤TA≤70°C. Junction temperature can rise to Tjmax = 150°C.
(8) Human body model, 1.5 kΩin series with 100 pF.
DC Electrical Characteristics (1)(2)
Symbol Parameter Conditions LF147 LF347B LF347 Units
Min Typ Max Min Typ Max Min Typ Max
VOS Input Offset Voltage RS=10 kΩ, TA=25°C 1 5 3 5 5 10 mV
Over Temperature 8 7 13 mV
ΔVOS/ΔAverage TC of Input RS=10 kΩ10 10 10 μV/°C
T Offset Voltage
IOS Input Offset Current Tj=25°C, (2) (3) 25 100 25 100 25 100 pA
Over Temperature 25 4 4 nA
IBInput Bias Current Tj=25°C, (2) (3) 50 200 50 200 50 200 pA
Over Temperature 50 8 8 nA
RIN Input Resistance Tj=25°C 1012 1012 1012 Ω
(1) Refer to RETS147X for LF147D and LF147J military specifications.
(2) Unless otherwise specified the specifications apply over the full temperature range and for VS=±20V for the LF147 and for VS=±15V for
the LF347B/LF347. VOS, IB, and IOS are measured at VCM=0.
(3) The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature,
Tj. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the
junction temperature rises above the ambient temperature as a result of internal power dissipation, PD. Tj=TA+θjA PDwhere θjA is the
thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum.
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DC Electrical Characteristics (1)(2) (continued)
Symbol Parameter Conditions LF147 LF347B LF347 Units
Min Typ Max Min Typ Max Min Typ Max
AVOL Large Signal Voltage Gain VS=±15V, TA=25°C 50 100 50 100 25 100 V/mV
VO=±10V, RL=2 kΩ
Over Temperature 25 25 15 V/mV
VOOutput Voltage Swing VS=±15V, RL=10 kΩ±12 ±13. ±12 ±13. ±12 ±13. V
555
VCM Input Common-Mode ±11 +15 ±11 +15 ±11 +15 V
VS=±15V
Voltage Range −12 −12 −12 V
CMRR Common-Mode Rejection RS≤10 kΩ80 100 80 100 70 100 dB
Ratio
PSRR Supply Voltage Rejection See (4) 80 100 80 100 70 100 dB
Ratio
ISSupply Current 7.2 11 7.2 11 7.2 11 mA
(4) Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with
common practice from VS= ± 5V to ±15V for the LF347 and LF347B and from VS= ±20V to ±5V for the LF147.
AC Electrical Characteristics (1)(2)
Symbol Parameter Conditions LF147 LF347B LF347 Units
Min Typ Max Min Typ Max Min Typ Max
Amplifier to Amplifier TA=25°C, −120 −120 −120 dB
Coupling f=1 Hz−20 kHz
(Input Referred)
SR Slew Rate VS=±15V, TA=25°C 8 13 8 13 8 13 V/μs
GBW Gain-Bandwidth Product VS=±15V, TA=25°C 2.2 4 2.2 4 2.2 4 MHz
enEquivalent Input Noise TA=25°C, RS=100Ω, 20 20 20 nV / √Hz
Voltage f=1000 Hz
inEquivalent Input Noise Tj=25°C, f=1000 Hz 0.01 0.01 0.01 pA / √Hz
Current
THD Total Harmonic Distortion AV=+10, RL=10k, <0.0 <0.0 <0.0 %
2 2 2
VO=20 Vp-p,
BW=20 Hz−20 kHz
(1) Unless otherwise specified the specifications apply over the full temperature range and for VS=±20V for the LF147 and for VS=±15V for
the LF347B/LF347. VOS, IB, and IOS are measured at VCM=0.
(2) Refer to RETS147X for LF147D and LF147J military specifications.
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Typical Performance Characteristics
Input Bias Current Input Bias Current
Figure 2. Figure 3.
Positive Common-Mode
Supply Current Input Voltage Limit
Figure 4. Figure 5.
Negative Common-Mode
Input Voltage Limit Positive Current Limit
Figure 6. Figure 7.
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Typical Performance Characteristics (continued)
Negative Current Limit Output Voltage Swing
Figure 8. Figure 9.
Output Voltage Swing Gain Bandwidth
Figure 10. Figure 11.
Bode Plot Slew Rate
Figure 12. Figure 13.
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Typical Performance Characteristics (continued)
Distortion
vs Undistorted Output Voltage
Frequency Swing
Figure 14. Figure 15.
Open Loop Frequency Common-Mode Rejection
Response Ratio
Figure 16. Figure 17.
Power Supply Rejection Equivalent Input Noise
Ratio Voltage
Figure 18. Figure 19.
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Typical Performance Characteristics (continued)
Open Loop Voltage Gain Output Impedance
Figure 20. Figure 21.
Inverter Settling Time
Figure 22.
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Pulse Response
RL=2 kΩ, CL=10 pF
Small Signal Inverting Large Signal Inverting
Small Signal Non-Inverting Large Signal Non-Inverting
Current Limit (RL=100Ω)
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APPLICATION HINTS
The LF147 is an op amp with an internally trimmed input offset voltage and JFET input devices (BI-FET II).
These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for
clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large
increase in input current. The maximum differential input voltage is independent of the supply voltages. However,
neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to
flow which can result in a destroyed unit.
Exceeding the negative common-mode limit on either input will force the output to a high state, potentially
causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force
the amplifier output to a high state. In neither case does a latch occur since raising the input back within the
common-mode range again puts the input stage and thus the amplifier in a normal operating mode.
Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if
both inputs exceed the limit, the output of the amplifier will be forced to a high state.
The amplifiers will operate with a common-mode input voltage equal to the positive supply; however, the gain
bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings
to within 3V of the negative supply, an increase in input offset voltage may occur.
Each amplifier is individually biased by a zener reference which allows normal circuit operation on ±4.5V power
supplies. Supply voltages less than these may result in lower gain bandwidth and slew rate.
The LF147 will drive a 2 kΩload resistance to ±10V over the full temperature range. If the amplifier is forced to
drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing
and finally reach an active current limit on both positive and negative swings.
Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in
polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through
the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed
unit.
As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in
order to ensure stability. For example, resistors from the output to an input should be placed with the body close
to the input to minimize “pick-up” and maximize the frequency of the feedback pole by minimizing the
capacitance from the input to ground.
A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and
capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole.
In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed
loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less
than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the
input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor
and the resistance it parallels is greater than or equal to the original feedback pole time constant.
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Typical Applications
Figure 23. Digitally Selectable Precision Attenuator
All resistors 1% tolerance
• Accuracy of better than 0.4% with standard 1% value resistors
No offset adjustment necessary
• Expandable to any number of stages
• Very high input impedance
A1 A2 A3 VO
Attenuation
0 0 0 0
001 −1 dB
010 −2 dB
011 −3 dB
100 −4 dB
101 −5 dB
110 −6 dB
111 −7 dB
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Figure 24. Long Time Integrator with Reset, Hold and Starting Threshold Adjustment
• VOUT starts from zero and is equal to the integral of the input voltage with respect to the threshold voltage:
• Output starts when VIN≥VTH
• Switch S1 permits stopping and holding any output value
• Switch S2 resets system to zero
Figure 25. Universal State Variable Filter
For circuit shown:
fo=3 kHz, fNOTCH=9.5 kHz
Q=3.4
Passband gain:
Highpass—0.1
Bandpass—1
Lowpass—1
Notch—10
• fo×Q≤200 kHz
• 10V peak sinusoidal output swing without slew limiting to 200 kHz
• See LM148 data sheet for design equations
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 12
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PACKAGE OPTION ADDENDUM
www.ti.com 10-Feb-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LF147-MD8 ACTIVE DIESALE Y 0 100 Green (RoHS
& no Sb/Br) Call TI Level-1-NA-UNLIM -55 to 125
LF147J ACTIVE CDIP J 14 25 TBD Call TI Call TI -55 to 125 LF147J
LF347BN/NOPB ACTIVE PDIP NFF 14 25 Green (RoHS
& no Sb/Br) Call TI | SN Level-1-NA-UNLIM 0 to 70 LF347BN
LF347M NRND SOIC D 14 55 TBD Call TI Call TI 0 to 70 LF347M
LF347M/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 LF347M
LF347MX NRND SOIC D 14 2500 TBD Call TI Call TI 0 to 70 LF347M
LF347MX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 LF347M
LF347N/NOPB ACTIVE PDIP NFF 14 25 Green (RoHS
& no Sb/Br) Call TI | SN Level-1-NA-UNLIM 0 to 70 LF347N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Feb-2020
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LF347MX SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LF347MX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LF347MX SOIC D 14 2500 367.0 367.0 35.0
LF347MX/NOPB SOIC D 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 2
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PACKAGE OUTLINE
C
14X .008-.014
[0.2-0.36]
TYP
-15
0
AT GAGE PLANE
-.314.308 -7.977.83[ ]
14X -.026.014 -0.660.36[ ]
14X -.065.045 -1.651.15[ ]
.2 MAX TYP
[5.08] .13 MIN TYP
[3.3]
TYP-.060.015 -1.520.38[ ]
4X .005 MIN
[0.13]
12X .100
[2.54]
.015 GAGE PLANE
[0.38]
A
-.785.754 -19.9419.15[ ]
B -.283.245 -7.196.22[ ]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
78
14
1
PIN 1 ID
(OPTIONAL)
SCALE 0.900
SEATING PLANE
.010 [0.25] C A B
www.ti.com
EXAMPLE BOARD LAYOUT
ALL AROUND
[0.05] MAX.002
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
METAL
(.063)
[1.6]
(R.002 ) TYP
[0.05]
14X ( .039)
[1]
( .063)
[1.6]
12X (.100 )
[2.54]
(.300 ) TYP
[7.62]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
SEE DETAIL A SEE DETAIL B
SYMM
SYMM
1
78
14
DETAIL A
SCALE: 15X
SOLDER MASK
OPENING
METAL
DETAIL B
13X, SCALE: 15X
MECHANICAL DATA
N0014A
www.ti.com
N14A (Rev G)
NFF0014A
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