DS1996L-F5+ - Hytronics

AVAILABLE

Functional Diagrams

Pin Configurations appear at end of data sheet.

Functional Diagrams continued at end of data sheet.

UCSP is a trademark of Maxim Integrated Products, Inc.

For pricing, delivery, and ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

SPECIAL FEATURES

 65,536 bits o f read/writ e nonvo latile memor y

 Overdrive mode boosts communicat ion

speed to 142 kbits per second

 256-bit scr atchpad ensures integrity of data

transfer

 Memory part it ioned into 256-bit pages for

packetiz ing data

 Dat a integr it y assured wit h st r ict r ead/ wr ite

protocols

 Operatin g temperature range from -40°C to

+70°C

 Over 10 years of data ret ent ion

F5 MICROCAN

DATA

GROUND

0.51

5.89

16.25

17.35

5E 0C

000000FBC52B

1-Wire



All dimensions are shown in millimeters

COMMON iButton FEATURES

 Unique, facto ry-lasered and t ested 64-bit

registration nu mber (8-bit family code + 48 -

bit serial n umber 8-b it CRC teste r) assu r e s

absolute traceab ility becaus e no two part s ar e

alike

 Mult idrop controller for MicroLAN

 Digital i d entifica tion a n d informa tion b y

momentary contact

 Chip-based data car r ier compactly sto res

information

 Dat a can be accessed w hi le affixed to object

 Econo mically co mmunicat es to bus master

with a single digital signal at 16. 3 kbit s per

second

 Standard 16 mm dia met er and 1-Wire®

proto col ensure compatibility with iButton®

family

 But t on shape is se l f-a l igning wit h cup-

shaped probes

 Durab le stainless st eel case engraved w it h

r egistr ation numbe r wit hs ta nds harsh

environments

 E asily affixe d wit h self-stick adhesive

backing, latched by it s flange, or locked with

a ring pressed onto it s r im

 Presence d etect or acknow ledg es w hen read er

first applies vo lt age

ORDERING INFORMATION

PART

TEMP

RANGE

PIN-

PACKAGE

DS1996L-F5+ -40°C to +70°C F5 MicroCan

+Den otes a lead(Pb)-free/RoHS-c ompliant package.

EXAMPLES OF ACCESSORIES

DS9096P Self-Stick Ad hesive Pad

DS9101 Multi-Purpose Clip

DS9093RA Mou nting L ock Ring

DS9093F Snap-I n Fob

DS9092 iButton Pr obe

DS1996

64Kb Memory iButton

iButton and 1-Wire are registered trademarks of Maxim Integr ated Pr oduc ts, Inc.

19-4896; Rev 8/09

DS1996

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iButton DESCRIPTION

The DS1996 Memor y iBut t on is a rugged read /wr ite dat a carrier that act s as a lo ca lized dat aba se that can

be easily accessed with minimal hardware. The nonvolatile memory offers a simple solution to storing

and retrieving vital information pertaining to the object to which the iButton is attached. Data is

transferred serially via the 1-Wire protocol which requires only a single data lead and a ground return.

The scrat chpad is an add itio nal page t hat act s as a bu ffer w hen wr iting t o memo r y. Dat a is fir st written t o

the scratchpad where it can be read back. After the data has been verified, a copy scratchpad command

will transfer the data to memory. This process ensures data integrity when modifying the memory. A

48-bit serial number is factory lasered into each DS1996 to provide a guaranteed unique identity which

allows for absolute traceability. The durable MicroCan package is highly resistant to environmental

hazards such as dirt, moisture, and shock. Its compact button-shaped profile is self-alig ning w it h mat ing

receptacles, a llo wing the DS1996 t o be eas ily u sed by human operato rs. Accesso ries permit the DS1996

to be mounted on almost any surface including plastic key fobs, photo-ID badges and printed circuit

boards. Applications include access control, work-in-progress tracking, electronic travelers, storage of

calibratio n co nstant s, and debit t ok ens.

OVERVIEW

The block d iagram in Figure 1 s hows t he re lat ionships b etween t he major cont ro l and memory sectio ns of

t he DS1996. The DS1996 has three main data co mpo ne nts: 1) 64-bit lasered ROM, 2) 256-bit scr atchpad

and 3) 65536-bit SRAM. The hierarchal structure of the 1-Wire protocol is shown in Figure 2. The bus

master must first provide one of the six ROM Function Commands, 1)Read ROM, 2) Match ROM, 3)

Search RO M, 4) S kip ROM, 5) Overdr ive-S kip R O M o r O ver d r i ve-Mat ch ROM. Upo n co mp let ion of a n

o verdr ive RO M command byt e execut ed at r eg ular speed, the device will enter Overdr ive mode w here all

subsequent communication occurs at a higher speed. The protocol required for these ROM Function

Commands is described in Figure 9. After a ROM Function Command is successfully executed, the

memory functions beco me accessible and the master may provide any one of the four memory functio n

co mmands. T he prot oco l for t hese memory function co mmands is described in Figur e 7. A ll data r ead and

written leas t signi ficant bit firs t.

PARASITE POWER

The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry ”steals” power

whenever t he d ata line is hig h. T he data lin e wil l pro vide sufficient po wer as lo ng as the spec ified timing

and voltage r equireme nt s are met. T he adva nt ag es of parasit e p ower ar e two-fold: 1) by paras iting off this

input, battery power is not consumed for 1-Wire ROM function commands, and 2) if the battery is

exhaust ed fo r an y reaso n, t he RO M may st ill be re ad nor ma lly. T he remain ing circu it r y o f the DS19 96 is

sole ly oper ated by bat tery energy.

64-BIT LASERED ROM

Each DS1996 co nt a ins a u nique ROM code that is 64 bit s lo ng. The fir st 8 bit s are a 1-Wire famil y cod e.

The ne xt 48 bits are a unique ser ial number. T he last 8 bit s are a CRC o f the fir st 56 bit s. ( Figure 3.)

The 1-Wir e CRC is ge nerat ed using a po lyno mial generato r consist ing o f a shift reg ister and XOR gat es

as shown in Figure 4. The polyno mial is X8 + X5 + X4 + 1. Additional information about the Dallas 1-

Wire Cycl ic R ed undancy Chec k is available i n the B ook of DS19xx iButton S tanda rd s .

The shi ft register b it s ar e initial ized t o zero. Then st art ing wit h t he least sig ni fica nt b it of the fa mi ly cod e,

1 bit at a time is s hift ed in. After t he 8th bit of t he f a mi ly cod e has be e n e nt e r ed , the n t he seria l nu m ber is

entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC

value. Shi fting in t he 8 bits o f CRC should r eturn the shi ft register to all zer os.

DS1996

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DS1996 BLOCK DIAGRAM Figure 1

DS1996

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HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2

64-BIT LASERED ROM Figure 3

8-B it CRC Code 48-Bit Serial Num ber 8-B it Fa mil y Co d e (0CH )

MSB LSB MSB LSB MSB LSB

1-WIRE CRC GENERATOR Fi gure 4

BUS

MASTER

OTHER

DEVICES

DS 1996

COMMAND AVAILABLE DAT A FIELDS

LEVEL: COMMANDS: AFFECTED:

READ ROM 64-BIT ROM

MATCH ROM 64-BIT ROM

SE ARCH ROM 64-BIT ROM

SKI P ROM N/A

OVERDRIVE SKIP ROM N/A

OVERDRIVE MATC H ROM 64-BI T ROM

WRITE SC RATCHPAD 256-BI T SC RATC HPAD

READ SCRATCHPAD 256-BIT SCRATCHPAD

COPY SCRATCHPAD 64K-BIT MEMORY

READ MEMORY 64K-BIT ME MORY

DS 1996- SPECIFIC

MEMORY FUNCTION

COMMANDS

(SEE FIGURE 7)

1-WIRE ROM FUNCTION

COMMANDS (SE E FIGURE 9)

1-WI RE BUS

DS1996

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MEMORY

The memory map in Figure 5 shows a 32-byte page called the scratchpad and additional 32-byte pages

called memory. The DS1996 cont a ins 256 pages which comprise the 65536-bit SR AM. The scr atchp ad i s

an additiona l page that acts as a buffer w hen writing to memory.

ADDRESS REGISTERS AND TRANS FER STATUS

Because of the serial dat a transfer, the DS1996 em plo ys t hree addr ess regist er s, called T A1, TA2 and E/S

(Figure 6). Registers TA1 and TA2 must be loaded with the target address to which the data will be

written o r from which d ata will be se nt t o the master up on a Read command. Reg ist er E / S acts like a b yte

counter and Transfer Status register. It is used to ver ify data integrit y wit h Write co mmands. Therefore,

t he mast er only h as read acce ss t o this regist er . T he lower 5 b it s of the E/S r egist er indicat e the addr ess of

t he last b yte t hat h as been written t o the scratchpa d. T his ad dr ess is cal led End ing O ffset . Bit 5 of the E / S

integ er multip le of 8. B it 6, OF or ”Over flo w,” is set if mo r e b it s ar e se nt b y t he mast er than can be stored

in the scratchpad. Note that the lowest 5 bits of the target address also determine the address wit hin the

scrat chpad, w here inter mediat e sto rage o f d ata w ill begin. T his address is ca lled byt e o ffset . If t he tar get

address for a Write command is 13CH for example, then the scratchpad will store incoming data

beginning at the byte offset 1CH and will be full after only 4 bytes. The corresponding ending offset in

this example is 1FH. For best economy of speed and efficiency, the target address for writing should

point to t he beginning o f a ne w page, i. e., t he byt e o ffset w ill be 0. T hus t he full 32-byt e cap ac ity o f t he

scratchpad is available, result ing also in the ending offset of 1FH. However, it is possible to write one or

several contiguous bytes somewhere within a page. The ending offset together with the Partial and

Overflow Flag is mainly a means to support the master checking the data integrity after a Write

co mma nd. The h ighest valued b it o f t he E/S r eg ist er, ca lled AA or Aut horizat io n Accept ed, act s as a flag

to indicate that the data stored in the scratchpad has already been copied to the target memory add r e ss.

Writing data to the scratchpad c lears this flag.

WRITING WITH VERIFICATION

To write data to the DS19 96, the scratchpad has t o be u sed as intermediat e stor ag e. F irst the master issues

t he Writ e S cr atchpad command to spec ify the desir ed tar g et ad dr ess, followed b y t he d ata t o be writ ten to

the scratchpad. In the next step, the master sends the Read Scratchpad command to read the scratchpad

and to verify data integrity. As preamble to the scratchpad data, the DS1996 sends the requested target

address TA1 and T A2 a nd t he content s of the E/S r egister . I f one of the f lag s O F or PF is set, dat a did not

arr ive co rr ect ly in t he scr at chpad. The ma st er does no t need to co nt inue r eading ; it can st art a new t rial t o

write data to the scratchpad. Similarly, a set AA flag indicates that the Write command was not

recognized by the iButton. If everyt hing went correctly, all three flags are cleared and the ending offset

indicates the address of the last byte written to the scratchpad. Now the master can continue verifying

every dat a b it . After the mast er has ver ified t he dat a, it has t o send t he Co py Scrat chpad co mma nd. Thi s

command must be followed exactly by the data of the three address registers TA1, TA2 and E/S as the

master has read them verifying the scratchpad. As soon as the iButton has received these bytes, it will

co py the dat a to the requested locatio n beg inning a t t he t ar g et address.

MEMORY FUNCTION COMMANDS

The “Memory Function Flow Chart” (Figure 7) describes the protocols necessary for accessing the

memory. An e xamp le fo llows the flowchart. The communication bet ween ma ster and DS19 96 takes place

either at regular speed (default, OD=0) or at Overdrive Speed (OD=1). If not explicitly set into the

Overdrive Mode t he DS1996 assumes regu lar speed.

DS1996

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Write Scratchpad Command [0FH]

After issuing the write scratchpad command, the master must first provide the 2-byte target address,

followed by t he dat a to be writt en to t he scrat chpad. The dat a will be w r it t en to the scrat chpad start ing at

the byte offset (T4:T0). The ending offset (E4: E0) will be the byte offset at which the bus master has

stopped writ ing data.

Read Scratchpad Command [AAH]

This command is used to verify scratchpad data and target address. After issuing the read scratchpad

co mmand, the mast er beg ins reading. T he first 2 bytes w ill be t he t ar g et ad dress. T he next byte w ill be the

ending o ffs et/data status byt e (E/S) fo llowed by the scrat chpad dat a beginning at t he byt e o ffs et (T4: T0).

The mast er may read dat a u nt il the end of the scratchpad after wh ich t he data r ead will be a ll logic 1’s.

DS1996 MEMORY MAP Figure 5

ADDRESS REGISTERS Fi gu re 6

DS1996

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MEMORY FUNCTION FLOW CHART Figure 7

1) TO BE TRANSMITTED OR RECEIVED AT OVERDRIVE SPEED IF OD=1

2) RESET PULSE TO BE TRANSMITTED AT OVERDRIVE SPEED IF OD=1;

RESET PULSE TO BE TRANSM ITTED AT RE GULAR SPEED IF OD=0

OR IF THE DS1996 IS TO BE RE SET F ROM OVERDRIVE SPEED TO REGULAR SPEED

DS1996

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MEMORY FUNCTION EXAMPLES

Example: Writ e t wo dat a byt es to me mo r y lo cat io ns 0026h and 0027h (t he se ve nth and 8th byt es o f page

1). Read ent ire memory.

MAS TER MODE

DATA (LSB FIRST)

COMMENTS

Reset

Reset pulse (480-960 µs)

Presence

Presence p ulse

CCh

Issu e “ skip ROM” command

0Fh

Issue “write scratchpad” command

26h

TA1, beginning o ffset=6

00h

TA2, address=0026h

<2 data bytes>

Writ e 2 bytes o f data t o scr atchpad

Reset

Reset pulse

Presence

Presence p ulse

CCh

Issu e “ skip ROM” command

AAh

Issue “read scr atchpad” command

RX 26h Read TA1, beg inn ing offset=6

00h

Read TA2, address=0026h

07h

Read E/S , ending offset=7 , flags=0

<2 data bytes>

Read scratchpad data and verify

Reset

Reset pulse

Presence

Presence p ulse

CCh

Issu e “ skip ROM” command

55h

Issue “co py scratchpad” command

26h

TA1

TA2 AUT HORIZATION C ODE

E/S

00h

07h

Reset

Reset pulse

Presence

Presence p ulse

CCh

Issu e “ skip ROM” command

F0h

Issue “read me mory” co mmand

00h

TA1, beginning o ffset=0

00h

TA2, address=0000h

<8192 byt es>

Read entire memory

Reset

Reset pulse

Presence

Presence p ulse, done

DS1996

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Copy Scratchpad [55H]

This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad

command, the master must provide a 3-byte authorization pattern which is obtained by reading the

scratchpad for verification. This pattern must exactly match the data contained in the three address

registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA (Authorization Accepted) flag

will be set and the copy will begin. A logic 0 will be transmitted after the data has been copied until a

reset pulse is issued by the master. Any attempt to reset the part will be ignored while the copy is in

pro gress. Co py t ypically t akes 30 µs.

The data to be copied is determined by the three address registers. The scratchpad data from the

beginning offset through the ending offset, will be copied to memory, starting at the target address.

Anywhere from 1 to 32 bytes may be copied to memory with this command. Whole bytes are copied

even if only partially written. The AA flag will be cleared only by executing a write scratchpad

command.

Read Memory [F0H]

The read memory command may be used to read the entire memory. After issuing the command, the

mast er must p r ov ide the 2-byte target address. After the 2 bytes, the master r eads data beginn ing fro m t he

target address and may continue until the end of memory, at which point logic 1’s will be read. It is

important to realize that the target address registers will contain the address provided. The ending

o ffset/ data st at us byt e is unaffected.

The hardware of the DS1996 provides a means to accomplish error-free wr iting t o the memo ry se ct ion.

To safeguard read ing dat a in the 1-Wire e nviro nment and to simu lt aneously sp eed up dat a transfers, it is

recommended to packetize data into data packets of the size of one memory page each. Such a packet

would typically store a 16-bit CRC wit h each page of data to ensure rapid, error-free data transfers that

eliminat e having t o read a page mu ltip le t imes t o deter mine if the rece ived data is cor rect or not . (See the

Book o f DS19 xx iButto n Standards, C hapt er 7 for t he reco mmended file struct ure to be used wit h the 1-

Wire e nvir onment. )

1-WIRE BUS SYSTEM

The 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances the

DS1996 is a slave device. The bus master is typically a microcontroller. The discussion of this bus

system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire

sig naling ( sig na l t yp es a nd timing) . A 1 -Wire proto co l de fines bus transact io ns in ter ms o f the bus state

dur ing sp ecified t ime slo t s that are init iat ed o n the fa lling edg e of sync pu lses fro m t he bus mast er. For a

mor e detailed pro toco l description, re fer to Chapt er 4 of the Boo k of DS19xx iButto n Standards.

HARDWARE CONFIGURATION

T he 1 -Wire bus has only a single line by definit io n; it is import ant t hat each de vice o n t he bus be able t o

dr ive it at t he appropriate t ime. To facilitat e t his, each device att ached to t he 1-Wire bus mu st have open

dr a in co nnect io n or 3-state outputs. The 1-Wire po rt of t he D S1996 is o pen dr a in wit h a n int er nal c ircu it

equivalent to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves

attached. At regular speed the 1-Wire bus has a maximum data rate of 16.3 kbits per second. The speed

can be boosted to 142 kbits per second by activating the Overdrive Mode. The 1-Wire bus requires a

pullup resistor of appro ximat ely 5 kΩ.

The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus

MUST be le ft in t he id le st at e if t he t r ansact ion is to resu me. If t his does not occur and the bus is left low

for more than 16 µs (Overdrive Speed) or more than 120 µs (regular speed), one or more of the devices

on the bus may be res et.

DS1996

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HARDWARE CONFIGURATION Figure 8

TRANSACTION SEQUENCE

The protocol for accessing t he DS1996 via the 1-Wire port is a s follow s :

 Initialization

 ROM Func tion C ommand

 Memory Function Command

 Transaction/Data

INITIALIZATION

All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence

consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the

slave(s).

The presence pu lse lets t he bus mast er kno w that t he DS1996 is on the bu s and is ready to o perate. Fo r

mor e details, se e the ”1-Wir e Signal ing” section.

ROM FUNCTION COMMANDS

Once the bus master has detected a presence, it can issue one of the six ROM function commands. All

ROM funct ion co mmands are 8 bit s lo ng. A list of these co mma nds fo llo ws (refer to flo wchart in Figure

9).

Read ROM [33H]

This command allows the bus master to read the DS1996’s 8-bit family code, unique 48-bit serial

nu mber , a nd 8-bit CRC. This co mma nd ca n o nl y be u sed if t her e is a s ing le DS1996 o n t he bu s. If mo re

t ha n o ne s la ve is pr e s e nt o n t he bu s, a d a t a co ll is ion wi ll oc cu r when a l l s la ves t r y to t r ans m it a t t he s a me

time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number

w ill usual ly result in a mismat ch o f the CRC.

= RECEIVE

Tx = TRANSMI T

DS1996

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Match ROM [55H]

The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a

specific DS1996 on a multidrop bus. Only the DS1996 that exactly matches the 64-bit ROM sequence

will respond to the su bsequent memo r y fu nct io n co mma nd. All slaves that do not mat ch the 64-bit R O M

sequence will wait for a r eset pu lse. This co mma nd can be used wit h a single o r mult iple de vices on the

bus.

Skip ROM [CCH]

This command can save time in a single drop bus system by allowing the bus master to access the

memory functions without providing the 64-bit R OM code. If more than o ne sla ve is prese nt on the bus

and a read co mmand is issued follo w ing t he Sk ip ROM command, dat a co llisio n will o ccur o n t he bus as

multiple slave s transmit simultan eou sly ( ope n d rain pulld ow ns wil l produ ce a wired –AND resu lt ) .

Search ROM [F0H]

When a system is initially brought up, the bus master might not know the number o f devices on the 1-

Wire bus or their 64-bit ROM codes. The searc h ROM command allo ws the bus mast er to use a pr ocess

of eliminatio n to ide nt ify t he 64-bit ROM co des o f all slave de vices o n t he bus. The search ROM pr ocess

is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the

desired value of that bit. The bus master performs this simple, 3-step routine on each bit of the ROM.

After one complete pass, the bus master knows the contents of the ROM in one device. The remaining

number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the

Book of DS19xx iButton Standards fo r a co mprehensive discu ssion of a search ROM, including an act ual

example.

Overdrive Skip ROM [3CH]

On a single-drop bus this command can save time by allowing the bus master to access the memory

funct io ns without pro vid ing the 64-bit RO M code. Unlike the normal Sk ip ROM comma nd t he Overdrive

Sk ip ROM set s t he DS1996 in t he Overdr ive Mo de (OD=1). All co mmu nicat ion fo llo wing t his co mma nd

has to occur at Overdr ive Speed until a reset pulse of minimum 480 µs dur atio n re sets all devices o n t he

bus to r egular speed (OD=0).

When issued on a multidrop bus this command will set all Overdrive-capable devices into Overdrive

mo de. To subsequent ly addr ess a spec ific O verdr ive-capa ble de vice, a reset pu lse at Overdr ive spee d ha s

to be issued followed by a Match ROM or Search ROM co mmand sequence. This will shorten the time

for the search process. If more than one slave supporting Overdrive is present on the bus and the

Overdrive Skip ROM co mmand is followed by a read command, data collisio n will occur on the bus as

multiple slave s transmit simultan eou sly ( ope n d rain pulld ow ns wil l produ ce a wired -AND resu lt).

Overdrive Match ROM [69H]

The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at Overdrive

Speed, allows t he bus mast er to add r ess a spec ific DS 1 996 on a mult idrop bus and to simulta neou s l y set it

in Over dr ive Mo de. Onl y t he DS1996 t hat exact ly matches t he 64-b it R OM sequence will re spond to t he

subsequent memory function command. Slaves already in Overdrive mode from a previous Overdrive

Skip or Match command will remain in Overdrive mode. All other slaves that do not match the 64-bit

ROM seque nce or do not support Overdr ive will r eturn to o r remain at r egular speed a nd wa it for a reset

pulse of minimum 480 µs duration. The Overdrive Match ROM command can be used with a single or

multiple de vices on the bus .

DS1996

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1-WIRE SIGNALING

The DS1996 requires strict protocols to ensure data integrity. The protocol consists of four types of

signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read

Data. All these signals except presence pulse are initiated by the bus master. The DS1996 can

communicate at two different speeds, regular speed and Overdrive speed. If not explicitly set into the

o verdr ive mode, the DS199 6 will commun icat e at regular speed. Wh ile in Over drive Mod e the fast t iming

applies to all wave forms.

The initializat ion sequence requ ired t o begin any co mmunication with t he DS1996 is shown in Figur e 10.

A reset pulse followed by a presence pu lse ind icates the DS1996 is read y to send or rece ive data g ive n t he

correct ROM command and memory function command. The bus master transmits (TX) a reset pulse

(tRSTL, minimum 480 µs at regular speed, 48 µ s at Overdrive speed) . T he bus master then releases the line

and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor. After

detecting t he rising edge o n t he data cont act , the DS199 6 waits (t PDH, 15-60 µ s at regular speed, 2-6 µ s at

Overdrive speed) and then transmits the presence pulse (tPDL, 60-240 µs at regular speed, 8-24 µs at

Overdrive speed).

A Reset Pu ls e of 480 µs or longer will exit the Overdrive Mode returning t he device to regular speed. If

the DS1996 is in Overdrive Mode and the Reset Pulse is no longer than 80 µs the device will remain in

Overdrive Mod e.

DS1996

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ROM FUNCTIONS FLOW CHART Figure 9

1) TO BE TRANSMITTED OR RECEIVE D AT OVERDRI VE

SPEED I F OD=1

2) THE PRESENCE PULSE WILL BE SHORT I F OD=1

DS1996

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ROM FUNCTIONS FLOW CHART Figure 9 (cont’d)

3) ALWAYS TO BE TRANSMITTE D AT OVERDRI VE SPEE D

DS1996

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INIT IALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 10

Regu lar Sp eed Overdrive Speed

480 µs ≤ tRSTL < ∞ * 48 µs ≤ tRSTL < 80 µs

480 µs ≤ tRSTH < ∞ ( inclu des rec ove ry time ) 48 µs ≤ tRSTH < ∞

15 µs ≤ PDH < 60 µs 2 µs ≤ tPDH < 6 µs

60 µs ≤ tPDL < 240 µs 7 µs ≤ tPDL < 24 µs

* In order not to mask int errupt s ignaling by ot her device s on the 1-Wir e bus, t RSTL + tR should always be

less than 960 µs.

READ/WRITE TIME SLOTS

The definit io ns of wr it e and read t ime slo ts are illust rat ed in F igure 11 . A ll t ime s lo t s ar e init iat ed by t he

master dr iving t he dat a line lo w. T he falling edge of the dat a line synchro nizes t he DS1996 t o the mast er

by triggering a delay circuit in the DS1996. Dur ing wr it e time s lot s, the delay circuit d etermines when t he

DS199 6 will sa mple t he dat a line. For a read dat a t ime slo t , if a ”0” is to be tr ansmit t ed, t he delay c ircu it

determines how lo ng t he DS1996 will ho ld t he dat a line lo w overriding t he 1 generated by the ma ster. If

t he dat a bit is a ”1”, the iButton will leave t he read data time slot u nchanged.

READ/WRITE TIMING DIAGRAM Figure 11

Write-One Time Slot

Regu lar Sp eed Overdrive Speed

60 µs ≤ tSLOT < 120 µs 6 µs ≤ tSLOT < 16 µs

1 µs ≤ tLOW1 < 15 µs 1 µs ≤ tLOW1 < 2 µs

1 µs ≤ tREC < ∞ 1 µs ≤ tREC < ∞

RESISTOR

MASTER

DS1996

RESISTOR

MASTER

DS1996

16 of 19

READ/WRITE TIMING DIAGRAM Figure 11 (c o nt’d )

Write-Zero Time Slot

Regu lar Sp eed Over d r ive Speed

60 µs ≤ tLOW0 < t SLOT < 120 µs 6 µs ≤ tLOW0 < tSLOT < 16 µs

1 µs ≤ tREC < ∞ 1 µs ≤ tREC < ∞

Read-Data Time Slot

Regu lar Sp eed Overdrive Speed

60 µs ≤ tSLOT < 120 µs 6 µs ≤ tSLOT < 16 µs

1 µs ≤ tLOWR < 15 µs 1 µs ≤ tLOWR < 2 µs

0 ≤ tRELEASE < 45 µs 0 ≤ tRELEASE < 4 µs

1 µs ≤ tREC < ∞ 1 µs ≤ tREC < ∞

tRDV = 15 µs tRDV = 2 µs

tSU < 1 µs tSU < 1 µs

RESISTOR

MASTER

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PHYSICAL SPECIFICATIONS

Size See mechanical drawing

Weight 3. 3 grams (F5 package)

Humidity 90% RH at 50°C

Altitude 10, 000 feet

Expect ed Ser v ice Life 10 years at 25°C

ABSOLUTE MAXIMUM RAT INGS*

Vo ltage on any Pin Re lat ive to Ground -0.5V to +7.0V

Operating Te mperat ur e -40°C to +70°C

Stor ag e T emperat ur e -40°C to +70°C

∗ This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operation sections of this specification is not implied. Exposure to

absolute maximu m rating cond itions for ext ended periods of time may affect reliability.

DC ELECTRICAL CHARACTERISTICS (VPUP=2.8V to 6.0V, -40°C to +70°C)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Logic 1

VIH

2.2

VCC +0.3

1, 7

Logic 0

VIL

-0.3

+0.3

Output Logic Lo w @ 4 mA

VOL

0.4

I nput L oa d C urre nt

µA

CAPACITANCE (TA = 25°C)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

I/O (1-Wire)

CIN/OUT

100

800

AC ELECTRICAL CHARACTERISTICS: REGULAR SPEED (-40°C to 70°C )

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

T ime Slo t

tSLOT

120

µs

Write 1 L ow T ime

tLOW1

µs

Write 0 L ow T ime

tLOW0

120

µs

Read Dat a V alid

tRDV

exac tly 15

µs

Relea s e Time

tRELEASE

µs

Read Dat a S et up

tSU

µs

Reco ver y Time

REC

µs

Re s e t Time High

tRSTH

480

µs

Reset Time Low

tRSTL

480

µs

Presence Detect Hig h

tPDH

µs

Presence Detect Lo w

tPDL

240

µs

DS1996

18 of 19

AC ELECTRICAL CHARACTERISTICS: OVERDRIVE SPEED (-40°C to 70°C )

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

T ime Slo t

tSLOT

µs

Write 1 L ow T ime

tLOW1

µs

Write 0 L ow T ime

tLOW0

µs

Read Dat a V alid

tRDV

exac tly 2

µs

Relea s e Time

tRELEASE

1.5

µs

Read Dat a S et up

tSU

µs

Reco ver y Time

tREC

µs

Re s e t Time High

tRSTH

µs

Reset Time Low

tRSTL

µs

Presence Detect Hig h

tPDH

µs

Presence Detect Lo w

tPDL

µs

NOTES:

1. All volt ag es are r eferenced to ground.

2. Input load is to ground.

3. An add it iona l reset or communication sequence canno t beg in until the reset h igh tim e has expire d.

4. Read data setu p t ime re fers to t he t ime the host must pull the 1-Wire bus lo w t o read a bit. Dat a is

guarant eed to be va lid within 1 µs of this fa lling edge.

5. Capacit ance o n t he dat a co nt act co uld be 80 0 p F w hen po wer is first applied. If a 5 kΩ r esisto r is used

to pullup the data line to VCC, 5 ms a fter p ower has been app lied, the parasite capac itance will no t

affect no r mal communic ations.

6. T he reset low time (t RSTL) should be restricted to a maximum of 960 µs, to allo w inter rupt signaling,

ot herwise, it could mask o r co nceal interrupt pulse s.

7. VIH is a function o f the ext er na l pu llup res istor and the VCC power supply.

DS1996

REVISION HISTORY

REVISION

DATE

DESCRIPTION

PAGES

CHANGED

070808

Updated the Ordering Information t ab le to only sho w t he lead-free

version (DS1996-F5+). 1

Updated the F5 M icro Can marking to mat c h PCN H020201. 1

Updated the wording in the Para s i t e Power section. 2

Changed the tPDL(MIN) spec from 8µs to 7µs i n Figure 10 a nd in the AC

Electrical Charact eristi cs: Overdrive S peed table. 15, 18

I n the DC Electrical Characteristics table, re moved t he VOH spec and

change d the VIL(MAX) spec from 0. 8V to 0. 3V. 17

8/09 Removed the UL#913 bullet in the Common iB utton Features sec tion. 1

Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.

Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical

Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.