Philips Semiconductors Product specification
N-channel enhancement mode IRFZ48N
TrenchMOSTM transistor
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT
standard level field-effect power
transistor in a plastic envelope using VDS Drain-source voltage 55 V
’trench’ technology. The device IDDrain current (DC) 64 A
featuresverylow on-stateresistance Ptot Total power dissipation 140 W
and has integral zener diodes giving TjJunction temperature 175 ˚C
ESD protection up to 2kV. It is RDS(ON) Drain-source on-state 16 mΩ
intended for use in switched mode resistance VGS = 10 V
power supplies and general purpose
switching applications.
PINNING - TO220AB PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 gate
2 drain
3 source
tab drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS Drain-source voltage - - 55 V
VDGR Drain-gate voltage RGS = 20 kΩ-55V
±VGS Gate-source voltage - - 20 V
IDDrain current (DC) Tmb = 25 ˚C - 64 A
IDDrain current (DC) Tmb = 100 ˚C - 45 A
IDM Drain current (pulse peak value) Tmb = 25 ˚C - 210 A
Ptot Total power dissipation Tmb = 25 ˚C - 140 W
Tstg, TjStorage & operating temperature - - 55 175 ˚C
ESD LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCElectrostatic discharge capacitor Human body model - 2 kV
voltage, all pins (100 pF, 1.5 kΩ)
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
Rth j-mb Thermal resistance junction to - - 1.1 K/W
mounting base
Rth j-a Thermal resistance junction to in free air 60 - K/W
ambient
d
g
s
123
tab
February 1999 1 Rev 1.000