Publication Number S70FL01GS_00
Revision 02
Issue Date April 25, 2013
S70FL01GS
1 Gbit (128 Mbyte) MirrorBit® Flash Non-Volatile Memory
CMOS 3.0 Volt Core
Serial Peripheral Interface with Multi-I/O
Data Sheet (Preliminary)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
2
S70FL01GS
S70FL01GS_00_02 April 25, 2013
D a t a S h e e t ( P r e l i m i n a r y )
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The followi ng descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
Publication Number S70FL01GS_00
Revision 02
Issue Date April 25, 2013
ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this docum
may be revised by subsequent versions or modifications due to changes in technical
specifications.
S70FL01GS
1 Gbit (128 Mbyte) MirrorBit® Flash Non-Volatile Memory
CMOS 3.0 Volt Core
Serial Peripheral Interface with Multi-I/O
Data Sheet (Preliminary)
Features
Serial Peripheral Interface (SPI)
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Extended Addressing: 32-bit address
– Serial Command set and footprint compatible with S25FL-A,
S25FL-K, and S25FL-P SPI families
– Multi I/O Command set and footprint compatible with
S25FL-P SPI family
READ Commands
– Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR
– AutoBoot – power up or reset and execute a Normal or Quad read
command automatically at a preselected address
– Common Flash Interface (CFI) data for configuration information
Programming (1.5 Mbytes/s)
– 512-byte Page Programming buffer
– Quad-Input Page Programming (QPP) for slow clock systems
Erase (0.5 Mbytes/s)
– Uniform 256-kbyte sectors
Cycling Endurance
– 100,000 Program-Erase Cycles on any sector typical
Data Retention
– 20 Year Data Retention typical
Security Features
One Time Program (OTP) array of 1024 bytes
Block Protection
– Status Register bits to control protection against program or erase
of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or password
Spansion 65 nm MirrorBit Technology with Eclipse
™
Architecture
Core Supply Voltage: 2.7V to 3.6V
I/O Supply Voltage: 1.65V to 3.6V
Temperature Range:
– Industrial (-40°C to +85°C)
– Automotive In-Cabin (-40°C to +105°C)
Packages (all Pb-free)
– 16-lead SOIC (300 mils)
General Description
This document contains information for the S70FL01GS device, which is a dual die stack of two S25FL512S die. For detailed
specifications, please refer to the discrete die data sheet:
Document
Publication Identification Number
(PID)
S25FL512S Data Sheet S25FL512S_00
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D a t a S h e e t ( P r e l i m i n a r y )
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2. Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3. Input/Output Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5. Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 Simultaneous Die Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3 Sequential Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.4 Sector/Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.5 Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.6 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.7 Bank Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.8 ASP Register, Password Register, PPB Lock Register, PPB Access
Register, DYB Access Register, DDR Data Learning Registers . . . . . . . . . . . . . . . . . . . . . . 10
5.9 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6. Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7. RESET# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8. Versatile I/O Power Supply (VIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
10. AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
11. SDR AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
11.1 DDR AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
11.2 Capacitance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
12. SOIC 16 Physical Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
12.1 SO3016 — 16-pin Wide Plastic Small Outline Package (300-mil Body Width) . . . . . . . . . . . 16
13. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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5
Figures
Figure 2.1 16-pin Plastic Small Outline Package (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 10.1 Input, Output, and Timing Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10.2 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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Tables
Table 3.1 Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 4.1 S70FL01GS Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 6.1 Product Group CFI Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 9.1 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 10.1 AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 11.1 SDR AC Characteristics (Single Die Package, VCC = 2.7V to 3. 6V ) . . . . . . . . . . . . . . . . . . .14
Table 11.2 DDR AC Characteristics 66 MHz Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 11.3 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
D a t a S h e e t ( P r e l i m i n a r y )
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7
1. Block Diagram
SI/IO0 S I/IO 0
WP#/IO2 WP#/IO2
HOLD#/IO3 H O LD #/IO 3
FL512S
Flash
S O/IO 1
SO/IO1
SCK S CK
CS#1 C S #
Memory V SS VSS
VC C VCC
S I/IO 0
WP#/IO2
H O L D # /IO 3
FL512S
Flash
Memory
S O/IO 1
V SS
S CK
CS#2 C S #
VC C
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S70FL01GS
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2. Connection Diagrams
Figure 2.1 16-pin Plastic Small Outline Package (SO)
HOLD#/IO3
1
16
SCK
VCC
2
15
SI/IO0
RESET#/RFU
3
14
VIO/RF
DNU
4
13
NC
DNU
5
12 DNU
CS2#
6
11
DNU
CS1#
7
10
VSS
SO/IO1
8
9
WP#/IO
Note:
1. VIO (pin 14) is not supported in the S70FL01GS device and is RFU. Refer to Section 8. for more details.
3. Input/Output Summary
Table 3.1 Signal List
Signal Name
Type
Description
RESET#
Input Hardware Reset: Low = device resets and returns to standby state, ready to receive a
command. The signal has an internal pull-up resistor and may be left unconnected in the
host system if not used.
SCK Input Serial Clock.
CS# Input Chip Select.
SI / IO0 I/O Serial Input for single bit data commands or IO0 for Dual or Quad commands.
SO / IO1 I/O Serial Output for single bit data commands. IO1 for Dual or Quad commands.
WP# / IO2
I/O Write Protect when not in Quad mode. IO2 in Quad mode. The signal has an internal
pull-up resistor and may be left unconnected in the host system if not used for Quad
commands.
HOLD# / IO3
I/O Hold (pause) serial transfer in single bit or Dual data commands. IO3 in Quad-I/O mode.
The signal has an internal pull-up resistor and may be left unconnected in the host
system if not used for Quad commands.
V
CC
Supply Core Power Supply.
VIO
Supply Versatile I/O Power Supply. Note: VIO is not supported in the S70FL01GS device. Refer
to Section 8. for more details.
V
SS Supply
Ground.
NC
Unused
Not Connected. No device internal signal is connected to the package connector nor is
there any future plan to use the connector for a signal. The connection may safely be
used for routing space for a signal on a Printed Circuit Board (PCB). However, any signal
connected to an NC must not have voltage levels higher than VCC.
RFU
Reserved
Reserved for Future Use. No device internal signal is currently connected to the
package connector but there is potential future use of the connector for a signal. It is
recommended to not use RFU connectors for PCB routing channels so that the PCB may
take advantage of future enhanced features in compatible footprint devices.
DNU
Reserved
Do Not Use. A device internal signal may be connected to the package connector. The
connection may be used by Spansion for test or other purposes and is not intended for
connection to any host system signal. Any DNU signal related function will be inactive
when the signal is at VIL. The signal has an internal pull-down resistor and may be left
unconnected in the host system or may be tied to VSS. Do not use these connections for
PCB signal routing channels. Do not connect any host system signal to this connection.
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9
4. Ordering Information
The ordering part number is formed by a valid combination of the following:
S70FL 01G S AG M F I 0 1
1
Packing Type (Note 1)
0
=
Tray
1
=
Tube
3
=
13” Tape and Reel
Device
Family
S70FL
Model Number (Sector
Type)
1 = Uniform 256-kB sectors
Model
Number
(Latency Type, Package Details, RESET#
support)
0 = EHPLC, SO footprint
Temperature
Range
I = Industrial (–40°C to + 85°C)
V = Automotive In-Cabin (-40°C to +105°C)
Package
Materials
F = Lead (Pb)-free
Package
Type
M = 16-pin SO package
Speed
AG = 133 MHz
DP = 66 MHz DDR
Device
Technology
S = 0.065 µm MirrorBit Process Technology
Density
01G = 1 Gbit
Spansion Stacked Memory 3.0 Volt-Only, Serial Peripheral Interface (SPI) Flash Memory
Notes:
1. EHPLC = Enhanced High Performance Latency Code table.
2. Uniform 256-kB sectors = All sectors are uniform 256-kB with a 512B programming buffer.
4.1 Valid Combinations
Table 4.1 lists the valid combinations configurations planned to be supported in volume for this device.
Table 4.1 S70FL01GS Valid Combinations Table
S70FL01GS Valid Combinations
Package Marking (1)
Base Ordering
Part Number Speed
Option Package and
Temperature Model
Number
Packing Type
S70FL01GS
AG
MFI
01
0, 1, 3
FL01GS+A+(temp)+ F+ (M o del N umber)
S70FL01GS DP FL01GS+D+(temp)+F+(Model Number)
Note:
1. Package Marking omits the leading “S70” and package type.
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5. Device Operations
5.1 Programming
Each Flash die must be programmed independently due to the nature of the dual die stack.
5.2 Simultaneous Die Operation
The user may only access one Flash die of the dual die stack at a time via its respective Chip Select.
5.3 Sequential Reads
Sequential reads are not supported across the end of the first Flash die to the beginning of the second. If the
user desires to sequentially read across the two die, data must be read out of the first die via CS1# and then
read out of the second die via CS2#.
5.4 Sector/Bulk Erase
A sector erase command must be issued for sectors in each Flash die separately. Full device Bulk Erase via
a single command is not supported due to the nature of the dual die stack. A Bulk Erase command must be
issued for each die.
5.5 Status Registers
Each Flash die of the dual die stack is managed by its own Status Registers. Reads and updates to the
Status Registers must be managed separately. It is recommended that Status Register control bit settings of
each die are kept identical to maintain consistency when switching between die.
5.6 Configuration Register
Each Flash die of the dual die stack is managed by its own Configuration Register. Updates to the
Configuration Register control bits must be managed separately. It is recommended that Configuration
Register control bit settings of each die are kept identical to maintain consistency when switching between
die.
5.7 Bank Address Register
It is recommended that the Bank Address Register bit settings of each die are kept identical to maintain
consistency when switching between die.
5.8 ASP Register, Password Register, PPB Lock Register, PPB Access
Register, DYB Access Register, DDR Data Learning Registers
It is recommended that the bit settings for all of the above registers in each die are kept identical to maintain
consistency when switching between die.
5.9 Block Protection
Each Flash die of the dual die stack will maintain its own Block Protection. Updates to the TBPROT and
BPNV bits of each die must be managed separately. By default, each die is configured to be protected
starting at the top (highest address) of each array, but no address range is protected. It is recommended that
the Block Protection settings of each die are kept identical to maintain consistency when switching between
die. In addition, any update to the FREEZE bit must be managed separately for each die. If the FREEZE bit is
set to a logic 1, it cannot be cleared to a logic 0 until a power-on-reset is executed on each die that has the
FREEZE bit set to 1.
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11
6. Read Identification (RDID)
The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the
two-byte device identification and the bytes for the Common Flash Interface (CFI) tables. Each die of the
FL01GS dual die stack will have identical identification data as the FL512S die, with the exception of the CFI
data at byte 27h, as shown in Table 6.1.
Table 6.1 Product Group CFI Device Geometry Definition
Byte
Data
Description
27h 1Bh Device Size = 2
N
byte
7. RESET#
Note that the hardware RESET# input (pin 3) is bonded out and active for the S70FL01GS device. For
applications that do NOT require use of the RESET# pin, it is recommended to not use RESET# for PCB
routing channels that would cause the RESET# signal to be asserted Low (VIL). Doing so will cause the
device to reset to standby state. The RESET# signal has an internal pull-up resistor and may be left
unconnected in the host system if not used.
8. Versatile I/O Power Supply (V
IO
)
Note that the Versatile I/O (VIO) power supply (pin 14) is not supported and pin 14 is RFU (Reserved for
Future Use) in the standard configuration of the S70FL01GS device. Contact your local sales office to confirm
availability with the VIO feature enabled.
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9. DC Charact eris tics
This section summarizes the DC Characteristics of the device.
Table 9.1 DC Characteristics
Symbol
Parameter
Test
Conditions
Min
Typ (1)
Max
Unit
V
IL
Input Low Voltage
-0.5
0.2 x V
CC
V
V
IH
Input High Voltage
0.7 x V
CC
V
CC
+0.4 V
V
OL
Output Low Voltage IOL = 1.6 mA, VCC = VCC min
0.15 x V
CC
V
V
OH
Output High Voltage IOH = –0.1 mA 0.85 x V
CC
V
I
LI
Input Leakage Current V
CC
= V
CC
Max, V
IN
= V
IH
or V
IL
±4
µA
I
LO
Output Leakage
Current
VCC = VCC Max, VIN = VIH or V
IL
±4
µA
I
CC1
Active Power Supply
Current (READ)
Serial SDR @ 50 MHz
Serial SDR @ 133 MHz
Quad SDR @ 80 MHz
Quad SDR @ 104 MHz
Quad DDR @ 66 MHz
Outputs unconnected during read data
return (2)
18
36
50
61
75
mA
I
CC2
Active Power Supply
Current (Page
Program)
CS# = V
CC
100
mA
I
CC3
Active Power Supply
Current (WRR)
CS# = V
CC
100
mA
I
CC4
Active Power Supply
Current (SE)
CS# = V
CC
100
mA
I
CC5
Active Power Supply
Current (BE) (3)
CS# = V
CC
100
mA
ISB (Industrial)
Standby Current RESET#, CS# = VCC; SI, SCK = VCC or
VSS, Industrial Temp
70
200
µA
Notes:
1. Typical values are at TAI = 25°C and VCC = 3V.
2. Output switching current is not included.
3. Bulk Erase is on a per-die basis, not for the whole device.
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13
10. AC Test Condit i ons
Figure 10.1 Input, Output, and Timing Reference Levels
Input Levels Output Levels
V
CC
+ 0.4V
0.7 x V
CC
0.85 x V
CC
0.5 x V
CC
Timing Reference Level
0.2 x V
CC
- 0.5V
0.15 x V
CC
Figure 10.2 Test Setup
Device
Under
Test CL
Table 10.1 AC Measurement Conditions
Symbol
Parameter
Min
Max
Unit
C
L
Load Capacitance 30
15 (4)
pF
Input Rise and Fall Times
2.4 ns
Input Pulse Voltage 0.2 x VCC to 0.8 V
CC
V
Input Timing Ref Voltage 0.5 V
CC
V
Output Timing Ref
Voltage
0.5 V
CC
V
Notes:
1. Output High-Z is defined as the point where data is no longer driven.
2. Input slew rate: 1.5 V/ns.
3. AC characteristics tables assume clock and data signals have the same slew rate (slope).
4. DDR Operation.
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11. SDR AC Characteristics
Table 11.1 SDR AC Characteristics (Single Die Package, VCC = 2.7V to 3.6V)
Symbol
Parameter
Min
Typ
Max
Unit
FSCK, R SCK Clock Frequency for READ and 4READ
instructions
DC
50
MHz
FSCK, C SCK Clock Frequency for single commands (4) DC
133 MHz
FSCK, C
SCK Clock Frequency for the following dual and
quad commands: DOR, 4DOR, QOR, 4QOR, DIOR,
4DIOR, QIOR, 4QIOR
DC
104
MHz
FSCK, QPP SCK Clock Frequency for the QPP, 4QPP commands DC
80 MHz
PSCK SCK Clock Period 1/ F
SCK
∞
tWH, tCH Clock High Time (5) 45% PSCK
ns
t
WL
, t
CL
Clock Low Time (5) 45% P
SCK
ns
tCRT, tCLCH Clock Rise Time (slew rate) 0.1
V/ns
tCFT, tCHCL Clock Fall Time (slew rate) 0.1
V/ns
tCS (7) CS# High Time (Read Instructions)
CS# High Time (Program/Erase) 10
50
ns
t
CSS
CS# Active Setup Time (relative to SCK) 3
ns
t
CSH
CS# Active Hold Time (relative to SCK) 3
3000 (6) ns
t
SU
Data in Setup Time 3
ns
t
HD
Data in Hold Time 2
ns
t
V
Clock Low to Output Valid
0
8.0 (2)
7.65 (3)
6.5 (4)
ns
t
HO
Output Hold Time 2
ns
t
DIS
Output Disable Time 0
8 ns
t
WPS
WP# Setup Time 20 (1)
ns
t
WPH
WP# Hold Time 100 (1)
ns
tHLCH HOLD# Active Setup Time (relative to SCK) 3
ns
tCHHH HOLD# Active Hold Time (relative to SCK) 3
ns
t
HHCH
HOLD# Non Active Setup Time (relative to SCK) 3
ns
t
CHHL
HOLD# Non Active Hold Time (relative to SCK) 3
ns
t
HZ
HOLD# enable to Output Invalid
8 ns
t
LZ
HOLD# disable to Output Valid
8 ns
Notes:
1. Only applicable as a constraint for WRR instruction when SRWD is set to a 1.
2. Full VCC range (2.7 - 3.6V) and CL = 30 pF.
3. Regulated VCC range (3.0 - 3.6V) and CL = 30 pF.
4. Regulated VCC range (3.0 - 3.6V) and CL = 15 pF.
5. ±10% duty cycle is supported for frequencies ≤ 50 MHz.
6. Maximum value only applies during Program/Erase Suspend/Resume commands.
7. When switching between die, a minimum time of tCS must be kept between the rising edge of one chip select and the falling edge of the
other for operations and data to be valid.
D a t a S h e e t ( P r e l i m i n a r y )
April 25, 2013 S70FL01GS_00_02
S70FL01GS
15
11.1 DDR AC Characteristics
Table 11.2 DDR AC Characteristics 66 MHz Operation
Symbol
Parameter
Min
Typ
Max
Unit
F
SCK,
R
SCK Clock Frequency for DDR READ instruction DC
66 MHz
PSCK,
R
SCK Clock Period for DDR READ instruction 15
∞
ns
t
crt
Clock Rise Time (slew rate) 1.5
V/ns
t
cft
Clock Fall Time (slew rate) 1.5
V/ns
tWH, tCH Clock High Time 45% PSCK
ns
tWL, t
CL
Clock Low Time 45% P
SCK
ns
t
CS
CS# High Time (Read Instructions) 10
ns
t
CSS
CS# Active Setup Time (relative to SCK) 3
ns
t
CSH
CS# Active Hold Time (relative to SCK) 3
ns
t
SU
IO in Setup Time 2
3000 (2) ns
t
HD
IO in Hold Time 2
ns
t
V
Clock Low to Output Valid 0
6.5 (1) ns
t
HO
Output Hold Time 0
ns
t
DIS
Output Disable Time
8 ns
t
LZ
Clock to Output Low Impedance 0
8 ns
t
IHTU
Time uncertainty due to variation in V
IH
50 ps
t
ILTU
Time uncertainty due to variation in V
IL
50 ps
t
IO_skew
First IO to last IO data valid time
600 ps
t
IORT
Output rise time given 3V swing and 2.0 V/ns slew
1.5 ns
t
IOFT
Output fall time given 3V swing and 2.0 V/ns slew
1.5 ns
Δ
T
V
Clock to data valid jitter
25 ps
Notes:
1. Regulated VCC range (3.0 - 3.6V) and CL =15 pF.
2. Maximum value only applies during Program/Erase Suspend/Resume commands.
11.2 Capacitance Characteristics
Table 11.3 Capacitance
Parameter
Test
Conditions
Min
Max
Unit
C
IN
Input Capacitance (applies to SCK, CS#1, CS#2, RESET#) 1 MHz
8 pF
C
OUT
Output Capacitance (applies to All I/O) 1 MHz
8 pF
Notes:
1. For more information on capacitance, please consult the IBIS models.
2. Capacitance values correspond to single die FL512S only.
PACKAGE
S03
016
Onct.)
S03016(mm)
JEDEC
MS-013(E)M
MS-013(E)M
SYMBOL
MIN
MAX
MIN
MAX
A
0.093
0.104
2.35
2.65
A1
0.004
0.012
0.10
0.30
A2
0.081
0.104
2.05
2.56
b
0.012
0.020
0.31
0.51
b1
0.011
0.019
0.27
0.48
c
o.ooe
0.013
0.20
0.33
c1
0.008
0.012
0.20
0.30
D
0.408BSC
10.30BSC
E
0.406BSC
10.3DBSC
E1
0.295BSC
7.50
BSC
e
0.050BSC
1.27BSC
L
0.016
0.050
DAD
1.27
L1
0.056
REF
UOREF
L2
0.010
BSC
0.25BSC
N
16
16
h
0.10
0.30
0.25
0.75
II
o·
8'
o·
8'
&1
5'
15'
5'
15'
112
0'
-
o·
-
sPANs
10N"
D_a_t_a_S_h_e_e_t
:_(_P_r_e_l_i_m_in_a_r--'y'---'--)
_
'
12. SOIC 16 Physical
Diagram
12.1
503016
-
16-pin
Wide Plastic Small Outline Package (300-mil Body
Width
)
SEE
DETAJL
B
/-·
(
\
_
I
NDEX
(0.250
x:
0.
75E
1)
&
NOTES:
1.
ALL
DIMENSIONS
ARE IN
BOTI-1
INCHES
AND
MILLMETERS.
2.
DIMENSIONING
AND
TOLERANCING
PER ASME
Y14.5M- 1994.
ill
DIMENSION
D DOES NOT INCLUDE MOLD
FLASH,
PROTRUSIONS
OR GATE BURRS. MOLD
FLASH,
PROTRUSIONS
OR GATE BURRS
SHALL
NOT
EXCEED
0.15
mm
PER
END.DIMENSION
E1 DOES NOT INCLUDE INTERUEAD
FLASH OR
PROTRUSION INTERLEAD
FLASH OR
PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE.D AND
E1
DIMENSIONS
ARE
DETERMINED
AT DATUM
H.
TI-lE
PACKAGE
TOP MAY BE SMALLER THAN TI-lE
PACKAGE
BOTTOM.DIMENSIONS
D AND E1 ARE
DETERMINED
AT
THE
OlJTMOST
EXTREMES
OF THE PLASTIC BODY
EXCLUSIVE OF
MOLD
FLASH,TIE
BAR BURRS, GATE BURRS AND INTERUEAD
FLASH.BUT
INCLUDING ANY
MISMATCH
BETWEEN THE
TOP
AND BOTTOM OF TI-lE
PLASTI
C
BODY.
DATUMS
A AND
B
TO BE
DETERMINED
AT DATUM
H.
6. "N" IS TI-lE
MAXIMUM
NUMBER OF TERMINAL POSITIONS
FOR
TI-lE SPECIFIED
PACKAGE
LENGTH.
TI-lE
DIMENSIONS
APPLY TO TI-lE FLAT SECTION OF THE UEAD
BETWEEN
0.10T00.25
mm FROM THE
UEADTIP.
DIMENSION
"b" DOES NOT INCLUDE
DAMBAR PROTRUSION.
ALLOWABLE
DAM
BAR
PROTRUSION
SHALL
BE 0.10 mm
TOTAL
IN EXCESS OF TI-lE
"b"
DIMENSION
AT MAXIMUM
MATERIAL
CONDITION.
THE
DAMBAR
CANNOT BE LOCATED ON
THE
LOWER RADIUS OF THE UEAD
FOOT.
nilS
CHAMFER
FEATURE
IS
OPTIONAL.
IF
IT
IS NOT
PRESENT,
Tl-IEN A PIN
1
IDENTIFIER
MUST BE
LOCATED
WITI-IIN TI-lE
INDEX
AREA
INDICATED.
10. LEAD
COPLANARITY
SHALL BE WITHIN 0.10 mm AS
MEASURED
FROM THE SEATING
PLANE.
II"'G1112\t VI.1 .t t
D a t a S h e e t ( P r e l i m i n a r y )
April 25, 2013 S70FL01GS_00_02
S70FL01GS
17
16
S70FL01GS
S70FL01GS_00_02
April
25,
2013
D a t a S h e e t ( P r e l i m i n a r y )
April 25, 2013 S70FL01GS_00_02
S70FL01GS
17
13. Revision History
Section Description
Revision 01 (November 6, 2012)
Initial release
Revision 02 (April 25, 2013)
Global Data sheet designation updated from Advance Information to Preliminary
DC Characteristics DC Characteristics table: changed Max value of ILI, ILO, ICC1, and ISB
D a t a S h e e t ( P r e l i m i n a r y )
Colophon
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contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
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18 S70FL01GS S70FL01GS_00_02 April 25, 2013