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7A Sink, 3A Source,
12ns, SOT23 MOSFET Drivers
MAX15070A/MAX15070B
General Description
The MAX15070A/MAX15070B are high-speed MOSFET
drivers capable of sinking 7A and sourcing 3A peak
currents. The ICs, which are an enhancement over
MAX5048 devices, have inverting and noninverting
inputs that provide greater flexibility in controlling the
MOSFET. They also feature two separate outputs work-
ing in complementary mode, offering flexibility in control-
ling both turn-on and turn-off switching speeds.
The ICs have internal logic circuitry that prevents shoot-
through during output-state changes. The logic inputs
are protected against voltage spikes up to +16V, regard-
less of V+ voltage. Propagation delay time is minimized
and matched between the inverting and noninverting
inputs. The ICs have a very fast switching time, com-
bined with short propagation delays (12ns typ), making
them ideal for high-frequency circuits. The ICs operate
from a +4V to +14V single power supply and typically
consume 0.5mA of supply current. The MAX15070A has
standard TTL input logic levels, while the MAX15070B
has CMOS-like high-noise-margin (HNM) input logic
levels.
Both ICs are available in a 6-pin SOT23 package and
operate over the -40NC to +125NC temperature range.
Applications
Power MOSFET Switching
Switch-Mode Power Supplies
DC-DC Converters
Motor Control
Power-Supply Modules
Features
S Independent Source and Sink Outputs
S +4V to +14V Single Power-Supply Range
S 7A Peak Sink Current
S 3A Peak Source Current
S Inputs Rated to +14V Regardless of V+ Voltage
S 12ns Propagation Delay
S Matched Delays Between Inverting and
Noninverting Inputs Within 500ps
S HNM or TTL Logic-Level Inputs
S Low-Input Capacitance: 10pF (typ)
S Thermal-Shutdown Protection
S Small SOT23 Package Allows Routing PCB Traces
Underneath
S -40°C to +125°C Operating Temperature Range
19-5516; Rev 3; 5/13
Ordering Information
Typical Operating Circuit
Note: All devices are specified over the -40°C to +125°C
operating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V Denotes an automotive-qualified part.
IN+
N
IN-
V+V+
N_OUT
GND
P_OUT
MAX15070A
MAX15070B
PART INPUT LOGIC
LEVELS PIN-PACKAGE
MAX15070AAUT+ TTL 6 SOT23
MAX15070AAUT/V+ TTL 6 SOT23
MAX15070BAUT+ HNM 6 SOT23
2 Maxim Integrated
7A Sink, 3A Source,
12ns, SOT23 MOSFET Drivers
MAX15070A/MAX15070B
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
(Voltages referenced to GND.)
V+, IN+, IN- .......................................................... -0.3V to +16V
N_OUT, P_OUT ...........................................-0.3V to (V+ + 0.3V)
N_OUT Continuous Output Current (Note 1) ................. -200mA
P_OUT Continuous Output Current (Note 1) ................ +125mA
Continuous Power Dissipation (TA = +70NC)
SOT23 (derate 8.7mW/NC above +70NC) .................. 696mW*
Operating Temperature Range ...................... -40NC to +125NC
Junction Temperature ................................................... +150NC
Storage Temperature Range ........................... -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
ELECTRICAL CHARACTERISTICS
(V+ = +12V, CL = 0F, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC. Parameters specified at
V+ = +4.5V apply to the MAX15070A only; see Figure 1.) (Note 3)
ABSOLUTE MAXIMUM RATINGS
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-lay-
er board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
SOT23
Junction-to-Ambient Thermal Resistance (BJA) ........115NC/W
Junction-to-Case Thermal Resistance (BJC) .................. 80NC/W
PACKAGE THERMAL CHARACTERISTICS (Note 2)
*As per JEDEC 51 standard.
Note 1: Continuous output current is limited by the power dissipation of the package.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY (V+)
Input Voltage Range MAX15070A 4 14 V
MAX15070B 6 14
Undervoltage Lockout VUVLO V+ rising 3.3 3.45 3.6 V
Undervoltage-Lockout
Hysteresis 200 mV
Undervoltage Lockout to Output
Rising Delay V+ rising 100 Fs
Undervoltage Lockout to Output
Falling Delay V+ falling 2Fs
Supply Current IV+ V+ = 14V, no switching 0.5 1 mA
V+ = 14V, switching at 1MHz 2.3
n-CHANNEL OUTPUT (N_OUT)
N_OUT Resistance RN_OUT
V+ = +12V,
IN_OUT = -100mA
TA = +25NC0.256 0.32
I
TA = +125NC0.45
V+ = +4.5V,
IN_OUT = -100mA
TA = +25NC0.268 0.33
TA = +125NC0.465
Power-Off Pulldown Resistance V+ = unconnected, IN_OUT = -1mA, TA = +25NC1.3 1.9 kI
Output Bias Current IBIASN VN_OUT = V+ 6 11 FA
Peak Output Current IPEAKN CL = 22nF 7.0 A
3Maxim Integrated
7A Sink, 3A Source,
12ns, SOT23 MOSFET Drivers
MAX15070A/MAX15070B
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +12V, CL = 0F, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC. Parameters specified at
V+ = +4.5V apply to MAX15070A only, see Figure 1.) (Note 3)
Note 3: Limits are 100% tested at TA = +25°C. Limits over operating temperature range are guaranteed through correlation using
the statistical quality control (SQC) method.
Note 4: Design guaranteed by bench characterization. Limits are not production tested.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
p-CHANNEL OUTPUT (P_OUT)
P_OUT Resistance RP_OUT
V+ = +12V,
IP_OUT = 100mA
TA = +25NC0.88 1.2
I
TA = +125NC1.7
V+ = +4.5V,
IP_OUT = 100mA
TA = +25NC0.91 1.25
TA = +125NC1.75
Output Leakage Current ILEAKP VP_OUT = 0V 0.01 1 FA
Peak Output Current IPEAKN CL = 22nF 3.0 A
LOGIC INPUTS (IN+, IN-)
Logic-High Input Voltage VIH MAX15070A 2.0 V
MAX15070B 4.25
Logic-Low Input Voltage VIL MAX15070A 0.8 V
MAX15070B 2.0
Logic-Input Hysteresis VHYS MAX15070A 0.2 V
MAX15070B 0.9
Logic-Input Leakage Current VIN+ = VIN- = 0V or V+, MAX15070A 0.02 FA
Logic-Input Bias Current VIN+ = VIN- = 0V or V+, MAX15070B 10
Input Capacitance 10 pF
SWITCHING CHARACTERISTICS FOR V+ = +12V (Figure 1)
Rise Time tR
CL = 1nF 6
nsCL = 5nF 22
CL = 10nF 36
Fall Time tF
CL = 1nF 4
nsCL = 5nF 11
CL = 10nF 17
Turn-On Delay Time tD-ON CL = 1nF (Note 4) 7 11 17 ns
Turn-Off Delay Time tD-OFF CL = 1nF (Note 4) 7 12 18 ns
Break-Before-Make Time tBBM 2 ns
SWITCHING CHARACTERISTICS FOR V+ = +4.5V (MAX15070A only) (Figure 1)
Rise Time tR
CL = 1nF 5
nsCL = 5nF 16
CL = 10nF 25
Fall Time tF
CL = 1nF 4
nsCL = 5nF 10
CL = 10nF 14
Turn-On Delay Time tD-ON CL = 1nF (Note 4) 7 13 21 ns
Turn-Off Delay Time tD-OFF CL = 1nF (Note 4) 7 14 22 ns
Break-Before-Make Time tBBM 2 ns
THERMAL CHARACTERISTICS
Thermal Shutdown Temperature rising (Note 4) 166 NC
Thermal-Shutdown Hysteresis (Note 4) 13 NC
4 Maxim Integrated
7A Sink, 3A Source,
12ns, SOT23 MOSFET Drivers
MAX15070A/MAX15070B
Typical Operating Characteristics
(CL = 1000pF, TA = +25NC, unless otherwise noted. See Figure 1.)
RISE TIME vs. SUPPLY VOLTAGE
MAX15070A toc01
SUPPLY VOLTAGE (V)
RISE TIME (ns)
121086
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
2.0
41
4
TA = +125°C
TA = +25°C
TA = +85°C
TA = -40°C
TA = 0°C
FALL TIME vs. SUPPLY VOLTAGE
MAX15070A toc02
SUPPLY VOLTAGE (V)
FALL TIME (ns)
12106 8
2.0
2.5
3.0
3.5
4.5
4.0
5.0
5.5
1.5
41
4
TA = +125°C
TA = +25°C
TA = +85°C
TA = -40°C
TA = 0°C
PROPAGATION DELAY (LOW TO HIGH)
vs. SUPPLY VOLTAGE
MAX15070A toc03
SUPPLY VOLTAGE (V)
PROPAGATION DELAY (ns)
121086
10
12
14
16
18
8
41
4
TA = +125°C
TA = +25°C
TA = +85°C
TA = -40°C
TA = 0°C
PROPAGATION DELAY (HIGH TO LOW)
vs. SUPPLY VOLTAGE
MAX15070A toc04
SUPPLY VOLTAGE (V)
PROPAGATION DELAY (ns)
121086
10
12
14
16
18
20
8
41
4
TA = +125°C
TA = +85°C
TA = -40°C
TA = 0°C
TA = +25°C
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX15070A toc05
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
121086
0.5
1.0
1.5
2.0
2.5
3.0
0
41
4
40kHz 75kHz
100kHz
500kHz
1MHz
DUTY CYCLE = 50%
CL = 0
SUPPLY CURRENT vs. LOAD CAPACITANCE
MAX15070A toc06
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
16001200400 800
0.5
1.0
1.5
2.0
3.0
2.5
3.5
4.0
0
0 2000
V+ = 12V
f = 100kHz
DUTY CYCLE = 50%
SUPPLY CURRENT vs. TEMPERATURE
MAX15070A toc07
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
1109580655035205-10-25
0.6
0.8
1.0
1.2
1.4
0.4
-40 125
V+ = 12V
f = 100kHz, CL = 0
DUTY CYCLE = 50%
MAX15070A INPUT THRESHOLD
VOLTAGE vs. SUPPLY VOLTAGE
MAX15070A toc08
SUPPLY VOLTAGE (V)
INPUT THRESHOLD VOLTAGE (V)
12106 8
0.5
1.0
1.5
2.0
3.0
2.5
3.5
4.0
0
41
4
FALLING
RISING
MAX15070A
SUPPLY CURRENT vs. INPUT VOLTAGE
MAX15070A toc09
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
54321
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
0.4
01
4
INPUT LOW TO HIGH
INPUT HIGH TO LOW
5Maxim Integrated
7A Sink, 3A Source,
12ns, SOT23 MOSFET Drivers
MAX15070A/MAX15070B
Typical Operating Characteristics (continued)
(CL = 1000pF, TA = +25NC, unless otherwise noted. See Figure 1.)
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +14V, CL = 5000pF)
MAX15070A toc16
VOUTPUT
5V/div
VIN+
5V/div
20ns/div
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +14V, CL = 10,000pF)
MAX15070A toc17
VOUTPUT
5V/div
VIN+
5V/div
20ns/div
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +4V, CL = 5000pF)
MAX15070A toc10
VOUTPUT
2V/div
VIN+
2V/div
20ns/div
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +4V, CL = 10,000pF)
MAX15070A toc11
VOUTPUT
2V/div
VIN+
2V/div
20ns/div
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +4V, CL = 5000pF)
MAX15070A toc12
VOUTPUT
2V/div
VIN+
2V/div
20ns/div
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +4V, CL = 10,000pF)
MAX15070A toc13
VOUTPUT
2V/div
VIN+
2V/div
20ns/div
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +14V, CL = 5000pF)
MAX15070A toc14
VOUTPUT
5V/div
VIN+
5V/div
20ns/div
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +14V, CL = 10,000pF)
MAX15070A toc15
VOUTPUT
5V/div
VIN+
5V/div
20ns/div
6 Maxim Integrated
7A Sink, 3A Source,
12ns, SOT23 MOSFET Drivers
MAX15070A/MAX15070B
Pin Description
Functional Diagram
Pin Configuration
6V+
5 P_OUT
1IN+
SOT23
TOP VIEW
GND 2
IN- 3N_OUT
4
MAX15070A
MAX15070B
+
N
N_OUT
P_OUT
IN-
V+
GND
P
BREAK-
BEFORE-
MAKE
CONTROL
IN+
MAX15070A
MAX15070B
PIN NAME FUNCTION
1 IN+ Noninverting Logic Input. Connect IN+ to V+ when not used.
2 GND Ground
3 IN- Inverting Logic Input. Connect IN- to GND when not used.
4 N_OUT Driver Sink Output. Open-drain n-channel output. Sinks current for power MOSFET turn-off.
5 P_OUT Driver Source Output. Open-drain p-channel output. Sources current for power MOSFET turn-on.
6 V+ Power-Supply Input. Bypass V+ to GND with a 1FF low-ESR ceramic capacitor.
7Maxim Integrated
7A Sink, 3A Source,
12ns, SOT23 MOSFET Drivers
MAX15070A/MAX15070B
Detailed Description
Logic Inputs
The MAX15070A/MAX15070Bs’ logic inputs are pro-
tected against voltage spikes up to +16V, regardless of
the V+ voltage. The low 10pF input capacitance of the
inputs reduces loading and increases switching speed.
These ICs have two inputs that give the user greater
flexibility in controlling the MOSFET. Table 1 shows all
possible input combinations. The difference between the
MAX15070A and the MAX15070B is the input threshold
voltage. The MAX15070A has TTL logic-level thresholds,
while the MAX15070B has HNM (CMOS-like) logic-level
thresholds (see the Electrical Characteristics). Connect
IN+ to V+ or IN- to GND when not used. Alternatively,
the unused input can be used as an on/off control input
(Table 1).
Undervoltage Lockout (UVLO)
When V+ is below the UVLO threshold, the n-channel is
on and the p-channel is off, independent of the state of
the inputs. The UVLO is typically 3.45V with 200mV typi-
cal hysteresis to avoid chattering. A typical falling delay
of 2Fs makes the UVLO immune to narrow negative tran-
sients in noisy environments.
Driver Outputs
The ICs provide two separate outputs. One is an open-
drain p-channel, the other an open-drain n-channel. They
have distinct current sourcing/sinking capabilities to inde-
pendently control the rise and fall times of the MOSFET
gate. Add a resistor in series with P_OUT/N_OUT to slow
the corresponding rise/fall time of the MOSFET gate.
Figure 1. Timing Diagram and Test Circuit
Table 1. Truth Table
L = Logic-low, H = Logic-high.
IN+
VIL
90%
10%
tD-OFF
P_OUT AND
N_OUT
CONNECTED
TOGETHER
tD-ON
tFtR
IN+
IN-
V+
V+
CL
N_OUT
GND
P_OUT
TEST CIRCUIT
TIMING DIAGRAM
INPUT
OUTPUT
VIH
MAX15070A
MAX15070B
IN+ IN- p-CHANNEL n-CHANNEL
L L Off On
L H Off On
H L On Off
H H Off On
8 Maxim Integrated
7A Sink, 3A Source,
12ns, SOT23 MOSFET Drivers
MAX15070A/MAX15070B
Applications Information
Supply Bypassing, Device
Grounding, and Placement
Ample supply bypassing and device grounding are
extremely important because when large external capac-
itive loads are driven, the peak current at the V+ pin can
approach 3A, while at the GND pin, the peak current can
approach 7A. VCC drops and ground shifts are forms of
negative feedback for inverters and, if excessive, can
cause multiple switching when the IN- input is used and
the input slew rate is low. The device driving the input
should be referenced to the ICs’ GND pin, especially
when the IN- input is used. Ground shifts due to insuffi-
cient device grounding can disturb other circuits sharing
the same AC ground return path. Any series inductance
in the V+, P_OUT, N_OUT, and/or GND paths can cause
oscillations due to the very high di/dt that results when
the ICs are switched with any capacitive load. A 1FF
or larger value ceramic capacitor is recommended,
bypassing V+ to GND and placed as close as possible
to the pins. When driving very large loads (e.g., 10nF)
at minimum rise time, 10FF or more of parallel storage
capacitance is recommended. A ground plane is highly
recommended to minimize ground return resistance and
series inductance. Care should be taken to place the
ICs as close as possible to the external MOSFET being
driven to further minimize board inductance and AC path
resistance.
Power Dissipation
Power dissipation of the ICs consists of three compo-
nents, caused by the quiescent current, capacitive
charge and discharge of internal nodes, and the output
current (either capacitive or resistive load). The sum of
these components must be kept below the maximum
power-dissipation limit of the package at the operating
temperature.
The quiescent current is 0.5mA typical. The current
required to charge and discharge the internal nodes
is frequency dependent (see the Typical Operating
Characteristics).
For capacitive loads, the total power dissipation is
approximately:
P = CLOAD x (V+) 2 x FREQ
where CLOAD is the capacitive load, V+ is the supply
voltage, and FREQ is the switching frequency.
Layout Information
The ICs’ MOSFET drivers source and sink large currents
to create very fast rise and fall edges at the gate of the
switching MOSFET. The high di/dt can cause unaccept-
able ringing if the trace lengths and impedances are not
well controlled. The following PCB layout guidelines are
recommended when designing with the ICs:
• Place one or more 1FF decoupling ceramic
capacitor(s) from V+ to GND as close as possible to
the IC. At least one storage capacitor of 10FF (min)
should be located on the PCB with a low resistance
path to the V+ pin of the ICs. There are two AC cur-
rent loops formed between the IC and the gate of
the MOSFET being driven. The MOSFET looks like
a large capacitance from gate to source when the
gate is being pulled low. The active current loop is
from N_OUT of the ICs to the MOSFET gate to the
MOSFET source and to GND of the ICs. When the
gate of the MOSFET is being pulled high, the active
current loop is from P_OUT of the ICs to the MOSFET
gate to the MOSFET source to the GND terminal of
the decoupling capacitor to the V+ terminal of the
decoupling capacitor and to the V+ terminal of the
ICs. While the charging current loop is important, the
discharging current loop is critical. It is important to
minimize the physical distance and the impedance
in these AC current paths.
• In a multilayer PCB, the component surface layer sur-
rounding the ICs should consist of a GND plane con-
taining the discharging and charging current loops.
Chip Information
Process: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character,
but the drawing pertains to the package regardless of RoHS
status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
6 SOT23 U6+1 21-0058 90-0175
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 9
© 2013 Maxim Integrated Products, Inc. The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
7A Sink, 3A Source,
12ns, SOT23 MOSFET Drivers
MAX15070A/MAX15070B
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 11/10 Initial release
1 11/11 Added MAX15070AAVT/V+ to data sheet 1, 2, 3, 8, 9
2 8/12 Removed Evaluation Kit Available banner 1
3 5/13 Updated Ordering Information 1