MAX1169
58.6ksps, 16-Bit,
2-Wire Serial ADC in a 14-Pin TSSOP
________________________________________________________________
Maxim Integrated Products
1
19-2654; Rev 2; 12/10
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX1169 is a low-power, 16-bit successive-
approximation analog-to-digital converter (ADC). The
device features automatic power-down, an on-chip
4MHz clock, a +4.096V internal reference, and an
I2C-compatible 2-wire serial interface capable of both
fast and high-speed modes.
The MAX1169 operates from a single supply and con-
sumes 5mW at the maximum conversion rate of
58.6ksps. AutoShutdown™ powers down the device
between conversions, reducing supply current to less
than 50µA at a 1ksps throughput rate. The option of a
separate digital supply voltage allows direct interfacing
with +2.7V to +5.5V digital logic.
The MAX1169 performs a unipolar conversion on its
single analog input using its internal 4MHz clock. The
full-scale analog input range is determined by the inter-
nal reference or by an externally applied reference volt-
age ranging from 1V to VAVDD.
The four address select inputs (ADD0 to ADD3) allow
up to 16 MAX1169 devices on the same bus.
The MAX1169 is packaged in a 14-pin TSSOP and
operates over an extended temperature range. Refer to
the MAX1069 data sheet for a 14-bit device in a pin-
compatible package.
Applications
Hand-Held Portable Applications
Medical Instruments
Battery-Powered Test Equipment
Solar-Powered Remote Systems
Received-Signal-Strength Indicators
System Supervision
Features
oHigh-Speed I2C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed Mode
o+4.75V to +5.25V Single Supply
o+2.7V to +5.5V Adjustable Logic Level
oInternal +4.096V Reference
oExternal Reference: 1V to VAVDD
oInternal 4MHz Conversion Clock
o58.6ksps Sampling Rate
oAutoShutdown Between Conversions
oLow Power
5.0mW at 58.6ksps
4.2mW at 50ksps
2.0mW at 10ksps
0.23mW at 1ksps
3µW in Shutdown
oSmall 14-Pin TSSOP Package
Ordering Information
PART TEMP RANGE PIN-
PACKAGE
INL
(LSB)
MAX1169BEUD+ -40°C to +85°C 14 TSSOP ±2
14
13
12
11
10
9
8
1
2
3
4
5
6
7
ADD3
REF
REFADJ
AGNDSADD2
SDA
SCL
DGND
TOP VIEW
MAX1169
AIN
AGND
AVDDDVDD
ADD0
ADD1
TSSOP
Pin Configuration
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
EVALUATION KIT
AVAILABLE
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND.........................................................-0.3V to +6V
DVDD to DGND ........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AGNDS to AGND...................................................-0.3V to +0.3V
AIN, REF, REFADJ to AGND ..................-0.3V to (VAVDD + 0.3V)
SCL, SDA, ADD_ to DGND.......................................-0.3V to +6V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +85°C)
14-Pin TSSOP (derate 9.1mW/°C above +85°C) .........864mW
Operating Temperature Ranges
MAX1169_EUD ................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
ELECTRICAL CHARACTERISTICS
(VAVDD = +4.75V to +5.25V, VDVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external
reference applied to REF, REFADJ = AVDD, CREF = 10µF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY (Note 1)
Resolution 16 Bits
Relative Accuracy (Note 2) INL MAX1169B ±2 LSB
Differential Nonlinearity DNL MAX1169B, no missing codes 16-bit
NMC 0.7 1.7 LSB
Offset Error 2 5 mV
Offset-Error Temperature
Coefficient 1.0 ppm/°C
Gain Error (Note 3) ±0.25 ±0.5 %FSR
Gain Temperature Coefficient 0.1 ppm/°C
DYNAMIC PERFORMANCE (fIN(sine wave) = 1kHz, VIN = VREF(P-P), fSAMPLE = 58.6ksps)
Signal-to-Noise Plus Distortion SINAD 86 90 dB
Total Harmonic Distortion THD Up to the 5th harmonic -102 -90 dB
Spurious-Free Dynamic Range SFDR 92 105 dB
Signal-to-Noise Ratio SNR 87 90 dB
Full-Power Bandwidth FPBW -3dB point 4 MHz
Full-Linear Bandwidth SINAD > 81dB 33 kHz
CONVERSION RATE (Figure 11)
Fast mode 7.1 7.5
Conversion Time
(SCL Stretched Low) tCONV High-speed mode 5.8 6 μs
Fast mode 19
Throughput Rate (Note 4) fSAMPLE High-speed mode 58.6 ksps
Internal Clock Frequency fCLK 4 MHz
Track/Hold Acquisition Time tACQ (Note 5) 1100 ns
Fast mode 50
Aperture Delay, Figure 11c
(Note 6) tAD High-speed mode 30 ns
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +4.75V to +5.25V, VDVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external
reference applied to REF, REFADJ = AVDD, CREF = 10µF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Fast mode 100
Aperture Jitter, Figure 11c tAJ High-speed mode 100 ps
ANALOG INPUT (AIN)
Input Voltage Range VAIN 0 VREF V
Input Leakage Current On/off-leakage current, VAIN = 0V or VAVDD,
no clock, fSCL = 0 ±0.01 ±10 μA
Input Capacitance CIN 35 pF
INTERNAL REFERENCE (bypass REFADJ with 0.1μF to AGND and REF with 10μF to AGND)
REF Output Voltage VREF 4.056 4.096 4.136 V
Reference Temperature
Coefficient TCREF T
A= -40°C to +85°C ±35 ppm/°C
Reference Short-Circuit Current IREFSC 10 mA
REFADJ Output Voltage 4.056 4.096 4.136 V
REFADJ Input Range For small adjustments, from 4.096V ±60 mV
EXTERNAL REFERENCE (REFADJ = AVDD)
REFADJ Buffer Disable Voltage Pull REFADJ high to disable the internal
bandgap reference and reference buffer
VAVDD
- 0.1 V
REFADJ Buffer Enable Voltage VAVDD
- 0.4 V
Reference Input Voltage Range (Note 7) 1.0 VAVDD V
VREF = +4.096V, VIN = VREF(P-P),
fIN(sine wave) = 1kHz, fSAMPLE = 58.6ksps 27
REF Input Current IREF
VREF = +4.096V, shutdown 0.1
μA
DIGITAL INPUTS/OUTPUTS (SCL, SDA)
Input High Voltage VIH 0.7
VDVDD V
Input Low Voltage VIL 0.3
VDVDD V
Input Hysteresis VHYST 0.1
VDVDD V
Input Current IIN ±10 μA
Input Capacitance CIN 15 pF
Output Low Voltage VOL I
SINK = 3mA 0.4 V
ADDRESS SELECT INPUTS (ADD3, ADD2, ADD1, ADD0)
Input High Voltage 0.7
VDVDD V
Input Low Voltage 0.3
VDVDD V
Input Hysteresis 0.1
VDVDD V
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +4.75V to +5.25V, VDVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external
reference applied to REF, REFADJ = AVDD, CREF = 10µF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Current ±10 μA
Input Capacitance 15 pf
POWER REQUIREMENTS (AVDD, AGND, DVDD, DGND)
Analog Supply Voltage AVDD 4.75 5.25 V
Digital Supply Voltage DVDD 2.7 5.5 V
fSAMPLE = 58.6ksps 1.8 2.5
fSAMPLE = 10ksps 0.7 mA
fSAMPLE = 1ksps 40
Internal reference
(powered down
between conversions,
R/W = 0) Shutdown 0.4 5 μA
fSAMPLE = 58.6ksps 1.8 2.5
fSAMPLE = 10ksps 1.4 mA
fSAMPLE = 1ksps 1.1
Internal reference
(always on, R/W = 1)
Shutdown 0.4 5 μA
fSAMPLE = 58.6ksps 0.90 1.8
fSAMPLE = 10ksps 0.36 mA
fSAMPLE = 1ksps 40
Analog Supply Current IAVDD
External reference
(REFADJ = AVDD)
Shutdown 0.4 5 μA
fSAMPLE = 58.6ksps 260 400
fSAMPLE = 10ksps 65
fSAMPLE = 1ksps 6
Digital Supply Current IDVDD
Shutdown 0.2 5
μA
Power-Supply Rejection Ratio PSRR VAVDD = 5V ±5%, full-scale input (Note 8) 5 16 LSB/V
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figure 1a and Figure 2)
Serial Clock Frequency fSCL 400 kHz
Bus Free Time Between a STOP
and a START Condition tBUF 1.3 μs
Hold Time for Start Condition tHD, STA 0.6 μs
Low Period of the SCL Clock tLOW 1.3 μs
High Period of the SCL Clock tHIGH 0.6 μs
Setup Time for a Repeated
START Condition (Sr) tSU, STA 0.6 μs
Data Hold Time tHD, DAT (Note 9) 0 900 ns
Data Setup Time tSU, DAT 100 ns
Rise Time of Both SDA and SCL
Signals, Receiving tR (Note 10) 20 + 0.1CB 300 ns
Fall Time of SDA Transmitting tF (Note 10) 20 + 0.1CB 300 ns
Setup Time for STOP Condition tSU, STO 0.6 μs
Capacitive Load for Each Bus CB 400 pF
Pulse Width of Spike Suppressed tSP 50 ns
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
_______________________________________________________________________________________ 5
Note 1: DC accuracy is tested at VAVDD = +5.0V and VDVDD = +3.0V. Performance at power-supply tolerance limits is guaranteed
by power-supply rejection test.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3: Offset nullified.
Note 4: One sample is achieved every 18 clocks in continuous conversion mode:
Note 5: The track/hold acquisition time is two SCL cycles as illustrated in Figure 11:
Note 6: A filter on SDA and SCL delays the sampling instant and suppresses noise spikes less than 10ns in high-speed mode and
50ns in fast mode.
Note 7: ADC performance is limited by the converter’s noise floor, typically 225μVP-P.
Note 8:
PSRR
V (5.25V)-V (4.75V) 2
V
5.25V
FS FS
N
REF
=
⎡
⎣⎤
⎦×
-- 4.75V where N is the number of bits ( ).16
t2
1
f
ACQ SCL
=×
⎛
⎝
⎜
⎞
⎠
⎟
f1 clocks
ft
SAMPLE SCL C
-1
=+
⎛
⎝
⎜
⎞
⎠
⎟
8
ONV
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +4.75V to +5.25V, VDVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external
reference applied to REF, REFADJ = AVDD, CREF = 10μF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figure 1b and Figure 2)
Serial Clock Frequency fSCLH (Note 11) 1.7 MHz
Hold Time (Repeated) Start
Condition tHD, STA 160 ns
Low Period of the SCL Clock tLOW 320 ns
High Period of the SCL Clock tHIGH 120 ns
Setup Time for a Repeated
START Condition tSU, STA 160 ns
Data Hold Time tHD, DAT (Note 9) 0 150 ns
Data Setup Time tSU, DAT 10 ns
Rise Time of SCL Signal
(Current Source Enabled) tRCL (Note 10) 10 80 ns
Rise Time of SCL Signal After
Acknowledge Bit tRCL1 (Note 10) 20 160 ns
Fall Time of SCL Signal tFCL (Note 10) 20 80 ns
Rise Time of SDA Signal tRDA (Note 10) 20 160 ns
Fall Time of SDA Signal tFDA (Note 10) 20 160 ns
Setup Time for STOP Condition tSU, STO 160 ns
Capacitive Load for Each Bus CB 400 pF
Pulse Width of Spike Suppressed tSP 10 ns
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
6 _______________________________________________________________________________________
Note 9: A master device must provide a data hold time for SDA (referred to VIL of SCL) in order to bridge the undefined region of
SCL’s falling edge (see Figure 1).
Note 10: CB= total capacitance of one bus line in pF. tRand tFmeasured between 0.3 VDVDD and 0.7 VDVDD.
Note 11: fSCL must meet the minimum clock low time plus the rise/fall times.
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +4.75V to +5.25V, VDVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external
reference applied to REF, REFADJ = AVDD, CREF = 10μF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Figure 1. I
2
C Serial Interface Timing
tHD,STA
tHD,STA
tHIGH
tHIGH
tR
tRCL
tF
tFCL
tHD,STA
S Sr A
SCL
SDA
tSU,STA tSU,STO
tSU,STO
tRCL1
tRtF
tBUF
tBUF
tLOW
tSU,DAT tHD,DAT
tHD,DAT
PS
tSU,DAT tHD,STA
S Sr A
SCL
SDA
tSU,STA
tLOW
PS
HS-MODE F/S-MODE
A. F/S-MODE I2C SERIAL INTERFACE TIMING
B. HS-MODE I2C SERIAL INTERFACE TIMING tRDA tFDA
PARAMETERS ARE MEASURED FROM 30% TO 70%.
Figure 2. Load Circuit
VOUT
VDD
IOL = 3mA
IOH = 0mA
400pF
DIGITAL
I/O
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
_______________________________________________________________________________________
7
ANALOG SUPPLY CURRENT vs. ANALOG
SUPPLY VOLTAGE (INTERNAL REFERENCE)
MAX1169 toc01
VAVDD (V)
IAVDD (mA)
5.155.054.954.85
1.65
1.67
1.69
1.71
1.73
1.75
1.63
4.75 5.25
VDVDD = 3V
TA = +85°C
TA = +70°C
TA = +25°C
TA = 0°C
TA = -40°C770
780
790
800
810
820
830
760
ANALOG SUPPLY CURRENT vs. ANALOG
SUPPLY VOLTAGE (EXTERNAL REFERENCE)
MAX1169 toc02
VAVDD (V)
IAVDD (μA)
5.155.054.954.854.75 5.25
VDVDD = 3V
TA = +85°C
TA = +70°C
TA = +25°C
TA = 0°C
TA = -40°C
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
MAX1169 toc04
VDVDD (V)
IDVDD (μA)
5.14.73.9 4.33.53.1
120
140
160
180
200
220
240
260
280
100
2.7 5.5
VAVDD = 5V
TA = +85°C
TA = -40°C
OFFSET ERROR
vs. TEMPERATURE
MAX1169 toc06
TEMPERATURE (°C)
OFFSET ERROR (μV)
6035-15 10
-600
-400
-200
0
200
400
600
800
-800
-40 85
GAIN ERROR
vs. TEMPERATURE
MAX1169 toc07
TEMPERATURE (°C)
GAIN ERROR (% FSR)
6035-15 10
-0.006
-0.004
-0.002
0
0.002
0.004
0.006
0.008
-0.008
-40 85
Typical Operating Characteristics
(VDVDD = +3.0V, VAVDD = +5.0V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied
to REF, REFADJ = AVDD, CREF = 10μF, TA= +25°C, unless otherwise noted.)
DIGITAL SHUTDOWN CURRENT
vs. DIGITAL SUPPLY VOLTAGE
MAX1169 toc05
VDVDD (V)
IDVDD (nA)
4.3 4.7 5.13.93.53.1
100
50
150
200
250
300
350
0
2.7 5.5
VAVDD = 5V
fSAMPLE = 0
R/W = 0
TA = +70°C
TA = +85°C
TA = +25°C
TA = 0°C
TA = -40°C
ANALOG SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1169 toc03
VAVDD (V)
IAVDD (nA)
5.155.054.954.85
200
100
300
400
500
600
700
0
4.75 5.25
TA = +85°C
TA = +70°C
TA = +25°C
TA = 0°C
TA = -40°C
VDVDD = 3V
fSAMPLE = 0
R/W = 0
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDVDD = +3.0V, VAVDD = +5.0V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied
to REF, REFADJ = AVDD, CREF = 10μF, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. CONVERSION RATE
(HIGH-SPEED MODE, INTERNAL REFERENCE)
MAX1169 toc08
CONVERSION RATE (ksps)
SUPPLY CURRENT (μA)
605030 402010
200
400
600
800
1000
1200
1400
1600
1800
2000
0
070
INTERNAL REFERENCE, fSCL = 1.7MHz
IAVDD, R/W = 1
IAVDD, R/W = 0
IDVDD, R/W = 1 OR 0
100
200
300
400
500
600
700
800
900
0
SUPPLY CURRENT vs. CONVERSION RATE
(HIGH-SPEED MODE, EXTERNAL REFERENCE)
MAX1169 toc09
CONVERSION RATE (ksps)
SUPPLY CURRENT (μA)
605030 402010070
EXTERNAL REFERENCE, fSCL = 1.7MHz
IDVDD, R/W = 1 OR 0
IAVDD, R/W = 1 OR 0
SUPPLY CURRENT vs. CONVERSION RATE
(FAST MODE, INTERNAL REFERENCE)
MAX1169 toc10
CONVERSION RATE (ksps)
SUPPLY CURRENT (μA)
2015105
200
400
600
800
1000
1200
1400
1600
1800
0
025
INTERNAL REFERENCE, fSCL = 400kHz
IAVDD, R/W = 1
IAVDD, R/W = 0
IDVDD, R/W = 1 OR 0 100
200
300
400
500
600
0
SUPPLY CURRENT vs. CONVERSION RATE
(FAST MODE, EXTERNAL REFERENCE)
MAX1169 toc11
CONVERSION RATE (ksps)
SUPPLY CURRENT (μA)
2015105025
EXTERNAL REFERENCE, fSCL = 400kHz
IDVDD, R/W = 1 OR 0
IAVDD, R/W = 1 OR 0
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
_______________________________________________________________________________________
9
INTERNAL +4.096V REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1169 toc12
VAVDD (V)
VREF (V)
5.155.054.954.85
4.080
4.085
4.090
4.095
4.100
4.075
4.75 5.25
VDVDD = 3V
TA = +85°C
TA = +70°C
TA = +25°C
TA = 0°C
TA = -40°C
INTERNAL REFERENCE VOLTAGE
vs. REF LOAD
MAX1169 toc13
IREF (mA)
VREF (V)
54321
3.95
4.00
4.05
4.10
4.20
3.90
06
fSCL = 0
INTERNAL REFERENCE MODE
LOAD APPLIED TO REF
4.15
5
10
15
20
25
30
35
0
EXTERNAL REFERENCE CURRENT
vs. EXTERNAL REFERENCE VOLTAGE
MAX1169 toc14
VREF (V)
IREF (μA)
5432106
AIN = AGNDS
58.6ksps
fSCL = 1.7MHz
19ksps
fSCL = 400kHz
EXTERNAL REFERENCE CURRENT AND
REFERENCE VOLTAGE vs. VREFADJ
MAX1169 toc15
VREFADJ (V)
IREFADJ (μA)
VREF (V)
4.204.154.104.054.00
-20
-10
0
10
20
30
-30
4.00
4.05
4.10
4.15
4.20
4.25
3.95
3.95 4.25
AIN = AGNDS
IREFADJ
VREF
Typical Operating Characteristics (continued)
(VDVDD = +3.0V, VAVDD = +5.0V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied
to REF, REFADJ = AVDD, CREF = 10μF, TA= +25°C, unless otherwise noted.)
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
10 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDVDD = +3.0V, VAVDD = +5.0V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied
to REF, REFADJ = AVDD, CREF = 10μF, TA= +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. FREQUENCY
MAX1169 toc17
FREQUENCY (kHz)
SFDR (dB)
120
110
100
90
80
70
60
50
40
30
20
10
0
1 10 100
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
MAX1169 toc19
FREQUENCY (kHz)
THD (dB)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
1 10 100
SINAD vs. FREQUENCY
MAX1169 toc20
FREQUENCY (kHz)
SINAD (dB)
120
110
100
90
80
70
60
50
40
30
20
10
0
1 10 100
-2.0
-1.5
0.5
0
1.5
2.0
0 32,768
16,384 49,152 65,536
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1169 toc21
DIGITAL OUTPUT CODE
INL (LSB)
1.0
-1.0
-0.5
FFT
MAX1169 toc22
FREQUENCY (kHz)
MAGNITUDE (dB)
23.4417.5611.725.86
-120
-100
-80
-60
-40
-20
0
-140
0 29.30
fSAMPLE = 58.6ksps
fIN(SINE WAVE) = 1kHz
VIN = VREF(P-P)
SIGNAL-TO-NOISE RATIO
vs. FREQUENCY
MAX1169 toc16
FREQUENCY (kHz)
SNR (dB)
120
110
100
90
80
70
60
50
40
30
20
10
0
1 10 100
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1169 toc18
DIGITAL OUTPUT CODE
DNL (LSB)
49,15216,384 32,768
-2.0
-1.0
-0.5
0
0.5
1.0
1.5
2.0
-2.5
0 65,536
Detailed Description
The MAX1169 ADC uses successive-approximation
conversion (SAR) techniques and on-chip track-and-
hold (T/H) circuitry to capture and convert an analog
signal to a serial 16-bit digital output.
The MAX1169 performs a unipolar conversion on its
single analog input using its internal 4MHz clock. The
full-scale analog input range is determined by the inter-
nal reference or by an externally applied reference volt-
age ranging from 1V to VAVDD.
The flexible 2-wire serial interface provides easy con-
nection to microcontrollers (μCs) and supports data
rates up to 1.7MHz. Figure 3 shows the simplified func-
tional diagram for the MAX1169 and Figure 4 shows the
typical application circuit.
Power Supply
To maintain a low-noise environment, the MAX1169
provides separate analog and digital power-supply
inputs. The analog circuitry requires a +5V supply and
consumes only 900μA at sampling rates up to
58.6ksps. The digital supply voltage accepts voltages
from +2.7V to +5.5V to ensure compatibility with low-
voltage ASICs. The MAX1169 wakes up in shutdown
mode when power is applied irrespective of the AVDD
and DVDD sequence.
Analog Input and Track/Hold
The MAX1169 analog input contains a T/H capacitor,
T/H switches, comparator, and a switched capacitor
digital-to-analog converter (DAC) (Figure 5).
As shown in Figure 11c, the MAX1169 acquisition peri-
od is the two clock cycles prior to the conversion peri-
od. The T/H switches are normally in the hold position.
During the acquisition period, the T/H switches are in
the track position and CT/H charges to the analog input
signal. Before a conversion begins, the T/H switches
move to the hold position retaining the charge on CT/H
as a sample of the analog input signal.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
zero within the limits of 16-bit resolution. This is equiva-
lent to transferring a charge of 35pF ×(VAIN - VAGNDS)
from CT/H to the binary weighted capacitive DAC,
forming a digital representation of the analog input sig-
nal. During the conversion period, the MAX1169 holds
SCL low (clock stretching).
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
______________________________________________________________________________________ 11
Pin Description
PIN NAME FUNCTION
1 DGND Digital Ground
2 SCL Clock Input
3 SDA Data Input/Output
4 ADD2 Address Select Input 2
5 ADD1 Address Select Input 1
6 ADD0 Address Select Input 0
7 DVDD Digital Power Input. Bypass to DGND with a 0.1μF capacitor.
8 AVDD Analog Power Input. Bypass to AGND with a 0.1μF capacitor.
9 AGND Analog Ground
10 AIN Analog Input
11 AGNDS Analog Signal Ground. Negative reference for analog input. Connect to AGND.
12 REFADJ Internal Reference Output and Reference Buffer Input. Bypass to AGND with a 0.1μF capacitor.
Connect REFADJ to AVDD to disable the internal bandgap reference and reference-buffer amplifier.
13 REF Reference Buffer Output and External Reference Input. Bypass to AGND with a 10μF capacitor
when using the internal reference.
14 ADD3 Address Select Input 3
MAX1169
The time required for the T/H to acquire an input signal
is a function of the analog input source impedance. If
the input signal source impedance is high, lengthen the
acquisition time by reducing fSCL. The MAX1169 pro-
vides two SCL cycles (tACQ) in which the track-and-
hold capacitance must acquire a charge representing
the input signal. Minimize the input source impedance
(RSOURCE) to allow the track-and-hold capacitance to
charge within the allotted time. RSOURCE should be
less than 11.3kΩfor fSCL = 400kHz and less than 2kΩ
for fSCL = 1.7MHz. RSOURCE is calculated with the fol-
lowing equation:
RfIn
(22
)CR
SOURCE
SCL NIN
IN
≤××× −
2
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
12 ______________________________________________________________________________________
Figure 3. MAX1169 Simplified Functional Diagram
AIN
AGNDS
CONTROL
LOGIC
4MHz
INTERNAL
OSCILLATOR
OUTPUT SHIFT
REGISTER
T/H SAR
ADC
REF
CLOCK
IN OUT
+4.096V
REFERENCE
REFADJ
REF
5kΩ
ADD0
ADD1
ADD2
ADD3
DVDD
AVDD
DGND
SCL
SDA
AGND
8
13
12
11
91
2
3
4
5
6
7
10
14
MAX1169
AV = 1.0
Figure 4. Typical Application Circuit
AIN
REF
10μF
0.1μF
REFADJ
AGNDS
AVDD
0.1μF
AGND DGND
ANALOG
SOURCE
ADD1
ADD0
ADD2
SCL
SDA
DVDD
0.1μF
3.0V
5.0V μC
VDD
SDA
SCL
RPRP
ADD3 VSS
8
13
12
11 14
91
2
3
4
5
6
7
10
I2C ADDRESS IS 0110111.
MAX1169
where RSOURCE is the analog input source impedance,
fSCL is the maximum system SCL frequency, N is 16
(the number of bits of resolution), CIN is 35pF (the sum
of CT/H and input stray capacitance), and RIN is 800Ω
(the T/H switch resistances).
To improve the input-signal bandwidth under AC
conditions, drive AIN with a wideband buffer
(>4MHz) that can drive the ADC’s input capacitance
and settle quickly (see the
Input Buffer
section).
An RC filter at AIN reduces the input track-and-hold
switching transient by providing charge for CT/H.
Analog Input Bandwidth
The MAX1169 features input-tracking circuitry with a
4MHz small-signal bandwidth. The 4MHz input band-
width makes it possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using under-
sampling techniques. Use anti-alias filtering to avoid
high-frequency signals being aliased into the frequency
band of interest.
Analog Input Range and Protection
Internal electrostatic discharge (ESD) protection diodes
clamp AIN, REF, and REFADJ to AVDD and AGNDS/
AGND (Figure 6). These diodes allow the analog inputs
to swing from (VAGND - 0.3V) to (VAVDD + 0.3V) without
causing damage to the device. For accurate conver-
sions, the inputs must not go more than 50mV beyond
their rails.
If the analog inputs exceed 300mV beyond their
rails, limit the current to 2mA.
Internal Clock
The MAX1169 contains an internal 4MHz oscillator that
drives the SAR conversion clock. During conversion, SCL
is held low (clock stretching). An internal register stores
data when the conversion is in progress. When the
MAX1169 releases SCL, the master reads the conversion
results at any clock rate up to 1.7MHz (Figure 11).
Digital Interface
The MAX1169 features an I2C-compatible, 2-wire serial
interface consisting of a bidirectional serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facili-
tate bidirectional communication between the
MAX1169 and the master at rates up to 1.7MHz. The
master (typically a microcontroller) initiates data trans-
fer on the bus and generates SCL.
SDA and SCL require pullup resistors (500Ωor greater,
Figure 4). Optional resistors (24Ω) in series with SDA
and SCL protect the device inputs from high-voltage
spikes on the bus lines. Series resistors also minimize
crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. Nine clock cycles are required to transfer the
data into or out of the MAX1169. The data on SDA must
remain stable during the high period of the SCL clock
pulse as changes in SDA while SCL is high are control
signals (see the
START and STOP Conditions
section).
Both SDA and SCL idle high.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA with SCL high.
The master terminates a transmission with a STOP con-
dition (P), a low-to-high transition on SDA while SCL is
high (Figure 7). The STOP condition frees the bus and
places all devices in F/S mode (see the
Bus Timing
section). Use a repeated START condition (Sr) in place
of a STOP condition to leave the bus active and in its
current timing mode (see the
HS Mode
section).
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
______________________________________________________________________________________ 13
Figure 5. Equivalent Input Circuit
CT/H
AIN
AGNDS
CAPACITIVE
DAC
REF
TRACK
HOLD
TRACK
HOLD
HOLD
TRACK
*RSOURCE
ANALOG
SIGNAL
SOURCE
*MINIMIZE RSOURCE TO ALLOW THE TRACK-AND-HOLD CAPACITANCE (CT/H) TO
CHARGE TO THE ANALOG SIGNAL SOURCE VOLTAGE WITHIN THE ALLOTTED TIME (tACQ).
MAX1169
Figure 6. Internal Protection Diodes
AIN
REFADJ
AVDD
AGND
REF
AGNDS
MAX1169
MAX1169
Acknowledge Bits
Successful data transfers are acknowledged with an
acknowledge bit (A) or a not-acknowledge bit (A). Both
the master and the MAX1169 (slave) generate acknowl-
edge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse
(Figure 8). To generate a not acknowledge, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse and leaves it high
during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the master should reattempt com-
munication at a later time.
Slave Address
A master initiates communication with a slave device by
issuing a START condition followed by a slave address
byte. As shown in Figure 9, the slave address byte con-
sists of 7 address bits and a read/write bit (R/W). When
idle, the MAX1169 continuously waits for a START con-
dition followed by its slave address. When the
MAX1169 recognizes its slave address, it acquires the
analog input signal and prepares for conversion. The
first 3 bits (MSBs) of the slave address have been fac-
tory programmed and are always 011. Connecting
ADD3–ADD0 to DVDD or DGND, programs the last 4
bits (LSBs) of the slave address high or low.
Since the MAX1169 does not require setup or configu-
ration, the least significant bit (LSB) of the address byte
(R/W) controls power-down. In external reference mode
(REFADJ = AVDD), R/Wis a don’t care. In internal refer-
ence mode, setting R/W= 1 places the device in nor-
mal operation and setting R/W= 0 powers down the
internal reference following the conversion (see the
Internal Reference Shutdown
section).
After receiving the address, the MAX1169 (slave)
issues an acknowledge by pulling SDA low for one
clock cycle.
Bus Timing
At power-up, the MAX1169 bus timing defaults to fast
mode (F/S mode), allowing conversion rates up to
19ksps. The MAX1169 must operate in high-speed
mode (HS mode) to achieve conversion rates up to
58.6ksps. Figure 1 shows the bus timing for the
MAX1169 2-wire interface.
HS Mode
At power-up, the MAX1169 bus timing is set for F/S
mode. The master selects HS mode by addressing all
devices on the bus with the HS mode master code 0000
1XXX (X = don’t care). After successfully receiving the
HS mode master code, the MAX1169 issues a not
acknowledge, allowing SDA to be pulled high for one
clock cycle (Figure 10). After the not acknowledge, the
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
14 ______________________________________________________________________________________
Figure 8. Acknowledge Bits
12 8 9
ACKNOWLEDGE
NOT ACKNOWLEDGE
SCL
S
SDA
Figure 7. START and STOP Conditions
SPSr
SCL
SDA
MAX1169 is in HS mode. The master must then send a
repeated START followed by a slave address to initiate
HS mode communication. If the master generates a
STOP condition, the MAX1169 returns to F/S mode.
Data Byte (Read Cycle)
Initiate a read cycle to begin a conversion. A read
cycle begins with the master issuing a START condition
followed by 7 address bits and 1 read bit (R/W). The
standard I2C-compatible interface requires that R/W=
1 to read from a device; however, since the MAX1169
does not require setup or configuration, the read mode
is inherent and R/Wcontrols power-down (see the
Internal Reference Shutdown
section). If the address
byte is successfully received, the MAX1169 (slave)
issues an acknowledge and begins conversion.
As seen in Figure 11, the MAX1169 holds SCL low dur-
ing conversion. When the conversion is complete, SCL
is released and the master can clock data out of the
device. The most significant byte of the conversion is
available first and contains D15 to D8. The least signifi-
cant byte contains D7 to D0. Data can be continuously
converted as long as the master acknowledges the
conversion results. Issuing a not acknowledge frees the
bus, allowing the master to generate a STOP or repeat-
ed START.
Applications Information
Power-On Reset
When power is first applied, internal power-on reset cir-
cuitry activates the MAX1169 in shutdown. When the
internal reference is used, allow 12ms for the reference
to settle when CREF = 10μF and CREFADJ = 0.1μF.
Automatic Shutdown
The MAX1169 automatic shutdown reduces the supply
current to less than 0.6μA between conversions. The
MAX1169 I2C-compatible interface is always active.
When the MAX1169 receives a valid slave address, the
device powers up. The device is then powered down
again when the conversion is complete. The automatic
shutdown function does not change with internal or
external reference. When the internal reference is cho-
sen, the internal reference remains active between con-
versions unless internal reference shutdown is requested
(see the
Internal Reference Shutdown
section).
Internal Reference Shutdown
The R/Wbit of the slave address controls the MAX1169
internal reference shutdown. In external reference
mode (REFADJ = AVDD), R/Wis a don’t care. In inter-
nal reference mode, setting R/W= 1 places the device
in normal operation and setting R/W= 0 prepares the
internal reference for shutdown.
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
______________________________________________________________________________________ 15
Figure 10. F/S-Mode to HS-Mode Transfer
123
000
894567
01XXX
Sr
S
F/S MODE HS MODE
SDA A
Figure 9. MAX1169 Slave Address Byte
SCL
SDA
S
123
110
894567
ADD3 ADD2 ADD1 ADD0 R/W A
ACKNOWLEDGE
MAX1169
If the internal reference is used and R/W= 0, shutdown
occurs when the master issues a not-acknowledge bit
while reading the conversion results. The internal refer-
ence and internal reference buffer are disabled during
shutdown, reducing the analog supply current to less
than 1μA.
A dummy conversion is required to power up the inter-
nal reference. The MAX1169 internal reference begins
powering up from shutdown on the 9th falling edge of a
valid address byte. Allow 12ms for the internal refer-
ence to settle before obtaining valid conversion results.
Reference Voltage
The MAX1169 provides an internal or accepts an exter-
nal reference voltage. The ADC input range is from
VAGNDS to VREF. (See the
Transfer Function
section.)
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
16 ______________________________________________________________________________________
Figure 11. Read Cycle
S
1
SLAVE ADDRESS
71
R
NUMBER OF BITS
P OR Sr
1
18
RESULT #1 A
18
RESULT #1 A
1
8
RESULT A
18
RESULT A
1
CLOCK STRETCH
tCONV
tACQ
A
8
RESULT #2 A
1
CLOCK STRETCH
tCONV
tACQ
NUMBER OF BITS
89567
BIT3 BIT2 BIT1 BIT0 A
CLOCK STRETCH
tAD
tACQ
tAJ
SCL
SDA
123
D12D14 D13
tCONV
8
RESULT #2 A
1NUMBER OF BITS
P OR Sr
1
A
18
RESULT #N A
18
RESULT #N
CLOCK STRETCH
tCONV
tACQ
(MOST SIGNIFICANT BYTE) (LEAST SIGNIFICANT BYTE)
(MOST SIGNIFICANT BYTE) (LEAST SIGNIFICANT BYTE)
(LEAST SIGNIFICANT BIT)
(MOST SIGNIFICANT BYTE)
(MOST SIGNIFICANT BYTE) (LEAST SIGNIFICANT BYTE)
ANALOG INPUT
TRACK AND HOLD TRACKHOLD HOLD
B. CONTINUOUS CONVERSIONS
A. SINGLE CONVERSION
SLAVE TO MASTER
MASTER TO SLAVE
C. ACQUISITION DETAIL
D15
4
RS
1
SLAVE ADDRESS A
711
CLOCK STRETCH
tACQ tCONV
Internal Reference
The MAX1169 contains an internal 4.096V bandgap ref-
erence. This bandgap reference is connected to
REFADJ through a 5kΩresistor. Bypass REFADJ with a
0.1μF capacitor to AGND. The MAX1169 reference
buffer has a unity gain to provide +4.096V at REF.
Bypass REF with a 10μF capacitor to AGND when the
internal reference is used (Figure 12).
The internal reference is adjustable to ±1.5% using the
circuit of Figure 13.
External Reference
For external reference operation, disable the internal
reference by connecting REFADJ to AVDD. During con-
version, an external reference at REF must deliver up to
100μA of DC load current and have an output imped-
ance of less than 10Ω.
For optimal performance, buffer the reference through
an op amp and bypass REF with a 10μF capacitor.
Consider the MAX1169’s equivalent input noise
(38μVRMS) when choosing a reference.
Transfer Function
The MAX1169 has a standard unipolar transfer function
with a valid analog input voltage range from VAGNDS to
VREF. Output data coding is binary with 1LSB =
(VREF/2N) where N is the number of bits (16). Code
transitions occur halfway between successive-integer
LSB values. Figure 14 shows the MAX1169 input/output
(I/O) transfer function.
Input Buffer
Most applications require an input buffer amplifier to
achieve 16-bit accuracy. If the input signal is multi-
plexed, the input channel should be switched immedi-
ately after acquisition, rather than near the end of or
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
______________________________________________________________________________________ 17
Figure 12. Internal Reference
4.096V
BANDGAP
REFERENCE
5kΩ
SAR
ADC REF
0.1μF
10μF
REF
REFADJ
4.096V
AGNDDGND
AV = 1.0
12
13
9
1
MAX1169
Figure 13. Adjusting the Internal Reference
4.096V
BANDGAP
REFERENCE
5kΩ
SAR
ADC REF
0.1μF
10μF
REF
REFADJ
4.096V
AGNDDGND
AV = 1.0
12
13
9
1
MAX1169
0.1μF
150kΩ
100kΩ
POTENTIOMETER
68kΩ
AVDD
5.0V
8
MAX1169
after a conversion. This allows more time for the input
buffer amplifier to respond to a large step-change in
input signal. The input amplifier must have a high
enough slew rate to complete the required output volt-
age change before the beginning of the acquisition
time. At the beginning of acquisition, the internal sam-
pling capacitor array connects to AIN (the amplifier out-
put), causing some output disturbance.
Ensure that the sampled voltage has settled to within
the required limits before the end of the acquisition
time. If the frequency of interest is low, AIN can be
bypassed with a large enough capacitor to charge the
internal sampling capacitor with very little ripple.
However, for AC use, AIN must be driven by a wide-
band buffer (at least 4MHz), which must be stable with
the ADC’s capacitive load (in parallel with any AIN
bypass capacitor used) and also settle quickly. Refer to
Maxim’s website at www.maxim-ic.com for application
notes on how to choose the optimum buffer amplifier for
your ADC application.
Layout, Grounding, and Bypassing
Careful printed circuit (PC) board layout is essential for
the best system performance. Boards should have sep-
arate analog and digital ground planes and ensure that
digital and analog signals are separated from each
other. Do not run analog and digital (especially clock)
lines parallel to one another, or digital lines underneath
the device package.
Figure 4 shows the recommended system ground con-
nections. Establish an analog ground point at AGND
and a digital ground point at DGND. Connect all analog
grounds to the star analog ground. Connect the digital
grounds to the star digital ground. Connect the digital
ground plane to the analog ground plane at one point.
For lowest noise operation, make the ground return to
the star ground’s power supply low impedance and as
short as possible.
High-frequency noise in the AVDD power supply
degrades the ADC’s high-speed comparator perfor-
mance. Bypass AVDD to AGND with a 0.1μF ceramic
surface-mount capacitor. Make bypass capacitor con-
nections as short as possible. If the power supply is
very noisy, connect a 10Ωresistor in series with AVDD
and a 4.7μF capacitor from AVDD to AGND to create a
lowpass RC filter.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function
once offset and gain errors have been nullified. The
MAX1169 INL is measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples (Figure 11).
Aperture Delay
Aperture delay (tAD) is the time from the falling edge of
SCL to the instant when an actual sample is taken
(Figure 11).
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-
to-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
SNR = ((6.02 N) + 1.76) dB
In reality, noise sources besides quantization noise
exist, including thermal noise, reference noise, clock jit-
ter, etc. Therefore, SNR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
spectral components minus the fundamental, the first
five harmonics, and the DC offset.
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
18 ______________________________________________________________________________________
Figure 14. Unipolar Transfer Function
INPUT VOLTAGE (LSB)
BINARY OUTPUT CODE (LSB)
012 3
65536
1LSB = VREF
6553565533
0...000
0...001
0...010
0...011
1...111
1...110
1...101
1...100
AGNDS
VREF
VREF
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals:
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the
ADC’s full-scale range, calculate the ENOB as follows:
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fun-
damental itself, expressed as:
where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component.
THD =×
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
20
2
log V+V+V+V
V
2232425
1
ESINAD - 1.76
NOB =⎛
⎝
⎜⎞
⎠
⎟
602.
SINAD db() log
=×⎛
⎝
⎜
⎞
⎠
⎟
20 Signal
Noise
RMS
RMS
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
______________________________________________________________________________________ 19
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
14 TSSOP U14-1 21-0066 90-0113
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Chip Information
PROCESS: BiCMOS
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 10/02 Initial release —
1 12/09 Updated Ordering Information and Electrical Characteristics 1, 2
2 12/10 Removed commercial temperature range 1, 2
