Data Sheet SiI3132 PCI Express to Serial ATA Controller Data Sheet Document # SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. May, 2010 Copyright Notice Copyright (c) 2007-2010 Silicon Image, Inc. All rights reserved. These materials contain proprietary and confidential information (including trade secrets, copyright, and other interests) of Silicon Image, Inc. You may not use these materials except only for your bona fide non-commercial evaluation of your potential purchase of products and/or services from Silicon Image or its affiliates, and/or only in connection with your purchase of products and/or services from Silicon Image or its affiliates, and only in accordance with the terms and conditions herein. You have no right to copy, modify, transfer, sublicense, publicly display, create derivative works of or distribute these materials, or otherwise make these materials available, in whole or in part, to any third party. Patents The subject matter described herein contains one or more inventions claimed in patents and/or patents pending owned by Silicon Image, Inc., including but not limited to the inventions claimed in US patents #6,914,637, #6,151,334, #6,026,124, #5,974,464 and #5,825,824. Trademark Acknowledgment Silicon ImageTM, VastLaneTM, SteelVineTM, PinnaClearTM, SimplayTM, Simplay HDTM, SatalinkTM, InstaPortTM, and TMDSTM are trademarks or registered trademarks of Silicon Image, Inc. in the United States and other countries. HDMI(R), the HDMI logo and High-Definition Multimedia InterfaceTM are trademarks or registered trademarks of, and are used under license from, HDMI Licensing, LLC. x.v.ColorTM is a trademark of Sony Corporation. Further Information To request other materials, documentation, and information, contact your local Silicon Image, Inc. sales office or visit the Silicon Image, Inc. web site at www.siliconimage.com. Revision History Revision A A01 A02 C D E Date 4/8/2005 8/15/2005 8/11/2006 2/2/2007 2/23/2007 5/7/2010 Comment Derived from preliminary datasheet rev 0.3 Updated register description for BAR0 Offset 50H Corrected inconsistent sentences (minor fixes including mistyping) Removed confidential markings (no longer under NDA); updated Marking Specification. Changes to package drawing. New formatting applied. Added I2C section; rewrote Initialization Sequence section; copyedited and brought to current standards. (c) 2007-2010 Silicon Image. Inc. All rights reserved. ii (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Table of Contents Overview .............................................................................................................................................................................. 1 Features ............................................................................................................................................................................ 1 Overall Features............................................................................................................................................................ 1 PCI Express Features.................................................................................................................................................... 1 Serial ATA Features ...................................................................................................................................................... 1 Pin Diagram...................................................................................................................................................................... 2 Electrical Characteristics ...................................................................................................................................................... 3 Electrical Characteristics .................................................................................................................................................. 3 SATA Interface Timing Specifications ............................................................................................................................. 5 SATA Interface Transmitter Output Jitter Characteristics ................................................................................................ 5 PCI Express Interface Timing Specifications ................................................................................................................... 6 PCI Express Interface Transmitter Output Jitter Characteristics ...................................................................................... 6 CLKI SATA Reference Clock Input Requirement............................................................................................................ 6 Power Supply Noise Requirements .................................................................................................................................. 6 Pin Descriptions.................................................................................................................................................................... 7 PCI Express Pins .............................................................................................................................................................. 7 Flash Data and Address Pins ............................................................................................................................................ 7 FLSAH Control, I2C, and LED Pins................................................................................................................................. 8 Serial ATA Pins................................................................................................................................................................. 8 Test Pins............................................................................................................................................................................ 8 Power/Ground Pins........................................................................................................................................................... 9 Pin List by Pin Number .................................................................................................................................................. 10 Package Drawing................................................................................................................................................................ 11 Marking Specification .................................................................................................................................................... 12 Ordering Information...................................................................................................................................................... 12 Programming Model........................................................................................................................................................... 13 SiI3132 Block Diagram.................................................................................................................................................. 13 SiI3132 SATA Port Block Diagram................................................................................................................................ 14 Direct Command Transfer Method - Host controlled write to Slot............................................................................ 15 Indirect Command Transfer Method - SiI3132 controlled command transfer........................................................... 15 Data Structures ............................................................................................................................................................... 16 The Command Slot..................................................................................................................................................... 16 The Scatter/Gather Entry (SGE)................................................................................................................................. 16 The Scatter/Gather Table (SGT) ................................................................................................................................. 16 The Port Request Block (PRB)................................................................................................................................... 17 The PRB Control Field ............................................................................................................................................... 18 The PRB Protocol Override Field .............................................................................................................................. 19 Standard ATA Command PRB Structure .................................................................................................................... 19 PACKET Command PRB Structure ........................................................................................................................... 21 Soft Reset PRB Structure ........................................................................................................................................... 22 External Command PRB Structure ............................................................................................................................. 22 Interlocked Receive PRB Structure ............................................................................................................................ 23 Operation ........................................................................................................................................................................ 24 Methods to Issue Commands...................................................................................................................................... 24 Reset and Initialization ............................................................................................................................................... 24 PERST# Reset ........................................................................................................................................................ 24 Global Reset ........................................................................................................................................................... 25 Port Reset ............................................................................................................................................................... 25 Device Reset........................................................................................................................................................... 25 Port Initialize .......................................................................................................................................................... 25 Port Ready .............................................................................................................................................................. 25 Port Reset Operation................................................................................................................................................... 25 Initialization Sequence ............................................................................................................................................... 25 SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. iii SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Initialize Port and Retrieve Device Signature ........................................................................................................ 26 Port Multiplier Enumeration Procedure.................................................................................................................. 26 ATAPI PACKET Device Procedure ....................................................................................................................... 26 Disk Drive Procedure ............................................................................................................................................. 27 Interrupts and Command Completion ........................................................................................................................ 27 Interrupt Sources ........................................................................................................................................................ 27 Command Completion -- The Slot Status Registers.................................................................................................. 30 The Attention Bit ........................................................................................................................................................ 31 Interrupt Service Procedure........................................................................................................................................ 31 Interrupt No Clear on Read ........................................................................................................................................ 31 Error Processing ......................................................................................................................................................... 31 Error Recovery Procedures......................................................................................................................................... 32 Auto-Initialization .............................................................................................................................................................. 34 Auto-Initialization from Flash ........................................................................................................................................ 34 Auto-Initialization from EEPROM................................................................................................................................. 35 Register Definitions............................................................................................................................................................ 37 PCI Configuration Space................................................................................................................................................ 37 Device ID - Vendor ID............................................................................................................................................... 38 PCI Status - PCI Command ....................................................................................................................................... 38 PCI Class Code - Revision ID ................................................................................................................................... 39 BIST - Header Type - Latency Timer - Cache Line Size.......................................................................................... 39 Base Address Register 0 ............................................................................................................................................. 39 Base Address Register 1 ............................................................................................................................................. 40 Base Address Register 2 ............................................................................................................................................. 40 Subsystem ID -- Subsystem Vendor ID..................................................................................................................... 40 Expansion ROM Base Address .................................................................................................................................. 41 Capabilities Pointer .................................................................................................................................................... 41 Max Latency - Min Grant - Interrupt Pin - Interrupt Line........................................................................................ 41 Header Write Enable................................................................................................................................................... 42 Power Management Capability................................................................................................................................... 42 Power Management Control + Status ......................................................................................................................... 43 MSI Capability ........................................................................................................................................................... 43 Message Address ........................................................................................................................................................ 44 MSI Message Data ..................................................................................................................................................... 44 PCI Express Capability............................................................................................................................................... 44 Device Capabilities..................................................................................................................................................... 45 Device Status and Control .......................................................................................................................................... 45 Link Capabilities ........................................................................................................................................................ 46 Link Status and Control.............................................................................................................................................. 46 Global Register Offset ................................................................................................................................................ 47 Global Register Data .................................................................................................................................................. 47 Port Register Offset .................................................................................................................................................... 47 Port Register Data....................................................................................................................................................... 47 Advanced Error Reporting Capability........................................................................................................................ 48 Uncorrectable Error Status ......................................................................................................................................... 48 Uncorrectable Error Mask .......................................................................................................................................... 49 Uncorrectable Error Severity...................................................................................................................................... 49 Correctable Error Status ............................................................................................................................................. 49 Correctable Error Mask .............................................................................................................................................. 50 Advanced Error Capabilities and Control .................................................................................................................. 50 Header Log ................................................................................................................................................................. 51 Internal Register Space - Base Address 0 ...................................................................................................................... 51 Global Port Slot Status ............................................................................................................................................... 52 Global Control ............................................................................................................................................................ 52 Global Interrupt Status................................................................................................................................................ 53 PHY Configuration..................................................................................................................................................... 53 iv (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Data Sheet BIST Control .............................................................................................................................................................. 54 BIST Pattern ............................................................................................................................................................... 54 BIST Status................................................................................................................................................................. 54 I2C Control.................................................................................................................................................................. 55 I2C Status .................................................................................................................................................................... 56 I2C Slave Address ....................................................................................................................................................... 56 I2C Data Buffer........................................................................................................................................................... 57 Flash Address ............................................................................................................................................................. 57 Flash Memory Data / GPIO Control........................................................................................................................... 57 Internal Register Space - Base Address 1 .................................................................................................................. 58 Port LRAM................................................................................................................................................................. 59 Port Slot Status ........................................................................................................................................................... 59 Port Control Set .......................................................................................................................................................... 60 Port Status................................................................................................................................................................... 61 Port Control Clear....................................................................................................................................................... 61 Port Interrupt Status.................................................................................................................................................... 62 Port Interrupt Enable Set / Port Interrupt Enable Clear.............................................................................................. 63 32-bit Activation Upper Address ................................................................................................................................ 63 Port Command Execution FIFO ................................................................................................................................. 63 Port Command Error .................................................................................................................................................. 63 Port FIS Configuration ............................................................................................................................................... 65 Port PCI Express Request FIFO Threshold ................................................................................................................ 65 Port 8B/10B Decode Error Counter ........................................................................................................................... 66 Port CRC Error Counter ............................................................................................................................................. 66 Port Handshake Error Counter ................................................................................................................................... 67 Port PHY Configuration ............................................................................................................................................. 67 Port Device Status ...................................................................................................................................................... 68 Port Device QActive................................................................................................................................................... 68 Port Context................................................................................................................................................................ 69 SControl...................................................................................................................................................................... 69 SStatus ........................................................................................................................................................................ 70 SError ......................................................................................................................................................................... 71 SActive ....................................................................................................................................................................... 71 SNotification............................................................................................................................................................... 72 Internal Register Space - Base Address 2 ...................................................................................................................... 72 Global Register Offset ................................................................................................................................................ 72 Global Register Data .................................................................................................................................................. 72 Port Register Offset .................................................................................................................................................... 73 Port Register Data....................................................................................................................................................... 73 Power Management ............................................................................................................................................................ 74 Flash, GPIO, EEPROM, and I2C Programming ................................................................................................................. 75 Flash Memory Access..................................................................................................................................................... 75 PCI Direct Access....................................................................................................................................................... 75 Register Access........................................................................................................................................................... 75 Flash Write Operation............................................................................................................................................. 75 Flash Read Operation ............................................................................................................................................. 75 I2C Operation.................................................................................................................................................................. 75 I2C Master Write Operation........................................................................................................................................ 76 I2C Master Read Operation......................................................................................................................................... 76 Setup for a Read Operation .................................................................................................................................... 76 Read the Data ......................................................................................................................................................... 77 I2C Slave Read Operations ......................................................................................................................................... 77 Standards Documents ......................................................................................................................................................... 78 SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. v SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. List of Figures Figure 1. Pin Diagram (Top View) ....................................................................................................................................... 2 Figure 2. Eye Diagram ......................................................................................................................................................... 4 Figure 3. Package Drawing 88 QFN .................................................................................................................................. 11 Figure 4. Marking Specification......................................................................................................................................... 12 Figure 5. SiI3132 Block Diagram....................................................................................................................................... 13 Figure 6. Port Logic Block Diagram .................................................................................................................................. 14 Figure 7. SiI3132 Interrupt Map......................................................................................................................................... 29 Figure 8. Auto-Initialization from Flash Timing ................................................................................................................ 34 Figure 9. Auto-Initialization from EEPROM Timing......................................................................................................... 35 vi (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. List of Tables Table 1. Absolute Maximum Ratings ................................................................................................................................... 3 Table 2. DC Specifications ................................................................................................................................................... 3 Table 3. SATA Interface DC Specifications.......................................................................................................................... 4 Table 4. PCI Express Interface DC Specifications ............................................................................................................... 4 Table 5. SATA Interface Timing Specifications.................................................................................................................... 5 Table 6. SATA Interface Transmitter Output Jitter Characteristics, 1.5 Gbit/s ..................................................................... 5 Table 7. SATA Interface Transmitter Output Jitter Characteristics, 3 Gbit/s ........................................................................ 5 Table 8. PCI Express Interface Timing Specifications ......................................................................................................... 6 Table 9. PCI Express Interface Transmitter Output Jitter Characteristics ............................................................................ 6 Table 10. CLKI SerDes Reference Clock Input Requirement.............................................................................................. 6 Table 11. Power Supply Noise Requirement ........................................................................................................................ 6 Table 12. Scatter/Gather Entry (SGE) ................................................................................................................................ 16 Table 13. Scatter/Gather Table (SGT.................................................................................................................................. 17 Table 14. Control Field Bit Definitions .............................................................................................................................. 18 Table 15. Protocol Override Bit Definitions....................................................................................................................... 19 Table 16. Port Request Block for Standard ATA Command ............................................................................................... 19 Table 17. PRB FIS Area Definition .................................................................................................................................... 20 Table 18. Port Request Block for PACKET Command ...................................................................................................... 21 Table 19. Port Request Block for Soft Reset Command..................................................................................................... 22 Table 20. Port Request Block for External Commands ...................................................................................................... 23 Table 21. Port Request Block For Receiving Interlocked FIS............................................................................................ 24 Table 22. Interrupt Steering ................................................................................................................................................ 27 Table 23. Port Interrupt Causes and Control ...................................................................................................................... 30 Table 24. Auto-Initialization from Flash Timing ................................................................................................................ 34 Table 25. Flash Data Description ....................................................................................................................................... 34 Table 26. Auto-Initialization from EEPROM Timing......................................................................................................... 35 Table 27. Auto-Initialization from EEPROM Timing Symbols.......................................................................................... 35 Table 28. EEPROM Data Description ................................................................................................................................ 36 Table 29. SiI3132 PCI Configuration Space ...................................................................................................................... 37 Table 30. SiI3132 Internal Register Space - Base Address 0............................................................................................. 51 Table 31. SiI3132 Internal Register Space - Base Address 1............................................................................................. 58 Table 32. Port LRAM layout .............................................................................................................................................. 59 Table 33. Port LRAM Slot layout....................................................................................................................................... 59 Table 34. Command Error Codes ....................................................................................................................................... 64 Table 35. Default FIS Configurations................................................................................................................................. 65 Table 36. Address Offsets to Port Device Status Registers ................................................................................................ 68 Table 37. Address Offsets to Port Device QActive Registers............................................................................................. 68 Table 38. SError Register Bits (DIAG Field) ..................................................................................................................... 71 Table 39. SiI3132 Internal Register Space - Base Address 2............................................................................................. 72 Table 40. Power Management Register Bits....................................................................................................................... 74 Table 41. Referenced Documents ....................................................................................................................................... 78 Table 42. Standards Groups Contact Information .............................................................................................................. 78 SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. vii SiI3132 PCI Express to Serial ATA Controller Data Sheet viii (c) 2007-2010 Silicon Image, Inc. All rights reserved Silicon Image, Inc. SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet PCI Express Features Overview The Silicon Image SiI3132 controller is a two-port PCI Express to Serial ATA controller. It provides multipleport Serial ATA connectivity with minimal host overhead and host-to-device latency. The controller supports a 1-lane 2.5 Gbit/s PCI Express bus and the Serial ATA Generation 2 transfer rate of 3.0 Gbit/s (300 MByte/s). * * * * * Supports 1-lane 2.5 Gbit/s PCI Express Internal application interface multiplexed to 2 ports All registers appear in unified memory space All registers accessible through I/O space Full-chip command completion status accessible with single PCI Express access Serial ATA Features * * * Features Overall Features * * * * * * * Host Protocol: * Optimized for transaction oriented designs with minimal Host overhead * Supports two command issuance mechanisms: * Efficient in both embedded and PC implementations * Reduces dependency on bridge behavior Supports up to 4-Mbit external flash for BIOS expansion Supports a master/slave I2C interface Supports external flash or serial EEPROM for programmable subsystem vendor ID / subsystem product ID Fabricated in a 0.18 CMOS process with a 1.8 volt core and 3.3 volt I/Os Available in an 88-pin QFN package (10x10 mm, 0.4 mm lead pitch) with an ePad An EPAD must be soldered to PCB GND JTAG boundary scan SiI-DS-0138-E * * * * * * Integrated Serial ATA Link and PHY logic Compliant with Serial ATA 1.0 specifications Supports Serial ATA Generation 2 transfer rate of 3.0 Gbit/s Plesiochronous, Single PLL architecture, 1 PLL for 2 ports Output Swing Control Supports two independent Serial ATA channels: * Independent Link, Transport, and data FIFO * Independent command fetch, scatter/gather, and command execution with hard-coded state machines -- no code space or download * Supports Legacy Command Queuing (LCQ) * Supports Native Command Queuing (NCQ) * Supports Non-zero offsets NCQ * Supports Out of order data delivery NCQ * Supports FIS-based switching with Port Multipliers 31 Commands and Scatter/Gather Tables per port on-chip Protocol Override per Command Staggered Spin-up Control (c) 2007-2010 Silicon Image, Inc. All rights reserved. 1 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Pin Diagram Figure 1 shows the pin assignments of the controller. A description of the pin functions is in the Pin Descriptions section beginning on page 7. The package is a 10 mm x 10 mm 88-pin QFN with an ePad, which must be soldered to ground. Figure 1. Pin Diagram (Top View) 2 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Electrical Characteristics Electrical Characteristics Specifications are for commercial temperature range, 0 oC to +70 oC, unless otherwise specified. Table 1. Absolute Maximum Ratings Symbol VDDO VDDD VDDSRX, VDDSTX, VDDSPLL, VDDPRX, VDDPTX, VDDPTXPLL, VDDPRXPLL, VDDX VIN IOUT JA TSTG *Note: The ePad must be soldered to the PCB ground. Parameter I/O Supply Voltage Core Supply Voltage Supply Voltage for SATA and PCI Express Receivers, Transmitters, and PLLs, respectively Input Voltage DC Output Current Thermal Resistance, Junction to Ambient, Still Air Storage Temperature Min -- -- -- Max 4.0 2.15 Unit V V 2.15 V -0.3 -- -- VDD + 0.3 16 V mA 22.2* C/W -65 150 o C Table 2. DC Specifications Symbol VDDD VDDSRX VDDSTX VDDSPLL VDDPRX VDDPTX VDDPTXPLL VDDPRXPLL VDDX VDDO IDD1.8V-3G IDD1.8V-1.5G VIH VIL V+ VVH IIH Parameter Core Supply Voltage SATA Receiver Supply Voltage SATA Transmitter Supply Voltage SATA SerDes PLL Supply Voltage PCI Exp Receiver Supply Voltage PCI Exp Transmitter Supply Voltage PCI Exp Transmitter PLL Supply Voltage PCI Exp Receiver PLL Supply Voltage Oscillator Supply Voltage Supply Voltage (I/O) Supply Current (1.8 V Supply) Supply Current (1.8 V Supply) Input HIGH Voltage Input LOW Voltage Input HIGH Voltage Input LOW Voltage Hysteresis Voltage Input HIGH Current IIL VOH VOL IOZ Input LOW Current Output HIGH Voltage Output LOW Voltage 3-State Leakage Current Condition -- -- -- -- -- -- -- -- -- -- 3 GHz Operating 1.5 GHz Operating 3.3 V I/O 3.3 V I/O 3.3 V I/O 3.3 V I/O 3.3 V I/O VIN = VDD Type -- -- -- -- -- -- -- -- -- -- -- -- -- -- Schmitt Schmitt Schmitt -- Min Typ Max Unit 1.71 1.8 1.89 V 3.0 -- -- 2.0 -- -- 0.5 0.4 -10 3.3 450 380 -- -- 1.8 0.9 -- -- 3.6 570 500 -- 0.8 2.3 -- -- 10 V mA mA V V V V V VIN = VSS -- -- -- -- -- -- -- -10 2.4 -- -10 -- -- -- -- 10 -- 0.4 10 A V V A A Note: 3.3 V power consumption depends on LED, JTAG, Enclosure management status. If all are disabled, 3.3 V power consumption is insignificant. SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 3 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Table 3. SATA Interface DC Specifications Symbol Parameter Condition Terminated by 50 . BAR1 1050h [4:0] = 0x0C* Min Typ Max Unit VSATA_DOUT TX+/TX- differential peak-to-peak voltage swing. 400 550 700 mV -- 240 -- -- mV -- -- -- -- -- -- 50 -- 85 85 40 40 125 -- 100 100 -- -- 240 50 115 115 -- -- mV mV Condition Terminated by 50 Ratio Min 800 -3.0 Typ 1000 -3.5 Max 1200 -4.0 Unit mV dB -- 175 -- 1200 mV DC impedance DC impedance DC impedance DC impedance 80 80 40 40 100 100 50 50 120 120 60 60 Rx Powered Down Impedance DC impedance 200 -- -- k Electrical Idle Detect Threshold Measured at the Rx pins 65 -- 175 mV RX+/RX- differential peak-to-peak input sensitivity VSATA_SQ RX+/RX- OOB Signal Detection Threshold VSATA_ACCM Tx AC common-mode voltage Z SATA_DIN Tx Pair Differential impedance Z SATA_DOUT Rx Pair Differential impedance Z SATA_SIN Tx Single-Ended impedance Z SATA_SOUT Rx Single-Ended impedance *Note: 0x0A is a reset value. VSATA_DIN Table 4. PCI Express Interface DC Specifications Symbol VPCI_DOUT VPCI_DE-RATIO V PCI_DIN Z PCI_DIN Z PCI_DOUT Z PCI_SIN Z PCI_SOUT Z PCI_RX-HIGHIMP-DC Z PCI_RX-IDLEDET-DIFFp-p Parameter TX+/TX- differential peak-to-peak voltage swing. Tx De-Emphasized Differential Output Voltage RX+/RX- differential peak-to-peak input sensitivity Tx Pair Differential impedance Rx Pair Differential impedance Tx Single-Ended impedance Rx Single-Ended impedance Maximum Amplitude Minimum Amplitude Peak-to peak Total Jitter Figure 2. Eye Diagram 4 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. SATA Interface Timing Specifications Table 5. SATA Interface Timing Specifications Symbol Parameter Condition TTX_RISE_FALL Rise and Fall time at transmitter TTX_TOL_FREQ Tx Frequency Long Term Stability TTX_AC_FREQ Tx Spread-Spectrum Modulation Deviation TTX_SKEW Tx Differential Skew 20%-80% at Gen 1 20%-80% at Gen 2 -- CLKI = SSC AC modulation, subject to the Downspread SSC triangular modulation (30-33 kHz) profile per 6.6.4.5 in SATA 1.0 specification -- Min 100 67 -350 Typ Max Unit -- 273 136 ps -- +350 ppm -5000 -- +0 ppm -- -- 15 ps Min Typ Max Unit -- 80 -- ps -- 40 -- ps -- 100 -- ps -- 60 -- ps Min Typ Max Unit -- 60 -- ps -- 15 -- ps -- 70 -- ps -- 20 -- ps SATA Interface Transmitter Output Jitter Characteristics Table 6. SATA Interface Transmitter Output Jitter Characteristics, 1.5 Gbit/s Symbol Parameter TJ5UI_15G Total Jitter, Data-Data 5 UI DJ5UI_15G Deterministic Jitter, Data-Data 5 UI TJ250UI_15G Total Jitter, Data-Data 250 UI DJ250UI_15G Deterministic Jitter, Data-Data 250 UI Condition Measured at Tx output pins peak-to-peak phase variation Random data pattern Measured at Tx output pins peak-to-peak phase variation Random data pattern Measured at Tx output pins peak-to-peak phase variation Random data pattern Measured at Tx output pins peak-to-peak phase variation Random data pattern Table 7. SATA Interface Transmitter Output Jitter Characteristics, 3 Gbit/s Symbol Parameter TJfBAND/10_3G Total Jitter, fC3dB = fBAUD/10 DJfBAND/10_3G Deterministic Jitter, fC3dB = fBAUD/10 TJfBAND/500_3G Total Jitter, fC3dB = fBAUD/500 DJfBAND/500_3G Deterministic Jitter, fC3dB = fBAUD/500 SiI-DS-0138-E Condition Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load (c) 2007-2010 Silicon Image, Inc. All rights reserved. 5 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. PCI Express Interface Timing Specifications Table 8. PCI Express Interface Timing Specifications Symbol TPCI_UI TPCI_TX_RISE_FALL TPCI_TX-IDLE-MIN TPCI_TX-IDLE-SETTO-IDLE TPCI_TX-IDLE-TOTO-DIFF-DATA TPVPERL TPERST-CLK TPERST Parameter Tx / Rx Unit Interval Rise and Fall time at transmitter Minimum time spent in Electrical Idle Maximum time to transition to a valid Electrical Idle after sending an Electrical Idle ordered set Maximum time to transition to valid TX specifications after leaving an Electrical Idle condition Power stable to PERST# inactive REFCLK stable before PERST# inactive PERST# active time Condition SSC disabled 20%-80% -- Min 399.88 0.125 50 Typ 400 -- -- Max 400.12 -- -- Unit ps UI UI -- -- -- 20 UI -- -- -- 20 UI -- -- -- 100 100 100 -- -- -- -- -- -- ms us us Min Typ Max Unit -- 65 -- ps Min -- 0.7xV DDX Typ 25 Max -- Unit MHz -- -- V PCI Express Interface Transmitter Output Jitter Characteristics Table 9. PCI Express Interface Transmitter Output Jitter Characteristics Symbol Parameter TJPCIe Total Jitter Condition Defined by PCI Express Base Specification Rev 1.1 CLKI SATA Reference Clock Input Requirement Table 10. CLKI SerDes Reference Clock Input Requirement Symbol TCLKI_FREQ Parameter Nominal Frequency Condition -- VCLKI_IH Input HIGH Voltage -- VCLKI_IL Input LOW Voltage -- -- -- 0.3xV DDX V TCLKI_J CLKI frequency tolerance -- -50 -- +50 ppm 25 MHz reference Measured at CLKI pin 10-12 Bit Error Ratio 1 sigma deviation Measured at CLKI pin 10-12 Bit Error Ratio peak-to-peak phase noise -- -- 4 ns -- -- 50 psrms -- -- 1 ns 40 -- 60 % Condition Min Typ Max Unit Peak-to-peak sine wave across 500 kHz to 3 GHz frequency range. Measured with differential probe triggered by noise source -- -- 50 mV -- -- 100 mV -- -- 200 mV TCLKI_RISE_FALL Rise and Fall time at CLKI TCLKI_RJ Random Jitter TCLKI_TJ Total Jitter TCLKI_RC_DUTY CLKI duty cycle 20%-80% Power Supply Noise Requirements Table 11. Power Supply Noise Requirement 6 Symbol Parameter VNOISE_VDDA 1.8 V Analog Power Noise VNOISE_VDDD 1.8 V Digital Power Noise VNOISE_VDDO 3.3 V IO Power Noise (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Pin Descriptions PCI Express Pins Name PRX+ PRXPTX+ PTXREFCLK+ Pin 25 26 30 29 20 REFCLK- 21 PERST_N 34 Type Differential Dir Input Description Receiver. Serial receiver differential pair; must be AC coupled. Differential Output Transmitter. Serial transmitter differential pair; must be AC coupled with a 100 nF capacitor. Differential Input Schmitt Input Reference Clock. Reference clock differential pair supplied by PCI Express system. This input signal must be compliant with PCI Express Card Electromechanical Specification, Revision 1.0a. Reset. PERST_N initializes the PCI Express interface and sets internal registers to their initial state. Flash Data and Address Pins Name FL_ADDR18 FL_ADDR17 FL_ADDR16 FL_ADDR15 FL_ADDR14 FL_ADDR13 FL_ADDR12 FL_ADDR11 FL_ADDR10 FL_ADDR09 FL_ADDR08 FL_ADDR07 FL_ADDR06 FL_ADDR05 FL_ADDR04 FL_ADDR03 FL_ADDR02 FL_ADDR01 FL_ADDR00 FL_DATA7 FL_DATA6 FL_DATA5 FL_DATA4 FL_DATA3 FL_DATA2 FL_DATA1 FL_DATA0 SiI-DS-0138-E Pin 71 70 69 68 65 64 63 62 61 59 58 57 56 55 53 52 51 50 49 47 46 45 43 42 41 40 39 Type 8 mA Dir Input output Description Flash Address. The 18 FL_ADDRnn pins are the Flash Memory address pins for up to 512 kB of flash memory. These pins have an internal 70 k pullup resistor. 8 mA Input output Flash Data. The 8 FL_DATAn pins comprise the 8-bit flash memory data bus. These pins have an internal 70 k pullup resistor. (c) 2007-2010 Silicon Image, Inc. All rights reserved. 7 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. FLSAH Control, I2C, and LED Pins Name FL_RD_N Pin 72 Type 8 mA FL_WR_N 73 8 mA FL_CS_N 74 8 mA I2C_SDAT 82 Schmitt 4 mA I2C_SCLK 83 Schmitt 4 mA LED1 LED0 36 37 Open drain 12 mA Dir Description Input Flash Read Enable. Output Active LOW. This pin has an internal 70 k pullup resistor. Input Flash Write Enable. Output Active LOW. This pin has an internal 70 k pullup resistor is required on each of these pins. Input Flash Chip Select. Output Active LOW. This pin has an internal 70 k pullup resistor. Input I2C Serial Data. Output Serial Interface (I2C) data line (internally connected to PHY I2C data line). This pin has an internal 70 k pullup resistor. Input I2C Serial Clock. Output Serial Interface (I2C) clock (internally connected to PHY I2C clock). This pin has an internal 70 k pullup resistor. Output Activity LEDs. Activity LED drivers for channels 1 and 0. Serial ATA Pins Name RX1+ RX1RX0+ RX0TX1+ TX1TX0+ TX0XTALI/CLKI Pin 4 5 18 17 9 8 13 14 87 Type Differential XTALO 86 Analog Name TMS Pin 76 Type LVTTL TCK TDI 77 78 Schmitt LVTTL TDO TRSTN 79 80 4 mA LVTTL SCAN_MODE 81 LVTTL Differential Analog Dir Input Description Receiver. Serial receiver differential pair; must be AC coupled. Output Transmitter. Serial transmitter differential pair; must be AC coupled. Input Crystal In. Crystal oscillator pin for SerDes reference clock. When an external clock source is selected, the 25 MHz external clock comes through this pin. The clock must have a 1.8 V swing and the precision recommendation is 50 ppm. Refer to Table 10 on page 6 for details. Output Crystal Out. Crystal oscillator pin for SerDes reference clock. A 25 MHz crystal must be used. Test Pins 8 Dir Input Description JTAG Test Mode Select. A 70 k pullup resistor is required on this pin. Input JTAG Test Clock. Input JTAG Test Data In. This pin has an internal 70 k pullup resistor is required on this pin. Output JTAG Test Data Out. Input JTAG Test Reset. This pin must be tied to ground if JTAG function is not used. This pin has an internal 70 k pullup resistor. Input Scan Mode. Used for factory testing; do not connect. This pin has an internal 60 k pulldown resistor. (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Power/Ground Pins All like-named power and ground pins shown in this section are connected together within the package. Name VDDSRX Description Receiver Power. These pins provide power for the Serial ATA receivers. VSSRX 6, 16 Receiver Ground. These pins provide the ground reference for the Serial ATA receivers. VDDSTX 7, 10, 12, Transmitter Power. 15 These pins provide power for the Serial ATA transmitters. VSSTX 11 Transmitter Ground. This pin provides the ground reference for the Serial ATA transmitters. VDDPRX 27 Receiver Power. This pin provides power for the PCI Express receivers. VDDPTX 32 Transmitter Power. This pin provides power for the PCI Express transmitters. VDDPTXPLL 33 PLL Power. This pin provides power for the PCI Express transmitter PLL. VDDPRXPLL 23 PLL Power. This pin provides power for the PCI Express receiver PLL. VSSA 24, 28, 31 PCI-E Ground. These pins provide the ground reference for the PCI Express SerDes. VDDSPLL 2 PLL Power. This pin provides power for the Serial ATA PLL and crystal oscillator. VSSSPLL 1 PLL Ground. This pin provides the ground reference for the Serial ATA PLL. VSSREF 22 Reference Clock Ground. This pin provides the Ground reference for the PCI-Express reference clock receiver. VDDX 85 Oscillator Power. This pin provides power for the crystal oscillator associated with the XTALI and XTALO pins. VSSX 88 Oscillator Ground. This pin provides the ground reference for the crystal oscillator. VDDO 44, 67 I/O Power. These pins provide power for the digital I/O. VDDD 38, 54, Digital Power. 75 These pins provide power for the digital logic. VSSD 35, 48, 60, Digital Ground. 66, 84 These pins provide the ground reference for the digital portion of the chip. SiI-DS-0138-E Pin 3, 19 (c) 2007-2010 Silicon Image, Inc. All rights reserved. Supply 1.8 V Ground 1.8 V Ground 1.8 V 1.8 V 1.8 V 1.8 V Ground 1.8 V Ground Ground 1.8 V Ground 3.3 V 1.8 V Ground 9 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Pin List by Pin Number See tables above for complete descriptions and more information. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name VSSSPLL VDDSPLL VDDSRX RX1+ RX1VSSRX VDDSTX TX1TX1+ VDDSTX VSSTX VDDSTX TX0+ TX0VDDSTX VSSRX RX0RX0+ VDDSRX REFCLK+ REFCLKVSSREF VDDPRXPLL VSSA PRX+ PRXVDDPRX VSSA PTXPTX+ VSSA VDDPTX VDDPTXPLL PERST_N VSSD LED1 LED0 VDDD FL_DATA0 FL_DATA1 FL_DATA2 FL_DATA3 FL_DATA4 VDDO Description PLL ground (Serial ATA) PLL power (Serial ATA) Receiver power (Serial ATA) Serial Receiver differential pair (Channel 1) Receiver ground (Serial ATA) Transmitter power (Serial ATA) Serial Transmitter differential pair (Channel 1) Transmitter power (Serial ATA) Transmitter ground (Serial ATA) Transmitter power (Serial ATA) Serial Transmitter differential pair (Channel 0) Transmitter power (Serial ATA) Receiver ground (Serial ATA) Serial Receiver differential pair (Channel 0) Receiver power (Serial ATA) Reference Clock differential pair (PCI Express) Reference Clock ground (PCI-E) PLL power (PCI Express receiver) PCI-E ground Serial Receiver differential pair (PCI Express) Receiver power (PCI Express) PCI-E ground Serial Transmitter differential pair (PCI Express) PCI-E ground Transmitter power (PCI Express) PLL power (PCI Express transmitter) Reset Digital Ground Activity LED (channel 1) Activity LED (channel 0) Digital Power Flash Data I/O Power Pin 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 ePad Name FL_DATA5 FL_DATA6 FL_DATA7 VSSD FL_ADDR00 FL_ADDR01 FL_ADDR02 FL_ADDR03 FL_ADDR04 VDDD FL_ADDR05 FL_ADDR06 FL_ADDR07 FL_ADDR08 FL_ADDR09 VSSD FL_ADDR10 FL_ADDR11 FL_ADDR12 FL_ADDR13 FL_ADDR14 VSSD VDDO FL_ADDR15 FL_ADDR16 FL_ADDR17 FL_ADDR18 FL_RD_N FL_WR_N FL_CS_N VDDD TMS TCK TDI TDO TRSTN SCAN_MODE I2C_SDAT I2C_SCLK VSSD VDDX XTALO XTALI/CLKI VSSX ePad Description Flash Data Digital Ground Flash Address Digital Power Flash Address Digital Ground Flash Address Digital Ground I/O Power Flash Address Flash Read Enable Flash Write Enable Flash Chip Select Digital Power JTAG Test Mode select JTAG Test Clock JTAG Test Data In JTAG Test Data Out JTAG Test Reset Scan Mode I2C Serial Data I2C Serial Clock Digital Ground Oscillator Power Crystal Out Crystal In Oscillator Ground Ground Note: The ePad must be connected to ground. 10 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Package Drawing An ePad must be soldered to PCB ground and the landing area must be incorporated on the PCB within the footprint of the package corresponding to the ePad. The size of this landing area should be at least the maximum size of the Exposed Pad of the package (6.65 x 6.65 mm), but can be larger. If the traces are within the maximum size of the pad, they may short to the pad when the package has an Exposed Pad with the maximum dimension. Symbol e L b D2 E2 A A1 A2 Dimensions (mm) Typ Max 0.40 0.30 0.40 0.50 0.15 0.20 0.25 5.85 6.001 6.65 5.85 6.001 6.65 0.85 0.90 0.00 0.02 0.05 0.65 0.70 Min Symbol Min A3 D D1 E E1 P 0.24 Dimensions (mm) Typ 0.20 REF 10.00 BSC 9.75 BSC 10.00 BSC 9.75 BSC 0.42 Max 12 0.60 Figure 3. Package Drawing 88 QFN SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 11 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Marking Specification Marking drawings are not to scale. Pin Location Logo SiI3132CNU LLLLLL.LL-L YYWW XXXXXXX SiI P/N Lot# (=Job#) Datecode Tracecode Figure 4. Marking Specification Ordering Information Production Part Numbers: Part 88-pin QFN lead free package with an exposed pad The universal package can be used in both lead-free and ordinary process lines. 12 (c) 2007-2010 Silicon Image, Inc. All rights reserved Part Number SiI3132CNU SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Programming Model SiI3132 Block Diagram JTAG PCI Express Configuration and Global Registers Interrupt Logic Application Interface Port Logic 0 PCI Express TxLink PCI Express PLL JTAG Boundary Scan PCI Express Transaction Layer Flash Controller I2C Controller Test Control Flash Pins EEPROM I2C Test Pins SATA PLL XTAL PCI Express Serdes PCI Express RxLink Port Logic 1 SATA XTAL PCI Express PCI Express Core SATA The SiI3132 controller programs the major logic modules illustrated in Figure 5. Figure 5. SiI3132 Block Diagram The PCI Express Core logic block provides PCI Express 1.0a compatibility. The Global Register File block corresponds to the registers addressed by Base Address Register 0; refer to PCI Express Capability section on page 44 for more information. The initialization function provided by the I2C Controller and Flash Controller is described in the PCI Express Capability section on page 44. SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 13 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. SiI3132 SATA Port Block Diagram The block diagram illustrated in Figure 6 shows the logic structure of each of the SiI3132 SATA Ports. PCI Exp - LRAM DMA Controller Data Path A 2 Addresses Local Arbiter Command Fetch FIFO 31 x 5 Command Fetch Machine Command Execute FIFO 31 x 5 Port Register File Command Receive FIFO 31 x 5 PCI Exp - SATA DMA Controller Data Path B 1 Address Data Path A (Initiator / Target) P o r t Initiator A PCI Exp Application Interface P o r t Rx FIFO Registers B SATA PHY Data Path B (Initiator) Target LRAM 512 x 64 Dual Port Command Execution Machine Data Path B PCI Exp / SATA Data FIFO 256 x 64 SATA Enhanced Link Figure 6. Port Logic Block Diagram The Port Logic consists of: * a Local Arbiter that arbitrates between the two DMA Controllers * a DMA Controller for the PCI Express to LRAM Data Path * a DMA Controller for the PCI Express to Serial-ATA Data Path * a 512 x 64 Local RAM (LRAM) that contains: 31 LRAM slots each of which is 128 bytes (16 Qwords) and 128 bytes used to support 16 Port Multiplier devices (1 Qword per device) * a data FIFO that contains 2048 bytes (256 Qwords) * a state machine to fetch commands * a state machine to execute commands * a serial-ATA Link * a serial-ATA PHY Each of the two state machines has an associated FIFO which, when not empty, indicates that processing is required. The FIFO is loaded with a 5-bit command slot number to activate a state machine. The slot number can range from 0 to 30, corresponding to the maximum number of active commands supported. Command flow begins with a host driver building a command in a non-cached region of host memory. The data structure is referred to as a PRB (Port Request Block). The 64-byte PRB is transferred into an available command slot in the LRAM by one of two methods: the direct method or the indirect method. The host driver is responsible for determining which slots are available. Either of the two command transfer methods may be used for each command transfer. The two methods are described in the following sections. 14 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Data Sheet Direct Command Transfer Method - Host controlled write to Slot In systems that have the capability to perform burst writes, this is the preferred method of command transfer. Embedded systems would most likely use this method. LRAM is directly mapped through use of Base Address Register 1 and appears as a block of memory to the host driver. The host driver writes the PRB contents into the appropriate slot in LRAM. Ideally, this operation is performed as a single PCI Express transaction. The 5-bit slot number (0-30) is written to the Command Execution FIFO. The Active bit associated with the selected slot becomes set in the Global Port Slot Status register. The Command Fetch FIFO and Command Fetch State Machine are not used for the direct method of command transfer. Indirect Command Transfer Method - SiI3132 controlled command transfer The host driver builds a PRB in host memory, selects a free slot, and writes the physical address of the PRB into the Command Activation register corresponding to the selected slot. This causes the SiI3132 controller to push the 5-bit slot number (0-30) into the Command Fetch FIFO. The Command Fetch State Machine, while in an idle state, continuously interrogates the Command Fetch FIFO for a non-empty condition. Upon retrieval of a 5-bit slot number from the FIFO, the Command Fetch State Machine retrieves the physical address of the PRB from the corresponding Command Activation register, sets the Active bit associated with the selected slot in the Port Slot Status register, and queues a PCI Express read of the PRB into the associated Slot in LRAM. The Command Fetch State Machine waits for completion of the transfer, pushes the 5-bit slot number into the Command Execution FIFO, and returns to the idle state, waiting for a non-empty condition in the Command Fetch FIFO. The Command Execution State Machine is responsible for directing the flow of the command and response FISs between the command slot and the Serial ATA link, directing the flow of data between PCI Express and the Serial ATA link, and posting completion status to the host. It is also responsible for error handling when exceptions occur in the normal command flow. Command execution begins when the idle Command Execution State Machine recognizes that the Serial ATA bus is in a non-busy state and the Command Execution FIFO is non-empty. The Command Execution State Machine retrieves the 5bit slot number (0-30) from the Command Execution FIFO and uses it to index the command slot in LRAM. The command FIS is addressed and sent to the Serial ATA link to be sent to the device. Control flags in the command slot determine the type of data transfer. The Command Execution State Machine waits for a response FIS from the device and directs its activities accordingly. If the received FIS is a data FIS, the DMA address and count are determined by examining the scatter/gather entries in the PRB and, if necessary, walking a scatter/gather table. The DMA address and count are loaded into the DMA controller and the controller is armed. A DMA activate FIS causes similar behavior, with data flowing from PCI Express to the Serial ATA link. When the command has completed, the Command Completion bit in the Port Interrupt Status register is set to reflect the successful completion of the command. If an error occurred, the Command Error bit is set in the Port Interrupt Status register. The basic command flow proceeds as follows: 1. The host builds a 64-byte Port Request Block (PRB) that contains: * The Register- Host to Device FIS to send to the SATA device. * Up to two scatter/gather entries to define regions of host memory to be accessed for associated read/write data. Additional scatter/gather entries may be associated with the command. * Various optional control flags to direct the SiI3132 controller to perform special processing, to control interrupt assertion, to vary the normal protocol flow, etc. 2. The host issues the command to the SiI3132 controller. 3. The controller executes the command, performing all interaction with the SATA device and transferring data between host memory and the SATA device. 4. The controller asserts a PCI Express interrupt to indicate command completion. 5. The host reads the SiI3132 port slot status to determine which command(s) have completed. SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 15 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Data Structures The Command Slot Each port within the SiI3132 controller contains 31 command slots. The slots are numbered 0 through 30. Each command issued by the host occupies a single command slot. The host decides which slot to use and issues a command to the selected slot. A command slot occupies 128 bytes within the SiI3132 RAM array and consists of a 64-byte PRB (Port Request Block) and a 64-byte scatter/gather table. The host builds the PRB. It contains the Register-Host to Device FIS to transmit to the attached SATA device and up to two scatter/gather entries that define host memory regions to be used for any read/write data associated with the command. If more scatter/gather entries are required to define additional host memory regions, the controller will fetch them from host memory as needed. The host may append the additional SGT (scatter/gather table) entries to the PRB, or one of the scatter/gather entries in the PRB may be used to define an SGT that resides in host memory. The host may issue commands to any number of available command slots. The host may freely intermix non-queued, legacy queued, native queued, PIO, and DMA command types in any available slot. Commands are always executed in the order that they were issued. The controller enforces command type issuance to the SATA device and does not allow incompatible command types to be issued to a device. This relieves the host of the burden of making sure that incompatible command types are not intermixed in the device. The host is responsible for managing slot usage. The host must keep track of which slots have commands outstanding and which slots are available for new commands. Issuing a command to a slot that is currently in use will result in unpredictable behavior. For queued commands, the slot number is used as the queue tag. The host must ensure that the tag number in the Register-Host to Device FIS defined in the PRB matches the slot number to which the command is issued. The Scatter/Gather Entry (SGE) A scatter/gather entry (SGE) defines a region of host memory to be used for data transfer associated with a command. Each scatter/gather entry defines a single contiguous physically addressed region. Table 12. Scatter/Gather Entry (SGE) 31 0 Data Address Low TRM (31) LNK (30) DRD (29) 0x00 Data Address High 0x04 Data Count 0x08 XCF (28) Reserved[27:0] 0x0C The first quadword, at offset 0, contains the physical address of the region in host memory. The entire 64-bit address must be defined. On 32-bit systems the upper 32 bits must be zero. The data address may point to a region to be used for data transfer, or it may point to a Scatter/Gather Table (SGT), which is a collection of four SGEs. The LNK bit (bit 30 at offset 0x0C) defines the type of region. When LNK is zero, the region is a data region; when LNK is one, the region is a scatter/gather table that will be fetched by the SiI3132 controller to obtain a data region definition. The Data Count field at offset 0x08 defines the length, in bytes, of the contiguous data region. When the LNK bit is set to one, indicating an SGT link, the controller ignores this field. The TRM bit (bit 31 at offset 0x0C), when set to one, indicates that this is the final SGE associated with the command and no additional SGEs follow it. The DRD bit (bit 29 at offset 0x0C), when set to one, directs the controller to discard the data read from the device for the length associated with the data count. When this bit is set to one, the controller ignores the data address. The XCF bit (bit 28 at offset 0x0C) indicates whether the region defined by this SGE is to be used for data transfer (XCF set to 0) or an external command fetch (XCF set to 1). See the External Command PRB Structure section on page 22 for additional information on external command processing. The Scatter/Gather Table (SGT) The SGT is a contiguous collection of four SGEs. The PRB contains two SGEs. When more than two SGEs are required to fully define the entire data transfer of a command, the SiI3132 controller fetches them in groups of four SGEs at a 16 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. time, which is one SGT. The SGT occupies the upper 64 bytes of a command slot in SiI3132 RAM. When needed, only one SGT resides in RAM at a time. The controller fetches each required SGT, overwriting the previous SGT in RAM. Because the first two SGEs reside in the PRB RAM area, they are always available in case the controller needs to rescan the scatter/gather list for out-of-order data delivery. SGTs must reside on a quadword-aligned boundary in host memory. In other words, bits[2:0] of the physical address of the SGT in host memory must be zero. Table 13. Scatter/Gather Table (SGT 31 0 SGE0 Data Address Low 0x00 SGE0 Data Address High 0x04 SGE0 Data Count SGE0 TRM SGE0 LNK SGE0 DRD SGE0 XCF 0x08 Reserved[27:0] SGE1 Data Address Low 0x10 SGE1 Data Address High 0x14 SGE1 Data Count SGE1 TRM SGE2 TRM SGE1 LNK SGE2 LNK SGE1 DRD SGE1 XCF 0x18 Reserved[27:0] SGE3 LNK 0x1C SGE2 Data Address Low 0x20 SGE2 Data Address High 0x24 SGE2 Data Count 0x28 SGE2 DRD SGE2 XCF Reserved[27:0] 0x2C SGE3 Data Address Low 0x30 SGE3 Data Address High 0x34 SGE3 Data Count SGE3 TRM 0x0C SGE3 DRD SGE3 XCF 0x38 Reserved[27:0] 0x3C The Port Request Block (PRB) The host builds a PRB to define a command to be executed by the controller. The PRB occupies the first 64 bytes of a command slot in SiI3132 RAM. Once a command is issued, the PRB is overwritten in the RAM as necessary to keep track of command context and execution status. The host should not depend on being able to read the contents of the PRB in slot RAM after a command is issued. Upon completing command execution the PRB area of the command slot may contain status information that can be read by the host, depending on the command type. The PRB structure can take several forms, depending on the command type that it defines. The PRB contains the following major elements: * A Control Field to indicate the type of PRB and any features to execute. * A Protocol Override field that can alter the normal SATA protocol flow. * A FIS area that contains the initial FIS to be transmitted to the device upon PRB execution. * Up to two scatter/gather entries (SGEs) to define areas of host memory that will be used for any data transfer associated with the PRB. For PACKET commands, the first SGE contains the 12- or 16-byte ATAPI command to be transmitted to the device. Regardless of whether the command is to be issued with the direct or indirect method, the host driver should build the PRB as a structure in host memory. If the command is to be issued using the direct method, the PRB can be copied from host RAM to the appropriate slot in RAM. If the command is to be issued using the indirect method, the host driver should write the physical address of the PRB to the Command Activation register associated with the desired command slot. The PRB must reside on a quadword-aligned boundary in host memory. In other words, bits[2:0] of the physical address of the PRB in host memory must be zero. The PRB can take various forms, depending on the type of command being issued. The command types are: Standard ATA Commands. This includes all the common ATA commands such as READ SECTORS, WRITE SECTORS, READ DMA, WRITE DMA, IDENTIFY DEVICE, SMART, etc. Also included are the queued SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 17 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. commands in both legacy and SATA native queue modes. For these commands, the PRB contains the entire Register - Host to Device FIS containing the ATA command. By default, the controller decodes the ATA command type and executes the necessary SATA protocol automatically. As an option, the host driver can execute any desired SATA protocol on a per-command basis. PACKET Commands. ATAPI PACKET commands operate in a similar fashion to the standard ATA commands. The Register - Host to Device FIS contains the ATA PACKET command. The 12- or 16-byte ATAPI command is placed in the area normally reserved for the first SGE. The SiI3132 controller does not decode the contents of the 12- or 16-byte ATAPI command, so the host driver indicates the direction of any data transfer associated with the command. Soft Reset. A special form of the PRB instructs the controller to transmit a soft-reset sequence to a device. The controller creates the necessary Register-Host to Device FISs required for the sequence. No SGEs are required for this PRB type. Other than the control field, the only item that needs to be populated is the PMP field, to direct the soft reset sequence to the proper device in the event that a port multiplier is attached. Upon successful command completion, the Register-Device to Host FIS is available in the command slot, allowing the host driver to view the device signature. External Command. The external command feature allows the host driver to transmit any arbitrary FIS that will not fit in the FIS area of the PRB. This feature is useful in custom applications that have a need to send large FISs or Data FISs in a fashion that does not comply with the defined SATA protocol. Interlocked FIS Reception. The interlocked FIS feature allows the host driver to receive any desired FIS type directly to a host memory buffer, bypassing all SATA protocol for that FIS type. To use this feature, the host first specifies the FIS type(s) to be interlocked. Then, any number of available command slots can be reserved for the reception of FISs matching the defined type(s). The PRB Control Field The Control Field (offset 0x00, bits [15:0]) is used to indicate the type of PRB and features that are desired. For a standard ATA command, this field will normally contain a default value of 0x0000. Table 14 describes the bit functions for each bit in the Control Field. Table 14. Control Field Bit Definitions Bit 0 Name control_protocol_override 1 2 control_retransmit control_external_command 3 control_receive 4 control_packet_read 5 control_packet_write 6 control_interrupt_mask 7 15:8 18 control_soft_reset reserved Description The Protocol Override Field is to be used instead of the default protocol for this command. Allows retransmission if an error occurs during an external command transmission. The command FIS shall be fetched from host memory. This feature is used to send arbitrary FISs that will not fit in the command FIS area of the PRB. Reserves a command slot to be used to receive an interlocked FIS as described by the port FIS_CONFIG register. Indicates that the packet command associated with this PRB will transfer data from the device to the host. This bit must be set for all packet commands that perform read data transfers. Indicates that the packet command associated with this PRB will transfer data from the host to the device. This bit must be set for all packet commands that perform write data transfers. Setting this bit to one will prevent the SiI3132 controller from issuing a normal successful completion interrupt for this command. Causes the SiI3132 controller to issue a soft reset FIS sequence to the device. Must be zero (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. The PRB Protocol Override Field The Protocol Override Field (offset 0x00, bits [31:16]) is used to specify a protocol behavior other than the default for this PRB. PRBs for which the default protocol is to be used should set this field to 0x0000. The SiI3132 controller will decode the 8-bit ATA command at PRB offset 0x0A and automatically execute the default protocol for the command. In certain cases it might be desirable to specify a non-default protocol to be used, such as with vendor specific device commands. To override the protocol, the host driver must set control_protocol_override (Control Field, bit 0) to 1 and place the desired protocol in this field. Table 15 on the next page describes the Protocol Override bit definitions. Table 15. Protocol Override Bit Definitions Bit 16 17 18 19 20 21 Name protocol_packet protocol_legacy_queue protocol_native_queue protocol_read protocol_write protocol_transparent 31:22 Description This command is to be executed as an ATAPI packet command. This command is to be executed as an ATA legacy queued command. This command is to be executed as a SATA native queued command. This command is expected to transfer data from device to host. This command is expected to transfer data from host to device. This command is to be executed with no protocol. After the initial command FIS is successfully sent to the device, completion status will be posted without waiting for additional device transmissions. Must be zero. Reserved There is no distinction between DMA and PIO data transfers in the protocol. The SiI3132 controller is a native Serial ATA device and relies on the SATA interface protocol to determine the data transfer type between the device and the controller. From the host driver perspective, all commands, whether PIO or DMA, transfer data through use of scatter/gather entries defined in the PRB and scatter/gather tables. Standard ATA Command PRB Structure Table 16 shows the layout for standard ATA commands. The Control and Protocol override fields must be populated as described above. Table 16. Port Request Block for Standard ATA Command 31 0 Protocol Override Control 0x00 Received Transfer Count (Reserved Input) Features / Error Command / Status C R R R 0x04 PMP FIS Type 0x08 Dev/Head Cyl High Cyl Low Sector Number 0x0C Features (Exp) Cyl High (Exp) Cyl Low (Exp) Sector Num (Exp) 0x10 Device Control Reserved Sector Count (Exp) Sector Count 0x18 Reserved - Must Be Zero 0x1C SGE0 Data Address Low 0x20 SGE0 Data Address High 0x24 SGE0 Data Count SGE0 TRM SGE0 LNK SGE0 DRD SGE0 XCF 0x28 Reserved[27:0] SGE1 LNK SGE1 DRD 0x2C SGE1 Data Address Low 0x30 SGE1 Data Address High 0x34 SGE1 Data Count SGE1 TRM 0x14 Reserved SGE1 XCF 0x38 Reserved[27:0] 0x3C The Received Transfer Count field (offset 0x04) is reserved as an input to the SiI3132 controller and should be populated with a value of all zeroes. Upon successful command completion, this field will contain the total number of SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 19 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. data bytes received during the command execution. The host driver may use this field to determine the transfer size for commands in which the total transfer size is unknown, such as ATAPI inquiries. The FIS area (offset 0x08 through 0x1F) must be populated with the initial FIS to be sent to the device. This area contains the FIS header and all task file registers to describe the ATA command. Table 17 describes the FIS area fields. Table 17. PRB FIS Area Definition Offset 0x08 0x0C 0x10 Bit(s) 7:0 Name FIS Type 11:8 PMP 14:12 15 Reserved Command/Device Control 23:16 31:24 7:0 15:8 23:16 31:24 Task File Command Features Sector Number (LBA[7:0]) Cylinder Low (LBA[15:8]) Cylinder High (LBA[23:16]) Device/Head (LBA[27:24] for nonextended commands) Sector Number (Exp.) (LBA[31:24] for extended commands) Cylinder Low (Exp.) (LBA[39:32] for extended commands) Cylinder High (Exp.) (LBA[47:40] for extended commands) Features (Exp.) Sector Count Sector Count (Exp.) Reserved Device Control Reserved 7:0 15:8 23:16 0x14 0x18 20 31:24 7:0 15:8 23:16 31:24 31:0 Description The FIS type field must be populated with a valid SATA FIS type. In all but special custom cases this value will be 0x27, which defines a Register-Host to Device FIS type. 4-bit Port Multiplier Port field that defines the port to which this command is directed. If no port multiplier is attached, this field should be populated with all zeros. Must be zero. This bit must be set to 1 to indicate that this FIS contains a command. Populate with the desired ATA command type. Populate with the desired features for this ATA command. These fields should be populated with desired commandspecific parameters. These fields should be populated with desired commandspecific parameters. These fields should be populated with desired commandspecific parameters. The Reserved field must be 0 for standard ATA commands that use the Register -Host to Device FIS to initiate a command. This field is reserved and must be 0 for standard ATA commands that use the Register - Host to Device FIS to initiate a command. (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. PACKET Command PRB Structure Table 18 shows the layout for PACKET commands. The Control and protocol override fields must be populated as described above. The PACKET PRB FIS area is structured the same as a standard ATA command. The FIS area contains the PACKET ATA command. After the initial PACKET command is transmitted, the device responds with a PIO Setup FIS, requesting a 12- or 16-byte ATAPI command. The host driver must populate the area normally used for the first SGE with the desired ATAPI command. The length of the ATAPI command is determined by the value of the packet length bit (Port Control, bit 5). If packet length is 0, 12 bytes are transmitted. If packet length is one, 16 bytes are transmitted. The packet length field must be initialized with the packet length value returned by the device in the IDENTIFY PACKET command. Table 18 on the next page shows a representative 12-byte ATAPI command layout. The highlighted ATAPI packet is an example typical of some commands; other command packets will have different formats within the highlighted bytes. Table 18. Port Request Block for PACKET Command 31 0 Protocol Override Control 0x00 Received Transfer Count Features / Error Command / Status C R R 0x04 R PMP FIS Type 0x08 Dev/Head Cyl High Cyl Low Sector Number 0x0C Features (Exp) Cyl High (Exp) Cyl Low (Exp) Sector Num (Exp) 0x10 Device Control Reserved Sector Count (Exp) Sector Count 0x14 Reserved 0x18 Reserved - Must Be Zero 0x1C LBA LBA (MSB) Reserved ATAPI opcode 0x20 XFR Length (MSB) Reserved LBA (LSB) LBA 0x24 Reserved SGE1 TRM SGE1 LNK SGE1 DRD XFR Length (LSB) 0x28 Reserved 0x2C SGE1 Data Address Low 0x30 SGE1 Data Address High 0x34 SGE1Data Count 0x38 SGE1 XCF Reserved[27:0] 0x3C The SiI3132 controller does not decode the ATAPI command to determine the necessity or direction of any associated data transfer. The host driver must supply this information by setting control_packet_read (control field, bit 4) or control_packet_write (control field, bit 5) for any PACKET command that requires data transfer. Failure to set one of these bits for an ATAPI command that requests data transfer will result in an Overrun or Underrun Command Error condition. SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 21 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Soft Reset PRB Structure To send a soft-reset sequence, the host driver only needs to fill in the PMP field (offset 0x8, bits[11:8]) and set control_soft_reset (control field, bit 7). The controller will send a soft reset sequence to the device and wait for a Register - Device to Host FIS to deliver the device signature and terminate the command. Upon successful command completion, the host may inspect the FIS area of the slot in SiI3132 RAM (offset 0x08 through 0x1F) to determine the returned device signature. A soft reset is executed in the same manner as other PRBs, in the order in which it was issued. Port Ready (Port Status, bit 31) must be 1 in order to issue this command. The lightly shaded areas of Table 19 depict valid fields in slot RAM following successful command completion. These fields do not need to be supplied as inputs and may remain in any state upon command issuance. Table 19. Port Request Block for Soft Reset Command 31 0 N/A Control (0x0080) 0x00 N/A C 0x04 Features / Error Command / Status FIS Type 0x08 Dev/Head Cyl High R Cyl Low R R PMP Sector Number 0x0C Features (Exp) Device Control Cyl High (Exp) Reserved Cyl Low (Exp) Sector Count (Exp) Sector Num (Exp) Sector Count 0x10 0x14 N/A 0x18 N/A 0x0C N/A 0x10 N/A 0x14 N/A 0x18 N/A 0x1C N/A 0x20 N/A 0x24 N/A 0x28 N/A 0x2C N/A 0x30 N/A 0x34 N/A 0x38 N/A 0x3C External Command PRB Structure An external command PRB is indicated by setting control_external_command (control field, bit 2). External commands execute in a manner similar to standard commands except that the initial command FIS is fetched from host memory instead of the PRB FIS area. By default, an external command uses the transparent protocol. That means the command is terminated immediately following the successful transmission of the external command FIS. If this is not the desired protocol, the host driver can set control_protocol_override (control field, bit 0) and place the desired protocol in the Protocol Override field (offset 0x00, bits [31:16]). The external command FIS length may be of any size (up to the 8 kB SATA limit) and is automatically padded to a Dword boundary. The SiI3132 controller will frame the FIS, adding SOF, EOF, and CRC. The host memory FIS image must contain the FIS header (FIS Type, PMP, etc.). The PRB PMP field (offset 0x08, bits [11:8]) must be populated to direct the FIS to the desired port multiplier port, or must be 0 if no port multiplier is attached. For port multiplier applications, it is important that the PMP field in the host-resident FIS and the PRB match for proper operation. The location of the external command FIS is defined in additional SGEs with the XCF bit (SGE offset 0x0C, bit 28) set to one. Any type of command may be sent using an external command, including commands that have associated data transfers. Data transfer host memory locations are defined in SGEs with the XCF bit (SGE offset 0x0C, bit 28) set to zero. SGEs used to define the external command FIS and SGEs used to define data transfer may be freely mixed in any order. The presence or absence of the XCF bit informs the controller whether an SGE should be used for the current transfer operation. 22 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Table 20. Port Request Block for External Commands 31 0 Protocol Override Control 0x00 Received Transfer Count Reserved N/A 0x04 PMP Reserved N/A 0x0C N/A 0x10 N/A 0x14 N/A 0x18 Reserved - Must Be Zero 0x1C SGE0 Data Address Low 0x20 SGE0 Data Address High 0x24 SGE0 Data Count SGE0 TRM SGE1 TRM SGE0 LNK SGE1 LNK 0x08 SGE0 DRD SGE0 XCF 0x28 Reserved[27:0] 0x2C SGE1 Data Address Low 0x30 SGE1 Data Address High 0x34 SGE1 Data Count 0x38 SGE1 DRD SGE1 XCF Reserved[27:0] 0x3C Interlocked Receive PRB Structure Reserving a command slot to receive an interlocked FIS is indicated by setting control_receive (control field, bit 3). To receive an interlocked FIS into host memory, the host driver first specifies the FIS type(s) to be interlocked by writing the appropriate value to the Port FIS Configuration register (port registers, offset 0x1028). The PRB is populated with SGEs that define the host memory region(s) that will be used to receive the interlocked FIS. When a FIS of the defined type is received, it is written to the defined host memory area and the command is completed. If an error occurs during receipt of the FIS, or if the SGEs define an area that is not large enough to contain the entire FIS, the FIS is rejected with an R_ERR response and the command is not completed. When an interlocked FIS is received without error into a memory region that is large enough to contain it, the command is successfully completed and the host driver may use the received FIS in any manner. The command slot is then free, and can be redefined as a receive slot or as any other command type. After successfully receiving an interlocked FIS, the low-level link will be receiving WTRM primitives from the transmitting device, which is expecting a response. By default, the controller waits for the host driver to write a response bit to the port control register. If the host driver writes Interlock Accept (Port Control Set register, bit 12), an R_OK response is transmitted. If the host driver writes Interlock Reject (Port Control Set register, bit 11), an R_ERR response is transmitted. The host driver may also choose to set Auto Interlock Accept (Port Control Set register, bit 14) before performing interlocked operations. By setting this bit, an R_OK response is sent for all subsequently received interlocked FISs, without additional intervention from the host driver. In this mode, it is possible to receive one or more additional interlocked FISs before the host driver has had a chance to reserve command slots to receive them. If this occurs, any interlocked FIS that arrives without a reserved slot available will be acknowledged and discarded. SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 23 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Table 21. Port Request Block For Receiving Interlocked FIS 31 0 Protocol Override Control Received Transfer Count 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 Reserved - Must Be Zero 0x1C SGE0 Data Address Low 0x20 SGE0 Data Address High 0x24 SGE0 Data Count SGE0 TRM SGE1 TRM SGE0 LNK SGE1 LNK SGE0 DRD SGE0 XCF 0x28 Reserved[27:0] 0x2C SGE1 Data Address Low 0x30 SGE1 Data Address High 0x34 SGE1 Data Count 0x38 SGE1 DRD SGE1 XCF Reserved[27:0] 0x3C Operation Methods to Issue Commands Before a command is executed, it must reside in a slot in SiI3132 controller RAM and must inform the controller that the PRB is ready to be executed. To accomplish this, the host must issue the command in one of two ways: Indirect Method. The indirect method is the most common and flexible method of issuing commands. With this method, the host builds the PRB in host memory and writes the physical address of the PRB into one of 31 Command Activation registers, each associated with a command slot. This causes the controller to fetch the PRB from host memory and deposit it in the selected slot of SiI3132 RAM. After the command is fetched, the controller automatically informs the execution unit that the command is ready for execution. The host may issue commands through additional Command Activation registers at any time regardless of whether the previous PRB has been fetched. The controller will fetch the PRBs in the order requested when the necessary resources are available. Direct Method. The host may write the 64-byte PRB directly into SiI3132 slot RAM. The RAM area is defined in the port register map and the host can easily calculate the slot offset to write the PRB. After the PRB is written to RAM, the host informs the execution unit that it is ready to process by writing the slot number into the command execution FIFO register. When the direct command issue method is used, it is not possible to append scatter/gather entries to the PRB without defining a LNK in one of the PRB resident scatter/gather entries. Reset and Initialization The SiI3132 controller has a hierarchical reset structure that allows initialization of the entire chip, a single port, an attached device, or the internal command queue. In general, asserting a reset at a HIGH level causes all underlying circuits to be reset. There are five levels of reset and initialization possible. The resets, listed from highest to lowest level, are described in the sections that follow. PERST# Reset The PERST# reset pin, when asserted, holds the entire chip in a reset state. All configuration, global, and port registers are initialized to their default state. When de-asserted, PCI Express configuration space is programmable, but the global 24 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Data Sheet and port register spaces and the port state machines/command queue remain in a reset state until the Global and Port Resets are de-asserted through software control. Global Reset The Global Reset (Global Control register, bit 31), when asserted, initializes all global registers, except PHY Configuration, and all port registers to the default state. All port resets are set to one (asserted) while Global Reset is asserted. The Global Reset must be cleared to 0 to allow access to the global register space or to release any Port Reset. Software may use the Global Reset to initialize all ports with a single operation. Port Reset Each port contains a Port Reset bit (Port Control Set and Port Control Clear registers, bit 0) that remains set to 1 after the Global Reset is cleared to zero. While Port Reset is asserted, all port registers, except Port PHY Configuration and OOB Bypass (Port Control Set/Clear, bit 25), are initialized to their default state. The port state machines are reset and the command queue is cleared. The Port Reset must be cleared to 0 by writing a 1 to bit 0 of the Port Control Clear register to release the Port Reset condition. Software may assert the port reset condition at any time by writing a 1 to bit 0 of the Port Control Set register. Device Reset Each port contains a Device Reset (Port Control Set, bit 1) that may be used by software to reset an attached device without affecting the contents of the port registers. Writing a 1 to bit 1 of Port Control Set causes the execution state machines and pending command queue to be initialized. Then, a COMRESET is transmitted to the attached device. The effect of this sequence is to clear any outstanding commands and reset the attached device. The Device Reset bit is selfclearing. After the reset sequence has completed, the bit will be cleared to 0. Port Initialize Each port contains a Port Initialize (Port Control Set, bit 2) that may be used by software to initialize the port data structures without affecting the contents of the port registers or resetting the device. Writing a 1 to bit 1 of Port Control Set causes the execution state machines and pending command queue to be initialized. The effect of this sequence is to clear any outstanding commands. The Port Initialize bit is self-clearing. After the initialization sequence has completed, the bit will be cleared to 0. Port Ready Each port contains a Port Ready indicator (Port Status, bit 31) that is cleared to 0 by any of the above reset conditions. The Port Ready signal, when 1, indicates that the port is ready to execute commands. For all resets except Port Initialize, the Port Ready signal will not be asserted until a PHY ready condition is achieved. When Port Initialize is set, Port Ready will be cleared to 0 then set to 1 after any currently active data transfers or FIS transmission or reception operations have completed and port initialization has completed. Port Reset Operation Upon release of Port Reset, the low-level power management state machine is enabled and OOB signaling is initiated to the device. The SiI3132 controller starts OOB signaling by transmitting a COMRESET to the device. If the device responds with COMINIT and the OOB sequence is successful, a PHY ready condition results, indicating that a link has been successfully established and the device may transmit an initial register FIS. At this time, the Port Ready signal will be asserted, indicating that the host driver may issue commands. If the device does not respond within the prescribed time allowed for OOB, the low-level power management machine initiates another OOB sequence after a fixed delay. The period between OOB attempts is approximately 100 ms. Upon receipt of an initial Register - Device to Host FIS that clears the task file status BSY state, the port is allowed to transmit commands to the device. Initialization Sequence The following is an example sequence of events that software might use to initialize the controller and enumerate an attached device or port multiplier. The sequence assumes that the system is powered up, the PERST# Reset has been deasserted, and the system has enumerated the PCI Express bus. Configuration space, including the Base Address Registers, has been initialized. It is now necessary to enable each port and to determine the device type, if any, that is attached to that port. SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 25 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Initialize Port and Retrieve Device Signature These steps initialize each port and retrieves the device signature for that port. Perform these steps for each port to be initialized. 1. Remove the Global Reset by writing 0x00000000 to the Global Control register (Global offset 0x40). 2. Clear Port Reset by writing 1 to the Port Reset bit of the Port Control Clear register (Port offset (port 0x2000) + 0x1004, bit 0). 3. If 32-bit platform and 32-bit activation is desired, write a 1 to the 32-bit Activation bit of the Port Control Set register (Port offset (port 0x2000) + 0x1000, bit 10). 4. To enable interrupts for command completion and command errors, write 0x00000003 to the Port Interrupt Enable Set / Port Interrupt Enable Clear (Port offset (port 0x2000) + 0x1010). 5. To determine if device is present, poll the SStatus register (Port offset (port 0x2000) + 0x1f04) for a PHYRDY condition indicated if the DET field (bits[3:0]) have a value of 0x3. 6. Wait until the Port Ready bit in the Port Status register (Port offset (port 0x2000) + 0x1000, bit 31) is set to 1. If desired, an interrupt may be armed in the Port Interrupt Set Register (bit 2). Any change in Port Ready state asserts an interrupt. 7. If the software supports port multipliers, build a Soft Reset PRB in host memory. Set the PMP field to 0x0F to direct the command to the control port of the port multiplier. Issue the command to any available slot. Important: If the software does not support port multipliers, skip this step. Sending this command will cause the port multiplier to disable legacy access to device 0. 8. Upon successful completion of the soft reset command, read the device signature from the command slot (Port offset (port 0x2000) + (slot 0x80) + 0x14(LSB), 0x0C, 0x0D, 0x0E(MSB)). 9. Continue with one of the following, depending on the device signature: a. If the signature is 0x96690101, perform the Port Multiplier Enumeration Procedure. b. If the signature is 0xEB140101, perform the ATAPI PACKET Device Procedure. c. If the signature is 0x00000101, perform the Disk Drive Procedure. 10. Repeat Steps 2 through 9 for each port to be initialized. Port Multiplier Enumeration Procedure The attached device is a port multiplier. Perform these steps. 1. Enable Port Multiplier context switching by writing a 1 to PM Enable in the Port Control Set register (Port offset (port 0x2000) + 0x1000, bit 13). 2. Read the Port Multiplier GSCR[2] register by issuing a Read Port Multiplier command to the control port. This register contains the number of device ports on the Port Multiplier. 3. Enable the PHY by writing a 1, then a 0, to the SControl register (PSCR[2]) DET field. Issue a Port Multiplier Write command for each of these operations. 4. Wait for a PHYRDY condition in the port by polling the Port Control Set register (PSCR[0]) . 5. Clear the X-bit and all other error bits in the SError register (PSCR[1]) by writing all ones to the register with a Write Port Multiplier command. The port is now ready for operation. 6. Issue a Soft Reset command with the PMP field set to the appropriate port. This will return a device signature for the attached device. 7. Issue the appropriate Identify Device or Identify Packet Device command and any associated Set Features, Set Write Multiple commands necessary to initialize the device. 8. Repeat Steps 3 through 7 for each Port Multiplier Device Port. ATAPI PACKET Device Procedure The attached device is an ATAPI PACKET device. Perform these steps. 1. Issue an Identify Packet Device command to get device specific parameters. 2. While the drive is not ready and timeout has not expired, issue the Test unit ready PACKET command. 3. If the command completes successfully, go to Step 5. 4. If the command error indicates a Device error condition due to drive not ready, do the following: a. Write a 1 to the Port Control Set Register (port 0x2000) + 0x1000, bit 2). b. Wait until Port Ready in Port Status register (Port offset (port 0x2000) + 0x1000, bit 31) is 1. If desired, an interrupt may be armed by setting bit 2 in the Port Interrupt Enable Set / Port Interrupt Enable Clear to 1. Any change in Port Ready state asserts an interrupt. 5. The drive is ready for use. Issue appropriate Set Features, Set Read Multiple commands as needed. 26 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Disk Drive Procedure The attached device is a disk drive. Perform these steps. 1. Issue an Identify Device command to get device-specific parameters 2. The drive is ready for use. Issue appropriate Set Features, Set Read Multiple commands as needed. Interrupts and Command Completion Each port of the controller produces a single interrupt, which is an accumulation of various possible interrupt events. In its default mode, the device combines the interrupts from the ports into a single interrupt that may be used either for INTA emulation or for a Message Signaled Interrupt. In certain embedded environments, it might be desirable for each port to generate an independent interrupt. Software may configure each port to direct its interrupt to one of four emulated interrupts. The Interrupt Steering field in the Port Interrupt Enable Set / Port Interrupt Enable Clear register (Port offset 0x1010/1014, bit [31:30]) is used to direct the port interrupt. By default, this field is set to 0, indicating that the interrupt is directed to INTA. The register may be set to one of four values, shown in Table 22. Table 22. Interrupt Steering Interrupt Steering Value 0 1 2 3 Interrupt INTA INTB INTC INTD Interrupt Sources Figure 7 on page 29 depicts a logical representation of the interrupt routing for the SiI3132 controller. For each port, the possible interrupt causes are: Command Completion. Indicates that one or more commands have successfully completed. This interrupt is cleared in one of two ways, depending on the state of Interrupt NCoR (Port Control Set register, bit 3). Reading the Global Port Slot Status register clears this interrupt condition if Interrupt NCoR is 0. Writing a one to bit 0 or bit 16 of the Port Interrupt Status register clears this interrupt condition if Interrupt NCoR is 1. This interrupt is enabled or disabled with the corresponding bit in the Port Interrupt Enable Set / Port Interrupt Enable Clear register. Command Error. Indicates that a command did not complete successfully. The port Port Command Error register will contain an error code indicating the actual cause of failure. When this bit is set, Port Ready is set to 0 and no additional commands will be processed until the port is initialized by one of the reset methods and Port Ready is asserted. Writing a one to bit 1 or bit 17 of the Port Interrupt Status register clears this interrupt condition. This interrupt is enabled or disabled with the corresponding bit in the Port Interrupt Enable Set / Port Interrupt Enable Clear. Port Ready. Indicates that the Port Ready state has changed from zero to one. Writing a 1 to bit 2 or bit 18 of the port Interrupt Status Register clears this interrupt condition. This interrupt is enabled or disabled with the corresponding bit in the Port Interrupt Enable Set / Port Interrupt Enable Clear register. Power Management Change. Indicates that the port power management state has been modified. The current power management state can be determined by reading the port SStatus register. Writing a 1 to bit 3 or bit 19 of the Port Interrupt Status register clears this interrupt condition. This interrupt is enabled or disabled with the corresponding bit in the Port Interrupt Enable Set / Port Interrupt Enable Clear register. PHY Ready Change. Indicates that the PHY state has changed from Not Ready to Ready or from Ready to Not Ready. The current PHY state can be determined by reading the port SStatus register. Writing a one to bit 4 or bit 20 of the Port Interrupt Status register clears this interrupt condition. This interrupt is enabled or disabled with the corresponding bit in the Port Interrupt Enable Set / Port Interrupt Enable Clear register. COMWAKE Received. Indicates that a COMWAKE OOB signal has been decoded on the receiver. Writing a one to bit 5 or bit 21 of the Port Interrupt Status register clears this interrupt condition. This interrupt is enabled SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 27 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. or disabled with the corresponding bit in the Port Interrupt Enable Set / Port Interrupt Enable Clear register. Unrecognized FIS. Indicates that the F-bit has been set in the Serror Diag field. Writing a one to bit 6 or bit 22 of the Port Interrupt Status register clears this interrupt condition. This interrupt is enabled or disabled with the corresponding bit in the Port Interrupt Enable Set / Port Interrupt Enable Clear register. Device Exchanged. Indicates that the X-bit has been set in the Serror Diag field. The X-bit is set upon receipt of a COMINIT from the device. Writing a one to bit 7 or bit 23 of the Port Interrupt Status register clears this interrupt condition. This interrupt is enabled or disabled with the corresponding bit in the Port Interrupt Enable Set / Port Interrupt Enable Clear register. 8b/10b Decode Error Threshold Exceeded. Indicates that the 8b/10b Decode Error counter has exceeded the programmed non-zero threshold value. Writing any value to the Port 8B/10B Decode Error Counter register or writing a 1 to bit 8 or 24 of the Port Interrupt Status register clears this interrupt condition. This interrupt is enabled by writing a non-zero value to the threshold field (bit [31:16]) of the Port 8B/10B Decode Error Counter register. Writing a 0 the threshold field disables this interrupt. CRC Error Threshold Exceeded. Indicates that the CRC Error counter has exceeded the programmed non-zero threshold value. Writing any value to the Port CRC Error Counter register or writing a 1 to bit 9 or bit 25 of the Port Interrupt Status register clears this interrupt condition. This interrupt is enabled by writing a nonzero value to the threshold field (bit [31:16]) of the Port CRC Error Counter register. Writing a 0 to the threshold field disables this interrupt. Handshake Error Threshold Exceeded. Indicates that the Handshake Error counter has exceeded the programmed non-zero threshold value. A handshake error occurs when an R_ERR primitive is received. Writing any value to the Port Handshake Error Counter register or writing a 1 to bit 10 or bit 26 of the Port Interrupt Status register clears this interrupt condition. This interrupt is enabled by writing a non-zero value to the threshold field (bit [31:16]) of the Port Handshake Error Counter register. Writing a 0 to the threshold field disables this interrupt. SDB Notify. Indicates that a Set Device Bits FIS has been received with the N-bit set in the control field. ATAPI and Port Multiplier devices optionally use this feature to signal the host that an event has occurred that requires further scrutiny. Writing a 1 to bit 11 or bit 27 of the Port Interrupt Status register clears this interrupt condition. This interrupt is enabled or disabled with the corresponding bit in the Port Interrupt Enable Set / Port Interrupt Enable Clear register. 28 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Global_Int_En_0 Control_Interrupt_Mask Cmd_Complete_Int_En Q Command Success S Exec_Cmd_Complete Int_Select_0 Port_Interrupt_NCoR R CLR Q Int_Select_1 Reset Read_Slot_Status Cmd_Completion_W1C Int_Select_2 Port_0_IntA Port_0_IntB Port_0_IntC Cmd_Err_Int_En Exec_Cmd_Err Command_Err_W1C S R Q CLR Command Error Int_Select_3 Port_0_IntD Q Reset Port_Ready_Int_En Port_Ready_Assertion Port_Ready_Int W1C S R Q CLR Port_0_Global_Int_Status Q Reset PM_Change_Int_En PM_Change PhyRdy_Change_Int_En PhyRdy_Change ComWake_Int_En ComWake Attention (Slot_Status[31]) UnRecFis_Int_En UnrecFis DevXchg_Int_En DevXchg 8b/10b_Error_Threshold CRC_Error_Threshold Hshk_Error_Threshold SDB_Notify_Int_En SDB_Notify Port 0 Global_Int_En_1 Port_0_IntB Port_1_IntB INTB ULA Port_1_IntA Port 1 Port_1_IntB Port_1_IntC Port_1_IntD Port_1_Global_Int_Status Port_0_IntC PCI_CFG_INT_DIS INTC Port_1_IntC Port_0_IntD INTA INTD Port_1_IntD Port_0_IntA Port_1_IntA I2C_Interrupt I2C_Int_Enable Figure 7. SiI3132 Interrupt Map SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 29 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Table 23. Port Interrupt Causes and Control Interrupt Cause Interrupt Status Bit Masked Raw To Clear: To Enable: To Disable: Write 1 to Interrupt Enable Set bit 0 Write 1 to Interrupt Enable Clear bit 0 OR Write 1 to control_interrupt_mask in PRB Control field Write 1 to Interrupt Enable Set bit 1 Write 1 to Interrupt Enable Set bit 2 Write 1 to Interrupt Enable Set bit 3 Write 1 to Interrupt Enable Set bit 4 Write 1 to Interrupt Enable Set bit 5 Write 1 to Interrupt Enable Set bit 6 Write 1 to Interrupt Enable Set bit 7 Write 1 to Interrupt Enable Clear bit 1 Write 1 to Interrupt Enable Clear bit 2 Write 1 to Interrupt Enable Clear bit 3 Write 1 to Interrupt Enable Clear bit 4 Write 1 to Interrupt Enable Clear bit 5 Write 1 to Interrupt Enable Clear bit 6 Write 1 to Interrupt Enable Clear bit 7 Write non-zero value to 8b/10b Decode Error Counter bits[31:16] Write 0 to 8b/10b Decode Error Counter bits[31:16] Write non-zero value to CRC Error Counter bits[31:16] Write 0 to CRC Error Counter bits[31:16] Write non-zero value to Handshake Error Counter bits[31:16] Write zero to Handshake Error Counter bits[31:16] Write 1 to Interrupt Enable Set bit 11 Write 1 to Interrupt Enable Clear bit 11 If Interrupt W1C == 0 Read Slot Status Command Complete 0 16 Command Error 1 17 Port Ready 2 18 Power Management Change 3 19 PHY Ready Change 4 20 5 21 6 22 Device Exchanged 7 23 8b/10b Decode Error Threshold 8 24 CRC Error Threshold 9 25 Handshake Error Threshold 10 26 Set Device Bits Notification Received 11 27 COMWAKE Received Unrecognized FIS Received If Interrupt W1C == 1 Write 1 to Port Interrupt Status bit 0 or 16, OR write one to desired port bit(s) in Global Interrupt Status. Write 1 to Interrupt Status bit 1 or 17 Write 1 to Interrupt Status bit 2 or 18 Write 1 to Interrupt Status bit 3 or 19 Write 1 to Interrupt Status bit 4 or 20 Write 1 to Interrupt Status bit 5 or 21 Write 1 to Interrupt Status bit 6 or 22 Write 1 to Interrupt Status bit 7 or 23 Write 1 to Interrupt Status bit 8 or 24 OR Write any value to 8b/10b Decode Error Counter bits[15:0] Write 1 to Interrupt Status bit 9 or 25 OR Write any value to CRC Error Counter bits[15:0] Write 1 to Interrupt Status bit 10 or 26 OR Write any value to Handshake Error Counter bits[15:0] Write 1 to Interrupt Status bit 11 or 27 Command Completion -- The Slot Status Registers The Slot Status registers are designed such that with a single read, an interrupt service routine can determine the successful completion state of outstanding commands, dismiss the command completion interrupt, and determine if any other enabled interrupt events are pending in a port. 30 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Data Sheet The Port Slot Status register (Port offset 0x1800) or Global Port Slot Status (Global offset 0x00 + (port 4)) bits 0 through 30 reflect the status of each of the 31 command slots in a port. When a PRB is issued to a command slot, the corresponding bit in the Slot Status register is set to 1, indicating that the command is in progress. When a command is successfully completed, the corresponding command slot bit is cleared in the Slot Status register. The host driver can read the Slot Status register at any time to determine the activity state of any issued commands. By default, a successfully completed command will set the command complete bit in the Port Interrupt Status register. If the Command Complete interrupt is enabled, an interrupt will be asserted simultaneously. The host driver can optionally set control_interrupt_mask in the PRB Control field to prevent the command complete bit from being set on a per-command basis. This is useful when the host issues a series of commands and wants to be interrupted only after a selected command completes. The command complete bit and associated interrupt are cleared when the Slot Status register is read, unless the host driver has set Interrupt No Clear on Read (Port Control Set or Port Control Clear register, bit 3) to 1. If Interrupt No Clear on Read is set, the host driver must write 1 to the Command Complete bit in the Port Interrupt Status register in order to clear the command complete bit and associated interrupt. The Attention Bit Bit 31 of the Slot Status register is the Attention bit. When set to 1, it indicates that an enabled interrupt source, other than command completion, is asserted. It is possible that the Slot Status register indicates an Attention condition while also showing that commands have successfully completed in bits 0 through 30. The interrupt service routine should always post-process any completed commands in addition to servicing a possible Attention condition. The Attention bit is set only for interrupt conditions that have been enabled as described in the Interrupt Sources section on page 27. The Attention bit remains set to 1 in the Slot Status register until all enabled interrupt conditions are cleared. Interrupt Service Procedure The SiI3132 controller services interrupt events with minimal host overhead. There are two methods the host can use to determine the cause of an interrupt within any of the ports. * The Global Interrupt Status register (Global offset 0x44) can be read to determine which ports are causing the interrupt. Then, the Slot Status register for the interrupting ports can be read to determine the cause of an interrupt. * Alternately, all port Slot Status registers can be read in a single burst operation from the Global Register space starting at Global offset 0x00. If Interrupt No Clear on Read (Port Control Set or Port Control Clear, Bit 3) is 0, any command complete interrupt is cleared. The host driver should then compare the outstanding command status in bits 0 through 30 to its internal copy of outstanding commands to determine which, if any, commands have successfully completed. Once the successful command completions have been noted, the host should check the Attention bit (bit 31) to determine if any other enabled interrupt events are pending on the port. If the Attention bit is one, the host should read the Port Interrupt Status register (Port offset (port 0x2000) + 0x1008) to determine the cause for the Attention condition. Once the Attention condition has been resolved and cleared, normal processing can continue. Interrupt No Clear on Read By default, the Command Completion interrupt condition is cleared when the port Slot Status register is read. In some cases, such as in debug environments, clearing of the Command Completion interrupt might not be the desired effect of reading the Slot Status register. In these cases, the host driver should set the Interrupt No Clear on Read bit (bit 3) in the Port Control Set register. When this bit is set, the host must clear the Command Completion interrupt by one of the following methods: * Write one to the corresponding port interrupt status bit(s) in the Global Interrupt Status register (Global offset 0x44). This method clears Command Complete interrupts for multiple ports in a single write operation.. * Write 1 to bit 0 or bit 16 of the Port Interrupt Status register (Port offset (port 0x2000) + 0x1008).This clears Command Complete only for the corresponding port. Error Processing When an error occurs during command processing, the controller records the error condition and halts execution until the host driver is able to restore normal operation. It does not attempt to automatically recover from error conditions. SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 31 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Rather, it provides the host with the necessary information to handle the error condition. Errors that occur during command execution cause the Command Error bit to be set to one in the Port Interrupt Status register (Port offset (port0x2000) + 0x1008) and an error code to be placed in the Port Command Error register (Port offset (port 0x2000) + 0x1024). Refer to the Port Command Error section on page 63 for a complete list of possible error codes. Then execution halts and Port Ready (Port Status Register, bit 31) is cleared to zero. Only the port with the error condition halts and all other ports will continue to process normally. If the Command Error interrupt is enabled, an interrupt is asserted and the Attention bit is asserted in the port Slot Status register. The corresponding Slot Status bit for the command in error will not be cleared to 0, because the command did not complete successfully. If only non-queued commands are outstanding, the slot number for the command in error is available in the Port Status register, bits[20:16]. The host may use this information to ascertain which outstanding command caused the error condition. To recover from a Command Error condition, it is necessary to initialize the port by one of the Port Reset methods described in the Reset and Initialization starting on page 24. It might not be necessary to reset the device in all error cases. In fact, to properly recover from native queued error conditions, it may be necessary to send additional commands to the device in error to obtain additional error information. At the minimum, it will be necessary to assert a Port Initialize and wait for Port Ready before additional commands may be issued. Errors may be grouped into three categories to determine the proper recovery action: Recoverable errors. Error codes 1 and 2 are device specific errors. These errors occur when the device returns an error bit in the final register FIS or in a Set Device Bits FIS. Depending upon the severity of the error type reported by the device, it may not be necessary to reset the device. If the error code is 1, the register FIS received from the device is available in the command slot PRB. The host may determine the error reported by the device by examining the error register field of this structure. See the Error Recovery Procedures section below for more information regarding error recovery procedures. Locally detected data errors. Error code 3 is a unique error type. It indicates that the controller detected an error during command execution but the device failed to report the error upon command completion. For non-queued commands, this type of error type can be treated in the same as a recoverable error. If queued commands are outstanding, the device must be reset because it is necessary to make sure that all queued commands are flushed from the device when an error condition occurs. Since the device did not report an error, it is unlikely that the queue has been flushed in the device. Fatal Errors. All other error codes indicate that an error condition has occurred that requires both the device and the internal operational state of the SiI3132 controller to be reset. The most common method to perform this function is to issue a Device Reset. Error Recovery Procedures When a device returns error status for an outstanding command, the controller will halt command processing, post an error type of 1 or 2 in the Port Command Error register, set the command error bit in the Port Interrupt Status register and, if enabled, assert an interrupt to the host. The host driver can try to attempt error recovery without resetting the device that issued the error. Note that error recovery procedures should only be attempted for error types 1 and 2. Error type 3 is also recoverable if no queued commands are outstanding. Silicon Image recommends that all other error types result in a reset of the affected device(s). If the device in error is directly attached to the SiI3132 controller port, the host may issue a Port Initialize by setting bit 2 in the Port Control Set register and waiting for a Port Ready condition. The host may then re-issue any commands that were outstanding when the error occurred. If native queued commands were outstanding, the host should issue a READ LOG EXTENDED for Log Page 10h to determine the details of the error condition. Refer to the Serial ATA II specification for further details on error handling with native queuing. If the device in error is attached to a port multiplier, it is necessary for the host driver to wait until all outstanding commands to other devices attached to the port multiplier have completed before issuing the Port Initialize function. This is accomplished through a series of steps: 1. The host driver must note the PM port number for the device in error by extracting the PMP field (bit[8:5]) from the Port Context register (port offset 0x1E04). The PMP field contains the PM port number for the device in error. It is then necessary to determine if any commands are outstanding for non-error devices. If there are no commands outstanding for non-error devices, the host driver may proceed to step 4 to issue a Port Initialize command and wait for a Port Ready condition before reissuing commands. 32 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Data Sheet 2. If commands are outstanding to non-error devices, the host should set the Port Resume bit (bit 6) in the Port Control Set register. Setting this bit forces a Device Busy condition for the currently selected PM port (the port to which the device in error is attached) so that no additional issued commands will be sent to the device in error. Processing of commands that have already been issued continues. 3. The host driver must monitor command completion progress and determine when all commands for non-error devices have completed. Please note that the Port Slot Status register will still have a bit set for each outstanding command on the device in error. These bits will not be cleared and the host must ignore them while waiting for command completion on non-error devices. If another recoverable error occurs while waiting for commands to complete, the host driver must follow the same recovery steps for the new device in error, starting with step 1 above. It is possible to have multiple devices in an error recovery state concurrently. When the host driver detects that all commands for non-error devices have completed, it must perform the following steps. a. Clear Port Resume Port Control Clear register, Bit 6). b. Clear bit[16:13] in the Port Device Status register for the device(s) in error ((port 0x2000) + 0xF80 + (PM port of device in error 8)). This action clears the Device_Busy, Native_Queue, Legacy_Queue, and Service_Pending bits to ready the device for further command processing. c. Write zeroes (0x00000000) to the Port Device QActive register for the device(s) in error ((port 0x2000) + 0xF84 + (PM port of device in error 8)). This action ensures that all queued command context is removed before re-issuing commands. d. Issue a Port Initialize command and wait for Port Ready condition. 4. The host driver may now resume normal command processing. The host driver must determine which commands need to be reissued to the device in error. If native queued commands were outstanding to the device in error, the host must issue a READ LOG EXTENDED command to clear the pending error condition and determine the tag number (slot number) of the command in error before resuming command processing. Note: It is a good idea to clear Port Resume (Port Control Clear register, Bit 6) whenever Port Initialize or Port Device Reset command is issued. This ensures that the Port Resume bit is always cleared when starting normal processing in the event that an abnormal exit is taken from the error recovery procedure. SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 33 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Auto-Initialization The controller supports an external flash or EEPROM device for BIOS extensions and user-defined PCI configuration header data. Auto-Initialization from Flash The SiI3132 controller initiates the flash detection and configuration space loading sequence on the release of PERST#. It begins by reading the highest two addresses (7FFFFH and 7FFFEH), checking for the correct data signature pattern (AAH and 55H, respectively). If the data signature pattern is correct, the controller continues to sequence the address downward, reading a total of twelve bytes. If the Data Signature is correct (55H at 7FFFCH), the last eight bytes are loaded into the PCI Configuration Space registers. If both flash and EEPROM are installed, the PCI Configuration Space registers will be loaded with data from the EEPROM. While the sequence is active, the controller responds to all PCI bus accesses with a Target Retry. Figure 8. Auto-Initialization from Flash Timing Table 24. Auto-Initialization from Flash Timing Parameter t1 t2 Value 660 ns 4200 ns Description PCI reset to flash Auto-Initialization cycle begin Flash Auto-Initialization cycle time Table 25. Flash Data Description Address 7FFFFH 7FFFEH 7FFFDH 7FFFCH 7FFFBH 7FFFAH 7FFF9H 7FFF8H 7FFF7H 7FFF6H 7FFF5H 7FFF4H 34 Data Byte D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 Description Data Signature = AAH Data Signature = 55H AA = 120 ns flash device / Else, 240 ns flash device Data Signature = 55H PCI Device ID [23:16] PCI Device ID [31:24] PCI Class Code [15:08] PCI Class Code [23:16] PCI Sub-System Vendor ID [07:00] PCI Sub-System Vendor ID [15:08] PCI Sub-System ID [23:16] PCI Sub-System ID [31:24] (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Auto-Initialization from EEPROM The SiI3132 controller initiates the EEPROM detection and configuration space loading sequence after the flash read sequence. The SiI3132 controller supports EEPROMs with an I2C serial interface. The sequence of operations consists of the following. 1. START condition defined as a HIGH-to-LOW transition on I2C_SDAT while I2C_SCLK is HIGH. 2. Control byte = 1010 (Control Code) + 000 (Chip Select) + 0 (Write Address). 3. Acknowledge. 4. Starting address field = 00000000. 5. Acknowledge. 6. Sequential data bytes separated by Acknowledges. 7. STOP condition. While the sequence is active, the controller responds to all PCI bus accesses with a Target Retry. S 1 0 1 0 0 0 0 W A D D D N P I2C_SDAT t1 t2 I2C_SCLK t3 FL_CS_N Figure 9. Auto-Initialization from EEPROM Timing Table 26. Auto-Initialization from EEPROM Timing Parameter t1 t2 t3 Value 26.00 s 1.4 ms 10 s Description End of Auto-Initialization from flash to start of Auto-Initialization from EEPROM Auto-Initialization from EEPROM cycle time EEPROM serial clock period Table 27. Auto-Initialization from EEPROM Timing Symbols Parameter S W A D N P SiI-DS-0138-E Description START condition R/W 0 = Write Command, 1 = Read Command Acknowledge Serial data No-Acknowledge STOP condition (c) 2007-2010 Silicon Image, Inc. All rights reserved. 35 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Table 28. EEPROM Data Description Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 36 Data Byte D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 Description Memory Present Pattern = AAH Memory Present Pattern = 55H Data Signature = AAH Data Signature = 55H PCI Device ID [23:16] PCI Device ID [31:24] PCI Class Code [15:08] PCI Class Code [23:16] PCI Sub-System Vendor ID [07:00] PCI Sub-System Vendor ID [15:08] PCI Sub-System ID [23:16] PCI Sub-System ID [31:24] (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Register Definitions This section describes the registers within the SiI3132 controller. PCI Configuration Space As shown in Table 29, the PCI Configuration Space registers define the operation of the controller on the PCI Express bus. Table 29. SiI3132 PCI Configuration Space Address Offset 00H 04H 08H 0CH 10H 14H 18H 1CH 20H 24H 28H 2CH 30H 34H 38H 3CH 40H 44H 48H 4CH 50H 54H 58H 5CH 60H 64H 68H 6CH 70H 74H 78H 7CH 80H 84H-EFH F0H-FFH 100H 104H 108H 10CH 110H 114H 118H 11CH-12BH SiI-DS-0138-E Register Name Device ID PCI Status Vendor ID PCI Command Revision ID Latency Timer Cache Line Size PCI Class Code Header Type BIST Base Address Register 0 Base Address Register 1 Base Address Register 2 Reserved Reserved Subsystem ID Subsystem Vendor ID Expansion ROM Base Address Reserved Capabilities Ptr Reserved Max Latency Min Grant Interrupt Pin Interrupt Line Reserved Reserved Reserved Hdr Wr Ena Reserved Reserved Power Management Capabilities Next Capability Pwr Mgt Cap ID Data Reserved Control and Status Message Control Next Capability MSI Cap ID Message Address Reserved Message Data Reserved PCI Express Capabilities Register Next Capability PCI Exp Cap ID Device Capabilities Device Status Device Control Link Capabilities Link Status Link Control Reserved Indirect Access Advanced Error Reporting Capability Uncorrectable Error Status Uncorrectable Error Mask Uncorrectable Error Severity Correctable Error Status Correctable Error Mask Advanced Error Capabilities and Control Header Log (c) 2007-2010 Silicon Image, Inc. All rights reserved. 37 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Device ID - Vendor ID Address Offset: 00H Access Type: Read /Write Reset Value: 0x3132_1095 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Device ID Vendor ID This register defines the Device ID and Vendor ID associated with the SiI3132 controller. The register bits are defined as follows: * Bit [31:16]: Device ID (R/W) - Device ID. The value in this bit field is one of the following: a. The default value of 0x3132 to identify the device as a Silicon Image SiI3132 controller. b. The value loaded from an external memory device; if an external memory device, flash or EEPROM, is present with the correct signature, the Device ID is loaded from that device after reset. See the Auto-Initialization from Flash section on page 34 for more information. c. System programmed value; if bit 0 of the Configuration register (48H) is set, the Device ID is system programmable. * Bit [15:00]: Vendor ID (R) - Vendor ID. This field defaults to 0x1095 to identify the vendor as Silicon Image. PCI Status - PCI Command Address Offset: 04H Access Type: Read/Write/Write-One-to-Clear Reset Value: 0x0010_0000 IO Space Bus Master Memory Space Reserved Reserved Int Disable Reserved SERR Enable Reserved Par Error Resp Int Status Capabilities List Reserved Det M Par Err Reserved Det Par Err Sig Sys Err Rcvd M Abort Rcvd T Abort Sig T Abort 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 This register defines the various control functions associated with the PCI bus. The register bits are defined below. * Bit 31: Det Par Err (R/W1C) - Detected Parity Error. * Bit 30: Sig Sys Err (R/W1C) - Signaled System Error. * Bit 29: Rcvd M Abort (R/W1C) - Received Master Abort. * Bit 28: Rcvd T Abort (R/W1C) - Received Target Abort. * Bit 27: Sig T Abort (R/W1C) - Signaled Target Abort. * Bit 24: Det M Par Err (R/W1C) - Detected Master Data Parity Error. * Bit 20: Capabilities List (R) - PCI Capabilities List. This bit is hardwired to 1 to indicate that the controller implements Capabilities registers for Power Management, PCI-X, and Message Signaled Interrupt. * Bit [19]: Interrupt Status (R). * Bit [26:25,23:21,18:11,9,7,5:3]: Reserved (R) - This bit field is reserved and returns zeros on a read. * Bit [10]: Interrupt Disable (R/W). * Bit 08: SERR Enable (R/W) - SERR Enable. * Bit 06: Par Error Resp (R/W) - Parity Error Response Enable. * Bit 02: Bus Master (R/W) - Bus Master Enable. This bit set enables the controller to act as PCI bus master, for example, to issue Memory Requests. * Bit 01: Memory Space (R/W) - Memory Space Enable. This bit set enables the controller to respond to memory space accesses. * Bit 00: I/O Space (R/W) - I/O Space Enable. This bit is hardwired to 0; the controller does not respond to I/O space accesses. 38 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. PCI Class Code - Revision ID Address Offset: 08H Access Type: Read/Write Reset Value: 0x0180_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PCI Class Code Revision ID This register defines the various control functions associated with the PCI bus. The register bits are defined below. * Bit [31:08]: PCI Class Code (R) - PCI Class Code. This value in this bit field is one of the following: a. The default value of 018000h for Mass Storage Class. b. The value loaded from an external memory device; if an external memory device - flash or EEPROM - is present with the correct signature, the PCI Class Code is loaded from that device after reset. See the AutoInitialization from Flash section on page 34 for more information. c. System programmed value; if bit 0 of the Configuration register (48H) is set the PCI Class Code is system programmable. * Bit [07:00]: Revision ID (R) - Chip Revision ID. This bit field is hardwired to indicate the revision level of the chip design; revision 01H is defined by this specification. BIST - Header Type - Latency Timer - Cache Line Size Address Offset: 0CH Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 BIST Header Type Latency Timer Cache Line Size This register defines the various control functions associated with the PCI bus. The register bits are defined below. * Bit [31:24]: BIST (R). This bit field is hardwired to 00H. * Bit [23:16]: Header Type (R). This bit field is hardwired to 00H. * Bit [15:08]: Latency Timer (R). This field is hardwired to 00H. * Bit [07:00]: Cache Line Size (R/W). This bit field is Read/Write for legacy purposes. The field is not used by the SiI3132 controller. Base Address Register 0 Address Offset: 10H Access Type: Read/Write Reset Value: 0x0000_0000_0000_0004 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Base Address Register 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Base Address Register 0 0000100 This register defines the addressing of the Global Registers within the SiI3132 controller. The register bits are defined as follows: * Bit [63:07]: Base Address Register 0 (R/W). This register defines the base address for the 128-byte Memory Space containing the Global Registers. * Bit [06:00]: (R). This bit field is hardwired to 0000100B to indicate a 64-bit base address. SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 39 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Base Address Register 1 Address Offset: 18H Access Type: Read/Write Reset Value: 0x0000_0000_0000_0004 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Base Address Register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Base Address Register 1 00 0000 0000 0100 This register defines the addressing of the Port Registers and LRAM within the controller. The register bits are defined as follows: * Bit [63:15]: Base Address Register 1 (R/W). This register defines the base address for the 16 kB Memory Space containing the Port Registers. * Bit [14:00]: (R). This bit field is hardwired to 0004H to indicate a 64-bit base address. Base Address Register 2 Address Offset: 20H Access Type: Read/Write Reset Value: 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Base Address Register 2 000 0001 This register defines the addressing of the Indirect I/O registers within the SiI3132 controller. The register bits are defined as follows: * Bit [31:04]: Base Address Register 2 (R/W). This register defines the base address for the 128-byte I/O Space. * Bit [03:00]: (R). This bit field is hardwired to 000_0001B. Subsystem ID -- Subsystem Vendor ID Address Offset: 2CH Access Type: Read/Write Reset Value: 0x3132_1095 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Subsystem ID Subsystem Vendor ID This register defines the Subsystem ID fields associated with the PCI bus. The register bits are as follows. * Bit [31:16]: Subsystem ID (R/W) - Subsystem ID. The value in this bit field is one of the following: a. The default value of 0x3132 b. The value loaded from an external memory device; if an external memory device (flash or EEPROM) is present with the correct signature, the Subsystem ID is loaded from that device after reset. See Auto-Initialization from Flash section on page 34 for more information. c. System programmed value; if bit 0 of the Configuration register (48H) is set, the Subsystem ID is system programmable. * Bit [15:00]: Subsystem Vendor ID (R/W) - Subsystem Vendor ID. The value in this bit field is one of the following: a. The default value of 0x1095 b. The value loaded from an external memory device; if an external memory device (flash or EEPROM) is present with a correct signature, the Subsystem Vendor ID is loaded from that device after reset. See the AutoInitialization from Flash section on page 34 for more information. c. System programmed value; if bit 0 of the Configuration register (48H) is set, the Subsystem Vendor ID is system programmable. 40 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Expansion ROM Base Address Address Offset: 30H Access Type: Read/Write Reset Value: 0x0000_0000 Expansion ROM Base Address Exp ROM Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 000_0000_0000_0000_000 This register defines the Expansion ROM base address associated with the PCI bus. The register bits are defined as follows: * Bit [31:19]: Expansion ROM Base Address (R/W) - Expansion ROM Base Address. This bit field defines the upper bits of the Expansion ROM base address. * Bit [18:01]: (R). This bit field is hardwired to 00000H to indicate that the Expansion ROM address range is 512 kB. * Bit [00]: Exp ROM Enable (R/W) - Expansion ROM Enable. This bit is set to enable Expansion ROM access. Capabilities Pointer Address Offset: 34H Access Type: Read Reset Value: 0x0000_0054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved Capabilities Pointer This register defines the link to a list of new capabilities associated with the PCI bus. The register bits are defined below. * Bit [31:08]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [07:00]: Capabilities Pointer (R) - Capabilities Pointer. This bit field contains 54H, the address for the first Capabilities register set, the PCI Power Management Capability register. Max Latency - Min Grant - Interrupt Pin - Interrupt Line Address Offset: 3CH Access Type: Read/Write Reset Value: 0x0000_0100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Max Latency Min Grant Interrupt Pin Interrupt Line This register defines various control functions associated with the PCI bus. The register bits are defined as follows: * Bit [31:24]: Max Latency (R) - Maximum Latency. This bit field is hardwired to 00H. * Bit [23:16]: Min Grant (R) - Minimum Grant. This bit field is hardwired to 00H. * Bit [15:08]: Interrupt Pin (R) - Interrupt Pin Used. This bit field is hardwired to 01H to indicate that the controller uses the INTA interrupt. The INTB, INTC, and INTD interrupts can be used by enabling them in the Port Interrupt Enable Set / Port Interrupt Enable Clear registers but it is outside the PCI specification. * Bit [07:00]: Interrupt Line (R/W) - Interrupt Line. This bit field is used by the system to indicate interrupt line routing information. The controller does not use this information. SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 41 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Header Write Enable Address Offset: 48H Access Type: Read/Write Reset Value: 0x0000_0000 Ind Acc Ena Hdr Wr Ena 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved * * * Bit [31:02]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [01]: Ind Acc Ena (R) - Indirect Access Enable. This bit enables the Indirect Access registers at offset F0H-FFH. Bit [00]: Hdr Wr Ena (R) - Header Write Enable. This bit enables writing to registers defined as read-only by the PCI specification. This bit is required to meet PCI compliance testing and expects certain registers to be read-only. This bit is set to Enable Write Access to the registers; Device ID (03-02H), PCI Class Code (09-0BH), Subsystem Vendor ID (2D-2CH), and Subsystem ID (2F-2EH) in the PCI Configuration Header. Power Management Capability Address Offset: 54H Access Type: Read Only Reset Value: 0x0622_5C01 Reserved PME Clock Auxiliary Current Dev Special Init PME Support PPM D2 Support PPM D1 Support 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PPM Rev Next Capability Pointer120 Capability ID This register defines the power management capabilities associated with the PCI bus. The register bits are defined as follows: * Bit [31:27]: PME Support (R) - Power Management Event Support. This bit field is hardwired to 00H. The controller does not support PME. * Bit [26]: PPM D2 Support (R) - PCI Power Management D2 Support. This bit is hardwired to 1. * Bit [25]: PPM D1 Support (R) - PCI Power Management D1 Support. This bit is hardwired to 1. * Bit [24:22]: Auxiliary Current (R) - Auxiliary Current. This bit field is hardwired to 000B. * Bit [21]: Dev Special Init (R) - Device Special Initialization. This bit is hardwired to 1 to indicate that the controller requires special initialization. * Bit [20]: Reserved (R). This bit is reserved and returns 0 on a read. * Bit [19]: PME Clock (R) - Power Management Event Clock. This bit is hardwired to 0. * Bit [18:16]: PPM Rev (R) - PCI Power Management Revision. This bit field is hardwired to 010B to indicate compliance with the PCI Power Management Interface Specification revision 1.1. * Bit [15:08]: Next Capability Pointer (R) - PCI Next Capability Pointer. This bit field is hardwired to 5CH to point to the second Capabilities register, the MSI Capability register. * Bit [07:00]: Capability ID (R) - PCI Capability ID. This bit field is hardwired to 01H to indicate that this is a PCI Power Management Capability. 42 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Power Management Control + Status Address Offset: 58H Access Type: Read/Write Reset Value: 0x0C00_2000 Reserved PPM Power State PPM Data Sel PME Ena Reserved PPM Data Scale PPM Data PME Status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 This register defines the power management capabilities associated with the PCI bus. The register bits are defined as follows: * Bit [31:24]: PPM Data (R) - PCI Power Management Data. This bit field is hardwired to 0x0C to indicate a power consumption of 1.2 Watt. * Bit [23:16]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [15]: PME Status (R) - PME Status. This bit is hardwired to 0. The controller does not support PME. * Bit [14:13]: PPM Data Scale (R) - PCI Power Management Data Scale. This bit field is hardwired to 01B to indicate a scaling factor of 100 mW. * Bit [12:09]: PPM Data Sel (R/W) - PCI Power Management Data Select. This bit field is set by the system to indicate which data field is to be reported through the PPM Data bits (although current implementation hardwires the PPM Data to indicate 1.2 Watt). * Bit [08]: PME Ena (R) - PME Enable. This bit is hardwired to 0. The controller does not support PME. * Bit [07:02]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [01:00]: PPM Power State (R/W) - PCI Power Management Power State. This bit field is set by the system to dictate the current Power State: 00 = D0 (Normal Operation), 01 = D1, 10 = D2, and 11 = D3 (Hot). MSI Capability Address Offset: 5CH Access Type: Read/Write Reset Value: 0x0080_7005 Multiple Messag e Enable Multiple Messag e Capable MSI Enable Reserved 64-bit Addr 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Next Capability Pointer Capability ID This register defines the MSI Capability Message Control. The register bits are defined as follows: * Bit [31:24]: Reserved (R) - This bit field is reserved and returns zeros on a read. * Bit [23]: 64-bit Addr (R) - 64-bit Address Capable. This bit is hardwired to 1. * Bit [22:20]: Multiple Message Enable (R/W) - This bit field defaults to 000B. * Bit [19:17]: Multiple Message Capable (R/W) - This bit field defaults to 000B. * Bit [16]: MSI Enable (R/W) - This bit is set to enable Message Signaled Interrupts. * Bit [15:08]: Next Capability Pointer (R) -Next Capability Pointer. This bit field is hardwired to 70H to point to the third Capabilities register, the PCI Express Capability register. * Bit [07:00]: Capability ID (R) - This bit field is hardwired to 05H to indicate that this is a MSI Capability. SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 43 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Message Address Address Offset: 60H-67H Access Type: Read/Write Reset Value: 0x0000_0000_0000_0000 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Message Address Upper 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Message Address 00 This register specifies the memory address for an MSI memory write transaction. The memory address must be of a Dword (bits 1:0 must be 0). MSI Message Data Address Offset: 68H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved Message Data This register specifies the MSI Message Data. The register bits are defined as follows: * Bit [31:16]: Reserved (R) - This bit field is reserved and returns zeros on a read. * Bit [15:00]: Message Data (R/W) - This bit field specifies the Message Data for an MSI memory write transaction. PCI Express Capability Address Offset: 70H Access Type: Read Only Reset Value: 0x0011_0010 * * * * * * 44 Interrupt Message Number Reserved Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Device Type Version Next Capability Pointer Capability ID Bit [31:30,24]: Reserved (R) - These bits are reserved and return zero on a read. Bit [29:25]: Interrupt Message Number (R) - This bit field is hardwired to 0. Bit [23:20]: Device Type (R) - This bit field is hardwired to 0001B to indicate a PCI Express Legacy Endpoint device. Bit [19:16]: Version (R) - This bit field is hardwired to 01H to indicate compliance with the PCI Express Specification revision 1.0a. Bit [15:08]: Next Capability Pointer (R) - PCI Next Capability Pointer. This bit field is hardwired to 00H (this is the last capability). Bit [07:00]: Capability ID (R) - PCI Capability ID. This bit field is hardwired to 10H to indicate that this is a PCI Express Capability. (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Device Capabilities Address Offset: 74H Access Type: Read Only Reset Value: 0x0000_0003 * * * * * * * * * * Reserved L1 Latency L0s Latency Phantom Functions Slot Power 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Ext Tag Sup Reserved 15 Pwr Indicator Atten Indicator Atten Button 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Max Payload Bit [31:28,17:15]: Reserved (R) - These bits are reserved and return zero on a read. Bit [27:18]: Slot Power (R) - Captured Slot Power Limit Value and Limit Scale. This bit field is hardwired to 0. Bit [14]: Pwr Indicator (R) - Power Indicator Present. This bit field is hardwired to 0. Bit [13]: Atten Indicator (R) - Attention Indicator Present. This bit field is hardwired to 0. Bit [12]: Atten Button (R) - Attention Button Present. This bit field is hardwired to 0. Bit [11:09]: L1 Latency (R) - This bit field is hardwired to 000B. Bit [08:06]: L0s Latency (R) - This bit field is hardwired to 000B. Bit [05]: Ext Tag Sup (R) - Extended Tag Field Supported. This bit is hardwired to 0. Bit [04:03]: Phantom Functions (R) - This bit field is hardwired to 0. Bit [02:00]: Max Payload (R) - Max_Payload_Size Supported. This bit field is hardwired to 011B to indicate that a maximum 1024-byte payload is supported. Device Status and Control Address Offset: 78H Access Type: Read/Write/Write 1 to Clear Reset Value: 0x0000_2000 * * * * * * * * * * * * * Max Payload Size En Rlxd Ord UnsReq Rep En Fatal Err Rep En NonFtl Err Rep En Corr Err Rep En Max Read Request Size EnSnp Not Req Aux Pwr PM En Phntm Fnc En Ext Tag Fld En Reserved Trans Pending AUX Power Unsup Req Det Fatal Error Det Non-Fatal Error Corr Error Det Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Bit [31:22,15]: Reserved (R) - These bits are reserved and return zero on a read. Bit [21]: Trans Pending (R) - Transactions Pending. Bit [20]: AUX Power (R) - AUX Power Detected. This bit is hardwired to 0. Bit [19]: Unsup Req Det (R/W1C) - Unsupported Request Detected. Bit [18]: Fatal Error Det (R/W1C) - Fatal Error Detected. Bit [17]: Non-Fatal Error (R/W1C) - Non-Fatal Error Detected. Bit [16]: Corr Error Det (R/W1C) - Correctable Error Detected. Bit [14:12]: Max Read Request Size (R/W) - Allowable values are 000B to 011B (128 to 1024 bytes). Default is 010B (512 bytes). Bit [11]: EnSnp Not Req (R) - Enable No Snoop. This bit is hardwired to 0. Bit [10]: Aux Pwr PM En (R) - Auxiliary Power PM Enable. This bit is hardwired to 0. Bit [09]: Phntm Fnc En (R) - Phantom Functions Enable. This bit is hardwired to 0. Bit [08]: Ext Tag Fld En (R) - Extended Tag Field Enable. This bit is hardwired to 0. Bit [07:05]: Max Payload Size (R/W) - Allowable values are 000B to 011B (128 to 1024 bytes). Default is 000B (128 bytes). SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 45 SiI3132 PCI Express to Serial ATA Controller Data Sheet * * * * * Silicon Image, Inc. Bit [04]: En Rlxd Ord (R) - Enable Relaxed Ordering. This bit field is hardwired to 0. Bit [03]: UnsReq Rep En (R/W) - Unsupported Request Reporting Enable. Bit [02]: Fatal Err Rep En (R/W) - Fatal Error Reporting Enable. Bit [01]: NonFtl Err Rep En (R/W) - Non-Fatal Error Reporting Enable. Bit [00]: Corr Err Rep En (R/W) - Correctable Error Reporting Enable. Link Capabilities Address Offset: 7CH Access Type: Read Only Reset Value: 0x0000_7411 Port Number * * * * * * * L1 Exit Latency Reserved L0s Exit Latency ASPM Support 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Maximum Link Width Maximum Link Speed Bit [31:24]: Port Number (R) - This bit field is hardwired to 00H. Bit [23:18]: Reserved (R) - These bits are reserved and return zero on a read. Bit [17:15]: L1 Exit Latency (R) - This bit field is hardwired to 000B. Bit [14:12]: L0s Exit Latency (R) - This bit field is hardwired to 111B. Bit [11:10]: ASPM Support (R) - This bit field is hardwired to 01B. Bit [09:04]: Maximum Link Width (R) - This bit field is hardwired to 000001B. Bit [03:00]: Maximum Link Speed (R) - This bit field is hardwired to 0001B. Link Status and Control Address Offset: 80H Access Type: Read/Write Reset Value: 0x0011_0000 or 0x1011_0000 * * * * * * * * * * * * 46 Link Speed Reserved ASPM Control Negotiated Link Width Ext Synch Comm Clk Cfg Retrain Link Link Disable RCB Reserved Reserved Slot Clk Config Link Training Link Train Err 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Bit [31:29,15:08,02]: Reserved (R) - These bits are reserved and return zero on a read. Bit [28]: Slot Clk Config (R) - Slot Clock Configuration. This bit is 1 if the reference clock is detected. Bit [27]: Link Training (R) -This bit is hardwired to 0. Bit [26]: Link Train Err (R) - This bit is hardwired to 0. Bit [25:20]: Negotiated Link Width (R) - This bit field is hardwired to 000001B. Bit [19:16]: Link Speed (R) - This bit field is hardwired to 0001B. Bit [07]: Ext Synch (R/W) - Extended Synch. Bit [06]: Comm Clk Cfg (R/W) - Common Clock Configuration. Bit [05]: Retrain Link (R) - This bit is hardwired to 0. Bit [04]: Link Disable (R) - This bit is hardwired to 0. Bit [03]: RCB (R/W) - Read Completion Boundary. Bit [01:00]: ASPM Control (R/W) (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Global Register Offset Address Offset: F0H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved Dword Offset 00 This register provides indirect addressing of a Global Register otherwise accessible directly through Base Address Register 0. The Dword address offset for an indirect access is in bits 6 to 2; bits 31 to 7, 1, and 0 are reserved and should always be 0. This is physically the same register that is addressed by Base Address Register 2, Offset 00H. Global Register Data Address Offset: F4H Access Type: Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 As defined for indirectly accessed register This register provides the indirect access addressed by the Global Register Offset register. Port Register Offset Address Offset: F8H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved Dword Offset 00 This register provides indirect addressing of a Port Register otherwise accessible directly through Base Address Register 1. The Dword address offset for an indirect access is in bits 13 to 2; bits 31 to 14, 1, and 0 are reserved and should always be 0. This is physically the same register that is addressed by Base Address Register 2, Offset 08H. Port Register Data Address Offset: FCH Access Type: Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 As defined for indirectly accessed register This register provides the indirect access addressed by the Port Register Offset register. SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 47 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Advanced Error Reporting Capability Address Offset: 100H Access Type: Read Only Reset Value: 0x0001_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Next Capability Pointer * Version Extended Capability ID Bit [31:20]: Next Capability Pointer (R) - PCI Next Capability Pointer. This bit field is hardwired to 000H (this is the last capability). Bit [19:16]: Version (R) - This bit field is hardwired to 01H to indicate compliance with the PCI Express Specification revision 1.0a. Bit [15:00]: Extended Capability ID (R) - PCI Capability ID. This bit field is hardwired to 0001H to indicate that this is an Advanced Error Reporting Capability. * * Uncorrectable Error Status Address Offset: 104H Access Type: Read/Write 1 to Clear Reset Value: 0x0000_0000 * * * * * * * * * * * * 48 Reserved Training Error Reserved DL Protocol Err Reserved Unsup Req Err ECRC Error Malformed TLP Rx Overflow (0) Unexp Comp Comp Abort Comp Timeout FC Protocol Err Poisoned TLP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Bit [31:21,11:05,03:01]: Reserved (R) - These bits are reserved and return zero on a read. Bit [20]: Unsup Req Err (R/W1C) - Unsupported Request Error Status. Bit [19]: ECRC Error (R/W1C) - ECRC Error Status. Bit [18]: Malformed TLP (R/W1C) - Malformed TLP Status. Bit [17]: Rx Overflow (R) - Receiver Overflow Status; always 0. Bit [16]: Unexp Comp (R/W1C) - Unexpected Completion Status. Bit [15]: Comp Abort (R/W1C) - Completer Abort Status. Bit [14]: Comp Timeout (R/W1C) - Completion Timeout Status. Bit [13]: FC Protocol Err (R/W1C) - Flow Control Protocol Error Status. This bit is hardwired to 0 (as are its mask and error severity bits). Bit [12]: Poisoned TLP (R/W1C) - Poisoned TLP Status. Bit [04]: DL Protocol Err (R/W1C) - Data Link Protocol Error Status. Bit [00]: Training Error (R) - This bit is hardwired to 0 (as are its mask and error severity bits). (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Uncorrectable Error Mask Address Offset: 108H Access Type: Read/Write Reset Value: 0x0000_0000 Reserved Reserved Training Error Reserved DL Protocol Err Unsup Req Err ECRC Error Malformed TLP Rx Overflow (0) Unexp Comp Comp Abort Comp Timeout FC Protocol Err Poisoned TLP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 The bits of this register are the mask bits for corresponding bits of the Uncorrectable Error Status register. Uncorrectable Error Severity Address Offset: 10CH Access Type: Read/Write Reset Value: 0x0004_0010 Reserved Reserved Training Error Reserved DL Protocol Err Unsup Req Err ECRC Error Malformed TLP Rx Overflow (0) Unexp Comp Comp Abort Comp Timeout FC Protocol Err Poisoned TLP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 The bits of this register are the error severity bits for corresponding bits of the Uncorrectable Error Status register. Correctable Error Status Address Offset: 110H Access Type: Read/Write 1 to Clear Reset Value: 0x0000_0000 * * * * * * Reserved Rx Error Reserved REPLAY_NUM Bad DLLP Bad TLP Reserved Replay Timeout 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Bit [31:13,11:09,05:01]: Reserved (R) - These bits are reserved and return zero on a read. Bit [12]: Replay Timeout (R/W1C) - Replay Timer Timeout Status. Bit [08]: REPLAY_NUM (R/W1C) - REPLAY_NUM Rollover Status. Bit [07]: Bad DLLP (R/W1C) - Bad DLLP Status. Bit [06]: Bad TLP (R/W1C) - Bad TLP Status. Bit [00]: Rx Error (R/W1C) - Receiver Error Status. This bit is hardwired to 0 (as is the corresponding mask bit). SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 49 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Correctable Error Mask Address Offset: 114H Access Type: Read/Write Reset Value: 0x0000_0000 Reserved Reserved Rx Error Reserved REPLAY_NUM Bad DLLP Bad TLP Replay Timeout 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 The bits of this register are the mask bits for corresponding bits of the Correctable Error Status register. Advanced Error Capabilities and Control Address Offset: 118H Access Type: Read/Write Reset Value: 0x0000_00A0 Reserved * * * * * * 50 ECRC Chk En ECRC Chk Cap ECRC Gen En ECRC Gen Cap 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 First Error Pointer Bit [31: 09]: Reserved (R) - These bits are reserved and return zero on a read. Bit [08]: ECRC Chk En (R/W) - ECRC Check Enable. Bit [07]: ECRC Chk Cap (R) - ECRC Check Capable. This bit is hardwired to 1. Bit [06]: ECRC Gen En (R/W) - ECRC Generation Enable. Bit [05]: ECRC Gen Cap (R) - ECRC Generation Capable. This bit is hardwired to 1. Bit [04:00]: First Error Pointer (R). (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Header Log Address Offset: 11CH / 120H / 124H / 128H Access Type: Read Only Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Header Log (1st Dword) Header Byte 0 Header Byte 1 Header Byte 2 Header Byte 3 Header Log (2nd Dword) Header Byte 4 Header Byte 5 Header Byte 6 Header Byte 7 Header Log (3rd Dword) Header Byte 8 Header Byte 9 Header Byte 10 Header Byte 11 Header Log (4th Dword) Header Byte 12 Header Byte 13 Header Byte 14 Header Byte 15 This 16-byte register contains the header of a TLP associated with an error. Internal Register Space - Base Address 0 These registers are 32 or 64 bits wide and are the Global Registers of the SiI3132 controller. Access to this register space is through the PCI Memory space. Table 30. SiI3132 Internal Register Space - Base Address 0 Address Offset 00H 04H 08H-3FH 40H 44H 48H 4CH-5FH 60H 64H 68H 6CH 70H 74H 78H-7FH SiI-DS-0138-E Register Name Port 0 Slot Status Port 1 Slot Status Reserved Global Control Global Interrupt Status PHY Configuration Reserved I2C Control I2C Status I2C Slave Address I2C Data Buffer Flash Address GPIO Reserved Flash Data (c) 2007-2010 Silicon Image, Inc. All rights reserved. 51 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Global Port Slot Status Address Offset: 00H-07H Access Type: Read Reset Value: 0x0000_0000 Attention 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Slot Status These two registers provide the Status for the 31 Command Slots for each of the 2 ports. These registers also appear in Port register space. Reading this register clears the Command Completion Status for the port if the Interrupt No Clear on Read bit (bit 3) of the Port Control Set register is 0. The register bits are defined as follows: * Bit [31]: Attention (R) - This bit indicates that something occurred in the corresponding port and it requires the attention of the host. Other port registers must be examined to determine the origin of the error. This bit is the logical OR of the masked interrupt conditions, except for Command Completion, reported in the Port Interrupt Status register. * Bit [30:00]: Slot Status (R) - These bits are the Active status bits corresponding to Slot numbers 30 to 0. The Active status bit for a slot is set when the Slot number is written to the Command Execution FIFO using the direct command transfer method or when a Command Activation register is written using the indirect command transfer method.. Global Control Address Offset: 40H Access Type: Read/Write Reset Value: 0x8100_0000 Port 0 Int Enable Reserved Port 1 Int Enable Reserved 3Gb/s Capable Global Reset MSIACK I2C Int Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 This register controls various functions of the chip. * Bit [31]: Global Reset (R/W). This bit, when set to 1, asserts a port reset to all ports. This bit must be cleared to 0 to allow normal operation. Once set by this bit, all port resets will remain set to one until explicitly cleared to zero through the individual port control clear registers. Refer to the Port Control Set register description on page 60 for more information. * Bit [30]: MSI Acknowledge (W). Writing 1 to this bit acknowledges a Message Signaled Interrupt (MSI) and permits generation of another MSI. This bit is cleared immediately after the acknowledgement is recognized by the control logic, hence the bit will always be read as a 0. If all interrupt conditions are removed following an MSI, it is not necessary to assert this Acknowledge; another MSI will be generated when an interrupt condition occurs. * Bit [29]: I2C Int Enable (R/W). This bit, when set to 1, allows assertion of an interrupt when the I2C interrupt is asserted. When set to 0, the interrupt is masked. * Bit [28:25,23:2]: Reserved (R). These bits are reserved and will return zeroes when read. * Bit [24]: 3Gb/s Capable (R). This bit is hardwired to 1. * Bit [1:0]: Port Interrupt Enable (R/W). These bits, when set to 1, allow assertion of an interrupt of the corresponding ports. When set to 0, the corresponding port interrupts are masked. 52 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Global Interrupt Status Address Offset: 44H Access Type: Read/Write 1 Clear Reset Value: 0x0000_0000 Reserved Port 0 Interrupt Port 1 Interrupt I2C Interrupt Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 This register is used to determine the status of various chip functions. * Bit [31:30]: Reserved (R). This bit field is reserved and returns zeroes when read. * Bit [29]: I2C Interrupt (R). This bit indicates that the I2C Interrupt is pending. The interrupt source must be cleared (in the I2C Status register) for this bit to be 0. This bit will not report interrupt sources that are not enabled in the I2C Control register. * Bit [28:2]: Reserved (R). This bit field is reserved and returns zeroes when read. * Bit [1:0]: Port Interrupt Status (R/W1C). These bits, when set to 1, indicate that the corresponding port has an interrupt condition pending. Writing a 1 to any of these bits clears the corresponding Command Completion Interrupt Status, but not other interrupt sources. PHY Configuration Address Offset: 48H Access Type: Read/Write Reset Value: 0x0000_2C40 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved PHY Config This register is reset to 0x00002C40. * Bit [31:16]: Reserved (R/W) - This bit field is reserved and must be always be zeros. * Bit [15:04]: PHY Configuration (R/W) - These bits should not be changed from their defaults as erratic operation may result. * Bit [03:00]: SATA SSC (R/W) - If this bit field is set to 1111b, all channel Tx outputs Spread Spectrum Clocking. SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 53 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. BIST Control Address Offset: 50H Access Type: Read/Write Reset Value: 0x0000_0000 Reserved BISTcompsel BISTenable BISTpatsel 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved BISTrun This register is used to control Data Loopback BIST. * Bit [31]: BISTenable (R/W) - This bit enables the data paths for running data loopback BIST. * Bit [30]: BISTpatsel (R/W) - This bit selects whether a repeating pattern (supplied from the BIST Pattern register) or a pseudorandom pattern is used for running data loopback BIST. Setting the bit to 1 selects the repeating pattern. * Bit [29:18]: Reserved (R/W). These bits are reserved and must be written as zeros. * Bit [17:16]: BISTcompsel (R/W). This bit field selects the port from which loopback data is selected for pattern comparison. * Bit [15:04]: Reserved (R/W). These bits are reserved and must be written as zeros. * Bit [03:00]: BISTrun (R/W). This bit field selects the port(s) that transmit loopback data. BIST Pattern Address Offset: 54H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 BIST Pattern This register contains the 32-bit fixed pattern that is repeatedly transmitted in data loopback when the BISTpatsel bit (bit 30) of the BIST Control register is set to 1. BIST Status Address Offset: 58H Access Type: Read Reset Value: 0x8000_0000 BISTgood 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 * * * 54 Reserved BISTerrcnt Bit [31]: BISTgood (R) - This bit indicates that all comparisons have been good since initiating data loopback BIST. This bit is initialized to 1 when the BISTenable bit is zero in the BIST Control register. Bit [30:12]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [11:00]: BISTerrcnt (R). This bit field indicates the number of comparisons that have been in error since initiation of data loopback BIST. This counter is a saturating counter (it stops counting at 0FFFH). This counter is cleared when the BISTenable bit is 0 in the BIST Control register. (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. I2C Control Address Offset: 60H Access Type: Read/Write Reset Value: 0x0000_0000 START ACK/NACK Ctrl STOP SCL Enable Master Abort Transfer Byte Tx MT Int En Gen Call Disable Unit Enable STOP Det Int En Bus Error Int En Rx Full Int En Reserved Fast Mode Unit Reset Addr Det Int En Arb Loss Det Int En 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 This register contains bits to control the operation of the I2C interface. * Bit [31:16]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [15]: Fast Mode (R/W). This bit, when set, enables 400 kbit/s operation (instead of 100 kbit/s) * Bit [14]: Unit Reset (R/W). This bit, when set, resets the I2C controller. * Bit [13]: Addr Det Int En (R/W). Slave Address Detected Interrupt Enable - This bit enables interrupt generation when the Slave Address or the General Call Address is detected. * Bit [12]: Arb Loss Det Int En (R/W). Arbitration Loss Detected Interrupt Enable - This bit enables interrupt generation upon losing arbitration in Master Mode. If this bit is not set, and arbitration is lost during transmission of the control byte, the arbitration and transmission will be automatically repeated. * Bit [11]: STOP Det Int En (R/W). Slave STOP Detected Interrupt Enable - This bit enables interrupt generation when a STOP condition while in Slave Mode is detected. * Bit [10]: Bus Error Int En (R/W). Bus Error Interrupt Enable - This bit enables interrupt generation when an I2C error is detected. * Bit [09]: Rx Full Int En (R/W). Receive Buffer Full Interrupt Enable - This bit enables interrupt generation when a byte has been received and is in the I2C Data Buffer register. * Bit [08]: Tx MT Int En (R/W). Transmit Buffer Empty Interrupt Enable - This bit enables interrupt generation after the data byte in the I2C Data Buffer register is transmitted. * Bit [07]: Gen Call Disable (R/W). General Call Disable - This bit disables detection of a General Call Address. * Bit [06]: Unit Enable (R/W). This bit must be set to enable any I2C controller operations. * Bit [05]: SCL Enable (R/W). This bit must be set to enable the I2C Clock output for Master Mode operations. * Bit [04]: Master Abort (R/W). This bit may be set along with STOP to send a STOP without first transferring a byte. * Bit [03]: Transfer Byte (R/W). Set to initiate the transfer to/from the Data Buffer. * Bit [02]: ACK/NACK Ctrl (R/W). Set to send a NACK instead of an ACK after receiving a data byte. An ACK is sent in response to slave address detection regardless of this bit. Sending a NACK in Slave Mode will set the Bus Error status. * Bit [01]: STOP (R/W). Set to send a STOP following transfer of a byte (using Transfer Byte) or immediately (using Master Abort). * Bit [00]: START (R/W). Set to send a START prior to transfer of a byte (using Transfer Byte). SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 55 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. I2C Status Address Offset: 64H Access Type: Read/Write 1 to Clear Reset Value: 0x0000_0000 Read/Write ACK/NACK Status Bus Busy Unit Busy STOP Det Arb Loss Det Reserved Tx MT Bus Error Det Slave Addr Det Gen Call Det Rx Full 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 This register contains bits to report the status of the I2C interface. * Bit [31:11]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [10]: Bus Error Det (R/W1C). Bus Error Detected - This bit reports the detection of an illegal NACK either received in Master Mode or sent in Slave Mode. This bit is not set by the legal NACK at the end of a transfer that signals the end to the slave. * Bit [09]: Slave Addr Det (R/W1C). Slave Address Detected - This bit reports the detection of the Slave Address or of the General Call Address (when enabled). The byte received containing the address is placed into the I2C Data Buffer register. * Bit [08]: Gen Call Det (R/W1C). General Call Address Detected - This bit reports the detection of the General Call Address. * Bit [07]: Rx Full (R/W1C). I2C Data Buffer Receive Full - A data byte has been received and an ACK or NACK has been sent. This bit is set on the rising edge of the I2C clock allowing for some minimal (one bit) time for an interrupt before insertion of wait states. * Bit [06]: Tx MT (R). I2C Data Buffer Transmit Empty - A data byte has been transmitted and an ACK or NACK has been received. This bit is set on the rising edge of the I2C clock allowing for some minimal (one bit) time for an interrupt before insertion of wait states. * Bit [05]: Arb Loss Det (R/W1C). Arbitration Loss Detected - This bit indicates that arbitration has been lost. If the corresponding interrupt is not enabled, and the arbitration loss is detected during selection, i.e., during the control byte transmission, the arbitration will be repeated automatically; if arbitration is lost later during data transmission, no repeat is possible and is not attempted. * Bit [04]: STOP Det (R/W1C). Slave STOP Detected. * Bit [03]: Bus Busy (R). Indicates that the I2C bus is busy because of activity other than that generated by the I2C controller. * Bit [02]: Unit Busy (R). Indicates that the I2C controller is busy. * Bit [01]: ACK/NACK Status (R). Indicates status of last ACK or NACK sent or received. * Bit [00]: Read/Write (R). Indicates state of the R/W# bit of the I2C slave address (either the one sent in Master Mode or the one received in Slave Mode). I2C Slave Address Address Offset: 68H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved Slave Address This register contains the 7-bit Slave Address to which the I2C controller will respond. 56 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. I2C Data Buffer Address Offset: 6CH Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved Data Buffer This register contains the buffer for I2C send/receive data. Flash Address Address Offset: 70H Access Type: Read/Write Reset Value: 0xXXXX_XXXX Mem Access Start Mem Access Type Reserved 0b0001 Mem Present GPIO Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved Memory Address This register is the address and command/status register for the flash memory interface. The register bits are defined as follows: * Bit [31]: GPIO Enable (R/W). This bit, when set to 1, enables the use of the flash Data pins for General Purpose I/O. * Bit [30:27]: Reserved (R). This bit field is reserved and returns 0001 on a read. * Bit [26]: Mem Present (R) - Memory Present. This bit set indicates that the auto-initialization signature was read correctly from the flash Memory. * Bit [25]: Mem Access Start (R/W) - Memory Access Start. This bit is set to initiate an operation to flash memory. This bit is self-clearing when the operation is complete. * Bit [24]: Mem Access Type (R/W) - Memory Access Type. This bit is set to define a read operation from flash memory. This bit is cleared to define a write operation to flash memory. * Bit [23:19]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [18:00]: Memory Address (R/W). This bit field is programmed with the address for a flash memory read or write access. Flash Memory Data / GPIO Control Address Offset: 74H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved GPIO Control Transition Detect Memory Data This register contains the GPIO data/control fields and the flash memory data register. * Bit [31:24]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [23:16]: GPIO Control (R/W). The bits of this field are written to control the output type for corresponding flash data lines; if a bit is a 1 the corresponding output is an open drain output (only driven LOW); if a bit is 0 the SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 57 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. corresponding output is always driven. To use a GPIO pin as an input, the control bit must be set to 1 (open-drain output) and the data bit must be set to 1 (undriven). Bit [15:08]: Transition Detect (R/C). The bits of this field report signal transition detection on the corresponding Flash data input; reading the register resets the transition detect bits. Bit [07:00]: Memory Data (R/W) - Flash Memory Data. This bit field is used for flash write data on a write operation, and returns the flash read data on a read operation. For GPIO, this field is used to write the GPIO output register and to read the GPIO input signals. * * Internal Register Space - Base Address 1 These registers are 32 bits wide and are the Port Registers and LRAM of the SiI3132 controller. Access to these registers is through the PCI Memory space. Register descriptions that follow specify the address offset for Port 0; Port 1 registers are at the Port 0 offset plus 2000H. Table 31. SiI3132 Internal Register Space - Base Address 1 Address Offset 000H-F7FH F80H-FFFH 1000H 1004H 1008H 100CH 1010H 1014H 1018H 101CH 1020H 1024H 1028H 102CH 1030H-103FH 1040H 1044H 1048H 104CH 1050H 1054H-17FFH 1800H 1804H-1BFFH 1C00H-1CF7H 1CF8H-1E03FH 1E04H 1E08H-1EFFH 1F00H 1F04H 1F08H 1F0CH 1F10H 1F14H-1FFFH 2000H-3FFFH 58 Register Name Port 0 LRAM Slots Port Multiplier Device Status/QActive Registers Write: Port 0 Control Set / Read: Port 0 Status Write: Port 0 Control Clear Port 0 Interrupt Status Reserved Port 0 Interrupt Enable Set Port 0 Interrupt Enable Clear Reserved 32-bit Activation Upper Address Port 0 Command Execution FIFO Port 0 Command Error Port 0 FIS Configuration Port 0 PCI Exp Request FIFO Threshold Reserved Port 0 8B/10B Decode Error Counter Port 0 CRC Error Counter Port 0 Handshake Error Counter Reserved Port PHY Configuration Reserved Port 0 Slot Status Reserved Command Activation Registers Reserved Port Context Register Reserved Port 0 SControl Port 0 SStatus Port 0 SError Port 0 SActive (indirect location) Port 0 SNotification Reserved Port 1 Registers mapped as above (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Port LRAM Address Offset: 000H-FFFH Access Type: Read/Write Reset Value: indeterminate The Port LRAM consists of 31 Slots of 128 bytes each and a 32nd slot used to hold 16 Port Multiplier Device Specific Registers. Table 32. Port LRAM layout Address Offset 000H-07FH 080H-0FFH 100H-17FH 180H-EFFH F00H-F7FH F80H-F83H F84H-F87H F88H-F8BH F8CH-F8FH F90H-FF7H FF8H-FFBH FFCH-FFFH Description Slot 0 Slot 1 Slot 2 Slots 3-29 Slot 30 Port Multiplier Device 0 Status Register Port Multiplier Device 0 QActive Register Port Multiplier Device 1 Status Register Port Multiplier Device 1 QActive Register Port Multiplier Device Registers for Devices 2-14 Port Multiplier Device 15 Status Register Port Multiplier Device 15 QActive Register Table 33. Port LRAM Slot layout Address Offset Description 000H-01FH Current FIS and Control Port Request 020H-02FH Scatter/Gather Entry 0 or ATAPI command packet Block (PRB) 030H-03FH Scatter/Gather Entry 1 040H-047H Command Activation Register (Actual) 040H-07FH Scatter/Gather Table 1C00H-1C07H Command Activation Register (Shadow) Note: A Port LRAM Slot is 128 bytes used to define Serial-ATA commands. The addresses shown above are for slot 0. Port Slot Status Address Offset: 1800H Access Type: Read Reset Value: 0x0000_0000 Attention 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Slot Status This register provides the status for the 31 Command Slots for the Serial-ATA port. This register also appears along with the Global Port Slot Status register of the other port in Global register space. Reading this register clears the Command Completion Status for the port if the Interrupt No Clear on Read bit (bit 3) of the Port Control Set register is 0. The register bits are defined as follows: * Bit [31]: Attention (R) - This bit indicates that something occurred in the port that requires the attention of the host. Other port registers must be examined to determine the origin of the error. This bit is the logical OR of the masked interrupt conditions reported in the Port Interrupt Status register. * Bit [30:0]: Slot Status (R) - These bits are the Active status bits corresponding to Slot numbers 30 to 0. The Active status bit is set when a command is transferred to the Slot RAM. SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 59 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Port Control Set Address Offset: Set: 1000H Access Type: Write One To Set Reset Value: N/A Port Reset Device Reset Port Initialize Interrupt NCoR LED Disable Resume Packet Length Transmit BIST CONT Disable Scramble Disable Interlock Reject t 32-bit Activation PM Enable Interlock Accept Reserved LED On 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Auto Interlock Accept Reserved 26 OOB Bypass 31 30 29 28 27 This register is used to direct various port operations. A 1 written to a bit position sets that bit in the control register. * Bit [31:26,24:16]: Reserved (R). These bits are reserved. * Bit [25]: OOB Bypass (W1S). If this bit is set, the Link will bypass the OOB initialization sequence following a reset. This bit is reset by Global Reset, not by Port Reset. * Bit [15]: LED On (W1S). This bit turns on the LED Port Activity indicator regardless of the state of LED Disable (bit 4). * Bit [14]: Auto Interlock Accept (W1S). When this bit is set the link will accept any interlocked FIS reception. The link will transmit R_OK in response to the received FIS. * Bit [13]: PM Enable (W1S). This bit enables Port Multiplier support. * Bit [12]: Interlock Accept (W1S). This bit is used to signal the link to accept an interlocked FIS reception. The link will transmit R_OK in response to the received FIS. This bit is self-clearing. * Bit [11]: Interlock Reject (W1S). This bit is used to signal the link to reject an interlocked FIS reception. The link will transmit R_ERR in response to the received FIS. This bit is self-clearing. * Bit [10]: 32-bit Activation (W1S). When this bit is set to 1, a write to the low 32 bits of a Command Activation register causes the contents of the 32-bit Activation Upper Address register to be written to the upper 32 bits of the Command Activation register and triggers command execution. When this bit is 0, a write to the upper 32 bits or all 64 bits of a Command Activation register is required to trigger command execution. This bit is set for environments that do not address more than 232 bytes of host memory. * Bit [9]: Scrambler Disable (W1S). When this bit is set to 1, the Link scrambler operation is disabled. * Bit [8]: CONT Disable (W1S). When this bit is set to 1, the Link will not generate a CONT following repeated primitives. * Bit [7]: Transmit BIST (W1S). This bit causes transmission of a BIST FIS. * Bit [6]: Resume (W1S). This bit is used to enable processing of outstanding commands to additional devices connected to a port multiplier after a command error has occurred. When this bit is set, the internal BUSY status is set for the device corresponding to the value of the current Port Multiplier Port. This prevents additional commands from being sent to the device in error until a Port Initialize operation is performed. * Bit [5]: Packet Length (W1S). This bit directs the length of the packet command to be sent for commands with packet protocol. When this bit is 0, a 12-byte packet is sent. When this bit is 1, a 16-byte packet is sent. This bit should be set to the same value as derived from word 0 of the data returned by the identify packet command. * Bit [4]: LED Disable (R/W). This bit disables the operation of the LED Port Activity indicator. * Bit [3]: Interrupt No Clear on Read (W1S). When this bit is set to 1, a command completion interrupt may be cleared only by writing a one to the Command Completion bit in the Port Interrupt Status register. When this bit is 0, reading the Port Slot Status register may also be used to clear the Command Completion interrupt. * Bit [2]: Port Initialize (W1S). Setting this bit to 1 causes all commands to be flushed from the port and all command execution parameters to be set to an initialized state. Setting this bit to 1 causes the Port Ready bit in the Port Status register to be cleared to 0. When the initialization procedure is complete, the Port Ready bit is set to 1. This bit is self-clearing and is cleared upon execution by the port. 60 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. * Bit [1]: Device Reset (W1S). Setting this bit to 1 causes all commands to be flushed from the port and all command execution parameters to be set to an initialized state. Setting this bit to 1 causes the Port Ready bit in the Port Status register to be cleared to 0. The port will generate the COMRESET primitive on the Serial ATA bus. When the out of band sequence and initialization procedure is complete, the Port Ready bit is set to 1. This bit is selfclearing and is cleared upon execution by the port. Bit [0]: Port Reset (W1S). Setting this bit to 1 causes the port to be held in a reset state. No commands are executed while in this state. All port registers and functions are reset to their initial state, except as noted below. All commands are flushed from the port and all command execution parameters are set to an initialized state. Setting this bit to 1 causes the Port Ready bit in the Port Status register to be cleared to 0. Upon setting this bit to 0 from an asserted state, the port generates the COMRESET primitive on the Serial ATA bus. When the out of band sequence and initialization procedure is complete, the Port Ready bit is set to 1. This bit is set to 1 by the Global reset, which is set by a PCI reset, and remains set until cleared by the host by writing a 1 to bit 0 of the Port Control Clear register. The register bits that are not initialized by the Port Reset are: * OOB Bypass (bit 25) in Port Control (this register) * Port PHY Configuration register (all bits) * Port Status Address Offset: 1000H Access Type: Read Reset Value: 0x001F_0001 Port Reset Device Reset Port Initialize LED Disable Interrupt NCoR Resume Packet Length Transmit BIST CONT Disable 32-bit Activation Scramble Disable Interlock Reject Interlock Accept PM Enable Active Slot Auto Interlock Accept Reserved LED On Reserved OOB Bypass Port Ready 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 This register is used to determine the status of various port functions. * Bit [31]: Port Ready (R). This bit reports the Port Ready status. The transition from 0 to 1 of this bit generates the Port Ready Interrupt Status (bit 18/2 of the Port Interrupt Status register). * Bit [30:26,24:21]: Reserved (R). These bits are reserved. * Bit [20:16]: Active Slot (R). This bit field contains the slot number of the command currently being executed. When a command error occurs, this bit field indicates the slot containing the command in error. * Bit [25,15:0]: These bits reflect the current state of the corresponding bits in the Port Control Set register. Refer to that register for a complete description. Port Control Clear Address Offset: 1004H Access Type: Write 1 To Clear Reset Value: N/A SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. Port Reset Reserved Interrupt NCoR LED Disable Packet Length Resume Transmit BIST CONT Disable Scramble Disable 32-bit Activation Reserved PM Enable Auto Interlock Accept Reserved LED On Reserved OOB Bypass 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 61 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. This register is used to direct various port operations. A 1 written to a bit position clears that bit in the Port Control Set register. * Bit [31:26,24:16,12:11,2:1]: Reserved (R). These bits are reserved. * Bit [25, 15:13,10:3,0]: (W1C) Writing a 1 to these bits clears the associated bit position of the Port Control Set register. Refer to that register for bit descriptions. Port Interrupt Status Address Offset: 1008H Access Type: Read/Write 1 Clear Reset Value: 0x0000_0000 Cmd Completion Port Ready Command Error PM Change PhyRdyChg UnrecFIS Comwake DevExchg CRC Error Thresh 8b/10 Error Thresh SDB Notify Reserved Hshk Error Thresh Command Error Cmd Completion Port Ready PM Change UnrecFIS Comwake PhyRdyChg Reserved SDB Notify Hshk Error Thresh CRC Error Thresh 8b/10 Error Thresh DevExchg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 This register is used to report the interrupt status. The status bits in the upper half of the register report the described condition. The status bits in the lower half of the register are masked by the corresponding interrupt enable bits or by the setting in the corresponding threshold registers. Writing a 1 to either interrupt status bit clears it. * Bit [31:28,15:12]: Reserved (R). These bits are reserved. * Bit [27/11]: SDB Notify (W1C). This bit indicates that a Set Device Bits FIS was received with the N-bit (bit 15 of first Dword) set to 1. * Bit [26/10]: Handshake Error Threshold (W1C). This bit indicates that the Handshake error count is equal to or greater than the Handshake error threshold. Bit 10 is masked if the Port Handshake Error Counter Threshold register contains a zero threshold setting. When a 1 is written to this bit, both the status bit and the Handshake Error Counter are cleared. * Bit [25/9]: CRC Error Threshold (W1C). This bit indicates that the CRC error count is equal to or greater than the CRC error threshold. Bit 9 is masked if the Port CRC Error Counter Threshold register contains a zero threshold setting. When a 1 is written to this bit, both the status bit and the CRC Error Counter are cleared. * Bit [24/8]: 8b/10b Decode Error Threshold (W1C). This bit indicates that the 8b/10b Decode error count is equal to or greater than the 8b/10b Decode error threshold. Bit 8 is masked if the Port 8B/10B Decode Error Counter Threshold register contains a zero threshold setting. When a 1 is written to this bit, both the status bit and the 8b/10b Decode Error Counter are cleared. * Bit [23/7]: DevExchg (Device Exchanged) (W1C) - This bit is the X bit in the DIAG field of the SError register. It may be cleared by writing a 1 to the corresponding bit of either register. * Bit [22/6]: UnrecFIS (Unrecognized FIS Type) (W1C) - This bit is the F bit in the DIAG field of the SError register. It may be cleared by writing a corresponding one bit to either register. * Bit [21/5]: ComWake (W1C) - This bit is the W bit in the DIAG field of the SError register. It may be cleared by writing a corresponding one bit to either register. * Bit [20/4]: PhyRdyChg (W1C) - This bit is the N bit in the DIAG field of the SError register. It may be cleared by writing a corresponding one bit to either register. * Bit [19/3]: PM Change (W1C). This bit indicates that a change has occurred in the power management state. * Bit [18/2]: Port Ready (W1C). This bit indicates that the port has become ready to accept and execute commands. This status indicates that Port Ready (bit 31 in the Port Status register) has made a 0 to 1 transition. Clearing this status does not change the Port Ready bit in the Port Status register and this status is not set subsequently until the Port Ready bit changes state. * Bit [17/1]: Command Error (W1C). This bit indicates that an error occurred during command execution. The error type can be determined via the Port Command Error register. * Bit [16/0]: Command Completion (W1C). This bit indicates that one or more commands have completed execution. 62 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Port Interrupt Enable Set / Port Interrupt Enable Clear Address Offset: 1010H / 1014H Access Type: Read/Write 1 Set/Write 1 Clear Reset Value: 0x0000_0000 Cmd Completion Reserved DevExchg UnrecFIS Comwake PhyRdyChg PM Change Port Ready Command Error Reserved SDB Notify Interrupt Steering 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 The Interrupt Enable register is controlled by these registers. Writing to the Port Interrupt Enable Set register sets the Interrupt Enable bits. The enable bit is set for each corresponding bit to which 1 is written. Writing to the Port Interrupt Enable Clear register clears the Interrupt Enable bits; the enable bit is cleared for each corresponding bit to which a 1 is written. The Interrupt Enable register may be read at either address offset. Bits 8, 9, and 10 do not have an enable bit; the corresponding interrupts are enabled by corresponding threshold registers. * Bit [31:30]: Interrupt Steering (R/W). This bit field specifies which one of the four interrupts is to be used for interrupts from this port. INTA is selected by 00B; INTB by 01B; INTC by 10B; and INTD by 11B. * Bit [29:12,10:8]: Reserved (R). These bits are reserved and return 0s on a read. * Bit [11,7:0]: Interrupt Enables (R/W1S/W1C). These bits are the interrupt enables for the corresponding bits of the Interrupt Status register. 32-bit Activation Upper Address Address Offset: 101CH Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Upper Address This register contains the 32-bit value written to the upper half of the Command Activation register when the lower half of that register is written and the 32-bit Activation control bit (bit 10) is set in the Port Control Set register. Port Command Execution FIFO Address Offset: 1020H Access Type: Read/Write Reset Value: 0x0000_00XX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Execution Slot Reserved Number When written, this register causes the supplied slot number to be pushed into the tail of the command execution FIFO. A valid PRB must be populated in the associated slot in port LRAM. When read, this register supplies the entry at the head of the command execution FIFO. The FIFO is not popped as a result of a read operation. Port Command Error Address Offset: 1024H Access Type: Read Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Error Code SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 63 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. This register contains the error type resulting from a command error. Table 34 lists the error codes, error names, and error descriptions. Table 34. Command Error Codes Error Name DEVICEERROR Code Description 1 The ERR bit was set in a register - device to host FIS received from the device. The task file registers are written back to PRB slot for host scrutiny. SDBERROR 2 The ERR bit was set in a set device bits FIS received from the device. DATAFISERROR 3 The controller detected an error during command execution that was not reported by the device upon command completion. SENDFISERROR 4 The controller was unable to send the Initial command FIS for a command. This can occur if a low-level link error occurs during command transmission. INCONSISTENTSTATE 5 The controller detected an inconsistency in protocol. Any departure from standard Serial ATA protocol that causes indecision in the internal sequencers will cause this error. DIRECTIONERROR 6 A Data FIS was received when a write data protocol was specified or a DMA Activate FIS was received when a read data protocol was specified. UNDERRUNERROR 7 While transferring data from the controller to a device, the end of the Scatter Gather list was encountered before the entire transfer was completed. The device is requesting additional data but there is no Scatter Gather Entry to define the source of data. OVERRUNERROR 8 While transferring data from a device to the controller, the end of the Scatter Gather list was encountered before the entire transfer was completed. Data was received from the device but there is no Scatter Gather Entry to define where the data should be deposited. LLOVERRUNERROR 9 Low level overrun error. While transferring data from a device to the controller, the transfer count received in a PIO Setup or DMA Setup FIS has been satisfied and there is additional data being received from the device. PACKETPROTOCOLERROR 11 During the first PIO setup of Packet command, the data direction bit was invalid, indicating a transfer from device to host. PLDSGTERRORBOUNDARY 16 A requested Scatter Gather Table not aligned on a quadword boundary. All addresses defining Scatter Gather Tables must be quadword aligned. Bits[2:0] must be zeroes. PLDSGTERRORTARGETABORT 17 A PCI Target Abort occurred while the controller was fetching a Scatter Gather Table from host memory. PLDSGTERRORMASTERABORT 18 A PCI Master Abort occurred while the controller was fetching a Scatter Gather Table from host memory. PLDSGTERRORPCIPERR 19 A PCI Parity Error occurred while the controller was fetching a Scatter Gather Table from host memory. PLDCMDERRORBOUNDARY 24 The address of a PRB written to a Command Activation register was not aligned on a quadword boundary. All PRB addresses must be quadword aligned. Bits[2:0] must be zeroes. PLDCMDERRORTARGETABORT 25 A PCI Target Abort occurred while the controller was fetching a Port Request Block (PRB) from host memory. PLDCMDERRORMASTERABORT 26 A PCI Master Abort occurred while the controller was fetching a Port Request Block (PRB) from host memory. PLDCMDERRORPCIPERR 27 A PCI Parity Error occurred while the controller was fetching a Port Request Block (PRB) from host memory. PSDERRORTARGETABORT 33 A PCI Target Abort occurred while data transfer was underway between the controller and host memory. PSDERRORMASTERABORT 34 A PCI Master Abort occurred while data transfer was underway between the controller and host memory. PSDERRORPCIPERR 35 A PCI Parity Error occurred while data transfer was underway between the controller and host memory. SENDSERVICEERROR 36 A FIS was received while attempting to transmit a Service FIS. Following the receipt of a Set Device Bits FIS containing a service request, the device sent another FIS before allowing the host to send a Service FIS. 64 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Port FIS Configuration Address Offset: 1028H Access Type: Read/Write Reset Value: 0x1000_1555 FISOcfg FISD9cfg FISD4cfg FISC7cfg FISBFcfg FISB8cfg FISA6cfg FISA1cfg FIS5Fcfg FIS58cfg FIS46cfg FIS41cfg FIS39cfg FIS34cfg FIS27cfg Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 This register contains bits for controlling Serial ATA FIS reception. For each possible FIS type, a 2-bit code defines the desired reception behavior as follows: * 00 - Accept FIS without interlock. * 01 - Reject FIS without interlock * 10 - Interlock FIS. Receive FIS into slot reserved for interlocked FIS reception. If no slot has been reserved, reject the FIS. * 11 - Reserved. Bit[1:0] (FISOcfg) defines the 2-bit code for all other FIS types not defined by bits [29:2]. Table 35 defines the default behavior of FIS configuration. Table 35. Default FIS Configurations FIS Code FIS Name 27h 34h 39h 41h 46h 58h 5Fh A1h A6h B8h BFh C7h D4h D9h Others Register (Host to Device) Register (Device to Host) DMA Activate DMA Setup Data BIST Activate PIO Setup Set Device Bits reserved reserved reserved reserved reserved reserved reserved Configuration Bits Signals Default Value fis27cfg[1:0] 01b fis34cfg[1:0] 00b fis39cfg[1:0] 00b fis41cfg[1:0] 00b fis46cfg[1:0] 00b fis58cfg[1:0] 00b fis5Fcfg[1:0] 00b fisa1cfg[1:0] 00b fisa6cfg[1:0] 01b fisb8cfg[1:0] 01b fisbFcfg[1:0] 01b fisc7cfg[1:0] 01b fisd4cfg[1:0] 01b fisd9cfg[1:0] 01b fisocfg[1:0] 01b Default Action reject FIS without interlock accept FIS without interlock accept FIS without interlock accept FIS without interlock accept FIS without interlock accept far-end retimed loopback, reject any other accept FIS without interlock accept FIS without interlock reject FIS without interlock reject FIS without interlock reject FIS without interlock reject FIS without interlock reject FIS without interlock reject FIS without interlock reject FIS without interlock Port PCI Express Request FIFO Threshold Address Offset: 102CH Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved SiI-DS-0138-E PCI Exp Write Request Threshold Reserved PCI Exp Read Request Threshold (c) 2007-2010 Silicon Image, Inc. All rights reserved. Reserved 65 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. This register contains threshold levels at which the PCI Express master state machine requests the PCI Express bus relative to the amount of data or free space in the data FIFO. The data FIFO capacity is 2 kB (256 Qwords). When writing to host memory (reading data from a device), the PCI Express Write Request Threshold is compared to the amount of data in the data FIFO. When the FIFO contents exceed the threshold value, a request is issued to write the data to host memory, emptying the contents of the data FIFO. Before the SiI3132 controller loads its FIFO with data from the host memory that it intends to write to a device, it compares the PCI Express Read Request Threshold register to the amount of free space in the data FIFO. When the free space in the FIFO exceeds the threshold value, the controller proceeds to fill the FIFO from host memory. * Bit [31:27]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [26:19]: PCI Exp Write Request Threshold (R/W). This field defines the number of Qwords that must be in the data FIFO before issuing a PCI Express request. A value of 0 causes a request if the FIFO contains any amount of data. * Bit [18:16]: Reserved (R). This bit field is reserved and returns zeros on a read. This field is defined so that the host may write a byte count value into the threshold register. * Bit [15:11]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [10:3]: PCI Exp Read Request Threshold (R/W). This field defines the number of Qwords that must be available in the data FIFO before issuing a PCI Express request. A value of 0 causes a request if the FIFO contains any free space and the DMA is active. * Bit [2:0]: Reserved (R). This bit field is reserved and returns zeros on a read. This field is defined so that the host may write a byte count value into the threshold register. Port 8B/10B Decode Error Counter Address Offset: 1040H Access Type: Read/Write/Clear Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 8B/10B Decode Error Threshold 8B/10B Decode Error Counter This register counts the number of 8B/10B Decode Errors that have occurred since last cleared. * Bit [31:16]: 8B/10B Decode Error Threshold (R/W). This bit field defines the count at which an interrupt is asserted. When the count in bits 15:0 is equal to this value, an 8B/10B interrupt will be latched. A threshold value of 0 disables interrupt assertion and masks the corresponding interrupt status bit in the Port Interrupt Status register. * Bit [15:0]: 8B/10B Decode Error Count (R/WC). This bit field represents the count of 8B/10B errors that have occurred since this register was last written. Any write to this register field clears both the counter and the interrupt condition. Clearing the interrupt status bit also clears the counter. The count will not overflow. Once this register reaches its maximum count, it retains that count until cleared to 0 by a write operation. Port CRC Error Counter Address Offset: 1044H Access Type: Read/Write/Clear Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 CRC Error Counter Threshold CRC Error Counter This register counts the number of Serial ATA CRC Errors that have occurred since it was cleared the last time. * Bit [31:16]: Serial ATA CRC Error Threshold (R/W). This bit field defines the count at which an interrupt will be asserted. When the count in bits 15:0 is equal to this value, a Serial ATA CRC interrupt is latched. A threshold value of 0 disables interrupt assertion and masks the corresponding interrupt status bit in the Port Interrupt Status register. 66 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. * Bit [15:0]: Serial ATA CRC Error Count (R/WC). This bit field represents the count of Serial ATA CRC errors that have occurred since this register was written the last time. Any write to this register will clear both the counter and the interrupt condition. Clearing the interrupt status bit will also clear the counter and the count will not overflow. Once this register reaches its maximum count, it will retain that count until cleared to 0 by a write operation. Port Handshake Error Counter Address Offset: 1048H Access Type: Read/Write/Clear Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Serial ATA Handshake Error Counter Threshold Serial ATA Handshake Error Counter This register counts the number of Serial ATA Handshake Errors that have occurred since it was cleared the last time. * Bit [31:16]: Serial ATA Handshake Error Threshold (R/W). This bit field defines the count at which an interrupt is asserted. When the count in bits 15:0 is equal to this value, a Serial ATA Handshake interrupt will be latched. A threshold value of zero disables interrupt assertion and masks the corresponding interrupt status bit in the Port Interrupt Status register. * Bit [15:0]: Serial ATA Handshake Error Count (R/WC). This bit field represents the count of Serial ATA Handshake errors that have occurred since it was written the last time.. Any write to this register will clear both the counter and the interrupt condition. Clearing the interrupt status bit will also clear the counter. The count will not overflow. Once this register reaches its maximum count, it will retain that count until cleared to 0 by a write operation. Port PHY Configuration Address Offset: 1050H Access Type: Read/Write Reset Value: 0x0000_020C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PHY Status PHY Config The Port PHY Configuration register is reset by the Global Reset, not by the Port Reset. The reset value is 0x0000020C. * Bit[31:16]: PHY Status (R). These bits report status of the PHY (currently always 0). * Bit[15:5]: PHY Config (R/W). These bits configure the PHY. The value should not be changed because erratic operation may result. * Bit[4:0]: Tx Amplitude (R/W) These bits set the nominal output swing for the Transmitter. The amplitude is increased by 50 mV by an increment of the value. SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 67 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Port Device Status Table 36 gives the offset to the Port Device Status registers for each of the 16 possible port multiplier ports. Table 36. Address Offsets to Port Device Status Registers Address Offset F80H F88H F90H F98H PM Port 0 1 2 3 Address Offset FA0H FA8H FB0H FB8H PM Port 4 5 6 7 Address Offset FC0H FC8H FD0H FD8H PM Port 8 9 10 11 Address Offset FE0H FE8H FF0H FF8H PM Port 12 13 14 15 device_busy native_queue reserved legacy_queue service_pending 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 exec_active_slot pio_end_status These 16 registers contain information useful for diagnosing behavior of the execution unit. These 16 registers contain Port Multiplier device specific information. Address Offset bits 6 to 3 are the Port Multiplier Port number for the device to which the status bits apply. There is one register for each of 16 possible port multiplier ports. These registers are part of the LRAM. * Bit [31:17]: Reserved * Bit [16]: service_pending (R/W). Indicates that a service request has been received from this device and a SERVICE command has not yet been acknowledged. * Bit [15]: legacy_queue (R/W). Indicates that one or more legacy queued commands are outstanding to this device. * Bit [14]: native_queue (R/W). Indicates that one or more native queued commands are outstanding to this device. * Bit [13]: device_busy (R/W). Virtual BSY bit indicating that a command has been issued to the device without receipt of a final register FIS or that a data transfer is in progress. * Bit [12:08]: exec_active_slot (R/W). Contains the slot number of the last command active on this device. * Bit [07:00]: pio_end_status (R/W). Contains the PIO ending status of the last PIO setup command received from this device. Port Device QActive Table 37 gives the offset to the Port Device QActive registers for each of the 16 possible port multiplier ports. Table 37. Address Offsets to Port Device QActive Registers Address Offset F84H F8CH F94H F9CH PM Port 0 1 2 3 Address Offset FA4H FACH FB4H FBCH PM Port 4 5 6 7 Address Offset FC4H FCCH FD4H FDCH PM Port 8 9 10 11 Address Offset FE4H FECH FF4H FFCH PM Port 12 13 14 15 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 QActive[31:0] These 16 registers contain Port Multiplier device specific status indicating outstanding queued commands in the device. For each bit set to 1, a queued command, legacy or native, is outstanding associated with the slot number corresponding to the bit position. There is one register for each of 16 possible port multiplier ports. Address Offset bits 6 to 3 are the Port Multiplier Port number for the device to which the status bits apply. * Bit [31:00]: Each bit corresponds to a slot number that contains an active outstanding legacy or native queued command. 68 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Port Context Address Offset: 1E04H Access Type: Read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved * * * PM Port Slot Bit [31:09]: Reserved Bit [08:05]: PM Port (R). This field contains the Port Multiplier port number corresponding to the last FIS transferred (transmit or receive). After a device specific error causes a processing halt, this field contains the PM port corresponding to the device that returned error status. Bit [04:00]: Slot (R). This field contains the slot number of the last command processed by the execution unit. This slot number does not necessarily correspond to the command in error during error halt conditions. For native queue error recovery, the command slot in error must be determined by issuing a READ LOG EXTENDED to the device to determine the tag number of the command in error. SControl Address Offset: 1F00H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved PMP SPM IPM SPD DET This register is the SControl register as defined by the Serial ATA specification. * Bit [31:20]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [19:16]: PMP (R/W). This field identifies the currently selected Port Multiplier port for accessing the SActive register and some bit fields of the Diagnostic registers. * Bit [15:12]: SPM (R/W). This field selects a power management state. A non-zero value written to this field causes initiation of the select power management state. This field self-resets to 0 as soon as action begins to initiate the power management state transition. Value 0000 0001 0010 0100 others * Definition No power management state transition requested Transition to the Partial power management state initiated Transition to the Slumber power management state initiated Transition from a power management state initiated (ComWake asserted) Reserved Bit [11:08]: IPM (R/W) - This field identifies the interface power management states that may be invoked via the Serial ATA interface power management capabilities. Value 0000 0001 0010 0011 others SiI-DS-0138-E Definition No interface power management restrictions (Partial and Slumber modes enabled) Transitions to the Partial power management state are disabled Transitions to the Slumber power management state are disabled Transitions to both the Partial and Slumber power management states are disabled Reserved (c) 2007-2010 Silicon Image, Inc. All rights reserved. 69 SiI3132 PCI Express to Serial ATA Controller Data Sheet * Silicon Image, Inc. Bit [07:04]: SPD (R/W) - This field identifies the highest allowed communication speed the interface is allowed to negotiate. Value 0000 0001 0010 others * Definition No restrictions (default value) Limit to Generation 1 (1.5 Gbit/s) Limit to Generation 2 (3.0 Gbit/s) Reserved Bit [03:00]: DET (R/W) - This field controls host adapter device detection and interface initialization. Value 0000 0001 0100 Others Action No action COMRESET is periodically generated until another value is written to the field No action Reserved, no action SStatus Address Offset: 1F04H Access Type: Read Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved IPM SPD DET This register is the SStatus register as defined by the Serial ATA specification. * Bit [31:12]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [11:08]: IPM (R) - This field identifies the current interface power management state. Value 0000 0001 0010 0110 Others * Bit [07:04]: SPD (R) - This field identifies the negotiated interface communication speed. Value Definition 0000 0001 0010 Others * No negotiated speed Generation 1 communication rate (1.5 Gbit/s) Generation 2 communication rate (3.0 Gbit/s) Reserved Bit [03:00]: DET (R) - This field indicates the interface device detection and PHY state. Value 0000 0001 0011 0100 Others 70 Definition Device not present or communication not established Interface in active state Interface in Partial power management state Interface in Slumber power management state Reserved Action No device detected and PHY communication not established Device presence detected but PHY communication not established Device presence detected and PHY communication established PHY in offline mode as a result of the interface being disabled or running in a BIST loopback mode Reserved, no action (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. SError Address Offset: 1F08H Access Type: Read/Write 1 Clear Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 R R R R R X F T S H C D B W I N R R R R E P C T R R R R R R M I DIAG ERR This register is the SError register as defined by the Serial ATA specification. * Bit [31:16]: DIAG (R/W1C) - This field contains bits defined as shown in the following table. Writing 1 to the register bit clears the B, C, F, N, H, W, and X bits. Writing 1 to the corresponding bits in the Port Interrupt Status register also clears the F, N, W, and X bits. The B, C, and H bits operate independently of the corresponding error counter registers; if the error counters are used, these bits should be ignored. Table 38. SError Register Bits (DIAG Field) * Bit B C D Definition 10b to 8b decode error CRC error Disparity error F I N H R S T W X Unrecognized FIS type PHY Internal error PHYRDY change Handshake error Reserved Link Sequence error Transport state transition error ComWake Device Exchanged Description Latched decode error or disparity error from the Serial ATA PHY Latched CRC error from the Serial ATA PHY N/A, always 0; this error condition is combined with the decode error and reported as B error Latched Unrecognized FIS error from the Serial ATA Link N/A, always 0 Indicates a change in the status of the Serial ATA PHY Latched Handshake error from the Serial ATA PHY Always 0 N/A, always 0 N/A, always 0 Latched ComWake status from the Serial ATA PHY Latched ComInit status from the Serial ATA PHY Bit [15:00]: ERR - This field is not implemented; all bits are always 0. SActive Address Offset: 1F0CH Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Active bits This register provides indirect access of the Port Device QActive registers. It contains the Active bits used to determine the activity of native queued commands for the selected Port Multiplier port (selection in SControl). A 1 in any bit position indicates that the corresponding command is still active in the device. SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 71 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. SNotification Address Offset: 1F10H Access Type: Read/Write 1 to Clear Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved Notify bits This register reports the devices that have sent a Set Device Bits FIS with the Notification bit set. * Bit [31:16]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [15:00]: Notify bits (R/W1C) - These 16 bits correspond to the 16 possible devices connected to a Port Multiplier on this port. Internal Register Space - Base Address 2 These registers are 32-bits wide and provide Indirect Register Access to the registers of the SiI3132 controller. Access to this register space is through the PCI I/O space. Table 39. SiI3132 Internal Register Space - Base Address 2 Address Offset 00H 04H 08H 0CH Register Name Global Register Offset Global Register Data Port Register Offset Port Register Data Global Register Offset Address Offset: 00H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved Dword Offset 00 This register provides indirect addressing of a Global Register that is otherwise accessible directly through the Base Address 0 Register Space. The Dword address offset for an indirect access is in bits 6 to 2; bits 31 to 7, 1, and 0 are reserved and should always be 0. Global Register Data Address Offset: 04H Access Type: Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 As defined for indirectly accessed register This register provides the indirect access that is addressed by the Global Register Offset register. 72 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Port Register Offset Address Offset: 08H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved Dword Offset 00 This register provides indirect addressing of a Port Register otherwise accessible directly through the Base Address 1 Register Space. The Dword address offset for an indirect access is in bits 13 to 2; bits 31 to 14, 1, and 0 are reserved and should always be 0. Port Register Data Address Offset: 0CH Access Type: Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 As defined for indirectly accessed register This register provides the indirect access addressed by the Port Register Offset register. SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 73 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Power Management The register bits described in Table 40 control Power Management in a SiI3132 controller port. Table 40. Power Management Register Bits Register Port Interrupt Status SError Port Interrupt Status SControl SControl SStatus Bits PM Change (bit 3) W (bit 18) ComWake (bit 5) SPM (bits 15-12) IPM (bits 11-8) IPM (bits 11-8) Description This bit reports a change in the Power Management mode. It corresponds to the interrupt enabled by bit 3 of the Port Interrupt Enable register. This bit reports a ComWake received from the Serial ATA bus. It corresponds to the interrupt enabled by bit 5 of the Port Interrupt Enable register. This bit field initiates transitions to/from Partial or Slumber power management states; bit 14 corresponds to ComWake (exit power management); bit 13 corresponds to Slumber mode; bit 12 corresponds to Partial mode. This bit field disables transitions to Partial or Slumber power management states; bit 9 corresponds to Slumber mode; bit 8 corresponds to Partial mode. This bit field reports the power management state. 0110 - Slumber mode 0010 - Partial mode. There are two power management modes: Partial and Slumber. These power management modes may be software initiated through the SControl register or device initiated from the Serial ATA device. Transitions to and from either power management mode generate an interrupt, the Power Management Mode Change Interrupt, which may be masked in the Port Interrupt Enable register (bit 3). Partial/Slumber mode may be initiated by software through the SControl register. By setting the SPM field to either 0b0001 (Partial) or 0b0010 (Slumber), software causes a PMREQ to the Serial ATA device, which responds with either a PMACK or PMNAK. If a PMACK is received the Partial/Slumber mode is entered. If a PMNAK is ignored; the request remains asserted. The Serial ATA device may initiate Partial/Slumber mode. Software enables the acknowledgement of this request by setting the IPM field in the SControl register to 0b0001 (Partial), 0b0010 (Slumber), or 0b0011 (Partial or Slumber). If enabled, a PMACK is sent to the device; if not enabled, a PMNAK is sent. When the request is received and its acknowledgement is enabled, Partial/Slumber mode is entered. Partial/Slumber mode status is reported in the SStatus register (0b0010/0b0110 in the IPM field). Partial/Slumber mode is cleared by ComWake (asserted when the SPM field is set to 0b0100). 74 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Data Sheet Flash, GPIO, EEPROM, and I2C Programming Flash Memory Access The SiI3132 controller supports an external flash memory device of up to 4 Mbits (512 kB) capacity. Access to the flash memory is available using either PCI Direct Access or Register Access. PCI Direct Access Access to the Expansion ROM is enabled by setting bit 0 in the Expansion ROM Base Address register at Offset 30h of the PCI Configuration Space. When this bit is set, bits [31:19] of the same register are programmable by the system to set the base address for all flash memory accesses. Read and write operations with the flash memory are initiated by Memory Read and Memory Write commands on the PCI bus, which can be accessed as bytes, words, or Dwords. Register Access This type of flash memory access is carried out through a sequence of internal register read and write operations. The proper programming sequences are as follows: Flash Write Operation 1. Verify that Flash Address register bit 25 (Mem Access Start) is 0. The bit is 1 when a memory access is in progress. It is 0 when the memory access is complete and ready for another operation. 2. Program the write address for the flash memory access. The address field is bits [18:0] in the Flash Address register. 3. Program the write data for the flash memory access. The data field is bits [7:0] in the Flash Memory Data / GPIO Control register. 4. Program Flash Address register bit 24 (Mem Access Type) to 0 for a memory write. 5. Initiate the flash memory access by setting bit 25 in the Flash Address register. Flash Read Operation 1. Verify that Flash Address register bit 25 (Mem Access Start) is 0. The bit is 1 when a memory access is in progress. It is 0 when the memory access is complete and ready for another operation. 2. Program the read address for the flash memory access. The address field is bits [18:0] in the Flash Address register. 3. Program Flash Address register bit 24 (Mem Access Type) to 1 for a memory read. 4. Initiate the flash memory access by setting bit 25 in the Flash Address register. 5. Verify that Flash Address register bit 25 (Mem Access Start) is clear. The bit is 1 when a memory access is in progress. It is 0 when the memory access is complete. 6. Read the data from bits [7:0] in the Flash Memory Data / GPIO Control register. I2C Operation The SiI3132 controller provides a Multimaster I2C interface. For Auto-initialization of some PCI Configuration registers an external 256-byte EEPROM memory device may be connected to this I2C interface (refer to the Auto-Initialization on page 34). Four registers are provided for programmed read/write access to the interface: the I2C Slave Address register, I2C Control register, I2C Data Buffer register, and I2C Status register. SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 75 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. I2C Master Write Operation 1. Verify that I2C Status register bits 02 (Unit Busy) and 03 (Bus Busy) are 0. These bits are 1 when an access is in progress. They are 0 when the access is complete and another operation can be started. 2. Write 1 to clear bits [10:4] in the I2C Status register. These bits are set if an error occurred during a previous access. 3. Program the I2C Data Buffer register (bits 7:0) with the first byte to be sent. In most applications, the first byte should consist of the I2C Slave address and a 0 value for the RW bit (bit 7). 4. Initiate the I2C write by setting bits of the I2C Control register. At a minimum, set the following bits: a. Assert the START bit (Bit[0] is 1) for the first byte in a series. b. Leave the STOP bit clear (Bit[1] is 0) for bytes other than the last byte in a series. c. Leave the ACK/NACK Ctrl bit clear (Bit[2] is 0) to allow standard ACK/NACK support. d. Assert Transfer Byte (Bit[3] is 1). e. Clear the Master Abort bit (Bit[4] is 0). f. Assert bits [8:5]. g. Clear bits [15:14]. h. Set bits [13:9] to subscribe to interrupts as needed. 5. Poll I2C Status register bit 02 (I2C Unit Busy). The bit is 1 while an access is in progress. It becomes 0 when the access is complete. (Alternatively, the appropriate I2C Interrupt may be enabled. See the Global Control register and Global Interrupt Status register descriptions on pages 52 and 53, respectively.) 6. Check the I2C Status register for a value of 1 in bit 6 (Tx MT), bit 1 (ACK/NACK Status), and error bit 10. If the error bits are set or the slave returned a NACK, an error occurred and the write should be aborted. 7. To abort the write, write 0x2FFA to the I2C Control register to issue a Master Abort. In case I2C Status bits 02 (I2C Unit Busy) and 03 (Bus Busy) are set after issuing a Master Abort, reset the SiI3132 controller by setting I2C Control bit 14 (Unit Reset). Note: Leave the START bit clear (bit 0 of I2C Control register is 0) for bytes sent other than the first byte and leave the STOP bit clear (bit 1 of I2C Control register is 0) for bytes other than the last byte in a series. I2C Master Read Operation Setup for a Read Operation 1. Verify that I2C Status register bits 02 (Unit Busy) and 03 (Bus Busy) are 0. 2. Write 1 to clear bits [10:4] in the I2C Status register. 3. Program the I2C Data Buffer register (bits 7:0) with the first byte to be sent. In most applications, the first byte should consist of the I2C Slave address and a 1 value for the RW bit. 4. Initiate the I2C write by setting bits of the I2C Control register. At a minimum, set the following bits: a. Assert the START bit (Bit[0] is 1) for the first byte in a series. b. Leave the STOP bit clear (Bit[1] is 0) for bytes other than the last byte in a series. c. Leave the ACK/NACK Ctrl bit clear (Bit[2] is 0) to allow standard ACK/NACK support. d. Assert Transfer Byte (Bit[3] is 1). e. Clear the Master Abort bit (Bit[4] is 0). f. Assert bits [8:5]. g. Clear bits [15:14]. h. Set bits [13:9] to subscribe to interrupts as needed. 5. Poll I2C Status register bit 02 (I2C Unit Busy). The bit is 1 while an access is in progress. It becomes 0 when the access is complete. (Alternatively, the appropriate I2C Interrupt may be enabled. See the Global Control register and Global Interrupt Status register descriptions on pages 52 and 53, respectively.) 6. Check the I2C Status register for a value of 1 in bit 6 (Tx MT), bit 1 (ACK/NACK Status), and error bit 10. If the error bits are set or the slave returned a NACK, an error occurred and the read should be aborted. 76 (c) 2007-2010 Silicon Image, Inc. All rights reserved SiI-DS-0138-E Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Data Sheet Read the Data If an error did not occur and the I2C Slave returned an ACK to the first byte sent, setup the SiI3132 controller for a read by continuing: 1. Verify that I2C Status register bits 02 (Unit Busy) and 03 (Bus Busy) are 0. 2. Write 1 to clear bits [10:4] in the I2C Status register. 3. Initiate the I2C write by setting bits of the I2C Control register. At a minimum, set the following bits: a. Assert the START bit (Bit[0] is 1) for the first byte in a series. b. Leave the STOP bit clear (Bit[1] is 0) for bytes other than the last byte in a series. c. Leave the ACK/NACK Ctrl bit clear (Bit[2] is 0) to allow standard ACK/NACK support. d. Leave Transfer Byte clear (Bit[3] is 0). e. Clear the Master Abort bit (Bit[4] is 0). f. Assert bits [8:5]. g. Clear bits [15:14]. h. Set bits [13:9] to subscribe to interrupts as needed. 4. Poll I2C Status register bit 02 (I2C Unit Busy). The bit is 1 while an access is in progress. It becomes 0 when the access is complete. (Alternatively, the appropriate I2C Interrupt may be enabled. See the Global Control register and Global Interrupt Status register descriptions on pages 52 and 53, respectively.) 5. Check the I2C Status register for a 1 value in bit 7 (Rx Full) and error bit 10. If the error bits are set an error occurred and the read should be aborted. 6. To abort the write, write 0x2FFA to the I2C Control register to issue a Master Abort. In case I2C Status bits 02 (I2C Unit Busy) and 03 (Bus Busy) are set after issuing a Master Abort, reset the SiI3132 controller by setting I2C Control bit 14 (Unit Reset). Note: Leave the START bit clear (0 value for bit 0 of I2C Control register) for bytes sent other than the first byte and leave the STOP bit clear (0 value for bit 1 of I2C Control register) for bytes other than the last byte in a series. I2C Slave Read Operations To set SiI3132 controller to respond as an I2C slave, do the following. 1. Set the I2C Slave Address register with the static address assigned to the SiI3132-enabled I2C Slave 2. Poll I2C Status register bit 09 (Slave Addr Det). (Alternatively, the appropriate I2C Interrupt may be enabled.) 3. Verify that I2C Status register bits 02 (Unit Busy) and 03 (Bus Busy) are 0. 4. Write 1 to clear bits [10:4] in the I2C Status register. 5. Program the I2C Data Buffer register (bits 7:0) with the byte to be sent. 6. Initiate the I2C write by setting bits of the I2C Control register. At a minimum, set the following bits: a. Clear the START bit (Bit[0] is 0). b. Clear the STOP bit clear (Bit[1] is 0). c. Leave the ACK/NACK Ctrl bit clear (Bit[2] is 0) to allow standard ACK/NACK support. d. Assert Transfer Byte (Bit[3] is 1). e. Clear the Master Abort bit (Bit[4] is 0). f. Clear the SCL Enable bit (Bit[5] is 0). g. Assert bits [8:6]. h. Clear bits [15:14]. i. Set bits [13:9] to subscribe to interrupts as needed. 7. Poll I2C Status register bit 02 (I2C Unit Busy). The bit is 1 while an access is in progress. It becomes 0 when the access is complete. (Alternatively, the appropriate I2C Interrupt may be enabled. See the Global Control register and Global Interrupt Status register descriptions on pages 52 and 53, respectively.) 8. Check the I2C Status register for a value of 1 in bit 6 (Tx MT), bit 1 (ACK/NACK Status), and error bit 10. If the error bits are set or the master returned a NACK, an error occurred and the read should be aborted. 9. To abort the write, write 0x2FFA to the I2C Control register to issue a Master Abort. In case I2C Status bits 02 (I2C Unit Busy) and 03 (Bus Busy) are set after issuing a Master Abort, reset the SiI3132 controller by setting I2C Control bit 14 (Unit Reset). SiI-DS-0138-E (c) 2007-2010 Silicon Image, Inc. All rights reserved. 77 SiI3132 PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. Standards Documents Table 41 lists the abbreviations of the standards mentioned in this document. For more information on these specifications contact the responsible standards groups listed in Table 42. Table 41. Referenced Documents Abbreviation SATA-IO PCI-E Standards publication, organization, and date Serial ATA / High Speed AT Attachment Specification, Revision 1.0 PCI Express Base Specification, Revision 1.0a Table 42. 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