DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 DS92LV0411 / DS92LV0412 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface Check for Samples: DS92LV0411, DS92LV0412 FEATURES DESCRIPTION * The DS92LV0411 (serializer) and DS92LV0412 (deserializer) chipset translates a Channel Link LVDS video interface (4 LVDS Data + LVDS Clock) into a high-speed serialized interface over a single CML pair. 1 2 * * * * * * * * * * * * * * 5-Channel (4 data + 1 clock) Channel Link LVDS Parallel Interface Supports 24-bit Data 3-bit Control at 5 - 50 MHz AC Coupled STP Interconnect up to 10 Meters in Length Integrated Serial CML Terminations AT-SPEED BIST Mode and Status Pin Optional I2C Compatible Serial Control Bus Power Down Mode Minimizes Power Dissipation 1.8V or 3.3V Compatible Control Pin Interface >8 kV ESD (HBM) Protection -40 to +85C Temperature Range SERIALIZER - DS92LV0411 Data Scrambler for Reduced EMI DC-Balance Encoder for AC Coupling Selectable Output VOD and Adjustable DeEmphasis DESERIALIZER - DS92LV0412 Random Data Lock; No Reference Clock Required Adjustable Input Receiver Equalization EMI Minimization on Output Parallel Bus (Spread Spectrum Clock Generation and LVDS VOD Select) The DS92LV0411/DS92LV0412 enables applications that currently use the popular Channel Link or Channel Link style devices to seamlessly upgrade to an embedded clock interface to reduce interconnect cost or ease design challenges. The parallel LVDS interface also reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces. Programmable transmit de-emphasis, receive equalization, on-chip scrambling and DC balancing enables longer distance transmission over lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing easy "plug-and-go" operation. The DS92LV0411 and DS92LV0412 are programmable though an I2C interface as well as by pins. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics. The DS92LV0411 and DS92LV0412 can be used interchangeably with the DS92LV2411 or DS92LV2412. This allows designers the flexibility to connect to the host device and receiving devices with different interface types, LVDS or LVCMOS. APPLICATIONS * * * * * Embedded Video and Display Machine Vision, Industrial Imaging, Medical Imaging Office Automation -- Printers, Scanners, Copiers Security and Video Surveillance General purpose data communication 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2010-2013, Texas Instruments Incorporated DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com Applications Diagram Channel Link Channel Link II Camera/AFE Or HOST Graphics Processor RGB Style Display Interface VDDIO (1.8V or 3.3V) TxOUT3+/- High-Speed Serial Link 1 Pair/AC Coupled RxIN2+/- DOUT+ RxIN1+/RxIN0+/- TxOUT2+/- RIN+ DOUT- RIN100 ohm STP Cable RxCLKIN+/- CMF DS92LV0411 PDB MAPSEL CONFIG[1:0] 2 VDDIO 1.8V 3.3V (1.8V or 3.3V) 1.8V RxIN3+/- Optional Channel Link SCL SDA ID[x] Submit Documentation Feedback BISTEN VODSEL De-Emph TxOUT0+/TxCLKOUT+/- Frame Grabber Or RGB Display QVGA to XGA 24-bit Color Depth DS92LV0412 LOCK PASS SSC[2:0] LFMODE CONFIG[1:0] MAPSEL Optional TxOUT1+/- PDB BISTEN OEN OSSEL VODSEL SCL SDA ID[x] Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 Block Diagrams RxIN2+/RxIN1+/RxIN0+/RxCLKIN+/- Parallel to Serial Serial to Parallel RxIN3+/- DC Balance Encoder VODSEL De-Emph DOUT- Pattern Generator PLL CONFIG[1:0] MAPSEL PDB SCL SCA ID[x] DOUT+ Timing and Control BISTEN DS92LV0411 SSCG RINEQ Serializer RIN+ TxOUT[3] DC Balance Decoder Serial to Parallel CMF SSC[2:0] OEN VODSEL TxOUT[2] TxOUT[1] TxOUT[0] TxCLKOUT Error Detector PDB SCL SCA ID[x] BISTEN OSS_SEL LFMODE Timing and Control PLL PASS LOCK DS92LV0412 Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 3 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com RxIN0- MAPSEL RES7 VDDRX PDB VDDIO BISTEN VODSEL De-Emph 26 25 24 23 22 21 20 19 27 RES4 DS92LV0411 Pin Diagram 28 RxIN0+ 29 RxIN1- 30 RxIN1+ 31 DAP = GND DS92LV0411 (Top View) 18 RES3 17 VDDTX 16 DOUT+ 15 DOUT- 14 VDDHS 9 CONFIG[1] CONFIG[0] 10 8 36 RES0 RES5 7 VDDP SDA 11 6 35 SCL RxCLKIN+ 5 RES1 VDDL 12 4 34 ID[x] RxCLKIN- 3 RES2 RES6 13 2 33 RxIN3+ RxIN2+ 1 32 RxIN3- RxIN2- Figure 1. DS92LV0411 -- Top View 4 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 Table 1. DS92LV0411 PIN DESCRIPTIONS Pin Name Pin # I/O, Type Description Channel Link Parallel Input Interface RxIN[3:0]+ 2, 33, 31, 29 I, LVDS True LVDS Data Input These inputs require an external 100 differential termination for standard LVDS levels. RxIN[3:0]- 1, 34, 32, 30, 28 I, LVDS Inverting LVDS Data Input These inputs require an external 100 differential termination for standard LVDS levels. RxCLKIN+ 35 I, LVDS True LVDS Clock Input These inputs require an external 100 differential termination for standard LVDS levels. RxCLKIN- 34 I, LVDS Inverting LVDS Clock Input These inputs require an external 100 differential termination for standard LVDS levels. Control and Configuration PDB 23 I, LVCMOS w/ pull-down Power-down Mode Input PDB = 1, Device is enabled (normal operation). Refer to POWER UP REQUIREMENTS AND PDB PIN in the Applications Information Section. PDB = 0, Device is powered down When the Device is in the power-down state, the driver outputs (DOUT+/-) are both logic high, the PLL is shutdown, IDD is minimized. Control Registers are RESET. VODSEL 20 I, LVCMOS w/ pull-down Differential Driver Output Voltage Select -- Pin or Register Control VODSEL = 1, LVDS VOD is 450 mV, 900 mVp-p (typ) -- Long Cable / De-E Applications VODSEL = 0, LVDS VOD is 300 mV, 600 mVp-p (typ) De-Emph 19 I, Analog w/ pull-up MAPSEL 26 I, LVCMOS w/ pull-down Channel Link Map Select -- Pin or Register Control MAPSEL = 1, MSB on RxIN3+/-. (SeeFigure 23) MAPSEL = 0, LSB on RxIN3+/-. (See Figure 22) 10, 9 I, LVCMOS w/ pull-down Operating Modes Determines the device operating mode and interfacing device. (See Table 2) CONFIG[1:0] = 00: Interfacing to DS92LV2412 or DS92LV0412, Control Signal Filter DISABLED CONFIG[1:0] = 01: Interfacing to DS92LV2412 or DS92LV0412, Control Signal Filter ENABLED CONFIG [1:0] = 10: Interfacing to DS90UR124, DS99R124 CONFIG [1:0] = 11: Interfacing to DS90C124 ID[x] 4 I, Analog SCL 6 I, LVCMOS SDA 7 I/O, LVCMOS Serial Control Bus Data Input / Output - Optional Open Drain SDA requires an external pull-up resistor to 3.3V BISTEN 21 I, LVCMOS w/ pull-down BIST Mode -- Optional BISTEN = 1, BIST is enabled BISTEN = 0, BIST is disabled RES[7:0] 25, 3, 36, 27, 18, 13, 12, 8 I, LVCMOS w/ pull-down Reserved - tie LOW CONFIG[1:0] De-Emphasis Control -- Pin or Register Control De-Emph = open (float) - disabled To enable De-emphasis, tie a resistor from this pin to GND or control via register. (See Table 5) Serial Control Bus Device ID Address Select -- Optional Resistor to Ground and 10 k pull-up to 1.8V rail. (See Table 11) Serial Control Bus Clock Input - Optional SCL requires an external pull-up resistor to 3.3V Channel Link II Serial Interface DOUT+ 16 O, CML True Output. The output must be AC Coupled with a 0.1 F capacitor. DOUT- 15 O, CML Inverting Output. The output must be AC Coupled with a 0.1 F capacitor. Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 5 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com Table 1. DS92LV0411 PIN DESCRIPTIONS (continued) Pin Name Pin # I/O, Type Description Power and Ground (1) VDDL 5 Power Logic Power, 1.8 V 5% VDDP 11 Power PLL Power, 1.8 V 5% VDDHS 14 Power TX High Speed Logic Power, 1.8 V 5% VDDTX 17 Power Output Driver Power, 1.8 V 5% VDDRX 24 Power RX Power, 1.8 V 5% VDDIO 22 Power LVCMOS I/O Power and Channel Link I/O Power 1.8 V 5% OR 3.3 V 10% DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 9 vias. GND (1) 1= HIGH, 0 = LOW. The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage. RES 37 VDDA 38 GND LFMODE OSS_SEL MAPSEL VODSEL GND VDDL OEN BISTEN PASS/EQ LOCK GND VDDIO 36 35 34 33 32 31 30 29 28 27 26 25 DS92LV0412 Pin Diagram 24 TxOUT0- 23 TxOUT0+ 39 22 TxOUT1- RIN+ 40 21 TxOUT1+ RIN- 41 20 TxOUT2- CMF 42 19 TxOUT2+ DAP = GND DS92LV0412 (Top View) VDDA 43 18 TxCLKOUT- GND 44 17 TxCLKOUT+ GND 45 16 TxOUT3- VDDSC 46 15 TxOUT3+ VDDSC 47 14 GND 13 VDDTX 4 5 6 7 8 9 10 11 SDA SCL VDDL SSC[2] VDDP GND CONFIG[0] CONFIG[1] 12 3 SSC[1] ID[x] 2 PDB SSC[0] 48 1 GND Figure 2. DS92LV0412 -- Top View 6 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 DS92LV0412 PIN DESCRIPTIONS Pin Name Pin # I/O, Type Description Channel Link II Serial Interface RIN+ 40 I, CML True Input. The output must be AC Coupled with a 0.1 F capacitor. RIN- 41 I, CML Inverting Input. The output must be AC Coupled with a 0.1 F capacitor. CMF 42 I, Analog Common Mode Filter VCM center tap is a virtual ground which can be AC-coupled to ground to increase receiver common mode noise immunity. Recommended value is 4.7F or higher. Channel Link Parallel Output Interface RxIN[3:0]+ 15, 19, 21, 23 O, LVDS True LVDS Data Output RxIN[3:0]- 16, 20, 22, 24 O, LVDS Inverting LVDS Data Output RxCLKIN+ 17 O, LVDS True LVDS Clock Output RxCLKIN- 18 O, LVDS Inverting LVDS Clock Output 27 O, LVCMOS LOCK Status Output LOCK = 1, PLL is locked, output stated determined by OEN. LOCK = 0, PLL is unlocked, output states determined by OSS_SEL and OEN. (See Table 6) LVCMOS Outputs LOCK Control and Configuration PDB 1 I, LVCMOS w/ pull-down Power-down Mode Input PDB = 1, Device is enabled (normal operation). PDB = 0, Device is powered down and the outputs are Tri-State Control Registers are RESET. VODSEL 33 I, LVCMOS w/ pull-down Parallel LVDS Driver Output Voltage Select -- Pin or Register Control VODSEL = 1, LVDS VOD is 400 mV, 800 mVp-p (typ) -- Long Cable / De-E Applications VODSEL = 0, LVDS VOD is 250 mV, 500 mVp-p (typ) OEN 30 I, LVCMOS w/ pull-down Output Enable. (See Table 6) OSS_SEL 35 I, LVCMOS w/ pull-down Output Sleep State Select Input. (See Table 6) LFMODE 36 I, LVCMOS w/ pull-down SSCG Low Frequency Mode -- Pin or Register Control LF_MODE = 1, low frequency mode (TxCLKOUT = 10-20 MHz) LF_MODE = 0, high frequency mode (TxCLKOUT = 20-65 MHz) SSCG not avaialble above 65 MHz. MAPSEL 34 I, LVCMOS w/ pull-down Channel Link Map Select -- Pin or Register Control MAPSEL = 1, MSB on TxOUT3+/-. (See Figure 23) MAPSEL = 0, LSB on TxOUT3+/-. (See Figure 22) CONFIG[1 :0] 11, 10 I, LVCMOS w/ pull-down Operating Modes Determine the device operating mode and interfacing device. (See Table 2) CONFIG[1:0] = 00: Interfacing to DS92LV2411 or DS92LV0411, Control Signal Filter DISABLED CONFIG[1:0] = 01: Interfacing to DS92LV2411 or DS92LV0411, Control Signal Filter ENABLED CONFIG [1:0] = 10: Interfacing to DS90UR241, DS99R421 CONFIG [1:0] = 11: Interfacing to DS90C241 SSC[2:0] 7, 2, 3 I, LVCMOS w/ pull-down Spread Spectrum Clock Generation (SSCG) Range Select (See Table 9 and Table 10) 37 I, LVCMOS w/ pull-down Reserved RES Control and Configuration -- STRAP PIN EQ 28 [PASS] STRAP I, LVCMOS w/ pull-down EQ Gain Control of Channel Link II Serial Input EQ = 1, EQ gain is enabled (~13 dB) EQ = 0, EQ gain is disabled (~ 1.625 dB) Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 7 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com DS92LV0412 PIN DESCRIPTIONS (continued) Pin Name Pin # I/O, Type Description Optional BIST Mode BISTEN 29 I, LVCMOS w/ pull-down BIST Mode -- Optional BISTEN = 1, BIST is enabled BISTEN = 0, BIST is disabled PASS 28 O, LVCMOS PASS Output (BIST Mode) -- Optional PASS =1, no errors detected PASS = 0, errors detected Leave open if unused. Route to a test point (pad) recommended. Serial Control Bus Device ID Address Select -- Optional Resistor to Ground and 10 k pull-up to 1.8V rail. (See Table 11) Optional Serial Bus Control ID[x] 12 I, Analog SCL 5 I, LVCMOS Open Drain SDA 4 Serial Control Bus Clock Input - Optional SCL requires an external pull-up resistor to 3.3V. I/O, LVCMOS Serial Control Bus Data Input / Output - Optional Open Drain SDA requires an external pull-up resistor 3.3V. Power and Ground (1) VDDL 6, 31 Power Logic Power, 1.8 V 5% VDDA 38, 43 Power Analog Power, 1.8 V 5% VDDP 8 Power PLL Power, 1.8 V 5% VDDSC 46, 47 Power SSC Generator Power, 1.8 V 5%. Power must be connected to these pins regardless if the SSCG feature is used or not. VDDTX 13 Power Channel Link LVDS Parallel Output Power, 3.3 V 10% VDDIO 25 Power LVCMOS I/O Power and Channel Link I/O Power 1.8 V 5% OR 3.3 V 10% GND 9, 14, 26, 32, 39, 44, 45, 48 Ground Ground DAP DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 9 vias. (1) 8 1= HIGH, 0 = LOW. The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage - VDDn (1.8V) -0.3V to +2.5V Supply Voltage - VDDIO -0.3V to +4.0V Supply Voltage - VDDTX (1.8V, Ser)) -0.3V to +2.5V Supply Voltage - VDDTX (3.3V, Des) -0.3V to +4.0V -0.3V to (VDDIO + 0.3V) LVCMOS I/O Voltage LVDS Input Voltage -0.3V to (VDDIO + 0.3V) LVDS Output Voltage -0.3V to (VDDTX + 0.3V) -0.3V to (VDDn + 0.3V) CML Driver Output Voltage -0.3V to (VDD + 0.3V) Receiver Input Voltage Junction Temperature +150C Storage Temperature -65C to +150C 36L WQFN Package Maximum Power Dissipation Capacity at 25C 1/ JAC/W Derate above 25C JA(with 9 thermal via) 27.4 C/W JC(with 9 thermal via) 4.5 C/W 48L WQFN Package Maximum Power Dissipation Capacity at 25C 1/ JAC/W Derate above 25C JA(with 9 thermal via) 27.7 C/W JC(with 9 thermal via) 3.0 C/W ESD Rating (IEC, powered-up only), RD = 330, CS = 150 pF Air Discharge (DOUT+, DOUT-, RIN+, RIN-) 30 kV Contact Discharge (DOUT+, DOUT-, RIN+, RIN-) 8 kV ESD Rating (HBM) 8 kV ESD Rating (CDM) 1.25 kV 250 V ESD Rating (MM) For soldering specifications: http://www.ti.com/lit/SNOA549 (1) (2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 9 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com Recommended Operating Conditions Min Nom Max Units Supply Voltage (VDDn) 1.71 1.8 1.89 V Supply Voltage (VDDTX_Ser) 1.71 1.8 1.89 V Supply Voltage (VDDTX_Des) 3.0 3.3 3.6 V LVCMOS Supply Voltage (VDDIO) 1.71 1.8 1.89 V LVCMOS Supply Voltage (VDDIO) 3.0 3.3 3.6 V Operating Free Air Temperature (TA) -40 +25 +85 C 50 MHz 100 mVP-P OR RxCLKIN/TxCLKOUT Clock Frequency 5 Supply Noise (1) (1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the noise frequency is less than 400 kHz. DC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) (4) (5) Symbol Parameter Conditions Pin/Freq. Max Uni ts 2.2 VDDIO V 0.65* VDDIO VDDIO V GND 0.8 V GND 0.35* VDDIO V Min Typ DS92LV0411 LVCMOS INPUT DC SPECIFICATIONS VDDIO = 3.0 to 3.6V VIH High Level Input Voltage VDDIO = 1.71 to 1.89V VDDIO = 3.0 to 3.6V VIL IIN Low Level Input Voltage Input Current VDDIO = 1.71 to 1.89V VIN = 0V or VDDIO VDDIO = 3.0 to 3.6V PDB, VODSEL, MAPSEL, CONFIG[1:0], BISTEN VDDIO = 1.7 to 1.89V -15 1 +15 A -15 1 +15 A 2.2 VDDIO V 0.7* VDDIO VDDIO V GND 0.8 V GND 0.3* VDDIO V DS92LV0412 LVCMOS I/O DC SPECIFICATIONS VDDIO = 3.0 to 3.6V VIH High Level Input Voltage VDDIO = 1.71 to 1.89V VDDIO = 3.0 to 3.6V VIL IIN (1) (2) (3) (4) (5) 10 Low Level Input Voltage Input Current VDDIO = 1.71 to 1.89V VIN = 0V or VDDIO VDDIO = 3.0 to 3.6V PDB, VODSEL, OEN, MAPSEL, LFMODE, SSC[2:0], BISTEN VDDIO = 1.7 to 1.89V -15 1 +15 A -10 1 +10 A The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at VDD = 1.8V, VDDIO = 3.3V, Ta = +25 C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, VOD, VTH and VTL which are differential voltages. Specification is ensured by characterization and is not tested in production. Specification is ensured by design and is not tested in production. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 DC Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)(4)(5) Symbol VOH Parameter High Level Output Voltage VOL Low Level Output Voltage IOS Output Short Circuit Current Tri-State Output Current (6) IOZ Conditions Pin/Freq. Min Typ VDDIO = 3.3V IOH = -2 mA VDDIO - 0.25 VDDIO VDDIO = 1.8V IOH = -2 mA VDDIO - 0.2 VDDIO VDDIO = 3.3 V or 1.8V IOL = +0.5 mA VOUT = 0V PDB = 0V, OSS_SEL = 0V, VOUT = 0V or VDDIO LOCK, PASS Uni ts V GND VDDIO = 3.0 to 3.6 V Max 0.2 V -45 mA VDDIO = 1.71 to 1.89V -13 VDDIO = 3.0 to 3.6 V -10 +10 VDDIO = 1.71 to 1.89V -15 +15 A DS92LV0411 CHANNEL LINK PARALLEL LVDS RECEIVER DC SPECIFICATIONS VTH Differential Threshold High Voltage VTL Differential Threshold Low Voltage |VID| Differential Input Voltage Swing VCM Common Mode Voltage IIN Input Current +100 mV VCM = 1.2V, (See Figure 3) -100 RxIN[3:0]+/-, RxCLKIN+/-, 200 600 mV VDDIO = 3.3V 0 1.2 2.4 VDDIO = 1.8V 0 1.2 1.55 -15 1 +15 A VODSEL = L 100 250 400 mV VODSEL = H 200 400 600 mV V DS92LV0412 CHANNEL LINK PARALLEL LVDS DRIVER DC SPECIFICATIONS |VOD| Differential Output Voltage VODp-p Differential Output Voltage A - B VODSEL = L RL = 100 VOD Output Voltage Unbalance VOS Offset Voltage VOS Offset Voltage Unbalance IOS Output Short Circuit Current VOUT = GND IOZ Output Tri-State Current (6) OEN = GND, VOUT = VDDTX, or GND (6) VODSEL = H VODSEL = L TxCLKOUT-, TxOUT[3:0]+, TxOUT[3:0]- 1.0 VODSEL = H 500 mV p-p 800 mV p-p 4 50 mV 1.2 1.5 V 50 mV 1.2 1 V -5 -10 mA +10 A When the device output is at Tri-State the Deserializer will lose PLL lock. Resynchronization / Relock must occur before data transfer require tPLD Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 11 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com DC Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)(4)(5) Symbol Parameter Conditions Pin/Freq. Min Typ Max VODSEL = 0 225 300 375 VODSEL = 1 350 450 550 Uni ts DS92LV0411 Channel Link II CML DRIVER DC SPECIFICATIONS VOD VODp-p Differential Output Voltage Differential Output Voltage (DOUT+) - (DOUT-) RL = 100, De-emph = disabled, (SeeFigure 5) mV VODSEL = 0 600 mV p-p VODSEL = 1 900 mV p-p VOD Output Voltage Unbalance RL = 100, De-emph = disabled, VODSEL = L VOS Offset Voltage - Single-ended At TP A & B, (SeeFigure 4) RL = 100, De-emph = disabled VOS Offset Voltage Unbalance Single-ended At TP A & B, (SeeFigure 4) RL = 100, De-emph = disabled IOS Output Short Circuit Current DOUT+/- = 0V, De-emph = disabled RT Internal Termination Resistor VODSEL = 0 1 DOUT+, DOUT- VODSEL = 1 VODSEL = 0 50 mV 1.65 V 1.575 V 1 mV -35 mA 80 120 +50 mV DS92LV0412 CHANNEL LINK II CML RECEIVER DC SPECIFICATIONS VTH Differential Input Threshold High Voltage VTL Differential Input Threshold Low Voltage VCM Common mode Voltage, Internal VBIAS RT Input Termination VCM = +1.2V (Internal VBIAS) RIN+, -50 RIN- mV 1.2 80 100 V 120 80 90 mA 3 5 mA 10 13 mA 75 85 mA 3 5 mA 10 13 mA DS92LV0411 SUPPLY CURRENT IDDT1 IDDIOT1 IDDT2 Supply Current (includes load current) RL = 100, f = 50 MHz IDDIOT2 Checker Board Pattern, De-emph = 3 k, VODSEL = H, (See Figure 18) VDD= 1.89V Checker Board Pattern, De-emph = 6 k, VODSEL = L, (See Figure 18) VDD= 1.89V IDDZ IDDIOZ VDDIO = 3.6V PDB = 0V , (All other LVCMOS Inputs = 0V) VDDIO All VDD pins VDDIO= 1.89V VDDIO = 3.6V VDD= 1.89V Supply Current Power-down All VDD pins VDDIO= 1.89V VDDIO= 1.89V VDDIO = 3.6V VDDIO All VDD pins VDDIO 60 1000 A 0.5 10 A 1 30 A DS92LV0412 SUPPLY CURRENT IDD1 IDDTX1 Supply Current (Includes load current) 50 MHz Clock IDDIO1 Checker Board Pattern, VODSEL = H, SSCG [2:0] = 000 VDDn = 1.89 V All VDD(1:8) pins 85 95 mA VDDTX = 3.6 V VDDTX 40 50 mA VDDIO = 1.89 V VDDIO 0.3 0.8 mA 0.8 1.5 mA VDDIO = 3.6 V 12 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 DC Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)(4)(5) Symbol IDD2 IDDTX2 Parameter Conditions Supply Current (Includes load current) 50 MHz Clock Checker Board Pattern, VODSEL = H, SSCG [2:0] = 111 IDDIO2 Pin/Freq. Min Supply Current Power Down IDDTXZ PDB = 0V, All other LVCMOS Inputs = 0V IDDIOZ Max Uni ts VDDn = 1.89 V All VDD(1:8) pins 95 mA VDDTX = 3.6 V VDDTX 40 mA VDDIO = 1.89 V VDDIO 0.3 mA 0.8 mA VDDIO = 3.6 V IDDZ Typ VDD = 1.89 V All VDD(1:8) pins 0.15 2 mA VDDTX = 3.6 V VDDTX 0.01 0.1 mA VDDIO = 1.89 V VDDIO 0.01 0.08 mA 0.01 0.08 mA VDDIO = 3.6V Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units DS92LV0411 CHANNEL LINK PARALLEL LVDS INPUT tRSP0 Receiver Strobe Position-bit 0 0.66 1.10 1.54 ns tRSP1 Receiver Strobe Position-bit 1 2.86 3.30 3.74 ns tRSP2 Receiver Strobe Position-bit 2 5.05 5.50 5.93 ns tRSP3 Receiver Strobe Position-bit 3 7.25 7.70 8.13 ns tRSP4 Receiver Strobe Position-bit 4 9.45 9.90 10.33 ns tRSP5 Receiver Strobe Position-bit 5 11.65 12.10 12.53 ns tRSP6 Receiver Strobe Position-bit 6 13.85 14.30 14.73 ns 0.3 0.6 ns 0.3 0.6 ns TxCLKOUT = 5 MHz 900 2100 ps TxCLKOUT = 50 MHz 75 125 5 - 50 MHz 1 UI (2) RxCLKIN = 50 MHz, RxIN[3:0] (See Figure 7) DS92LV0412 CHANNEL LINK PARALLEL LVDS OUTPUT tLHT Low to High Transition Time tTHLT High to Low Transition Time tDCCJ Cycle-to-Cycle Output Jitter RL = 100 (1) ps tTTP1 Transmitter Pulse Position for bit 1 tTTP0 Transmitter Pulse Position for bit 0 2 UI tTTP6 Transmitter Pulse Position for bit 6 3 UI tTTP5 Transmitter Pulse Position for bit 5 4 UI tTTP4 Transmitter Pulse Position for bit 4 5 UI tTTP3 Transmitter Pulse Position for bit 3 6 UI tTTP2 Transmitter Pulse Position for bit 2 7 UI tTTP Offset Transmitter Pulse Position (bit 6-- bit 0) <+0.1 UI tDD Delay-Latency tTPDD Power Down Delay Active to OFF 50 MHz tTXZR Enable Delay OFF to Active 50 MHz (1) (2) 50 MHz 142*T 143*T ns 7 12 ns 40 55 ns tDCCJ is the maximum amount of jitter between adjacent clock cycles. UI - Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*PCLK). The UI scales with PCLK frequency. Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 13 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com Switching Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units DS92LV0411 Channel Link II CML OUTPUT tHLT Output Low-to-High Transition Time (See Figure 5) tHLT Output High-to-Low Transition Time (See Figure 6) RL = 100, De-emphasis = disabled, VODSEL = 0 200 ps RL = 100, De-emphasis = disabled, VODSEL = 1 200 ps RL = 100, De-emphasis = disabled, VODSEL = 0 260 ps RL = 100, De-emphasis = disabled, VODSEL = 1 200 ps tXZD Ouput Active to OFF Delay (See Figure 11) tPLD PLL Lock Time (3), (See Figure 9) RL = 100 tSD Delay - Latency, (See Figure 12) RL = 100 tDJIT Output Total Jitter (See Figure 14) RL = 100, De-Emph = disabled, RANDOM pattern, RxCLKIN = 43 and 50 MHz 0.26 Jitter Transfer Function -3 dB Bandwidth RxCLKIN = 43 MHz 2.2 RxCLKIN = 50 MHz 2.6 Jitter Transfer Function Peaking RxCLKIN = 43 MHz 1 RxCLKIN = 50 MHz 1 SSCG[2:0] = 000, 5 MHz 7 ms SSCG[2:0] = 111, 5 MHz 14 ms SSCG[2:0] = 000, 50 MHz 6 ms SSCG[2:0] = 111, 50 MHz 8 ms EQ = OFF SSCG[2:0] = 000 TxCLKOUT = 50 MHz Input Jitter Frequency < 2 MHz >0.9 UI EQ = OFF SSCG[2:0] = 000 TxCLKOUT = 50 MHz Input Jitter Frequency >6 MHz >0.5 UI STXBW STX 5 15 ns 1.5 10 ms 147*T 148*T ns UI MHz dB DS92LV0412 CHANNEL LINK II CML INPUT tDDLT tIJIT Lock Time Input Jitter Tolerance DS92LV0412 LVCMOS OUTPUTS tCLH Low to High Transition Time tCHL High to Low Transition Time tPASS BIST PASS Valid Time, BISTEN = 1 CL = 8 pF LOCK pin, PASS pin 5 15 ns 5 15 ns PASS pin 5 MHz 570 580 ns 50 MHz 50 65 ns DS92LV0412 SSCG MODE tDEV Spread Spectrum Clocking Deviation Frequency TxCLKOUT = 5 - 50 MHz, SSC[2:0] = ON 0.5 2 % tMOD Spread Spectrum Clocking Modulation Frequency TxCLKOUT = 5 - 50 MHz, SSC[2:0] = ON 8 100 kHz (3) 14 tPLD is the time required by the device to obtain lock when exiting power-down state with an active RxCLKIN. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 Recommended Timing for the Serial Control Bus Over recommended operating supply and temperature ranges unless otherwise specified. (Figure 20) Symbol fSCL tLOW tHIGH Parameter SCL Clock Frequency SCL Low Period SCL High Period Conditions Min Typ Max Units Standard Mode >0 100 kHz Fast Mode >0 400 kHz Standard Mode 4.7 s Fast Mode 1.3 s Standard Mode 4.0 s Fast Mode 0.6 s tHD:STA Hold time for a start or a repeated start condition Standard Mode 4.0 s Fast Mode 0.6 s tSU:STA Set Up time for a start or a repeated start condition Standard Mode 4.7 s Fast Mode 0.6 s tHD:DAT Data Hold Time Fast Mode 0 3.45 s 0 0.9 s Standard Mode 250 s Fast Mode 100 s Set Up Time for STOP Condition Standard Mode 4.0 s Fast Mode 0.6 s tBUF Bus Free Time Between STOP and START Standard Mode 4.7 s Fast Mode 1.3 tr SCL & SDA Rise Time Standard Mode 1000 ns Fast Mode 300 ns Standard Mode 300 ns Fast Mode 300 ns Max Units tSU:DAT tSU:STO tf Data Set Up Time SCL & SDA Fall Time s DC and AC Serial Control Bus Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ VIH Input High Level SDA and SCL VDDIO = 3.3V 0.7* VDDIO VDDIO V VIL Input Low Level Voltage SDA and SCL VDDIO = 3.3V GND 0.3* VDDIO V VHY Input Hysteresis VDDIO = 3.3V VOL SDA, IOL = 3mA VDDIO = 3.3V Iin SDA or SCL, Vin = 3.3V or GND tR SDA RiseTime - READ tF SDA Fall Time - READ tSU;DAT Set Up Time - READ tHD;DAT Hold Up Time - READ tSP Input Filter Cin Input Capacitance SDA, RPU = X, Cb 400pF, (See Figure 20) >50 0 -10 mV 0.36 V +10 A 430 ns 20 ns See Figure 20 560 ns See Figure 20 615 ns SDA or SCL Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 50 ns <5 pF Submit Documentation Feedback 15 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com AC Timing Diagrams and Test Circuits RxIN[3:0]+ RxCLKIN+ VTL VCM=1.2V VTH RxIN[3:0]RxClkIN- GND Figure 3. Channel Link DC VTH/VTL Definition A A' CA Scope 50: 50: B CB B' 50: 50: Single-Ended Figure 4. DS92LV0411 Output Test Circuit DOUT+ VOD- VOD+ DOUT- VOS VOD+ (DOUT+) - (DOUT+) VODp-p 0V VOD- Differential GND Figure 5. Channel Link II Single-ended and Differential Waveforms +VOD 80% 0V (DOUT+) - (DOUT-) 20% -VOD tLLHT tLHLT Figure 6. DS92LV0411 Output Transition Times 16 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 Figure 7. DS92LV0411 LVDS Receiver Strobe Positions Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 17 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com Cycle N TxCLKOUT bit 1 TxOUT[3:0] tTTP1 tTTP2 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1UI 2UI tTTP3 3UI tTTP4 4UI tTTP5 5UI tTTP6 tTTP7 6UI 7UI Figure 8. DS92LV0412 LVDS Transmitter Pulse Positions PDB RxCLKIN VIHMIN "X" active tPLD DOUT (Diff.) Driver On Driver OFF, VOD = 0V Figure 9. DS92LV0411 Lock Time 18 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 VIH(min) PDB RIN tDDLT LOCK VOH(min) TRI-STATE Figure 10. DS92LV0412 Lock Time VILMAX PDB RxCLKIN active "X" tXZD DOUT (Diff.) active Driver OFF, VOD = 0V RxIN[3:0] N-1 N N+1 N+2 | | Figure 11. DS92LV0411 Disable Time | tSD RxCLKIN | | | | | | DCA, DCB | | DOUT0-23 STOP START STOP START STOP START STOP STOP START BIT BIT BIT SYMBOL N-3 BIT BIT SYMBOL N-2 BIT BIT SYMBOL N-1 BIT BIT SYMBOL N | | SYMBOL N-4 Figure 12. DS92LV0411 Latency Delay Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 19 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 | | START STOP BIT SYMBOL N+3 BIT | | | START STOP BIT SYMBOL N+2 BIT | | RIN+/- START STOP BIT SYMBOL N+1 BIT | START STOP BIT SYMBOL N BIT www.ti.com tRD TxCLKOUT TxOUT[3:0] SYMBOL N-3 SYMBOL N-2 SYMBOL N-1 SYMBOL N Figure 13. DS92LV0412 Latency Delay tDJIT tDJIT VOD (+) DOUT (Diff.) TxOUT_E_O 0V VOD (-) tBIT (1 UI) Figure 14. DS92LV0411 Output Jitter 20 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 PDB RIN (Diff.) LOCK TxOUT[3:0] TxCLKOUT active serial stream X H H L L L Z Z Z Z Z f f Z Z Z PASS OFF OSC Output Active OFF Active OSC Output CONDITIONS: OEN = H, OSS_SEL = H, and OSC_SEL not equal to 000. Figure 15. DS92LV0412 Output State Diagram PDB VILmax RIN X tTPDD LOCK Z PASS Z TxCLKOUT Z TxOUT[3:0] Z Figure 16. DS92LV0412 Power Down Delay Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 21 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com PDB LOCK tTXZR OEN VIHmin Z TxCLKOUT Z TxOUT[3:0] Figure 17. DS92LV0412 Enable Delay +VOD RxCLKIN -VOD +VOD RxIN[odd] -VOD +VOD RxIN[even] -VOD Cycle N Cycle N+1 Figure 18. Checkerboard Data Pattern VILMAX BISTEN tPASS PASS (w/ errors) VOLMAX Prior BIST Result Current BIST Test - Toggle on Error Result Held Figure 19. BIST PASS Waveform 22 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 SDA tf tHD;STA tLOW tr tf tr tBUF tSP SCL tSU;STA tHD;STA tHIGH tHD;DAT START tSU;STO tSU;DAT STOP REPEATED START START Figure 20. Serial Control Bus Timing Diagram Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 23 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION The DS92LV0411 / DS92LV0412 chipset transmits and receives 24-bits of data and 3 control signals, formatted as Channel Link LVDS data, over a single serial CML pair operating at 140 Mbps to 1.4 Gbps serial line rate. The serial stream contains an embedded clock, video control signals and is DC-balance to enhance signal quality and supports AC coupling. The Des can attain lock to a data stream without the use of a separate reference clock source, which simplifies system complexity and overall cost. The Des also synchronizes to the Ser regardless of the data pattern, delivering true automatic "plug and lock" performance. It can lock to the incoming serial stream without the need of special training patterns or sync characters. The Des recovers the clock and data by extracting the embedded clock information, validating and then deserializing the incoming data stream providing a parallel Channel Link LVDS bus to the display, ASIC, or FPGA. The DS92LV0411 / DS92LV0412 chipset can operate with up to 24 bits of raw data with three slower speed control bits encoded within the serial data stream. For applications that require less the maximum 24 pclk speed bit spaces, the user will need to ensure that all unused bit spaces or parallel LVDS channels are set to valid logic states, as all parallel lanes and 27 bit spaces will always be sampled. Block Diagrams for the chipset are shown at the beginning of this datasheet. PARALLEL LVDS DATA TRANSFER The DS92LV0411/DS92LV0412 can be configured to accept/transmit 24-bit data with 2 different mapping schemes: The normal Channel Link LVDS format (MSBs on LVDS channel 3) can be selected by configuring the MAPSEL pin to HIGH. See Figure 15 for the normal Channel Link LVDS mapping. An alternate mapping scheme is available (LSBs on LVDS channel 3) by configuring the MAPSEL pin to LOW. See Figure 16 for the alternate LVDS mapping. The mapping schemes can also be selected by register control. The alternate mapping scheme is useful in some applications where the receiving system, typically a display, requires that the LSBs for the 24-bit color data be sent on LVDS channel 3. SERIAL DATA TRANSFER The DS92LV0411 transmits a 24-bit word of data in the following format: C1 and C0 represent the embedded clock in the serial stream. C1 is always HIGH and C0 is always LOW. b[23:0] contain the scrambled RGB data, plus two additional bits for encoding overhead. The control signals (VS,HS,DE) are also encoded within these two additional bits. This coding scheme is generated by the DS92LV0411 and decoded by the paring deserializer, such as the DS92LV0412, automatically. The DS92LV0412 receives a 24 bit word of data in the format as described above. It also synchronizes to the serializer regardless of the data pattern, delivering true automatic "plug and lock" performance. it can lock to the incoming serial stream without the need for special training patterns or sync characters. The DS92LV0412 recovers the clock and data by extracting the embedded clock information, validating and then deserializing the incoming data stream. Figure 21 illustrates the serial stream per PCLK cycle. C 1 C 0 Figure 21. Channel Link II Serial Stream 24 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 OPERATING MODES AND BACKWARD COMPATIBILITY (CONFIG[1:0]) The DS92LV0411 and DS92LV0412 are backward compatible with previous generations of Ser/Des. Configuration modes are provided for backwards compatibility with the DS90C241/DS90C124 and also the DS90UR241/DS90UR124 and DS99R241/DS99R124 by setting the respective mode with the CONFIG[1:0] pins as shown in Table 2 and Table 3. The selection also determine whether the Video Control Signal filter feature is enabled or disabled in Normal mode. Backward compatibility modes are selectable through the control pins only. The Control Signal Filter can be selected by pin or through register programming. Table 2. DS92LV0411 Configuration Modes CON FIG1 CON FIG0 Mode Des Device L L Normal Mode, Control Signal Filter disabled DS92LV0412, DS92LV2412 L H Normal Mode, Control Signal Filter enabled DS92LV0412, DS92LV2412 H L Backwards Compatible DS90UR124, DS99R124 H H Backwards Compatible DS90C124 Table 3. DS92LV0412 Configuration Modes CON FIG1 CON FIG0 Mode Des Device L L Normal Mode, Control Signal Filter disabled DS92LV0411, DS92LV2411 L H Normal Mode, Control Signal Filter enabled DS92LV0411, DS92LV2411 H L Backwards Compatible DS90UR241, DS99R421 H H Backwards Compatible DS90C241 BIT MAPPING SELECT The DS92LV0411 and DS92LV0412 can be configured to accept the LVDS parallel data with 2 different mapping schemes: LSBs on RxIN[3] shown in Figure 22 or MSBs on RxIN[3] shown in Figure 23. The user selects which mapping scheme is controlled by MAPSEL pin or by Register. NOTE While the LVDS interface has 28 bits defined, only 27 bits are recovered by the Ser and sent to the Des. This supports 24 bit RGB plus the three video control signals. The 28th bit is not sampled, sent or recovered. Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 25 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com RxCLKIN +/Previous cycle Current cycle RxIN3 +/- DE (bit 20) RxIN2 +/- R[1] (bit 22) R[0] (bit 21) B[6] (bit 16) B[5] (bit 15) B[4] (bit 14) G[6] (bit 10) G[5] (bit 9) G[4] (bit 8) G[3] (bit 7) R[5] (bit 3) R[4] (bit 2) R[3] (bit 1) R[2] (bit 0) B[1] (bit 26) B[0] (bit 25) G[1] (bit 24) VS (bit 19) HS (bit 18) B[7] (bit 17) G[7] (bit 11) R[6] (bit 4) RxIN1 +/- B[3] (bit 13) B[2] (bit 12) RxIN0 +/- G[2] (bit 6) R[7] (bit 5) G[0] (bit 23) Figure 22. 8-bit Channel Link Mapping: LSB's on RxIN3 RxCLKIN +/Previous cycle Current cycle B[7] (bit 26) RxIN3 +/- DE (bit 20) RxIN2 +/- RxIN1 +/- RxIN0 +/- VS (bit 19) B[1] (bit 13) B[0] (bit 12) G[0] (bit 6) R[5] (bit 5) R[7] (bit 22) R[6] (bit 21) B[4] (bit 16) B[3] (bit 15) B[2] (bit 14) G[4] (bit 10) G[3] (bit 9) G[2] (bit 8) G[1] (bit 7) R[3] (bit 3) R[2] (bit 2) R[1] (bit 1) R[0] (bit 0) B[6] (bit 25) G[7] (bit 24) HS (bit 18) B[5] (bit 17) G[5] (bit 11) R[4] (bit 4) G[6] (bit 23) Figure 23. 8-bit Channel Link Mapping: MSB's on RxIN3 26 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 VIDEO CONTROL SIGNAL FILTER The three control bits can be used to communicate any low speed signal. The most common use for these bits is in the display or machine vision applications. In a display application these bits are typically assigned as: Bit 26 - DE, Bit 24 - HS, Bit 25 - VS. In the machine vision standard, Camera Link, these bits are typically assigned: Bit 26 - DVAL, Bit 24 - LVAL, Bit 25 - FVAL. When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following restrictions: * Normal Mode with Control Signal Filter Enabled: - DE and HS -- Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3 PCLK or longer. * Normal Mode with Control Signal Filter Disabled: - DE and HS -- Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition pulse. * VS -- Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles. Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency noise on the control signals. See Figure 24. PCLK IN HS/VS/DE IN Latency PCLK OUT HS/VS/DE OUT Pulses 1 or 2 PCLKs wide Filetered OUT Figure 24. Video Control Signal Filter Wavefrom SERIALIZER FUNCTIONAL DESCRIPTION The Ser converts a Channel Link LVDS clock and data bus (4 LVDS data channels + 1 LVDS clock) to a single serial output data stream, and also acts as a signal generator for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins or through the optional serial control bus. The Ser features enhanced signal quality on the link by supporting: a selectable VOD level, a selectable de-emphasis signal conditioning and also the Channel Link II data coding that provides randomization, scrambling, and DC Balanacing of the data. The Ser includes multiple features to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the serial data and also the system spread spectrum clock support. The Ser features power saving features with a sleep mode, auto stop clock feature, and optional 1.8 V or 3.3V I/O compatibility. See also the Functional Description of the chipset's serial control bus and BIST modes. Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 27 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com EMI REDUCTION FEATURES Data Randomization & Scrambling Channel Link II Ser / Des feature a 3 step encoding process which enables the use of AC coupled interconnects and also helps to manage EMI. The serializer first passes the parallel data through a scrambler which randomizes the data. The randomized data is then DC balanced. The DC balanced and randomized data then goes through a bit shuffling circuit and is transmitted out on the serial line. This encoding process helps to prevent static data patterns on the serial stream. The resulting frequency content of the serial stream ranges from the parallel clock frequency to the nyquist rate. For example, if the Ser / Des chip set is operating at a parallel clock frequency of 50 MHz, the resulting frequency content of serial stream ranges from 50 MHz to 700 MHz ( 50 MHz *28 bits = 1.4 Gbps / 2 = 700 MHz ). Ser -- Spread Spectrum Compatibility The RxCLKIN of the Channel Link input is capable of tracking spread spectrum clocking (SSC) from a host source. The RxCLKIN will accept spread spectrum tracking up to 35kHz modulation and 0.5, 1 or 2% deviations (center spread). The maximum conditions for the RxCLKIN input are: a modulation frequency of 35kHz and amplitude deviations of 2% (4% total). SER -- INTEGRATED SIGNAL CONDITIONING FEATURES Ser -- VOD Select (VODSEL) The DS92LV0411 differential output voltage may be increased by setting the VODSEL pin High. When VODSEL is Low, the DC VOD is at the standard (default) level. When VODSEL is High, the DC VOD is increased in level. The increased VOD is useful in extremely high noise environments and also on extra long cable length applications. When using de-emphasis it is recommended to set VODSEL = H to avoid excessive signal attenuation especially with the larger de-emphasis settings. This feature may be controlled by the external pin or by register. Table 4. Ser -- Differential Output Voltage Input Effect VODSEL VOD mV VOD mVp-p H 450 900 L 300 600 Ser -- De-Emphasis (De-Emph) The De-Emph pin controls the amount of de-emphasis beginning one full bit time after a logic transition that the device drives. This is useful to counteract loading effects of long or lossy cables. This pin should be left open for standard switching currents (no de-emphasis) or if controlled by register. De-emphasis is selected by connecting a resistor on this pin to ground, with R value between 0.5 k to 1 M, or by register setting. When using DeEmphasis it is recommended to set VODSEL = H. Table 5. De-Emphasis Resistor Value Resistor Value (k) De-Emphasis Setting Open Disabled 0.6 - 12 dB 1.0 - 9 dB 2.0 - 6 dB 5.0 - 3 dB 28 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 0.00 VDD = 1.8V, TA = 25oC -2.00 DE-EMPH (dB) -4.00 -6.00 -8.00 -10.00 -12.00 -14.00 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 R VALUE - LOG SCALE (:) Figure 25. De-Emph vs. R value POWER SAVING FEATURES Ser -- Power Down Feature (PDB) The DS92LV0411 has a PDB input pin to ENABLE or POWER DOWN the device. This pin is controlled by the host and is used to save power, disabling the link when the display is not needed. In the POWER DOWN mode, the high-speed driver outputs are both pulled to VDD and present a 0V VOD state. Note - in POWER DOWN, the optional Serial Bus Control Registers are RESET. Ser -- Stop Clock Feature The DS92LV0411 will enter a low power SLEEP state when the RxCLKIN is stopped. A STOP condition is detected when the input clock frequency is less than 3 MHz. The clock should be held at a static Low or high state. When the RxCLKIN starts again, the device will then lock to the valid input RxCLKIN and then transmits the RGB data to the desializer. Note - in STOP CLOCK SLEEP, the optional Serial Bus Control Registers values are RETAINED. 1.8V or 3.3V VDDIO Operation The DS92LV0411 parallel control pin bus can operate with 1.8 V or 3.3 V levels (VDDIO) for host compatibility. The 1.8 V levels will offer a system power savings. OPTIONAL SERIAL BUS CONTROL Please see the following section on the Optional Serial Bus Control Interface. OPTIONAL BIST MODE Please see the following section on the chipset BIST Mode for details. Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 29 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com Deserializer Functional Description The Des converts a single input serial data stream to a wide parallel output bus, and also provides a signal check for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins and strap pins or through the optional serial control bus. The Des features enhance signal quality on the link with an integrated equalizer on the serial input and Channel Link II data encoding which provides randomization, scrambling, and DC balanacing of the data. The Des includes multiple features to reduce EMI associated with data transmission. This includes the randomization and scrambling of the data, the output spread spectrum clock generation (SSCG) support. The Des features power saving features with a power down mode, and optional LVCMOS (1.8 V) interface compatibility. OSCILLATOR OUTPUT -- OPTIONAL The DS92LV0412 provides an optional TxCLKOUT when the input clock (serial stream) has been lost. This is based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled by the external pin or through the registers. Clock-DATA RECOVERY STATUS FLAG (LOCK), OUTPUT ENABLE (OEN) and OUTPUT STATE SELECT (OSS_SEL) When PDB is driven HIGH, the CDR PLL begins locking to the serial input, LOCK is LOW and the Channel Link interface state is determined by the state of the OSS_SEL pin. After the DS92LV0412 completes its lock sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is available on the Channel Link outputs. The TxCLKOUT output is held at its current state at the change from OSC_CLK (if this is enabled via OSC_SEL) to the recovered clock (or vice versa). Note that the Channel Link outputs may be held in an inactive state (TriState(R)) through the use of the Output Enable pin (OEN). If there is a loss of clock from the input serial stream, LOCK is driven LOW and the state of the outputs are based on the OSS_SEL setting (configuration pin or register). Table 6. Des Output State Table INPUTS OUTPUTS PDB OEN OSS_SEL LOCK OTHER OUTPUTS L X X X TxCLKOUT is Tri-State TxOUT[3:0] are Tri-State PASS is Tri-State L X L L TxCLKOUT is Tri-State TxOUT[3:0] are Tri-State PASS is HIGH H L H L TxCLKOUT is Tri-State TxOUT[3:0] are Tri-State PASS is Tri-State H H H L TxCLKOUT is Tri-State or OSC Output through Register bit TxOUT[3:0] are Tri-State PASS is Tri-State H L X H TxCLKOUT is Tri-State TxOUT[3:0] are Tri-State PASS is HIGH H H X H TxCLKOUT is Active TxOUT[3:0] are Active PASS is Active (Normal operating mode) 30 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 DES -- INTEGRATED SIGNAL CONDITIONING FEATURES -- DES Des -- Common Mode Filter Pin (CMF) -- Optional The Des provides access to the center tap of the internal termination. A capacitor may be placed on this pin for additional common-mode filtering of the differential pair. This can be useful in high noise environments for additional noise rejection capability. A 0.1F capacitor may be connected to this pin to Ground. Des -- Input Equalizer Gain (EQ) The Des can enable receiver input equalization of the serial stream to increase the eye opening to the Des input. Note this function cannot be seen at the RxIN+/- input. The equalization feature may be controlled by the external pin or by register. Table 7. Receiver Equalization Configuration Table EQ (Strap Option) Effect L ~1.5 dB H ~13 dB EMI REDUCTION FEATURES Des -- VOD Select (VODSEL) The differential output voltage of the Channel Link interface is controlled by the VODSEL input. Table 8. Des -- Differential Output Voltage Table VODSEL Result L VOD is 250 mV TYP (500 mVp-p) H VOD is 400 mV TYP (800 mVp-p) Des -- SSCG Generation -- Optional The Des provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to 2% (4% total) at up to 100 kHz modulations is available. See Switching Characteristics Table. This feature may be controlled by external STRAP pins or by register. The LFMODE setting should be set appropriately if the SSCG is being used. Set LFMODE HIGH if the clock frequency is between 5 MHz and 20 MHz. Set LFMODE LOW if teh clock frequency is between 20 MHz and 50 MHz. Table 9. SSCG Configuration (LF_MODE = L) -- Des Output SSC[2:0] Inputs LF_MODE = L (20 -- 55 MHz) Result SSC2 SSC1 SSC0 fdev (%) fmod (kHz) L L L OFF OFF L L H 0.9 CLK/2168 L H L 1.2 L H H 1.9 H L L 2.3 H L H 0.7 H H L 1.3 H H H 1.7 Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 CLK/1300 Submit Documentation Feedback 31 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com Table 10. SSCG Configuration (LF_MODE = H) -- Des Output SSC[2:0] Inputs LF_MODE = H (5 -- 20 MHz) Result SSC2 SSC1 SSC0 fdev (%) fmod (kHz) L L L OFF OFF L L H 0.7 CLK/625 L H L 1.3 L H H 1.8 H L L 2.2 H L H 0.7 H H L 1.2 H H H 1.7 CLK/385 Frequency fdev(max) FPCLK+ FPCLK FPCLK- fdev(min) Time 1/fmod Figure 26. SSCG Waveform Power Saving Features Des -- Power Down Feature (PDB) The DS92LV0412 has a PDB input pin to ENABLE or POWER DOWN the device. This pin is controlled by the host and is used to save power, disabling the Des when the display is not needed. An auto detect mode is also available. In this mode, the PDB pin is tied HIGH and the Des will enter POWER DOWN when the serial stream stops. When the serial stream starts up again, the Des will lock to the input stream and assert the LOCK pin and output valid data. In the POWER DOWN mode, the LVDS data and clock output states are determined by the OSS_SEL status. Note - in POWER DOWN, the optional Serial Bus Control Registers are RESET. Des -- Stop Stream SLEEPFeature The DS92LV0412 will enter a low power SLEEP state when the input serial stream is stopped. A STOP condition is detected when the embedded clock bits are not present. When the serial stream starts again, the Des will then lock to the incoming signal and recover the data. Note - in STOP CLOCK SLEEP, the optional Serial Bus Control Registers values are RETAINED. 1.8V or 3.3V VDDIO Operation The DS92LV0412 parallel control bus can operate with 1.8 V or 3.3 V levels (VDDIO) for host compatibility. The 1.8 V levels will offer a system power savings. 32 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 Built In Self Test (BIST) An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST mode only a input clock is required along with control to the Ser and Des BISTEN input pins. The Ser outputs a test pattern (PRBS7) and drives the link at speed. The Des detects the PRBS7 pattern and monitors it for errors. A PASS output pin toggles to flag any payloads that are received with 1 to 24 errors. Upon completion of the test, the result of the test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to the Des BISTEN pin. Inter-operability is supported between this Channel Link II device and all reverse compatible devices-- see respective datasheets for details on entering BIST mode and control. Sample BIST Sequence See Figure 27 for the BIST mode flow diagram. Step 1: Place the serializer in BIST Mode by setting Ser BISTEN = H. The BIST Mode is enabled via the BISTEN pin. An RxCLKIN is required for all the Ser options. When the deserializer detects the BIST mode pattern and command the parallel data and control signal outputs are shut off. Step 2: Place the deserializer in BIST mode by setting the BISTEN = H. The Des is now in the BIST mode and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate. Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the data and the final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the BISTEN signal. Step 4: To return the link to normal operation, the ser and des BISTEN input are set Low. The Link returns to normal operation. Figure 28 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or deserializer Equalization). Normal Step 1: SER in BIST BIST Wait Step 2: Wait, DES in BIST BIST Start Step 3: DES in Normal Mode - check PASS BIST Stop Step 4: SER in Normal Figure 27. BIST Mode Flow Diagram Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 33 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com BER Calculations It * * * is possible to calculate the approximate Bit Error Rate (BER). The following is required: Pixel Clock Frequency (MHz) BIST Duration (seconds) BIST test Result (PASS) The BER is less than or equal to one over the product of 24 times the RxCLKIN rate times the test duration. If we assume a 65MHz RxCLKIN, a 10 minute (600 second) test, and a PASS, the BERT is 1.07 X 10E-12 The BIST mode runs a check on the data payload bits. The LOCK pin also provides a link status. It the recovery of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK pin will switch Low. The combination of the LOCK and At-Speed BIST PASS pin provides a powerful tool for system evaluation and performance monitoring. Deserializer Outputs Case 1 - Pass BISTEN (DS90UR907Q) BISTEN (Deserializer) TxCLKOUT (Diff.) TxOUT[3:0] (Diff.) DATA (internal) PASS Prior Result PASS PASS X X X FAIL Prior Result Normal PRBS Case 2 - Fail X = bit error(s) DATA (internal) BIST Result Held BIST Test BIST Duration Normal Figure 28. BIST Waveforms 34 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 Optional Serial Bus Control The DS92LV0411 and DS92LV0412 may be configured by the use of a serial control bus that is I2C protocol compatible. By default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap pins. A write of 01'h to reg_0x00'h will enable/allow configuration by registers; this will override the control/strap pins. Multiple devices may share the serial control bus since multiple addresses are supported. See Figure 29. The serial bus is comprised of three pins. The SCL is a Serial Bus Clock Input. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pull up resistor to VDDIO. For most applications a 4.7 k pull up resistor to 3.3V may be used. The resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven Low. 1.8V 10k 3.3V ID[X] 4.7k 4.7k RID SCL DS92LV0411/ DS92LV0412 SCL SDA SDA HOST To other Devices Figure 29. Serial Control Bus Connection The third pin is the ID[X] pin. This pin sets one of four possible device addresses. Three different connections are possible. The pin may be pulled to VDD (1.8V, NOT VDDIO)) with a 10 k resistor. Or a 10 k pull up resistor (to VDD1.8V, NOT VDDIO)) and a pull down resistor of the recommended value to set other three possible addresses may be used. See Table 11. The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See Figure 30. SDA SCL S START condition, or START repeat condition P STOP condition Figure 30. START and STOP Conditions Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 35 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop condition. A READ is shown in Figure 31 and a WRITE is shown in Figure 32. If the Serial Bus is not required, the three pins may be left open (NC). Table 11. ID[x] Resistor Value - DS92LV0411 Resistor RID k Address 7'b Address 8'b 0 appended (WRITE) 0.47 7b' 110 1001 (h'69) 8b' 1101 0010 (h'D2) 2.7 7b' 110 1010 (h'6A) 8b' 1101 0100 (h'D4) 8.2 7b' 110 1011 (h'6B) 8b' 1101 0110 (h'D6) Open 7b' 110 1110 (h'6E) 8b' 1101 1100 (h'DC) Table 12. ID[x] Resistor Value - DS92LV0412 Resistor RID k Address 7'b Address 8'b 0 appended (WRITE) 0.47 7b' 111 0001 (h'71) 8b' 1110 0010 (h'E2) 2.7 7b' 111 0010 (h'72) 8b' 1110 0100 (h'E4) 8.2 7b' 111 0011 (h'73) 8b' 1110 0110 (h'E6) Open 7b' 111 0110 (h'76) 8b' 1110 1100 (h'EC) Register Address Slave Address S A 2 A 1 A 0 0 Slave Address a c k a c k A 2 S A 1 A 0 Data 1 a c k a c k P Figure 31. Serial Control Bus -- READ Register Address Slave Address S A 2 A 1 A 0 0 a c k Data a c k a c k P Figure 32. Serial Control Bus -- WRITE 36 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 Table 13. DS92LV0411 SERIALIZER -- Serial Bus Control Registers ADD ADD Register Name (dec) (hex) 0 0 Ser Config 1 Bit(s) R/W 7 R/W 0 Reserved Reserved 6 R/W 0 MAPSEL 0: LSB on RxIN3 1: MSB on RxIN3 5 R/W 0 VODSEL 0: Low 1: High 0 Reserved Reserved 3:2 R/W 00 CONFIG 00: Control Signal Filter Disabled 01: Control Signal Filter Enabled 10: Reserved 11: Reserved 1 R/W 0 SLEEP Note - not the same function as PowerDown (PDB) 0: normal mode 1: Sleep Mode - Register settings retained. 0 R/W 0 REG 0: Configurations set from control pins 1: Configuration set from registers (except I2C_ID) 7 R/W 0 REG ID 0: Address from ID[X] Pin 1: Address from Register 6:0 R/W 7:5 R/W 000 4 R/W 3:0 R/W 4 1 2 1 2 Device ID De-Emphasis Control Defau Function lt (bin) 11010 ID[X] 00 Description Serial Bus Device ID, IDs are: 7b '1101 001 (h'69) 7b '1101 010 (h'6A) 7b '1101 011 (h'6B) 7b '1101 110 (h'6E) All other addresses are Reserved. De-E Setting 000: 001: 010: 011: 100: 101: 110: 111: set by external Resistor -1 dB -2 dB -3.3 dB -5 dB -6.7 dB -9 dB -12 dB 0 De-E EN 0: De-Emphasis Enabled 1: De-Emphasis Disabled 000 Reserved Reserved Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 37 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com Table 14. DS92LV0412 DESERIALIZER -- Serial Bus Control Registers ADD ADD Register Name (dec) (hex) 0 1 2 38 0 1 2 Des Config 1 Device ID Des Features 1 Bit(s) R/W Defau Function lt (bin) Description 7 R/W 0 LFMODE SSCG Mode -- low frequency support 0: 20 to 65 MHz Operation 1: 10 to 20 MHz Operation 6 R/W 0 MAPSEL Channel Link Map Select 0: LSB on TxOUT3+/1: MSB on TxOUT3+/- 5 R/W 0 Reserved Reserved 4 R/W 0 Reserved Reserved 3:2 R/W 00 CONFIG 00: Control Signal Filter Disabled 01: Control Signal Filter Enabled 10: Reserved 11: Reserved 1 R/W 0 SLEEP Note - not the same function as PowerDown (PDB) 0: normal mode 1: Sleep Mode - Register settings retained. 0 R/W 0 REG Control 0: Configurations set from control pins 1: Configuration set from registers (except I2C_ID) 7 R/W 0 REG ID 0: Address from ID[X] Pin 1: Address from Register 6:0 R/W 7 R/W 0 OEN Output Enable Input (See Table 6) 6 R/W 0 OSS_SEL Output Sleep State Select (See Table 6) 5:4 R/W 00 Reserved Reserved 3 R/W 0 VODSEL LVDS Driver Output Voltage Select 0: LVDS VOD is 250 mV, 500 mVp-p (typ) 1: LVDS VOD is 400 mV, 800 mVp-p (typ) 2:0 R/W 000 OSC_SEL 000: OFF 001:RESERVED 010: 25 MHz 40% 011: 16.7 MHz 40% 100: 12.5 MHz 40% 101: 10 MHz 40% 110: 8.3 MHz 40% 111: 6.3MHz 40% Submit Documentation Feedback 11100 ID[X] 00 Serial Bus Device ID, IDs are: 7b' 111 0001 (h'71) 7b' 111 0010 (h'72) 7b' 111 0011 (h'73) 7b' 111 0110 (h'76) All other addresses are Reserved. Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 Table 14. DS92LV0412 DESERIALIZER -- Serial Bus Control Registers (continued) ADD ADD Register Name (dec) (hex) 3 3 Des Features 2 Bit(s) R/W Defau Function lt (bin) 7:5 R/W 000 4 R/W 3 2:0 Description EQ Gain 000: 001: 010: 011: 100: 101: 110: 111: ~1.625 dB ~3.25 dB ~4.87 dB ~6.5 dB ~8.125 dB ~9.75 dB 11.375 dB 13 dB 0 EQ Enable 0: EQ = disabled 1: EQ = enabled R/W 0 Reserved Reserved R/W 000 SSC IF LFMODE = 0 then: 000: SSCG OFF 001: fdev = 0.9%, fmod = CLK/2168 010: fdev = 1.2%, fmod = CLK/2168 011: fdev = 1.9%, fmod = CLK/2168 100: fdev = 2.3%, fmod = CLK/2168 101: fdev = 0.7%, fmod = CLK/21300 110: fdev = 1.3%, fmod = CLK/1300 111: fdev = 1.57%, fmod = CLK/1300 IF LFMODE = 1, then: 001: fdev = 0.7%, fmod = CLK/625 010: fdev = 1.3%, fmod = CLK/625 011: fdev = 1.8%, fmod = CLK/625 100: fdev = 2.2%, fmod = CLK/625 101: fdev = 0.7%, fmod = CLK/385 110: fdev = 1.2%, fmod = CLK/385 111: fdev = 1.7%, fmod = CLK/385 Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 39 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com APPLICATIONS INFORMATION DISPLAY APPLICATION The DS92LV0411 and DS92LV0412 chipset is intended for interface between a host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888) and up to 1024 X 768 display formats. In a RGB888 application, 24 color bits (R[7:0], G[7:0], B[7:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are supported across the serial link with PCLK rates from 5 to 50 MHz. The chipset may also be used in 18-bit color applications. In this application three to six general purpose signals may also be sent from host to display. DS92LV0411 TYPICAL APPLICATION CONNECTION Figure 33 shows a typical application of the DS92LV0411 for a 50 MHz 24-bit Color Display Application. The LVDS inputs require external 100 ohm differential termination resistors. The CML outputs require 0.1 F AC coupling capacitors to the line. The line driver includes internal termination. Bypass capacitors are placed near the power supply pins. At a minimum, four 0.1 F capacitors and a 4.7 F capacitor should be used for local device bypassing. System GPO (General Purpose Output) signals control the PDB and BISTEN pins. The application assumes the companion deserializer (DS92LV0412) therefore the configuration pins are also both tied Low. In this example the cable is long, therefore the VODSEL pin is tied High and a De-Emphasis value is selected by the resistor R1. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO pin is connected also to the 1.8V rail. The Optional Serial Bus Control is not used in this example, thus the SCL, SDA and ID[x] pins are left open. A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable. Bypass capacitors are placed near the power supply pins. Ferrite beads are placed on the power lines for effective noise suppression. DS92LV0411 VDDIO VDDIO C10 C8 FB1 C3 1.8V VDDTX VDDHS C4 FB2 C5 FB3 C6 FB4 C7 FB5 C9 C11 VDDP C12 RxCLKIN- VDDL RxCLKIN+ RxIN3RxIN3+ Channel Link Interface VDDRX RxIN2RxIN2+ LVDS 100: Terminations RxIN1RxIN1+ DOUT+ DOUT- RxIN0RxIN0+ C1 Serial Channel Link II Interface 1.8V C2 10k ID[X] SCL SDA RID VDDIO VODSEL De-Emph R1 Host Control BISTEN PDB R C13 CONFIG1 CONFIG0 MAPSEL RES7 RES6 RES5 RES4 RES3 RES2 RES1 RES0 DAP (GND) NOTE: C1-C2 = 0.1 PF (50 WV) C3-C9 = 0.1 PF C10-C12 = 4.7 PF C13 = >10 PF R = 10 k: R1 (cable insertion loss specific) RID (see ID[x] Resistor Value Table) FB1-FB5: Impedance = 1 k:, low DC resistance (<1:) Figure 33. DS92LV0411 Typical Connection Diagram 40 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 DS92LV0412 TYPICAL APPLICATION CONNECTION Figure 34 shows a typical application of the DS92LV0412 for a 50 MHz 24-bit Color Display Application. The CML inputs require 0.1 F AC coupling capacitors to the line. The line driver includes internal termination. Bypass capacitors are placed near the power supply pins. At a minimum, four 0.1 F capacitors and a 4.7 F capacitor should be used for local device bypassing. System GPO (General Purpose Output) signals control the PDB and BISTEN pins. The application assumes the companion deserializer (DS92LV0412) therefore the configuration pins are also both tied Low. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO pin is connected also to the 1.8V rail. The Optional Serial Bus Control is not used in this example, thus the SCL, SDA and ID[x] pins are left open. A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable. Bypass capacitors are placed near the power supply pins. Ferrite beads are placed on the power lines for effective noise suppression. DS92LV0412 1.8V VDDL C11 3.3V FB4 FB1 VDDTX C6 C3 C8 C9 C12 VDDL FB2 VDDIO FB5 VDDA C4 VDDIO C7 VDDA C10 FB3 C13 VDDP C5 VDDSC VDDSC TxCLKOUT+ TxCLKOUT- C1 TxOUT3+ RIN+ TxOUT3- Serial Channel Link II Interface TxOUT2+ RINC2 Channel Link Interface TxOUT2TxOUT1+ CMF TxOUT1- C15 TxOUT0+ TxOUT0BISTEN Host Control PDB LOCK R C14 PASS 1.8V 10k ID[X] SCL SDA RID C1 - C2 = 0.1 PF (50 WV) C3 C10, C15 = 0.1 PF C11 - C13 = 4.7 PF C14 = >10 PF R = 10 k: RID (See ID[x] Resistor Value Table) FB1 - FB5: Impedance = 1 k: Low DC resistance ( <1:) 8 RES GND DAP (GND) OEN OSS_SEL LFMODE VODSEL MAPSEL CONFIG1 CONFIG0 SSC[2] SSC[1] SSC[0] Figure 34. DS92LV0412 Typical Connection Diagram Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 41 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com POWER UP REQUIREMENTS AND PDB PIN The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO, it is recommended to use a 10 k pull-up and a 22 uF cap to GND to delay the PDB input signal. TRANSMISSION MEDIA The DS92LV0411 / DS92LV0412 and their companion deserializer/serializer chipset is intended to be used in a point-to-point configuration, through a PCB trace, twisted pair or coaxial cables. The DS92LV0411 requires external parallel LVDS termination, but provides internal serial lane terminations to provide a clean signaling environment. The interconnect for LVDS should present a differential impedance of 100 Ohms. The interconnect for the Channel Link II interface should present a differential impedance of 100 Ohms or when configured for coaxial cables the interconnect should present an impedance of 50 Ohms. Use cables and connectors that have matched impedance to minimize impedance discontinuities. Shielded or un-shielded cables may be used depending upon the noise environment and application requirements. LIVE LINK INSERTION The serializer and deserializer devices support live link or cable hot plug applications. The automatic receiver lock to random data "plug & go" hot insertion capability allows the DS92LV0412 to attain lock to the active data stream during a live cable insertion event. ALTERNATE COLOR / DATA MAPPING Color Mapped data Pin names are provided to specify a recommended mapping for 24-bit and 18-bit Applications. When connecting to earlier generations of Channel Link II deserializer devices, a color mapping review is recommended to ensure the correct connectivity is obtained. Table 15 provides examples for interfacing between DS92LV0411 and different deserializers. 42 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 Table 15. Serializer Alternate Color / Data Mapping Channel Link RxIN3 RxIN2 RxIN1 RxIN0 Bit Number RGB (LSB Example) DS92LV2412 Bit 26 B1 B1 DS99R124Q DS90C124 Bit 25 B0 B0 Bit 24 G1 G1 Bit 23 G0 G0 Bit 22 R1 R1 Bit 21 R0 R0 Bit 20 DE DE ROUT20 ROUT20 ROUT19 N/A Bit 19 VS VS ROUT19 Bit 18 HS HS ROUT18 Bit 17 B7 B7 ROUT17 Bit 16 B6 B6ROUT10 ROUT16 ROUT16 Bit 15 B5 B5 ROUT15 ROUT15 Bit 14 B4 B4 ROUT14 ROUT14 Bit 13 B3 B3 ROUT13 ROUT13 ROUT12 ROUT18 TxOUT2 ROUT17 Bit 12 B2 B2 ROUT12 Bit 11 G7 G7 ROUT11 Bit 10 G6 G6 ROUT10 Bit 9 G5 G5 ROUT9 ROUT9 Bit 8 G4 G4 ROUT8 ROUT8 Bit 7 G3 G3 ROUT7 ROUT7 Bit 6 G2 G2 ROUT6 ROUT6 Bit 5 R7 R7 ROUT5 ROUT5 Bit 4 R6 R6 ROUT4 Bit 3 R5 R5 ROUT3 Bit 2 R4 R4 ROUT2 ROUT2 Bit 1 R3 R3 ROUT1 ROUT1 Bit 0 R2 R2 ROUT0 ROUT0 N/A DS92LV0411 Settings DS90UR124 N/A MAPSEL = 0 CONFIG [1:0] = 00 ROUT11 TxOUT1 ROUT10 ROUT4 TxOUT0 ROUT3 ROUT23 OS2 ROUT23 ROUT22 OS1 ROUT22 ROUT21 OS0 CONFIG [1:0] = 10 Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 ROUT21 CONFIG [1:0] = 11 Submit Documentation Feedback 43 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com Table 16. Deserializer Alternate Color / Data Mapping Channel Link TxOUT3 TxOUT2 TxOUT1 TxOUT0 Bit Number RGB (LSB Example) DS92LV2411 Bit 26 B1 B1 44 DS99R421Q DS90C241 Bit 25 B0 B0 Bit 24 G1 G1 Bit 23 G0 G0 Bit 22 R1 R1 Bit 21 R0 R0 Bit 20 DE DE DIN20 DIN20 DIN19 N/A Bit 19 VS VS DIN19 Bit 18 HS HS DIN18 Bit 17 B7 B7 DIN17 Bit 16 B6 B6ROUT10 DIN16 DIN16 Bit 15 B5 B5 DIN15 DIN15 Bit 14 B4 B4 DIN14 DIN14 Bit 13 B3 B3 DIN13 DIN13 DIN12 DIN18 RxIN2 DIN17 Bit 12 B2 B2 DIN12 Bit 11 G7 G7 DIN11 Bit 10 G6 G6 DIN10 Bit 9 G5 G5 DIN9 DIN9 Bit 8 G4 G4 DIN8 DIN8 Bit 7 G3 G3 DIN7 DIN7 Bit 6 G2 G2 DIN6 DIN6 Bit 5 R7 R7 DIN5 DIN5 Bit 4 R6 R6 DIN4 Bit 3 R5 R5 DIN3 Bit 2 R4 R4 DIN2 DIN2 Bit 1 R3 R3 DIN1 DIN1 Bit 0 R2 R2 DIN0 DIN0 N/A DS92LV0412 Settings DS90UR241 N/A MAPSEL = 0 Submit Documentation Feedback CONFIG [1:0] = 00 DIN11 RxIN1 DIN10 DIN4 RxIN0 DIN3 DIN923 OS2 DIN923 DIN922 OS1 DIN922 DIN921 OS0 CONFIG [1:0] = 10 DIN921 CONFIG [1:0] = 11 Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 DS92LV0411, DS92LV0412 www.ti.com SNLS331B - MAY 2010 - REVISED APRIL 2013 PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuit board layout and stack-up for the LVDS devices should be designed to provide low-noise power feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the tantalum capacitors should be at least 5X the power supply voltage being used. Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor will increase the inductance of the path. A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency. Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. PIN DESCRIPTIONS tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs. Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100 Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less. Information on the WQFN style package is provided in Application Note: AN-1187 (SNOA401). LVDS INTERCONNECT GUIDELINES See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details. * Use 100 coupled differential pairs * Use the S/2S/3S rule in spacings - S = space between the pair - 2S = space between pairs - 3S = space to LVCMOS signal * Minimize the number of vias * If vias are used, be sure to place vias to ground adjacent to the signal vias to ensure a constant return path for the signal * Use differential connectors when operating above 500Mbps line speed * Maintain balance of the traces * Minimize skew within the pair * Terminate as close to the TX outputs and RX inputs as possible Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 Submit Documentation Feedback 45 DS92LV0411, DS92LV0412 SNLS331B - MAY 2010 - REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision A (April 2013) to Revision B * 46 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 45 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: DS92LV0411 DS92LV0412 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) DS92LV0411SQ/NOPB ACTIVE WQFN NJK 36 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 85 LV0411SQ DS92LV0411SQE/NOPB ACTIVE WQFN NJK 36 250 RoHS & Green SN Level-3-260C-168 HR -40 to 85 LV0411SQ DS92LV0411SQX/NOPB ACTIVE WQFN NJK 36 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 85 LV0411SQ DS92LV0412SQ/NOPB ACTIVE WQFN RHS 48 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 85 LV0412SQ DS92LV0412SQE/NOPB ACTIVE WQFN RHS 48 250 RoHS & Green SN Level-3-260C-168 HR -40 to 85 LV0412SQ DS92LV0412SQX/NOPB ACTIVE WQFN RHS 48 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 85 LV0412SQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Sep-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS92LV0411SQ/NOPB WQFN NJK 36 DS92LV0411SQE/NOPB WQFN NJK DS92LV0411SQX/NOPB WQFN NJK DS92LV0412SQ/NOPB WQFN DS92LV0412SQE/NOPB DS92LV0412SQX/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 36 250 178.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 36 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Sep-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LV0411SQ/NOPB WQFN NJK 36 1000 367.0 367.0 38.0 DS92LV0411SQE/NOPB WQFN NJK 36 250 210.0 185.0 35.0 DS92LV0411SQX/NOPB WQFN NJK 36 2500 367.0 367.0 38.0 DS92LV0412SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS92LV0412SQE/NOPB WQFN RHS 48 250 210.0 185.0 35.0 DS92LV0412SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA NJK0036A SQA36A (Rev A) www.ti.com PACKAGE OUTLINE RHS0048A WQFN - 0.8 mm max height SCALE 1.800 PLASTIC QUAD FLATPACK - NO LEAD 7.15 6.85 A B PIN 1 INDEX AREA 0.5 0.3 7.15 6.85 0.30 0.18 DETAIL OPTIONAL TERMINAL TYPICAL 0.8 0.7 C SEATING PLANE 0.05 0.00 0.08 C 2X 5.5 (0.2) 5.1 0.1 (A) TYP 24 13 44X 0.5 DIM A OPT 1 OPT 2 (0.1) (0.2) 12 25 EXPOSED THERMAL PAD 2X 5.5 49 SYMM SEE TERMINAL DETAIL 1 PIN 1 ID (OPTIONAL) 36 48 37 SYMM 48X 0.5 0.3 48X 0.30 0.18 0.1 0.05 C A B 4214990/B 04/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT RHS0048A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 5.1) SYMM 37 48 48X (0.6) 1 36 48X (0.25) (1.05) TYP 44X (0.5) (1.25) TYP 49 SYMM (6.8) (R0.05) TYP ( 0.2) TYP VIA 25 12 13 24 (1.25) TYP (1.05) TYP (6.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:12X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL EDGE EXPOSED METAL SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK SOLDER MASK DEFINED SOLDER MASK DETAILS 4214990/B 04/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN RHS0048A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD (0.625) TYP (1.25) TYP 37 48 48X (0.6) 1 36 49 48X (0.25) 44X (0.5) (1.25) TYP (0.625) TYP SYMM (6.8) (R0.05) TYP METAL TYP 25 12 13 16X ( 1.05) 24 SYMM (6.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 49 68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:15X 4214990/B 04/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. 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