NTHD5903 Power MOSFET -20 V, -3.0 A, Dual P-Channel ChipFETE Features * * * * Low RDS(on) for Higher Efficiency Logic Level Gate Drive Miniature ChipFET Surface Mount Package Saves Board Space Pb-Free Package is Available http://onsemi.com ID MAX V(BR)DSS RDS(on) TYP -20 V 130 mW @ -4.5 V -3.0 A 215 mW @ -2.5 V Applications * Power Management in Portable and Battery-Powered Products; S1 i.e., Cellular and Cordless Telephones and PCMCIA Cards S2 G2 G1 MAXIMUM RATINGS (TA = 25C unless otherwise noted) Rating Symbol 5 secs Steady State Drain-Source Voltage VDS -20 V Gate-Source Voltage VGS "12 V Continuous Drain Current (TJ = 150C) (Note 1) TA = 25C TA = 85C Pulsed Drain Current ID PD Operating Junction and Storage Temperature Range -3.0 TJ, Tstg A -2.2 A W 2.1 1.1 ChipFET CASE 1206A STYLE 2 1.1 0.6 C -55 to +150 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces). PIN CONNECTIONS MARKING DIAGRAM D1 8 1 S1 1 D1 7 2 G1 2 D2 6 3 S2 3 D2 5 4 G2 4 8 A7 M G Maximum Power Dissipation (Note 1) TA = 25C TA = 85C P-Channel MOSFET "2.2 "1.6 "10 IDM IS P-Channel MOSFET A "3.0 "2.2 Continuous Source Current (Diode Conduction) (Note 1) D2 D1 Unit 7 6 5 A7 = Specific Device Code M = Month Code G = Pb-Free Package ORDERING INFORMATION Device Package Shipping NTHD5903T1 ChipFET 3000/Tape & Reel NTHD5903T1G ChipFET (Pb-Free) 3000/Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. (c) Semiconductor Components Industries, LLC, 2005 November, 2005 - Rev. 4 1 Publication Order Number: NTHD5903/D NTHD5903 THERMAL CHARACTERISTICS Characteristic Symbol Maximum Junction-to-Ambient (Note 2) tv5s Steady State RqJA Maximum Junction-to-Foot (Drain) Steady State RqJF Typ Max 50 90 60 110 30 40 Unit C/W C/W 2. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces). ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Symbol Test Condition Min VGS(th) VDS = VGS, ID = -250 mA -0.6 Gate-Body Leakage IGSS VDS = 0 V, VGS = "12 V "100 nA Zero Gate Voltage Drain Current IDSS VDS = -16 V, VGS = 0 V -1.0 mA VDS = -16 V, VGS = 0 V, TJ = 85C -5.0 Characteristic Typ Max Unit Static Gate Threshold Voltage V On-State Drain Current (Note 3) ID(on) VDS v -5.0 V, VGS = -4.5 V Drain-Source On-State Resistance (Note 3) rDS(on) VGS = -4.5 V, ID = -2.2 A 0.130 0.155 VGS = -3.6 V, ID = -2.0 A 0.150 0.180 VGS = -2.5 V, ID = -1.7 A 0.215 0.260 gfs VDS = -10 V, ID = -2.2 A 5.0 VSD IS = -2.2 A, VGS = 0 V -0.8 -1.2 V 3.7 7.4 nC 13 20 ns 35 55 25 40 25 40 40 80 Forward Transconductance (Note 3) Diode Forward Voltage (Note 3) -10 A W S Dynamic (Note 4) Total Gate Charge Qg VDS = -10 V, VGS = -4.5 V, ID = -2.2 A Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time 1.3 tr td(off) Fall Time tf Source-Drain Reverse Recovery Time trr 0.8 VDD = -10 V, RL = 10 W ID ^ -1.0 A, VGEN = -4.5 V, RG = 6 W IF = -2.2 A, di/dt = 100 A/ms 3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing. http://onsemi.com 2 NTHD5903 TYPICAL ELECTRICAL CHARACTERISTICS 10 10 -3.6 V 8 125C ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) VGS = -4 V - 10 V -3.4 V TJ = 25C -3 V 6 -2.8 V 4 -2.6 V VGS = -1.4 V -2.4 V 2 -2.2 V -1.8 V 0 2 3 4 5 TC = -55C 6 4 2 6 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0 1 2 3 4 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 25C 0 1 0 4 ID = -2.2 A TJ = 25C 3 2 1 0 0 1 2 3 4 5 TJ = 25C 0.35 0.3 VGS = -2.5 V 0.25 0.2 VGS = -3.6 V 0.15 VGS = -4.5 V 0.1 0.05 1 2 3 4 5 6 7 8 9 -ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance vs. Gate-to-Source Voltage Figure 4. On-Resistance vs. Drain Current and Gate Voltage 10 1.0E-6 ID = -2.2 A VGS = -4.5 V VGS = 0 V TJ = 150C 1.0E-7 IDSS, LEAKAGE (A) 1.4 1.2 TJ = 100C 1.0E-8 1.0E-9 1 TJ = 25C 1.0E-10 0.8 0.6 -50 5 0.4 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 1.6 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 8 1.0E-11 -25 0 25 50 75 100 125 150 0 4 8 12 16 TJ, JUNCTION TEMPERATURE (C) -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current vs. Voltage http://onsemi.com 3 20 NTHD5903 TYPICAL ELECTRICAL CHARACTERISTICS 5 VGS = 0 V TJ = 25C C, CAPACITANCE (pF) 500 400 Crss 300 200 Coss 100 0 -12 -8 -4 0 -VGS -VDS 4 8 12 16 20 10 9 4 8 7 3 6 5 Qgd Qgs 2 4 3 ID = -2.2 A TJ = 25C 1 2 1 0 0 0 1 2 3 Qg, TOTAL GATE CHARGE (nC) GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) 4 Figure 8. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge Figure 7. Capacitance Variation 100 5 VDD = -10 V ID = -1.0 A VGS = -4.5 V IS, SOURCE CURRENT (AMPS) td(off) tf tr t, TIME (ns) 11 Qg -VDS, DRAIN-TO-SOURCE VOLTAGE (V) VDS = 0 V Ciss -VGS, GATE-TO-SOURCE VOLTAGE (V) 600 td(on) 10 1 VGS = 0 V TJ = 25C 4 3 2 1 0 1 10 100 0 0.2 0.4 0.6 0.8 1 RG, GATE RESISTANCE (OHMS) -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 1.2 Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 Notes: PDM 0.2 t1 0.1 t2 0.1 t1 1. Duty Cycle, D = t 2 2. Per Unit Base = RthJA = 90C/W 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted 0.05 0.02 0.01 10-4 Single Pulse 10-3 10-2 10 -1 1 Square Wave Pulse Duration (sec) 10 Figure 11. Normalized Thermal Transient Impedance, Junction-to-Ambient http://onsemi.com 4 100 600 NTHD5903 SOLDERING FOOTPRINT* 2.032 0.08 2.032 0.08 0.457 0.018 0.635 0.025 1.092 0.043 0.635 0.025 0.178 0.007 0.457 0.018 0.711 0.028 0.66 0.026 0.254 0.010 0.66 0.026 Figure 12. Basic SCALE 20:1 mm inches Figure 13. Style 2 *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. BASIC PAD PATTERNS The basic pad layout with dimensions is shown in Figure 12. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 13 improves the thermal area of the drain connections (pins 5, 6, 7, 8) while remaining within the confines of the basic footprint. The drain copper area is 0.0019 sq. in. (or 1.22 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. http://onsemi.com 5 NTHD5903 PACKAGE DIMENSIONS ChipFET] CASE 1206A-03 ISSUE G D 8 7 q 6 L 5 HE 5 6 7 8 4 3 2 1 E 1 2 3 e1 4 b DIM A b c D E e e1 L HE q c e NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. A 0.05 (0.002) STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. MILLIMETERS NOM MAX 1.05 1.10 0.30 0.35 0.15 0.20 3.05 3.10 1.65 1.70 0.65 BSC 0.55 BSC 0.28 0.35 0.42 1.80 1.90 2.00 5 NOM MIN 1.00 0.25 0.10 2.95 1.55 INCHES NOM 0.041 0.012 0.006 0.120 0.065 0.025 BSC 0.022 BSC 0.011 0.014 0.071 0.075 5 NOM MIN 0.039 0.010 0.004 0.116 0.061 MAX 0.043 0.014 0.008 0.122 0.067 0.017 0.079 SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 ChipFET is a trademark of Vishay Siliconix. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. 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Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com http://onsemi.com 6 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NTHD5903/D