© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 4 1Publication Order Number:
NTHD5903/D
NTHD5903
Power MOSFET
−20 V, −3.0 A, Dual P−Channel ChipFETE
Features
•Low RDS(on) for Higher Efficiency
•Logic Level Gate Drive
•Miniature ChipFET Surface Mount Package Saves Board Space
•Pb−Free Package is Available
Applications
•Power Management in Portable and Battery−Powered Products;
i.e., Cellular and Cordless Telephones and PCMCIA Cards
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating Symbol 5 secs Steady
State Unit
Drain−Source Voltage VDS −20 V
Gate−Source Voltage VGS "12 V
Continuous Drain Current
(TJ = 150°C) (Note 1)
TA = 25°C
TA = 85°C
ID
"3.0
"2.2 "2.2
"1.6
A
Pulsed Drain Current IDM "10 A
Continuous Source Current
(Diode Conduction) (Note 1) IS−3.0 −2.2 A
Maximum Power Dissipation
(Note 1)
TA = 25°C
TA = 85°C
PD
2.1
1.1 1.1
0.6
W
Operating Junction and Storage
Temperature Range TJ, Tstg −55 to +150 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq
[1 oz] including traces).
G1G2
S1
D1
S2
D2
P−Channel MOSFETP−Channel MOSFET
Device Package Shipping†
ORDERING INFORMATION
NTHD5903T1 ChipFET 3000/Tape & Ree
l
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† For information on tape and reel specifications,
including part orientation and tape sizes, please
refer t o our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
−20 V 130 mW @ −4.5 V
ID MAXV(BR)DSS RDS(on) TYP
−3.0 A
215 mW @ −2.5 V
ChipFET
CASE 1206A
STYLE 2
MARKING
DIAGRAM
1
2
3
4
S1
G1
S2
G2
D1
D1
D2
D2
PIN
CONNECTIONS
8
7
6
5
5
6
7
81
2
3
4
NTHD5903T1G ChipFET
(Pb−Free) 3000/Tape & Ree
l
A7 = Specific Device Code
M = Month Code
G= Pb−Free Package
A7 M
G
NTHD5903
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2
THERMAL CHARACTERISTICS
Characteristic Symbol Typ Max Unit
Maximum Junction−to−Ambient (Note 2)
t v 5 s
Steady State
RqJA 50
90 60
110
°C/W
Maximum Junction−to−Foot (Drain) Steady State RqJF 30 40 °C/W
2. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces).
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Test Condition Min Typ Max Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = −250 mA−0.6 V
Gate−Body Leakage IGSS VDS = 0 V, VGS = "12 V "100 nA
Zero Gate Voltage Drain Current IDSS VDS = −16 V, VGS = 0 V −1.0 mA
VDS = −16 V, VGS = 0 V,
TJ = 85°C−5.0
On−State Drain Current (Note 3) ID(on) VDS v −5.0 V, VGS = −4.5 V −10 A
Drain−Source On−State Resistance (Note 3) rDS(on) VGS = −4.5 V, ID = −2.2 A 0.130 0.155 W
VGS = −3.6 V, ID = −2.0 A 0.150 0.180
VGS = −2.5 V, ID = −1.7 A 0.215 0.260
Forward Transconductance (Note 3) gfs VDS = −10 V, ID = −2.2 A 5.0 S
Diode Forward Voltage (Note 3) VSD IS = −2.2 A, VGS = 0 V −0.8 −1.2 V
Dynamic (Note 4)
Total Gate Charge QgVDS = −10 V, VGS = −4.5 V,
ID = −2.2 A
3.7 7.4 nC
Gate−Source Charge Qgs 0.8
Gate−Drain Charge Qgd 1.3
Turn−On Delay Time td(on) VDD = −10 V, RL = 10 W
ID ^ −1.0 A, VGEN = −4.5 V,
RG = 6 W
13 20 ns
Rise Time tr35 55
Turn−Off Delay Time td(off) 25 40
Fall Time tf25 40
Source−Drain Reverse Recovery Time trr IF = −2.2 A, di/dt = 100 A/ms40 80
3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
4. Guaranteed by design, not subject to production testing.
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3
TYPICAL ELECTRICAL CHARACTERISTICS
−3 V
125°C
0
10
5
8
6
632
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
4
2
01
Figure 1. On−Region Characteristics
0
10
8
324
6
4
2
1
0
5
Figure 2. Transfer Characteristics
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
1
24
3
2
0
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
R
DS(on),
DRAIN−TO−SOURCE RESISTANCE (
W
)
ID, DRAIN CURRENT (AMPS)
191
0
85
0.25
4
0.15
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
−ID, DRAIN CURRENT (AMPS)
−50 0−25 25
1.4
1.2
1
0.8
0.6 50 125100
Figure 5. On−Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
TJ = 25°C
VGS = −1.4 V
4
13
TC = −55°C
ID = −2.2 A
TJ = 25°C
0.4
0.05
75 150
TJ = 25°C
ID = −2.2 A
VGS = −4.5 V
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
4
25°C
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
1.6
VGS = −4.5 V
VGS = −3.6 V
−1.8 V
−2.2 V
05
7623
04 8
1.0E−11 2
0
16
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
12
VGS = 0 V
IDSS, LEAKAGE (A)
TJ = 150°C
TJ = 100°C
−2.4 V
−2.6 V
−2.8 V
−3.4 V
−3.6 V
VGS = −4 V − 10 V
0.35
0.2
0.1
0.3 VGS = −2.5 V
1.0E−10
1.0E−9
1.0E−8
1.0E−7
1.0E−6
TJ = 25°C
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4
TYPICAL ELECTRICAL CHARACTERISTICS
VDS = 0 V VGS = 0 V
84−12 12
600
300
200
100
020
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
C, CAPACITANCE (pF)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
−VGS, GATE−TO−SOURCE VOLTAGE (V)
TJ = 25°C
Coss
Ciss
Crss
500
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
101
10
1100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
t, TIME (ns)
VDD = −10 V
ID = −1.0 A
VGS = −4.5 V
100
−8 0
400
td(off)
td(on)
tf
tr
−VGS −VDS
−4 16
0.80
1
01.2
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage vs. Current
IS, SOURCE CURRENT (AMPS)
VGS = 0 V
TJ = 25°C
5
10.60.40.2
2
3
4
0
1
2
3
4
5
01234
0
1
2
3
4
5
6
7
8
9
10
11
Qg, TOTAL GATE CHARGE (nC)
ID = −2.2 A
TJ = 25°C
Qg
Qgd
Qgs
2
1
0.1
0.0110 1010
−4 −3 −2 −1
10 1 10 100 600
Square Wave Pulse Duration (sec)
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
Single Pulse
0.1
0.05
0.02 1. Duty Cycle, D =
2. Per Unit Base = RthJA = 90°C/W
3. TJM − TA = PDMZthJA(t)
4. Surface Mounted
t1
t2
PDM
Notes:
t1t2
Figure 11. Normalized Thermal Transient Impedance, Junction−to−Ambient
NTHD5903
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5
Figure 12. Basic Figure 13. Style 2
0.457
0.018
2.032
0.08
0.635
0.025
0.66
0.026
0.254
0.010
ǒmm
inchesǓ
SCALE 20:1
1.092
0.043
0.178
0.007
0.457
0.018
2.032
0.08
0.635
0.025
0.66
0.026
0.711
0.028
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in
Figure 12. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area,
particularly for the drain leads.
The minimum recommended pad pattern shown in
Figure 13 improves the thermal area of the drain
connections (pins 5, 6, 7, 8) while remaining within the
confines of the basic footprint. The drain copper area is
0.0019 sq. in. (or 1.22 sq. mm). This will assist the power
dissipation path away from the device (through the copper
leadframe) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.
NTHD5903
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6
PACKAGE DIMENSIONS
ChipFET]
CASE 1206A−03
ISSUE G
STYLE 2:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
E
A
b
e
e1
D
1234
8765
c
L
1234
8765
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
0.05 (0.002)
DIM
AMIN NOM MAX MIN
MILLIMETERS
1.00 1.05 1.10 0.039
INCHES
b0.25 0.30 0.35 0.010
c0.10 0.15 0.20 0.004
D2.95 3.05 3.10 0.116
E1.55 1.65 1.70 0.061
e0.65 BSC
e1 0.55 BSC
L0.28 0.35 0.42 0.011
0.041 0.043
0.012 0.014
0.006 0.008
0.120 0.122
0.065 0.067
0.025 BSC
0.022 BSC
0.014 0.017
NOM MAX
1.80 1.90 2.00 0.071 0.075 0.079
HE5°NOM
q5°NOM
HE
q
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NTHD5903/D
ChipFET is a trademark of Vishay Siliconix.
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