General Description
The Maxim ICL7135 is a high precision monolithic
41/2 digit A/D converter. Dual slope conversion reliabil-
ity is combined with ±1 in 20,000 count accuracy and
a 2.0000V full scale capability. It features high imped-
ance differential inputs, nearly ideal differential linearity,
true ratiometric operation, auto zero and auto-polarity.
The multiplexed BCD outputs and digit drivers provide
easy interface to external display drivers like the Maxim
ICM7211A. The only other external components needed
to make precision DVM/DPMs are a reference and a
clock. For more complex systems the BCD outputs are
enhanced by STROBE, OVERRANGE, UNDERRANGE,
RUN/HOLD and BUSY lines providing easy interface to
microprocessors and UARTs. This interfacing capability
makes the ICL7135 an ideal device for use in micropro-
cessor based data acquisition and control systems.
The ICL7135 has auto-zero accuracy better than 10µV,
zero drift of 0.5µV/°C, input bias current of 10pA max. and
rollover error of less than 1 count.
Applications
This device is used in a wide range of measurement
applications involving the manipulation and display of
analog data:
Benets and Features
●Improved 2nd Source
(See our “Maxim Advantage™” Page 3)
●±20,000 Count Resolution
●Guaranteed ±1 Count accuracy
●Over-range, under-range signals for auto-range
capability
●Easy interface to UARTs and µPs
●TTL compatible, Multiplexed BCD outputs
●True differential input. Zero reading guaranteed for
0 volt Input
●True polarity at zero for precise null detection
●Monolithic CMOS Design
●Pressure
●Voltage
●Resistance
●Temperature
●Weight
●Current
●Speed
●Material Thickness
The “’Maxim Advantage’” signifies an upgraded quality level. At no additional cost we offer a second-source device that is subject to the following:
guaranteed performance over temperature along with tighter test specifications on many key parameters; and device enhancements, when needed,
that result in improved performance without changing the functionality.
19-5041; Rev 1; 9/16
ICL7135 41/2 Digit A/D Converter with
Multiplexed BCD Outputs
ANALOG COMMON
NOTE: ALL PACKAGES HAVE THE SAME PINOUT.
INT OUT R/H
1
2
28
27
V-
REFERENCE OVERRANGE
STROBE
UNDERRANGE
3
4
26
25
REF. CAP-
REF. CAP+ BUSY
5
6
24
23
AZ IN
BUFF OUT POL
CLOCK IN
DIGITAL GND
7
8
22
21
IN LO (LSD) D1
9 20
IN HI D2
10 19
V+ D3
11 18
(MSD) D5
(LSB) B1
B2
D4
(MSB) B8
B4
12 17
13 16
14 15
ICL7135
D1 D1
D2
D3
D4
D2
D3
D4
D5
STROBE
B8 B3
B4 B2
B2 B1
B1
POL
OR BRT
B0
DQ
DQ
28 SEGMENT DRIVERS
LED DISPLAY
ICL7135
ICM7212
Pin Conguration Typical Operating Circuit
Ordering Information
PART TEMP. RANGE PIN-PACKAGE
ICL7135CJI 0°C to 70°C 28 Lead CERDIP
ICL7135CPI 0°C to 70°C 28 Lead Plastic DIP
ICL7135CQI 0°C to 70°C 28 Lead Plastic chip carrier
ICL7135C/D 0°C to 70°C Dice
Power Dissipation (Note 2)
CERDIP Package .....................................................1000mW
Plastic Package ...........................................................800mW
Operating Temperature ..........................................0°C to +70°C
Storage Temperature ...................................... -65°C to + 160°C
Lead Temperature (Soldering, 10 sec) .............................. 300°C
Supply Voltage V+ ................................................................+6V
V- ................................................................. -9V
Analog Input Voltage (either input) (Note 1)...................V+ to V-
Reference Input Voltage (either input) .......................... V+ to V-
Clock Input ..................................................................Gnd to V+
(V+ = +5V, V- = -5V, TA = 25°C, Clock Frequency Set for 3 Reading/Sec)
Note 1: Input voltages may exceed the supply voltages provided the input current is limited to +100µA.
Note 2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
(Note 1)
Note 1: Tested in 41/2 digit (20,000 count) circuit shown in Figure 1, clock frequency 120kHz.
Note 2: Tested with a low dielectric absorption integrating capacitor. See Component Selection Section.
Note 3: The temperature range can be extended to +70°C and beyond as long as the auto-zero and reference capacitors are
increased to absorb the higher leakage of the ICL7135.
Note 4: This specification relates to the clock frequency range over which the ICL7135 will correctly perform its various functions.
See “Max Clock Frequency” below for limitations on the clock frequency range in a system.
The electrical characteristics above are a reproduction of a portion of lntersil’s copyrighted (1983/1984) data book. This information does not constitute
any representation by Maxim that Intersil’s products will perform in accordance with these specifications. The “Electrical Characteristics Table” along
with the descriptive excerpts from the original manufacturer’s data sheet have been included in this data sheet solely for comparative purposes.
ICL7135 41/2 Digit A/D Converter with
Multiplexed BCD Outputs
www.maximintegrated.com Maxim Integrated
│
2
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
ICL7135 Electrical Characteristics
ANALOG
(Note 1)
(Note 2)
CHARACTERISTICS SYMBOL CONDITIONS MIN TYP MAX UNITS
Zero Input Reading VIN = 0.0V
Full Scale = 2.000V -0.0000 ±0.0000 +0.0000 Digital
Reading
Ratiometric Reading (Note 2) VIN = VREF
Full Scale = 2.000V +0.9995 +0.9999 +1.0000 Digital
Reading
Linearity over ± Full Scale
(Error of Reading from Best Straight Line) -2V ≤ VIN ≤ +2V 0.5 1 Digital
Count Error
Differential Linearity (Difference Between Worst-
Case Step of Adjacent Counts and Ideal Step) -2V ≤ VIN ≤ +2V .01 LSB
Rollover error (Difference in Reading for Equal
Positive and Negative Voltage Near Full Scale) -VIN ≡ VIN ≈ 2V 0.5 1 Digital
Count Error
Noise (P-P Value Not Exceeded 95% of Time) enVIN = 0V
Full Scale = 2.000V 15 µV
Leakage Current at Input IILK VIN = 0V 1 10 pA
Zero Reading Drift VIN = 0V
0° ≤ TA ≤ +70°C 0.5 2 µV/°C
Scale Factor Temperature
Coefcient (Note 3) TC
VIN = +2V
0° ≤ TA ≤ +70°C
(ext. ref. 0 ppm/°C)
2 5 ppm/°C
DIGITAL
INPUTS Clock In, Run/Hold
VINH 2.8 2.2 V
VINL 1.6 0.8
IINL VIN = 0V 0.02 0.1 mA
IINH VIN = +5V 0.1 10 µA
OUTPUTS
All Outputs VOL IOL = 1.6mA 0.25 0.40 V
B1, B2, B4, B8
D1, D2, D3, D4, D5
VOH IOH = -1mA 2.4 4.2 V
BUSY, STROBE, OVER-RANGE,
UNDER-RANGE, POLARITY VOH IOH = -10µA 4.9 4.99 V
SUPPLY
+5V Supply Range V+ +4 +5 +6 V
-5V Supply Range V- -3 -5 -8 V
+5V Supply Current I+ fC = 0 1.1 3.0 mA
-5V Supply Current I- fC = 0 0.8 3.0
Power Dissipation Capacitance CPD vs. Clock Freq 40 pF
Clock Clock Frequency (Note 4) DC 2000 1200 kHz
Note 1: Tested in 41/2 digit (20,000 count) circuit shown in Figure 1, clock frequency 120kHz.
Note 2: Tested with a low dielectric absorption integrating capacitor. See Component Selection Section.
Note 3: The Temperature range can be extended to +70°C and beyond as long as the auto-zero and reference capacitors are
increased to absorb the higher leakage of the ICL7135.
Note 4: This specification relates to the clock frequency range over which the ICL7135 will correctly perform its various functions.
See “Clock Frequency” below for limitations on the clock frequency range in a system.
Note 5: +5V Supply current for fc ≠ 0 is I+ = I+ (fc = 0) + CPD x 5V x fc.
Note 6: All pins are designed to withstand electrostatic discharge (ESD) levels in excess of 2000V. (Test circuit per MIL Std 883,
Method 3015.1)
●Guaranteed 2mA Max Supply Current
●Key Parameters Guaranteed Over Temperature
●Significantly Improved ESD Protection (Note 6)
●Low Noise
This device conforms to the Absolute Maximum Ratings on adjacent page.
Specifications below satisfy or exceed all ‘’tested” parameters on adjacent page.
(V+ = +5V, V- = -5V, TA = +25°C, Clock Frequency Set for 3 Reading/Sec)
●Maxim Quality and Reliability
ICL7135 41/2 Digit A/D Converter with
Multiplexed BCD Outputs
www.maximintegrated.com Maxim Integrated
│
3
Absolute Maximum Ratings:
Electrical Characteristics
ANALOG
(Note 1)
(Note 2)
CHARACTERISTICS SYMBOL CONDITIONS MIN TYP MAX UNITS
Zero Input Reading VIN = 0.0V, Full Scale = 2.000V
0° ≤ TA ≤ +70°C -0.0000 ±0.0000 -0.0000 Digital
Reading
Ratiometric Reading (Note 2)
VIN = VREF, Full Scale = 2.000V
TA = 25°C
0° ≤ TA ≤ +70°C
Digital
Reading
+0.9998 +0.9999 +1.0000
+0.9995 +0.9999 +1.0005
Linearity Over ± Full Scale
(Error of Reading from Best
Straight Line)
-2V ≤ VIN ≤ +2V 0.5 1 Digital
Count Error
Differential Linearity (Difference
Between Worst-Case Step of
Adjacent Counts and Ideal Step)
-2V ≤ VIN ≤ +2V .01 LSB
Rollover Error (Difference in
Reading for Equal Positive and
Negative Voltage Near Full Scale)
-VIN = +VIN ≈ +2V 0.5 1 Digital
Count Error
Noise (P-P value not exceeded
95% of time) enVIN = 0V, Full Scale = 2.000V 15 µV
Leakage Current at Input IILK
VIN = 0V TA = 25°C 1 10 pA
0° ≤ TA ≤ +70°C 250 pA
Zero Reading Drift VIN = 0V 0° ≤ TA ≤ +70°C µV/°C
Scale Factor Temperature
Coefcient (3) TC VIN = +2V 0° ≤ TA ≤ +70°C 2 5 ppm/°C
(ext. ref. 0ppm/°C)
INPUTS Clock In, Run/Hold
VINH 0° ≤ TA ≤ +70°C 2.8 2.2 V
VINL 0° ≤ TA ≤ +70°C 1.6 0.8
IINL VIN = 0V 0° ≤ TA ≤ +70°C 0.02 0.1 mA
IINH VIN = +5V 0° ≤ TA ≤ +70°C 0.1 10 µA
DIGITAL
OUTPUTS
All Outputs VOL IOL = 1.6mA 0.25 0.40 V
B1, B2, B4, B8
D1, D2, D3, D4, D5
VOH IOH = -1mA 2.4 4.2 V
BUSY, STROBE ,
OVER-RANGE,
UNDER-RANGE POLARITY
VOH IOH = -10µA 4.9 4.99 V
SUPPLY
+5V Supply Range V+ +4 +5 +6 V
-5V Supply Range V- -3 -5 -8 V
+5V Supply Current I+ fC = 0 TA = 25°C
0° ≤ TA ≤ +70°C
1.1 2.0 mA
3.0 mA
-5V Supply Current I- fC = 0 TA = 25°C
0° ≤ TA ≤ +70°C
0.8 2.0 mA
3.0 mA
Power Dissipation Capacitance CPD (Note 5) 40 pF
CLOCK Clock Frequency (Note 4) DC 2000 1200 kHz
Detailed Description
General Operation
The ICL7135 is divided into an Analog section and a
Digital section. The digital section includes the counters,
input and output interfaces, and control logic which controls
the timing of each measurement cycle. Each measurement
is divided into four phases: 1) auto-zero (AZ), 2) signal
integrate (INT), 3) reference deintegrate (DE), and 4) zero
integrator (ZI). The digital section controls the operation
of the analog section during each of these phases, using
counters and the state of the comparator to determine
when to start each of the four phases.
Auto-Zero Phase
During auto-zero Input HI and Input LO are disconnected
from the input pins and are internally shorted to Analog
COMMON. The output of the comparator is connected
to the inverting input of the Integrator, and at the same
time the non-inverting input of the integrator is connected
to the input of the buffer. This feedback loop charges the
autozero capacitor, CAZ, to compensate for the offset
voltages of the buffer amplifier, integrator, and comparator.
Also during auto-zero,the reference capacitor is
connected to the voltage reference and is charged to the
reference voltage. The auto-zero cycle is a minimum of
9800 clock cycles, except after an over-range reading.
After an over-range, the extended zero integrate phase
reduces the auto-zero phase to 3800 clock cycles.
Signal Integrate Phase
At the end of the auto-zero phase the auto-zero loop is
opened, and the Input High and Input Low are switched
to the external pins IN-HI and IN-LO. The analog section
integrates the differential voltage between Input High
and Input Low. The differential voltage must be within
the ICL7135’s common mode range. The voltage on the
integrator capacitor at the end of signal integrate is directly
proportional to the differential voltage between Input High
and Input Low, and is also directly proportional to the
length of the signal integrate phase. The signal integrate
phase lasts precisely 10,000 clock cycles. At the end of
this phase the input signal polarity is determined.
De-Integrate Phase
At the end of signal integrate, Input High and Input Low
are disconnected from the external pins. The integrator
non-inverting input pin is then internally connected to
Analog Common and the buffer input is connected to
one side of the reference capacitor. The other side of
the reference capacitor is connected to Analog Common.
The polarity at the output of the integrator (as detected
by the comparator at the end of signal integrate phase)
determines which terminal of the reference capacitor is
connected to the buffer input. The reference capacitor
polarity is chosen so that the integrator output will always
return towards Analog Common. Since the reference
capacitor was charged to the reference voltage during
the auto-zero phase, the integrator input voltage is now
the reference voltage. The De-Integrate phase lasts for
20,001 counts, or until the comparator detects that the
integrator output has crossed zero, whichever occurs first.
The time required to return to zero is proportional to the
input signal and is inversely proportional to the reference
voltage. The number of clock cycles required to return to
zero is counted by the digital section and is latched as the
measurement result.
IN
REF
V
Displayed reading = 10,000 x V
Zero Integrator Phase
The last of the four phases is the zero integrator phase.
The non-inverting input of the integrator is internally shorted
to Analog Common and the buffer input is internally
connected to the output of the comparator. This closes
a loop that forces the integrator output to zero. Normally
this phase lasts only 100 to 200 counts, sufficient time
to remove the small residual charge on the integrator
capacitor caused by the comparator delay and the one
count delay created by sampling the comparator output
only once per clock cycle. However, an overrange condition
will exist when the integrator output does not return to
zero by the end of the De-Integrate phase, and can leave
a residual voltage on the integrator capacitor. In this case,
the Zero Integrator phase is increased to 6200 counts to
ensure that the integrator capacitor is fully discharged
before the next measurement cycle is started.
Analog Section
Analog COMMON
Analog COMMON is the Analog ground reference for the
ICL7135. If Input Low is at a voltage other than Analog
Figure 1. ICL7135 Test Circuit
ICL7135 41/2 Digit A/D Converter with
Multiplexed BCD Outputs
www.maximintegrated.com Maxim Integrated
│
4
ANALOG COMMON
27Ω
100kΩ
100kΩ
100kΩ
SET VREF = 1.000V
VREF IN
ANALOG
GND
SIGNAL
INPUT
100kΩ
0.47µF
1.0µF
1µF
0.1µF
INT. OUT RUN/HOLD
1
2
28
27
V-
-5V
+5V
REFERENCE OVERRANGE
STROBE
UNDERRANGE
3
4
26
25
REF. CAP-
REF. CAP+ BUSY
5
6
24
23
A-Z IN
BUFF OUT POLARITY
CLOCK IN
DIGITAL GND OV
CLOCK
IN
120kHz
7
8
22
21
IN LO LSD D1
9 20
IN HI D2
10 19
V+ D3
11 18
MSD D5
LSB B1
B2
D4
MSB B8
B4
12 17
13 16
14 15
ICL7135
COMMON a common mode voltage will be introduced
and, although the ICL7135 has an excellent CMRR, Input
Low and Analog COMMON should be connected together
whenever possible. Analog COMMON is also the reference
point for the reference voltage. The Analog Common voltage is
normally connected to the system ground when using ±5V
supplies. When the ICL7135 is operated from a single
supply voltage the Analog Common should be connected
to a voltage source approximately halfway between V+
and ground.
Input Buffer
The ICL7135 input buffer is a CMOS buffer with a common
mode input voltage range of approximately V+ -1.0V to
V- +1.5V. The quiescent current is approximately 100µA
and the buffer can deliver up to 40µ of output current with
excellent linearity.
Integrator
The integrator amplifier, similar to the buffer amplifier, can
deliver 20µA of output current with high linearity while
swinging to within 0.3V of either supply rail. The integrator’s
non-inverting terminal is connected to IN LO during the
signal integrate phase, so the voltage on the IN LO
terminal sets the starting point for the integrator output
during signal integrate. If IN LO is at a voltage other than
ground, this will limit the maximum allowable swing at the
integrator output, and the value of the integrating capaci-
tor should be increased. (Refer to Component Selection)
Comparator
The comparator monitors the voltage on the integrator
capacitor during deintegrate. The digital section samples
the comparator output once per clock cycle and terminates
the deintegrate cycle when the comparator changes its
state as the integrator voltage passes through zero. The
offset voltage of the comparator is not critical since the
auto-zero phase compensates for the offset. The output of
the comparator is the only output from the analog section
to the digital section.
Digital Section
As shown in Figure 3, the digital section consists of coun-
ters, latches, output multiplexer, and control logic. The
control logic monitors the counters and the comparator
to determine the start of each phase, and sends control
signals to the analog section to drive the analog switches
to the proper state for each measurement phase. The
control section also responds to the external input, RUN/
HOLD, and creates the control outputs; OVERRANGE,
UNDERRANGE, BUSY, and STROBE.
RUN/HOLD
When RUN/HOLD is high or open the ICL7135 will
continuously perform conversions with each measure-
ment being 40,002 clock cycles long. When RUN/HOLD
goes low, the ICL7135 will complete the measurement in
progress then remain in the auto-zero cycle, holding the
last reading. If RUN/HOLD goes high after the maximum
period assigned to deintegrate, a new conversion will
start, with a delay of 1 to 10,001 clock cycles between
Figure 2. Analog Section of ICL7135
ICL7135 41/2 Digit A/D Converter with
Multiplexed BCD Outputs
www.maximintegrated.com Maxim Integrated
│
5
10IN HI
ANALOG
COMMON
IN LO
3
9
1
AZ
A/Z
A/Z + DE(±) + ZI
INT
A/Z
CREF+ CREF
RINT
BUFFERREF HI
8 2 7 6 5 4
11
V+
CAZ CINT
CREF
INT
AUTO
ZERO
INTEGRATOR
DE(+)
ZI
INPUT
HIGH
INPUT
LOW
COMPARATOR
A/Z
DE(-)
DE(-)
V-
DE(+)
INT ICL7135
the rising edge of the RUN/HOLD input and the BUSY
output. A RUN/HOLD pulse during the unused portion of
deintegrate phase will be ignored, but when in the auto-
zero phase a positive pulse of only 300ns (typical) will
start the conversion. Figure 5 shows a simple method
of obtaining one, and only one, conversion for each
measurement request.
BUSY
BUSY is a status output that goes high at the beginning
of signal integrate and stays high until the first clock
pulse after zero crossing during De-integrate (or end of
De-Integrate if overranged).The internal data latches are
loaded during the next clock cycle after the falling edge
of BUSY. Since BUSY is high for the 10,000 counts of
signal integrate + number of counts during De-Integrate
+1 clock cycle, a simple way of sending conversion data
down a single pair of wires is to logically ‘AND’ BUSY with
the clock and to subtract 10,001 counts from the number
received. Figure 6 shows a system using this method to
remotely display data.
Figure 3. ICL7135 Digital Section
Figure 4. Timing Diagram Figure 5. External RUN/HOLD Latch
ICL7135 41/2 Digit A/D Converter with
Multiplexed BCD Outputs
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│
6
MSB
POLARITY
FF
ANALOG
SECTION
ZERO
CROSS.
DET.
24 22 25 27 28 26 21
DIGITAL
GND
CLOCK
IN
OVER
RANGE
UNDER
RANGE
BUSY
CONTROL LOGIC
MULTIPLEXER
COUNTERS
LATCH LATCH LATCH LATCH LATCH
STROBERUN/
HOLD
LSB 13
14
15
16
B1
B2
B4
B8
12
11 23
D5V+ POLARITY
17
D4
18
D3
19
D2
20
D1
ICL7135
INTEGRATOR
OUTPUT
BUSY
OVER-RANGE
WHEN APPLICABLE
UNDER-RANGE
WHEN APPLICABLE
NORMAL DIGIT SCAN
1000*
COUNTS
AUTO ZERO
DIGIT SCAN
FOR OVER-RANGE
*FIRST D5 OF AZ AND
DE-INTEGRATE ARE ONE COUNT LONGER
DE-INTEGRATE
SIGNAL
INTEGRATE
*STROBE
D5
D4
D3
D2
D1
D5
D4
D3
D2
D1
AUTO-
ZERO
+
ZERO
INTEGRATOR
10,0001
COUNTS
SIGNAL
INT.
10,000
COUNTS
FULL MEASUREMENT CYCLE
40,002 COUNTS
DE-INTEGRATE
20,001
COUNTS MAX.
RUN/HOLD
FLIP-FLOP
START
PULSE
Q
D
R D
S
ICL7135
BUSY
Digit Outputs
The digit outputs go high sequentially, D5 to D1, for a period
of 200 clock cycles per digit. The 5 digits are continuously
scanned except after an over-range measurement. After
an over-range reading the digit scan stops after the
strobe sequence, and remains stopped until the start
of De-Integrate. For a continuous series of over-range
readings, the digits will be scanned for 21,000 counts out
of 40,002, resulting in a flashing display as an over-range
indicator. D5 is the most significant digit.
BCD Outputs
The 4 BCD output pins are positive logic signals whose
BCD data corresponds to the currently active digit strobe.
The ICL7135 does not have inter-digit blanking and the
BCD data changes simultaneously with the edges of the
digit outputs.
STROBE
The STROBE output is a negative going pulse that is
useful for latching the multiplexed BCD outputs into
external BCD latches. Five negative going STROBE
pulses occur in the center of the data corresponding to
each of the 5 digits of measurement results, once and
only once after the end of each conversion (immediately
after the falling edge of BUSY). The BCD data is valid
at both edges of STROBE, and data can be latched in
either a level sensitive latch, or an edge triggered latch.
Figures 11, 12 and 14 show the use of STROBE to latch
the BCD data. STROBE pulse width is 1µs less than 1/2
clock period.
Over-range and Under-range Outputs
These active high status outputs are set to a high level
at the end of BUSY if the measurement result is 1800
or less (Under-range), or greater than 19,999 (Over-
range). Under-range is reset at the beginning of the signal
integrate phase; over-range is reset at the beginning of
the de-integrate phase.
Polarity
The Polarity output is updated at the beginning of each
de-integrate phase, and is high for a positive input signal.
The Polarity output is valid for all inputs, including ±0 and
overrange signals.
Component Selection
The analog component values must be selected with care
to achieve optimum performance in each application.
Factors that affect the proper values include the reading
rate, input common mode voltage, the full scale and refer-
ence voltages, and the power supply voltages.
Integrating Resistor
Good linearity is obtained when the integrating resistor
value is chosen such that the buffer’s maximum output
current is between 5 and 40µA. The quiescent current of
the buffer is 100µA, and it can supply 20µA of output cur-
rent with excellent linearity. The buffer’s maximum output
current occurs with a full scale input voltage, and the inte-
grating resistor value may be calculated as:
INT
full scale voltage
R = 20µA
Integrating Capacitor
The maximum swing of the integrator during the signal
integrate phase can be calculated as:
INT INT
INT
I x T
Vswing = C
Where IINT = 20µA if RINT is chosen as described above
and TINT = 10,000 clock periods (83.3ms for 120kHz
clock frequency). The integrator swing range should be
maximized while avoiding saturation of the integrator
output. Normally the integrator will not saturate until its
output is within 0.3V of either supply, but for the best inte-
gral linearity the integrator’s output should remain at least
1V away from either supply. For ±5V supply and Analog
Common and IN LO connected to ground, a ±3.5V to ±4V
swing range is optimum. Rearranging the above formula
and inserting values as described above, CINT may be
calculated as:
INT
20µA x 83.3ms
C = x 0.47µF
3.5V
The integrator swing must be reduced if either Analog
Common or IN LO is not grounded, or if the supply voltage
is less than ±5V.
The integrating capacitor must have low dielectric absorption
to obtain low integral nonlinearity, rollover, and ratio
metric errors. The result of measurements with the
reference tied to the IN HI is a good indication of the
Figure 6. Serial Pulse Stream for Remote Reading
ICL7135 41/2 Digit A/D Converter with
Multiplexed BCD Outputs
www.maximintegrated.com Maxim Integrated
│
7
120kHz
CLOCK
TO REMOTE
COUNTER
# OF PULSES
= 10,001 + READING
CLK
IN
BUSY
ICL7135
amount of dielectric absorption in the integrating capacitor.
A good integrating capacitor will result in a reading of
9999, and any deviation from this reading is probably due
to dielectric absorption. Polypropylene capacitors have
been found to be suitable, as have Teflon capacitors.
Polystyrene and polycarbonate capacitors may also be
used in less critical applications.
Auto-Zero Capacitor
The size of the auto-zero capacitor will have a significant
effect on the overall system noise, with larger auto-zero
capacitors resulting in a quieter system. The dielectric
absorption of the auto-zero capacitor affects only the
speed of settling at power-up or recovery from overload
and nearly any capacitor type can be used. The zero
integrator phase of the ICL7135 allows the use of large
auto-zero capacitors while avoiding the “over-range hang-
over” and hysteresis effects that occur in A/D converters
without the zero integrator phase.
Reference Capacitor
Like the auto-zero capacitor, the reference capacitor’s
dielectric absorption is rarely critical. Low dielectric
absorption reference capacitors are only required where
fast settling time is needed in systems with a rapidly
changing reference voltage such as ratiometric ohms
measurement in multimeters.
The reference capacitor DOES need to be a low leakage
capacitor since it must store the reference voltage while
floating during both the signal integrate and the reference
deintegrate phases. Any leakage or charge loss during
these two phases results in an effective change in the
scale factor of the ICL7135. Low cost film capacitors such
as polyester or polystyrene have been found to be suitable
in most applications.
In addition to leakage requirements, another effect that
sets a lower limit on the value of the reference capacitor
is the “charge suckout” caused by stray capacitance on
the reference capacitor terminals. For a negative polarity
input signal, the reference capacitor does not shift its
common mode voltage, but with a positive polarity input
signal it undergoes mode shift equal to the reference
voltage. If there are stray capacitances on the reference
capacitor terminals, some of the charge on the reference
capacitor will be used to charge these stray capacitances
as the reference capacitor makes this common mode
voltage shift. This loss of charge reduces the voltage
on the reference capacitor, and causes positive polarity
signals to have a higher measured result than a corre-
sponding negative voltage. This error can be reduced by
minimizing the stray capacitance on the reference capacitor
terminals, and by increasing the value of the reference
capacitor.
Reference Voltage
The full scale reading of 20,000 will occur when VIN = 2 x
VREF. Since the 20,000 count resolution of the ICL7135
is equivalent to a 50ppm resolution, a high stability
reference is recommended for high accuracy absolute
measurements. Figure 7 shows two suitable methods of
generating the reference voltage.
Rollover Resistor and Diode
The ICL7135 is tested for rollover using the circuit
of Figure 1, with the 100kΩ resistor and diode in the
circuit. The diode is noncritical, and is typically a low
cost 1N4148. The resistor value is dependent on many
factors including integrator swing, clock frequency, and
the amount of rollover error due to “charge suckout” on
the reference capacitor. 100kΩ is the optimum value for
most circuits and is the value used in testing the ICL7135.
Speedup Resistor
The 27Ω speedup resistor in series with the integrat-
ing capacitor adds a pedestal voltage on top of the
integrating capacitor voltage. This pedestal voltage
causes zero crossing to occur earlier than would occur
without the resistor. The effect of the earlier zero crossing
is to give the comparator an overdrive voltage, speeding
its response and reducing the conversion error due to
comparator delay. If the integrator current is changed, the
speedup resistor value should be changed so that the IINT
x RSPEEDUP = 500µV.
Clock Frequency
The clock source should be free of short-term phase and
frequency jitter during the conversion period, but long
term stability is not critical. The clock frequency is chosen
to obtain the desired conversion rate, and to maximize
the normal mode rejection of power line frequency inter-
ference. The conversion rate is directly proportional to
the clock frequency, with each conversion taking 40,002
clock cycles. For maximum normal mode rejection,
Figure 7. External Reference Voltage
ICL7135 41/2 Digit A/D Converter with
Multiplexed BCD Outputs
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│
8
V-
REF HI
6.8 VOLT
ZENER
20
kΩ
6.8kΩ
IZ
V-
ANALOG
COMMON
ICL7135
V-
V+
REF HI
1.2 BANDGAP
REFERENCE
ANALOG
COMMON
ICL7135
the signal integration period should be an integral multiple
of the power line cycles.
CLK
LINE
CLK
f
Reading Rate (in readings per second) = 40,002
f x 10,000
f for maximum normal mode rejection =
N
Where fLINE is the line frequency, normally 50Hz or 60Hz
and N is the number of line cycles that occur during a
signal integration period. For maximum normal mode
rejection, N should be an integer.
For 60Hz rejection, suitable clock frequencies include
300kHz, 200kHz, 150kHz, 120kHz, 100kHz, and 75kHz.
Suitable frequencies for use with 50Hz power include
250kHz , 1662/3kHz, 125kHz, and 100kHz. The two most
common clock frequencies are 120kHz (3 readings per
second) and 100kHz (21/2 readings per second). Note
that a 100kHz clock frequency rejects both 50Hz and
60Hz normal mode signals.
The maximum clock rate is limited by the maximum rate
at which the digital logic will correctly function (typically
2MHz), and by the speed of response of the comparator.
The comparator delay, about 3µs, has the same effect on
the measurement result as does an offset voltage with
the same polarity of the input signal. At the recommended
clock frequency of 120kHz, this small offset is slightly less
than 1/2 count. At higher clock frequencies the value of
the speedup resistor in series with the integration capaci-
tor (normally 27Ω) should be increased. At frequencies
above 120kHz, ringing on the integrator output may cause
nonlinearities in the first few counts.
The minimum clock frequency is limited by the leakage
of the auto-zero and reference capacitors. While seldom
desired, measurement cycles as long as 10 seconds can
be performed with negligible error at room temperature.
Figures 8A and 8B show two methods of generating a
suitable clock signal for the ICL7135.
Application Hints
Grounds
As with all sensitive analog circuitry, it is important to
keep the Digital Ground separate from the .analog ground
(called Analog Common on the ICL7135) to minimize
errors caused by the coupling of noise from the digital
circuitry into the sensitive analog section. Analog Common
should be connected to Digital Ground at only one point,
and return currents from digital loads must not flow
through the analog ground lines. Avoid any unnecessary
current flow in the analog ground path.
Single 5V Supply Operation
The ICL7135 normally uses ±5V supplies, however, in
some applications the negative supply is not needed.
Specifically, the negative 5V supply is not required if
the input signal can be referenced to the center of the
ICL7135’s common mode voltage range AND the signal
voltage is less than ±1.5V. The integrator swing must be
reduced, and there will be a slight increase in system
noise and nonlinearity. See Figure 9 for recommended
component values.
Figure 8A. LM311 Clock Source
Figure 9. Single +5V Supply Operation
Figure 8B. Crystal Oscillator Clock Source
ICL7135 41/2 Digit A/D Converter with
Multiplexed BCD Outputs
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9
16kΩ
16kΩ
0.22µF
1kΩ
30kΩ
390pF
+5V
56kΩ
8
4
2
3
7
1
TO
ICL7135
CLOCK IN
LM311
+5
22MΩ
TO
ICL7135
CLOCK IN
100kHz OR
120kHz
TUNING
FORK
CRYSTAL
330kΩ
10pF5pF
MAX4069
MAX4069
CMOS
INVERTOR
ANALOG COMMON
27Ω
100kΩ
100kΩ
100kΩ
SET VREF = 1.000V
VREF IN
2.5V
SIGNAL
INPUT
100kΩ
1.0µF
2.0µF
1µF
0.1µF
INT. OUT RUN/HOLD
1
2
28
27
V-
-5V
REFERENCE OVERRANGE
STROBE
UNDERRANGE
3
4
26
25
REF. CAP-
REF. CAP+ BUSY
5
6
24
23
A-Z IN
BUFF OUT POLARITY
CLOCK IN
DIGITAL GND
CLOCK
IN
120kHz
7
8
22
21
IN LO LSD D1
9 20
IN HI D2
10 19
V+ D3
11 18
MSD D5
LSB B1
B2
D4
MSB B8
B4
12 17
13 16
14 15
ICL7135
Generating a Negative Supply from +5V
Figures 10A and 10B show two methods of generating a
negative supply for the ICL7135. The Maxim ICL7660 will
supply 2mA (the maximum supply current of the ICL7135)
at 4.85V drop, while the circuit using the CMOS inverter
will deliver approximately -3.5V. If the CMOS inverter is
used to generate a minus supply, the integrator swing
should be reduced to 2.5 to 3V.
Noise
The normal system noise around zero is about 15µV
peak-to-peak (not exceeded 95% of the time). Near full
scale, the noise increases to about 30µV. The main noise
source is the auto-zero loop, and increasing the value of
the auto-zero capacitor will reduce the noise. Other noise
sources include the buffer and integrator noise; com-
parator noise; and stray pickup in the input circuitry, the
integrator, and the reference capacitor. The noise caused
by stray pickup of interfering signals can be reduced by a
tight layout and shielding. If the interfering signal frequen-
cy is constant, the effects of stray pickup in the input and
integrator can be reduced by choosing a clock frequency
such that the signal integration period is an integral mul-
tiple of the interfering signal’s period. Since the length
of the de-integration period depends on the input signal
level, no single clock frequency can be chosen to reject
interfering signals during the de-integrate phase.
Typical Applications
Figure 11 uses Maxim’s ICL7211 LCD display driver to
drive 4 digits of LCD display. The backplane signal of the
ICL7211 and the CMOS exclusive OR gates are used
to drive the 1/2 digit and the polarity sign. The four AND
gates combine the digit outputs with the STROBE output
to generate the digit select signals that latch data into the
ICL7211. Since the Strobe occurs in the middle of each
digit’s data there is ample data setup and hold time to
ensure that valid data is latched. The OR gates will force
the BCD data to all ones when over-range goes high. The
ICL7211A will blank the display when all ones (hexF is
loaded).
The typical operating circuit on the first page of this data
sheet shows a 41/2 digit A/D with LED drive using the
Maxim ICL7212 display driver. In this case the polarity
and 1/2 digit segments are driven by D flip-flops that latch
polarity and 1/2 digit data at the end of each measure-
ment. The ICL7135 Overrange output drives the ICM7212
Brightness input, blanking the four least significant digits
when the input voltage is greater than full scale.
Some applications require non-multiplexed, latched BCD
outputs. The circuit shown in Figure 12 will demultiplex
and latch the ICL7135 output. If only the first rank of
latches is used, the data should not be used during the
800 clock cycle update period that takes place at the end
of each conversion since during this update period the
Figure 10B. Generating a Negative Supply
Figure 11. LCD Display with Digit Blanking on Overrange
Figure 10A. Generating a Negative Supply
ICL7135 41/2 Digit A/D Converter with
Multiplexed BCD Outputs
www.maximintegrated.com Maxim Integrated
│
10
V+
CLOCK
120 kHz
CLOCK
V- = -3.5V
CD 4009
GND
0.47µF
10µF
IN914
IN914
V-
ICL7135
CD4071
CD4081
CD4011
+5V
23 POL
+5V
1/2 CD4030
1/4 CD4030
4-1/2 DIGIT LCD DISPLAY
BP
20 D1 31 D1
5 BP
32 D2
33 D3
34 D4
30 B3
29 B2
28 B1
27 B0
19 D2
18 D3
17 D4
16 B8
15 B4
14 B2
13 B1
12 D5
26 STROBE
27 OR
1/4 CD4030
ICL7135
ICM7211A
-5V
VOUT = -5V
100µF
10µF
1
2
8
7
3
4
6
5
ICL7660
most significant digit (MSD) data will correspond to the
new reading and the least significant digit (LSD) data will
be old data from the previous conversion. The second
rank of latches shown in dotted lines will eliminate this
problem by updating all digits simultaneously with the
rising edge of D5.
There are many different possible ways of interfacing the
ICL7135 to a microprocessor. Figure 13 shows a method
that uses only 8 I/O lines. The digit outputs drive a priority
encoder, which converts the 1-of-5 format of the digit
outputs to a 3 bit binary code. When no digit is active (as
in over-range), the binary output code is 0, otherwise the
output corresponds to the digit number of the active digit.
By sending BUSY as either an input or an an interrupt, the
microprocessor can detect when new data is available.
Another possible interface scheme is to sense only digit
D5, then use time delays to choose when to read the
other digits’ data.
Interfacing with UARTs and
Microprocessors
Figure 14 shows a simple interface between a UART
and a free running ICL7135. The transmission of the five
data words is started by the five STROBE pulses. The
digit 5 word is 0000XXXX, digit 4 is 1000XXXX, digit 3
is 0100XXXX, etc. The polarity is transmitted indirectly
by using it to drive the Even Parity Enable Pin (EPE). A
parity flag at the receiver can be decoded as a positive
signal, no flag as negative, if EPE of the receiver is held
low. Figure 15 shows a more complex arrangement. DR
goes high when the UART receives a byte via the send
input, RRI. Since DR is connected to the ICL7135’S RUN/
HOLD input this starts a new conversion. At the end of
the conversion the falling edge of BUSY resets DR via
the UART’S DRR input. The transmit sequence is again
started by STROBE. A quad 2-input multiplexer is used to
superimpose polarity, over-range, and under-range onto
the D5 word since in this instance it is known that B2 =
B4 = B8 = 0.
To insure proper operation, it is necessary that the UART
clock be fast enough that each word is transmitted before
the next STROBE pulse arrives.
Figure 13. µP Interface
Figure 14. ICL7135 to UART InterfaceFigure 12. Non-Multiplexed, Latched BCD Output
ICL7135 41/2 Digit A/D Converter with
Multiplexed BCD Outputs
www.maximintegrated.com Maxim Integrated
│
11
B1 P10
B2 P11
B4 P12
B8
D1
D2
D3
D4
D5
BUSY
D1 Q0
MC
14532
PRIORITY
ENCODER
Q1
Q2
P1
P15
P16
P17
INT
D2
D3
D4
D5
P13
ICL7135 MAX8048
Q0 D0
D7
Q0
D0
D0
D3
Q0
Q0
Q3
DIGIT 1
BCD
DATA
DIGIT 3
BCD
DATA
Q7
D7 Q7
E0
B1 D0
D1
D2
D3
B2
B4
B8
E2
Q1
Q2
Q3
74LS375
Q0
E0
D0
D1
D2
D3 E2
Q1
Q2
Q3
74LS375
74LS375
Q0
E0
B1
D1 D2 B1
B2
B4
B8
POL
OR
STROBE
D5 D4 D3
D0
D1
D2
D3
D0
D1
D2
D3
B2
B4
B8
E2
Q1
Q2
Q3
Q0
Q1
Q2
Q3
B1
B2
B4
B8
B1
B2
B4
B8
74LS375
ICL7135
E0 E2 Q3
74LS375
D0
D1
D2
Q1
Q2
B1 Q0
E0
D3 E2
Q3
74LS374
74LS374
DIGIT 2
BCD
DATA
DIGIT 4
BCD
DATA
POLARITY
OVERRANGE
DIGIT 5
DATA
SERIAL OUTPUT
TO RECEIVING UART
TRO
UART
TR1602
TBR TBRL
+5V
NC
EPE
1
D4
D5
POL
D3D2D1B1B2B4B6
STROBE
RUN/HOLD
2345678
ICL7135
Figure 15. Complex ICL7135 to UART Interface
ICL7135 41/2 Digit A/D Converter with
Multiplexed BCD Outputs
www.maximintegrated.com Maxim Integrated
│
12
Chip Topography
43 2 1 28 27 26
INT OUT
5
AZ IN
6
BUFF OUT 7
8
9
10
11 12 13 14 15 16 17 18
25
24
23
22
R/H
DIGITAL GND
POL
CLOCK IN
21 BUSY
20
19
D1
D2
REF CAP-
REF CAP+
IN LO
IN HI
V+ D5B1B2B4B8D4D3
0.155”
(2.92mm)
0.134”
(3.40mm)
ANALOG
COMMON REF V-
UNDERRANGE
OVERRANGE
STROBE
TRO
EPE
DR
TBRL
TR1602
TBR
1Y 2Y 3Y ENABLE
74C157
1A
D4
D5
D3D2D1B1B2B4B8
POL
OVER
UNDER
2A 3A 1B
SELECT
2B 3B
1 2 3 4 5 6 7 8
RRI DRR
+5V
10kΩ
100pF
STROBE
RUN/HOLD
BUSY
ICL7135
1.470
0.062
(1.575)
RAD RAD
0.580
(14.730)
MIN
0.030
(0.762)
MAX 0.040 TYP
(1.016)
0.050 ± 0.015
86° 94°
TYP
86° 94°
TYP
(1.270 ± 0.381)
0.150 ± 0.005
(3.810 ± 0.127)
0.018 ± 0.003
(0.457 ± 0.076)
TYP
0.449 ± 0.001
(11.405 ± 0.025)
0.172 ± 0.003
(4.369 ± 0.076
0.420 ± 0.005
(10.668 ± 0.127)
0.045
(1.143) 0.035 RAD
(0.889)
0.022
(0.559)
0.685 ± 0.025
(17.399 ± 0.635)
0.008 ± 0.012
(0.203 - 0.305)
0.055 ± 0.005
(1.397 ± 0.127)
0.060 - 0.100
(1.524 - 2.540)
0.048 - 0.055
(1.219 - 1.397)
0.020 - 0.070
(0508 - 1.778)
0.125 MIN
(3.175)
0.125
(3.175)
MIN
0.200
(5.080)
MAX
0.018 ± 0.002
(0.457 ± 0.051)
TYP
28 Lead Plastic (PI)
θJA = 110°C/W, θJC = 50°C/W
28 Lead Plastic Chip Carrier (Quad Pak) (Q)
28 Lead Cerdip (JI)
θJA = 55°C/W
0.125
(3.175)
MIN
0.020
(0.508)
MIN
0.009 - 0.015
(1.229 - 0.381)
0.045
(1.143)
0.045
PIN 1
0.050 BC
(1.143) 0.010
(0.254)
0.010
(0.254)
0.045
(1.143)
0.010
(0.254)
0.070
(1.778) 0.145
(3.683)
95°± 5°
0.625 +0.025
-0.015
(15.875 )
+0.635
-0.381
(37.340)
0.070
(1.778)
0.600 - 0.620
(15.240 - 15.748) 0.540 ± 0.005
(13.720 ± 0.127)
0.490 ± 0.005
(12.446 ± 0.127)
0.530 - 0.550
MAX GLASS
(13.462 - 13.970)
0.600
(15.240)
0.100 ± 0.010
(2.540 ± 0.254)
0.100 ± 0.010 TYP
(2.540 ± 0.254)
MAX 1.490
GLASS SEALANT
(37.846) MAX
0.025
(0.635)
0.160
(4.064)
MAX
0.590 - 0.620
(14.986 - 15.748)
95°±5°
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 2/87 Initial release —
1 9/16 Updated Ratiometric Reading minimum specication in Electrical Characteristics table 2
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
ICL7135 41/2 Digit A/D Converter with
Multiplexed BCD Outputs
© 2016 Maxim Integrated Products, Inc.
│
13
Revision History
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
